Capacitance digital conversion circuit based on phase-sensitive integration

Abstract

The invention relates to the technical field of capacitance detection circuits, in particular to a capacitance digital conversion circuit based on phase-sensitive integration. The circuit comprises a phase shift circuit unit, a capacitance detection unit, a phase control unit and a digital processing unit. According to the invention, an excitation signal is converted into an excitation signal which is 90 degrees ahead by using a phase shift circuit through a phase shift circuit unit, a capacitance detection unit controls a single-pole double-throw switch S1 to alternately access the excitation signal and an inversion signal to a to-be-detected capacitor Cx and a reference capacitor C0, and a phase control unit utilizes integration-deintegration double stages in an integration stage. Phase signals are converted into high and low levels through a comparator so as to control overturning of a capacitor CF pole plate, the digital processing unit carries out phase sampling counting at 0 degree and 180 degrees, the capacitance value is calculated according to the ratio of the number of integration cycles to the number of deintegration half cycles, the influence of stray capacitance is reduced, and the measurement precision is improved.

Description

Technical Field

[0001] This invention relates to the field of capacitance detection circuit technology, and more specifically, to a capacitance digital conversion circuit based on phase-sensitive integration. Background Technology

[0002] In fields such as precision measurement and industrial inspection, the changes in capacitance under test are extremely small, potentially reaching the picofarad level or even lower. Therefore, capacitance detection circuits are needed to capture these minute capacitance changes. Capacitance detection technology converts the capacitance value into an observable and measurable signal form, such as voltage, charge, or frequency, to achieve accurate capacitance value detection. To accurately reflect the slight capacitance changes, a biased AC signal is usually introduced as a reference.

[0003] Miniature capacitive sensors (at the millimeter or micrometer level) have been widely used in aerospace, medical, and mechanical manufacturing fields. Meanwhile, weak capacitance detection circuits are also widely used in various sensors, such as micro-accelerometers, micro-gyroscopes, and micro-pressure sensors.

[0004] Currently, weak capacitance detection circuits are susceptible to stray capacitance (picofarad level), leading to increased measurement errors and making it difficult to meet the requirements of weak capacitance detection. In single-stage integrator circuits, the error of the reference capacitor accumulates in the measurement results, resulting in decreased accuracy. At the same time, fluctuations in the amplitude of the excitation signal also affect the conversion accuracy. Therefore, we propose a capacitance digital conversion circuit based on phase-sensitive integration. Summary of the Invention

[0005] The purpose of this invention is to solve the problem that weak capacitance detection circuits are easily affected by stray capacitance (picofarad level), which leads to increased measurement error and makes it difficult to meet the requirements of weak capacitance detection. In single-stage integration circuits, the error of the reference capacitor will accumulate in the measurement result, resulting in decreased accuracy. At the same time, fluctuations in the amplitude of the excitation signal will also affect the conversion accuracy.

[0006] To achieve the above objectives, the present invention provides a capacitance-to-digital converter circuit based on phase-sensitive integral, comprising a phase-shifting circuit unit, a capacitance detection unit, a phase control unit, and a digital processing unit. The phase-shifting circuit unit is connected to the capacitance detection unit, the capacitance detection unit is connected to the phase control unit, and the phase control unit is connected to the digital processing unit.

[0007] A sinusoidal excitation signal is generated by a microcontroller. The phase-shifting circuit unit converts the excitation signal into an excitation signal that is 90 degrees ahead. The capacitance detection unit controls the single-pole double-throw switch S1 to alternately connect the excitation signal and the inverted signal to the capacitor under test Cx and the reference capacitor C0. During the integration phase, the phase control unit uses the inverted signal to make the currents flowing through the capacitor under test Cx and the reference capacitor C0 in phase and superimpose them to charge the capacitor CF. During the de-integration phase, it switches to the original signal to make the currents cancel each other out and discharge. The phase signal is converted into high and low levels by a comparator to control the flipping of the capacitor CF plates. The digital processing unit samples and counts the phases at 0 degrees and 180 degrees and calculates the capacitance value based on the ratio of the number of integration cycles to the number of half-cycles of de-integration.

[0008] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0009] 1. This phase-sensitive integral-based capacitor digital conversion circuit uses a phase control unit with a two-stage phase-sensitive integral mechanism of "integration-deintegration". During the integration stage, the charge of the capacitor under test Cx and the reference capacitor C0 is accumulated. During the deintegration stage, the influence of the reference C0 is canceled. The capacitor under test Cx is directly calculated through the charge difference, thus eliminating the problem of reference capacitor Cx error accumulation. At the same time, the digital processing unit uses the ratio of the number of integration cycles to the number of half-cycles of deintegration to calculate the capacitance value, thus canceling the influence of excitation signal amplitude fluctuation.

[0010] 2. The phase-shifting circuit unit utilizes the "virtual short and virtual open" characteristics of the operational amplifier and combines RC parameter matching design to achieve a fixed 90-degree phase shift without the need for a complex phase detection circuit, reducing the number of components. Throughout the entire operation of the circuit, capacitor Cp2 is always connected to the virtual ground of operational amplifier A4 and will not affect the output of operational amplifier A4. The final output is insensitive to stray capacitors Cp1 and Cp2, which has good engineering benefits for accurate measurement of capacitance sensors.

[0011] As a further improvement to this technical solution, the phase-shifting circuit unit includes a phase-shifting circuit, wherein the phase-shifting circuit includes an operational amplifier A3 and a capacitor C1;

[0012] Pin 2 of the operational amplifier A3 is connected to one end of resistor R1 and one end of resistor R2. The other end of resistor R1 is connected to the input excitation signal UI and one end of capacitor C1. Pin 3 of the operational amplifier A3 is connected to the other end of capacitor C1 and one end of resistor R3. The other end of resistor R3 is grounded. Pin 1 of the operational amplifier A3 is connected to the other end of resistor R2.

[0013] As a further improvement to this technical solution, the phase-shifting circuit unit utilizes the virtual short and virtual open characteristics of operational amplifier A3, combined with an RC matching resistor network, to simplify the phase-shifting circuit.

[0014] The beneficial effect of the above-mentioned further improvement is that the phase-sensitive integral requires a 90-degree phase difference (orthogonality) between the reference signal and the measured signal to achieve selective response to signals with a specific phase. When the reference signal leads the excitation signal by 90 degrees, the circuit only responds to the component that is in phase and frequency with the excitation signal, while suppressing interference signals of other frequencies or phases.

[0015] As a further improvement to this technical solution, the capacitance detection unit includes a capacitance detection circuit, wherein the capacitance detection circuit includes operational amplifier A1, operational amplifier A2, comparator OC1, and comparator OC2;

[0016] Pin 2 of operational amplifier A1 is connected to one end of resistor R4 and one end of resistor R5. Pin 1 of operational amplifier A1 is connected to the other end of resistor R5, and one end of reference capacitor C0 and one end of single-pole double-throw switch S1. The other end of reference capacitor C0 is connected to one end of capacitor Cx under test and one end of single-pole double-throw switch S2. The other end of capacitor Cx under test is connected to the other end of single-pole double-throw switch S1. The other end of single-pole double-throw switch S2 is connected to capacitor CF. The other end of capacitor CF is connected to one end of single-pole double-throw switch S3. The other end of single-pole double-throw switch S1 is connected to pin 2 of operational amplifier A2. Pin 1 of operational amplifier A2 is connected to pin 3 of comparator OC2. Pin 2 of comparator OC1 is connected to the output of phase-shifting circuit.

[0017] As a further improvement to this technical solution, the capacitor detection unit is connected to a comparator OC1 at the output of the phase shift circuit, which converts the excitation signal that is 90 degrees ahead into high and low levels with different phases. By setting the single-pole double-throw switch S2 and single-pole double-throw switch S3 to positions 1 and 0 with phases of 90 degrees and 270 degrees respectively, the plates of capacitor CF are switched between the inverting input and output of operational amplifier A2.

[0018] The beneficial effects of the above-mentioned further improvements are that, through strictly synchronized switching actions, charge accumulation and release are performed only on the target signal that is in phase and frequency with the excitation signal, effectively suppressing the influence of stray capacitance and inter-frequency interference; at the same time, periodic integration-discharge cycles are achieved by switching plates to ensure that the charge change is linearly related to the capacitance value under test. Combined with subsequent counting and ratio calculation, high-precision measurement of picofarad level capacitance can be achieved without a high-precision A / D converter, which simplifies the circuit structure, reduces costs, and improves the anti-interference capability and stability of the measurement.

[0019] As a further improvement to this technical solution, during the integration phase, the phase control unit sets the single-pole double-throw switch S1 to a low level, the analog switch selection position to 0, and is excited by the inverted excitation signal. The current flowing through the capacitor under test Cx and the reference capacitor C0 are superimposed in phase to charge the capacitor CF, forming a voltage increment.

[0020] As a further improvement to this technical solution, during the deintegration stage, the phase control unit switches the selection terminal of the single-pole double-throw analog switch S1 to a high level, the analog switch selection position is 1, the original excitation signal flows through the capacitor under test Cx, the current flowing through the capacitor under test Cx cancels out the current of the reference capacitor C0, and discharges the capacitor CF to form a voltage increment.

[0021] As a further improvement to this technical solution, the phase control unit sets the capacitance value of the reference capacitor C0 to be smaller than that of the capacitor under test Cx, and the capacitance value of the capacitor CF to be larger than that of the capacitor under test Cx, thereby maintaining the linear relationship between the voltage change and the capacitor under test Cx during the integration process.

[0022] The beneficial effect of the above-mentioned further improvements is that, through a two-stage charge accumulation and cancellation mechanism, the inherent error of the reference capacitor is accurately separated and eliminated, retaining only the effective signal related to the capacitor under test. In the integration stage, an inverted signal is used to superimpose the currents of the capacitor under test and the reference capacitor in phase, achieving charge accumulation and obtaining the total charge containing the capacitance values ​​of both. In the de-integration stage, the original signal is switched back to cancel the currents in phase, and the value of the capacitor under test is directly calculated through the charge difference, effectively avoiding the accumulation of reference capacitor errors.

[0023] As a further improvement to this technical solution, the digital processing unit includes a stray capacitor circuit, wherein the stray capacitor circuit includes an operational amplifier A4;

[0024] Pin 2 of the operational amplifier A4 is connected to one end of resistor ZF, and in turn to one end of capacitor C2 and one end of capacitor Cp2. The other end of capacitor C2 is connected to one end of capacitor Cp1. The other end of capacitor Cp1 is grounded, and the other end of capacitor Cp2 is grounded. Pin 1 of the operational amplifier A4 is connected to the other end of resistor ZF.

[0025] As a further improvement to this technical solution, the digital processing unit calculates the capacitance value using the ratio of the number of integration cycles to the number of half-cycles of deintegration.

[0026] The beneficial effects of the above-mentioned further improvements are that they can effectively eliminate interference from factors such as excitation signal amplitude fluctuations and power supply drift, because the number of cycles in both stages is related to the characteristics of the excitation signal, and their ratio can offset these common effects, significantly improving measurement stability; at the same time, this method converts the capacitance value into a counting ratio of time quantities, achieving picofarad-level resolution without the need for a high-precision A / D converter.

[0027] In addition to the objectives, features, and advantages described above, the present invention has other objectives, features, and advantages. The invention will now be described in further detail with reference to the figures. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the overall process of the present invention;

[0029] Figure 2 This is a phase-shifting circuit diagram of the present invention;

[0030] Figure 3 This is a circuit diagram of the capacitance detection circuit of the present invention;

[0031] Figure 4 This is a circuit diagram of the stray capacitor of the present invention;

[0032] Figure 5 This is a schematic diagram of the workflow of the present invention;

[0033] Figure 6 The figure shows the results when the capacitance under test is 94.20pF.

[0034] The meanings of the labels in the diagram are as follows:

[0035] 100. Phase shifting circuit unit; 200. Capacitor detection unit; 300. Phase control unit; 400. Digital processing unit. Detailed Implementation

[0036] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] Currently, weak capacitance detection circuits are susceptible to stray capacitance (picofarad level), which increases measurement error and makes it difficult to meet the requirements of weak capacitance detection. In single-stage integration circuits, the error of the reference capacitor will accumulate in the measurement result, resulting in a decrease in accuracy. At the same time, fluctuations in the amplitude of the excitation signal will also affect the conversion accuracy.

[0038] Therefore, this invention proposes a method in which the excitation signal is converted into an excitation signal leading by 90 degrees by a phase-shifting circuit unit, the capacitance detection unit controls the single-pole double-throw switch S1 to alternately connect the excitation signal and the inverted signal to the capacitor under test Cx and the reference capacitor C0, the phase control unit uses the integration-de-integration dual-stage to convert the phase signal into high and low levels through a comparator to control the flipping of the capacitor CF plate, and the digital processing unit samples and counts the phase at 0 degrees and 180 degrees, and calculates the capacitance value based on the ratio of the number of integration cycles to the number of half-cycles of de-integration.

[0039] Specifically as follows:

[0040] Please see Figure 1As shown, the present invention provides a capacitor-to-digital converter circuit based on phase-sensitive integral, including a phase-shifting circuit unit 100, a capacitor detection unit 200, a phase control unit 300, and a digital processing unit 400. The phase-shifting circuit unit 100 is connected to the capacitor detection unit 200, the capacitor detection unit 200 is connected to the phase control unit 300, and the phase control unit 300 is connected to the digital processing unit 400.

[0041] A sinusoidal excitation signal is generated by a microcontroller. The phase-shifting circuit unit 100 uses the phase-shifting circuit to convert the excitation signal into an excitation signal that is 90 degrees ahead. The capacitance detection unit 200 controls the single-pole double-throw switch S1 to alternately connect the excitation signal and the inverted signal to the capacitor under test Cx and the reference capacitor C0. During the integration phase, the phase control unit 300 uses the inverted signal to make the current flowing through the capacitor under test Cx and the reference capacitor C0 in phase and superimpose them to charge the capacitor CF. During the de-integration phase, it switches to the original signal to make the current cancel out and discharge. The phase signal is converted into high and low levels by a comparator to control the flipping of the capacitor CF plate. The digital processing unit 400 samples and counts the phase at 0 degrees and 180 degrees and calculates the capacitance value based on the ratio of the number of integration cycles to the number of half-cycles of de-integration.

[0042] like Figure 2 As shown, the phase-shifting circuit unit 100 includes a phase-shifting circuit, which includes an operational amplifier A3 and a capacitor C1.

[0043] Pin 2 of operational amplifier A3 is connected to one end of resistor R1 and one end of resistor R2. The other end of resistor R1 is connected to the input excitation signal UI and one end of capacitor C1. Pin 3 of operational amplifier A3 is connected to the other end of capacitor C1 and one end of resistor R3. The other end of resistor R3 is grounded. Pin 1 of operational amplifier A3 is connected to the other end of resistor R2.

[0044] In this circuit, operational amplifier A3 forms a non-inverting amplification structure. The input excitation signal UI passes through a high-pass filter network composed of capacitor C1 and resistor R3, forming a specific phase signal at the non-inverting input (pin 3) of A3. At the same time, the inverting input (pin 2) of operational amplifier A3 introduces feedback through resistor R1, and resistor R2 forms a negative feedback loop to stabilize the gain.

[0045] The signal is amplified by operational amplifier A3. By utilizing the capacitive reactance of capacitor C1 and the impedance of resistor, the output signal Up is phase-shifted relative to the input UI. By properly selecting the parameters R1, R2, R3, and C1, a phase shift function of a specific angle (90°) can be achieved to meet the circuit's requirements for signal phase adjustment.

[0046] In order to better simplify the phase-shifting circuit, the phase-shifting circuit unit 100 utilizes the virtual short and virtual open characteristics of the operational amplifier A3, combined with an RC matching resistor network, to simplify the phase-shifting circuit.

[0047] By utilizing the virtual short (voltages at the non-inverting and inverting inputs are approximately equal) and virtual open (current flowing into the input is approximately zero) characteristics of operational amplifier A3, and matching an RC network, selecting resistor R1 equal to resistor R2, and ensuring that resistor R3 satisfies R3 = ωC1 (ω is the signal angular frequency), the phase-shifting circuit structure is simplified. The frequency characteristics of the RC network are used to make the output phase shift 90° relative to the input, reducing components, eliminating the need for calibration, lowering cost and PCB area, and improving stability.

[0048] like Figure 3 As shown, the capacitance detection unit 200 includes a capacitance detection circuit, which includes operational amplifier A1, operational amplifier A2, comparator OC1, and comparator OC2.

[0049] Pin 2 of operational amplifier A1 is connected to one end of resistor R4 and one end of resistor R5. Pin 1 of operational amplifier A1 is connected to the other end of resistor R5, and one end of reference capacitor C0 and one end of single-pole double-throw switch S1. The other end of reference capacitor C0 is connected to one end of capacitor Cx under test and one end of single-pole double-throw switch S2. The other end of capacitor Cx under test is connected to the other end of single-pole double-throw switch S1. The other end of single-pole double-throw switch S2 is connected to capacitor CF. The other end of capacitor CF is connected to one end of single-pole double-throw switch S3. The other end of single-pole double-throw switch S1 is connected to pin 2 of operational amplifier A2. Pin 1 of operational amplifier A2 is connected to pin 3 of comparator OC2. Pin 2 of comparator OC1 is connected to the output of phase-shifting circuit.

[0050] In this circuit, the sinusoidal excitation signal VS is processed by the phase shifting circuit and then input to comparator OC1. Comparator OC1 outputs a phase signal, which, combined with the control logic, drives comparator OC2.

[0051] Operational amplifier A1, along with resistors R4 and R5, forms an amplification path to initially amplify the signal containing information about the capacitor Cx under test. Switch S1 is used to switch the connection state of Cx. Operational amplifier A2, in conjunction with switches S2 and S3 and reference capacitors C0 and CF, uses the level control of different phases of the excitation signal to switch the switches based on the principles of charge transfer and integration. This causes the CF plate to switch between the inverting input and output of operational amplifier A2, realizing the integration and de-integration process of the charge related to Cx under test. Finally, by detecting the output of operational amplifier A2 and the comparator logic, the capacitance value is converted into a measurable electrical signal change, thus completing the detection of the capacitor Cx under test.

[0052] In order to better switch the plates of capacitor CF, the capacitor detection unit 200 is connected to comparator OC1 at the output of the phase shift circuit, which converts the excitation signal with a 90-degree lead into high and low levels with different phases. By setting single-pole double-throw switch S2 and single-pole double-throw switch S3 to positions 1 and 0 with phases of 90 degrees and 270 degrees respectively, the plates of capacitor CF are switched between the inverting input and output of operational amplifier A2.

[0053] The response signal current from the connection point of the capacitor under test and the reference capacitor flips the phase of the excitation current at 90° and 270°, charging capacitor CF in a phase-dependent manner. The input signal is connected to a 90° phase-shifting circuit, and then to a comparator OC1 with its inverting input grounded. This produces a high / low level with a phase of 0 to 90° and 270 to 360°, and a low / high level with a phase of 90 to 270°. These high and low levels are then passed to a two-to-one analog switch. By setting switches S2 and S3 to positions 1 and 0 for 90° and 270° phases respectively, the plates of CF are switched between the inverting input and output of operational amplifier A2. The time interval between phases 90° and 270° is labeled T1, and the time interval between phases 270° and 90° is labeled T2.

[0054] In order to better calculate the voltage increment during the integration phase, the phase control unit 300 sets the single-pole double-throw switch S1 to a low level and the analog switch to position 0 during the integration phase. The current flowing through the capacitor under test Cx and the reference capacitor C0 are superimposed in phase to charge the capacitor CF, forming the voltage increment.

[0055] During integration, the select terminal of the single-pole double-throw analog switch S1 is set to low level, the analog switch select position is 0, and it is excited by the inverted excitation signal. This makes the current signals flowing through the capacitor under test Cx and the reference capacitor C0 in phase. The operational amplifier is in deep negative feedback, and the currents flowing through the capacitor under test and the reference capacitor flow together through capacitor CF. ICX + IC0 = ICF. During the T1 period from 90° to 270° phase, the increment of VOA2 caused by ICX is 2VSCX / CF. Similarly, the increment of VOA2 caused by IC0 is 2VSC0 / CF.

[0056] During the T2 period, from 270° to 90° of the next cycle, the increment of VOA2 caused by ICX is -2VSCX / CF, and similarly, the increment of VOA2 caused by ICX is -2VSC0 / CF. Therefore, the incremental voltage change over one AC cycle during the integration process is:

[0057]

[0058] The net increment of voltage VOA2 during the continuous integration process over the set AC excitation N1 cycles is as follows:

[0059] point

[0060]

[0061] in, The net voltage increment, V S Where N is the input voltage, N1 is the number of cycles, and C is the input voltage. x C is the capacitor under test, C0 is the reference capacitor, and C... F It is a flip capacitor.

[0062] In order to better calculate the voltage increment during the deintegration stage, the phase control unit 300 switches the selection terminal of the single-pole double-throw analog switch S1 to a high level during the deintegration stage. The selection position of the analog switch is 1, the original excitation signal flows through the capacitor under test Cx, and the current flowing through the capacitor under test Cx cancels out the current of the reference capacitor C0, discharging the capacitor CF and forming the voltage increment.

[0063] By switching the selection terminal of the single-pole double-throw analog switch S1 to high level, the analog switch selection position is 1, the original excitation signal of the capacitor under test, the current flowing through the reference capacitor C0 is out of phase with the current flowing through the capacitor under test Cx, and the phase-sensitive integration process uses ICX-IC0 to charge the capacitor CF.

[0064] The measured capacitance value Cx is larger than the reference capacitance value C0. During the T1 period from 90° to 270°, the increment of VOA2 caused by ICX is -2VSCX / CF, the potential is positive, the integral is negative, and the absolute value decreases; the increment of VOA2 caused by ICX is 2VSCX / CF.

[0065] During T2, from 270° to 90° of the next cycle phase, the increment of VOA2 caused by ICX is 2VSCX / CF; the increment of VOA2 caused by ICO is -2VSC0 / CF, with negative potential and positive integral. The comparator OC2 output remains high during sampling at T1, incrementing count N1; it remains low during sampling at T2, incrementing count N2.

[0066] By observing that comparator OC2 is low during period T1 and high during period T2, the logic control unit detects the end of the entire process, disables the timer, and stops generating waveforms. The number of half-cycles of AC excitation used for de-integration is determined by the control chip reading the voltage at 0° and 180° phases, and counted as N2. During the de-integration process, the voltage change in one AC cycle is 4|VS|(C0-CX) / CF. After N2 half-cycles at the end of the entire process, the change in VOA2 is...

[0067]

[0068] In order to better maintain the linear relationship between the voltage change and the measured capacitor Cx, the phase control unit 300 sets the capacitance value of the reference capacitor C0 to be smaller than that of the measured capacitor Cx, and the capacitance value of the capacitor CF to be larger than that of the measured capacitor Cx, thereby maintaining the linear relationship between the voltage change and the measured capacitor Cx during the integration process.

[0069] After the excitation signal is processed, the capacitor under test (Cx) and the reference capacitor (C0) participate in charge transfer. Since the reference capacitor (C0) < Cx, its interference with charge distribution is small, and the main charge change is dominated by the capacitor under test (Cx). When the capacitor (CF) > Cx, the charge change ΔQ caused by the capacitor under test (Cx) can maintain good linearity with the voltage change ΔV of the capacitor under test (Cx) under a large capacitance value (CF). This allows the voltage change during integration to stably reflect the size of the capacitor under test (Cx), improving the detection linearity and accuracy. It also enables a small capacitance change to correspond to a measurable linear voltage output, which is convenient for subsequent signal processing and capacitance value calculation.

[0070] like Figure 4 As shown, the digital processing unit 400 includes a stray capacitor circuit, wherein the stray capacitor circuit includes an operational amplifier A4;

[0071] Pin 2 of operational amplifier A4 is connected to one end of resistor ZF, and then to one end of capacitor C2 and one end of capacitor Cp2. The other end of capacitor C2 is connected to one end of capacitor Cp1. The other end of capacitor Cp1 is grounded, and the other end of capacitor Cp2 is grounded. Pin 1 of operational amplifier A4 is connected to the other end of resistor ZF.

[0072] In this circuit, operational amplifier A4 forms a feedback amplification structure. The input signal UI is transmitted to the inverting input (pin 2) of operational amplifier A4 via capacitor C2. Due to their distributed characteristics, stray capacitors Cp1 and Cp2 are connected in parallel between the signal path and ground, which will have an additional capacitive effect on the signal. Based on the virtual short (pin 3 of the non-inverting input is grounded, and pin 2 of the inverting input is approximately at ground potential) and virtual open (the input current is approximately zero) characteristics of A4, the signal current mainly forms a loop through capacitor C2 and feedback impedance Zf. By detecting the signal at the output (pin 1) of A4, the phase and amplitude changes caused by stray capacitors Cp1 and Cp2 during signal transmission can be analyzed, and the interference of stray capacitors on the circuit can be evaluated.

[0073] In order to better calculate the capacitance value, the digital processing unit 400 uses the ratio of the number of integration cycles to the number of half-cycles of deintegration to calculate the capacitance value.

[0074] Converting capacitance values ​​into time-based counting ratios achieves picofarad-level resolution without the need for high-precision A / D converters, simplifying circuit structure and reducing costs. Furthermore, the ratio calculation relies solely on the inherent characteristics of the capacitor itself. Combined with phase synchronization control, stray capacitance interference can be suppressed, and the calculation can be performed quickly using integer operations. This effectively eliminates interference from factors such as excitation signal amplitude fluctuations and power supply drift, as the number of cycles in both stages is related to the characteristics of the excitation signal. The ratio can offset these common effects, significantly improving measurement stability.

[0075] like Figure 5 As shown, the main control chip first enables the timer to generate a signal. At this time, the selection terminal of switch S1 is at a low level, and the absolute value of the output increases linearly. Then, the main control chip switches the selection terminal of switch S1 to a high level after a certain time interval, and the absolute value of the output decreases linearly. During the process, it continuously judges whether OC2 outputs high during T1 or low during T2, and increments the count by one until the condition is no longer met. Finally, the count is incremented by one, the counting stops, and the timer is disabled.

[0076] For example, the experimental parameters are as follows:

[0077]

[0078]

[0079] like Figure 6 As shown, when the capacitance under test is 94.60pF, the output waveform of operational amplifier OA3 shows that the number of half-cycles N2 read by the microcontroller is 3220, and the calculated capacitance value is 95.00pF, with an error of 0.42%. This demonstrates that the proposed digital capacitance conversion circuit is accurate and reliable in detecting weak capacitance. The main reasons for the error are: zero-point offset of the operational amplifier, output even without an input signal, and shunt resistance in the capacitance sensor, which increases the actual output of the differentiating circuit.

[0080] In summary, the working principle of this solution is as follows:

[0081] This phase-sensitive integral-based capacitance-to-digital converter circuit uses a phase control unit 300 with a two-stage phase-sensitive integral mechanism of "integration-deintegration". During the integration stage, the charge of the capacitor under test Cx and the reference capacitor C0 is accumulated. During the deintegration stage, the influence of the reference C0 is canceled. The capacitor under test Cx is directly calculated through the charge difference, thus eliminating the problem of reference capacitor Cx error accumulation. At the same time, the digital processing unit 400 uses the ratio of the number of integration cycles to the number of half-cycles of deintegration to calculate the capacitance value, thus canceling the influence of excitation signal amplitude fluctuation.

[0082] The phase-shifting circuit unit 100 utilizes the "virtual short and virtual open" characteristics of the operational amplifier and combines RC parameter matching design to achieve a fixed 90-degree phase shift without the need for a complex phase detection circuit, reducing the number of components. Throughout the entire operation of the circuit, capacitor Cp2 is always connected to the virtual ground of operational amplifier A4 and will not affect the output of operational amplifier A4. The final output is insensitive to stray capacitors Cp1 and Cp2, which has good engineering benefits for accurate measurement of capacitance sensors.

[0083] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A capacitor-to-digital converter circuit based on phase-sensitive integration, characterized in that: It includes a phase shifting circuit unit (100), a capacitance detection unit (200), a phase control unit (300), and a digital processing unit (400). The phase shifting circuit unit (100) is connected to the capacitance detection unit (200), the capacitance detection unit (200) is connected to the phase control unit (300), and the phase control unit (300) is connected to the digital processing unit (400). A sinusoidal excitation signal is generated by a microcontroller. The phase-shifting circuit unit (100) uses the phase-shifting circuit to convert the excitation signal into an excitation signal that is 90 degrees ahead. The capacitor detection unit (200) controls the single-pole double-throw switch S1 to alternately connect the excitation signal and the inverted signal to the capacitor under test Cx and the reference capacitor C0. The phase control unit (300) uses the inverted signal during the integration phase to make the current flowing through the capacitor under test Cx and the reference capacitor C0 in phase and superimpose them to charge the capacitor CF. During the de-integration phase, it switches to the original signal to make the current cancel out and discharge. The phase signal is converted into high and low levels by the comparator to control the flipping of the capacitor CF plate. The digital processing unit (400) samples and counts the phase at 0 degrees and 180 degrees and calculates the capacitance value according to the ratio of the number of integration cycles to the number of half-cycles of de-integration.

2. The capacitor-to-digital converter circuit based on phase-sensitive integral as described in claim 1, characterized in that: The phase-shifting circuit unit (100) includes a phase-shifting circuit, wherein the phase-shifting circuit includes an operational amplifier A3 and a capacitor C1; Pin 2 of the operational amplifier A3 is connected to one end of resistor R1 and one end of resistor R2. The other end of resistor R1 is connected to the input excitation signal UI and one end of capacitor C1. Pin 3 of the operational amplifier A3 is connected to the other end of capacitor C1 and one end of resistor R3. The other end of resistor R3 is grounded. Pin 1 of the operational amplifier A3 is connected to the other end of resistor R2.

3. The capacitor-to-digital converter circuit based on phase-sensitive integral as described in claim 2, characterized in that: The phase-shifting circuit unit (100) utilizes the virtual short and virtual open characteristics of the operational amplifier A3, combined with an RC matching resistor network, to simplify the phase-shifting circuit.

4. The capacitor-to-digital converter circuit based on phase-sensitive integral as described in claim 1, characterized in that: The capacitance detection unit (200) includes a capacitance detection circuit, wherein the capacitance detection circuit includes operational amplifier A1, operational amplifier A2 and comparator OC1 and comparator OC2; Pin 2 of operational amplifier A1 is connected to one end of resistor R4 and one end of resistor R5. Pin 1 of operational amplifier A1 is connected to the other end of resistor R5, and one end of reference capacitor C0 and one end of single-pole double-throw switch S1. The other end of reference capacitor C0 is connected to one end of capacitor Cx under test and one end of single-pole double-throw switch S2. The other end of capacitor Cx under test is connected to the other end of single-pole double-throw switch S1. The other end of single-pole double-throw switch S2 is connected to capacitor CF. The other end of capacitor CF is connected to one end of single-pole double-throw switch S3. The other end of single-pole double-throw switch S1 is connected to pin 2 of operational amplifier A2. Pin 1 of operational amplifier A2 is connected to pin 3 of comparator OC2. Pin 2 of comparator OC1 is connected to the output of phase-shifting circuit.

5. The capacitor-to-digital converter circuit based on phase-sensitive integral as described in claim 1, characterized in that: The capacitor detection unit (200) is connected to comparator OC1 at the output of the phase shift circuit. It converts the excitation signal that is 90 degrees ahead into high and low levels with different phases. By setting single-pole double-throw switch S2 and single-pole double-throw switch S3 to positions 1 and 0 with phases of 90 degrees and 270 degrees respectively, the plates of capacitor CF are switched between the inverting input and output of operational amplifier A2.

6. The capacitor-to-digital converter circuit based on phase-sensitive integral as described in claim 1, characterized in that: During the integration phase, the phase control unit (300) sets the selection terminal of the single-pole double-throw switch S1 to a low level, and the analog switch selection position is 0. It is excited by the inverse excitation signal, and the current flowing through the capacitor under test Cx and the reference capacitor C0 are superimposed in phase to charge the capacitor CF, forming a voltage increment.

7. The capacitor-to-digital converter circuit based on phase-sensitive integral as described in claim 1, characterized in that: During the deintegration phase, the phase control unit (300) switches the selection terminal of the single-pole double-throw analog switch S1 to a high level, and the analog switch selection position is 1. The original excitation signal flows through the capacitor under test Cx. The current flowing through the capacitor under test Cx cancels out the current of the reference capacitor C0, and discharges the capacitor CF to form a voltage increment.

8. The capacitor-to-digital converter circuit based on phase-sensitive integral as described in claim 1, characterized in that: The phase control unit (300) maintains a linear relationship between the voltage change and the capacitor Cx under test during the integration process by setting the capacitance value of the reference capacitor C0 to be smaller than that of the capacitor Cx under test, and the capacitance value of the capacitor CF to be larger than that of the capacitor Cx under test.

9. The capacitor-to-digital converter circuit based on phase-sensitive integral as described in claim 1, characterized in that: The digital processing unit (400) includes a stray capacitance circuit, wherein the stray capacitance circuit includes an operational amplifier A4; Pin 2 of the operational amplifier A4 is connected to one end of resistor ZF, and in turn to one end of capacitor C2 and one end of capacitor Cp2. The other end of capacitor C2 is connected to one end of capacitor Cp1. The other end of capacitor Cp1 is grounded, and the other end of capacitor Cp2 is grounded. Pin 1 of the operational amplifier A4 is connected to the other end of resistor ZF.

10. The capacitor-to-digital converter circuit based on phase-sensitive integral as described in claim 1, characterized in that: The digital processing unit (400) calculates the capacitance value using the ratio of the number of integration cycles to the number of half-cycles of deintegration.

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