Control device with serial port communication

Abstract

The invention relates to a control device with serial port communication, and belongs to the technical field of computer communication. The serial communication circuit is expanded through the main control module and the serial transceiver chip. The n IO pins in the main control module are used for serial port receiving, and the other n IO pins are used for transmitting and receiving enabling and are respectively connected with the enabling pins of the serial port transmitting and receiving chip, so that the main control module can switch the transmitting / receiving state of the serial port transmitting and receiving chip, and the switching is more convenient. DI pins of the serial port transceiving chips are connected with TXD pins of the main control module, in the process that the main control module receives data, RO pins of the serial port transceiving chips are connected with serial port receiving IO pins and timer channel pins of the main control module, and the received data are stored in corresponding registers; the main control module uses a TXD pin to send data to the outside, the process operation is simple and convenient, and based on the reliability of the main control module and the serial port transceiver chip, the data receiving and sending process is safe.

Description

Technical Field

[0001] This invention relates to a control device with serial communication capability, belonging to the field of computer communication technology. Background Technology

[0002] Serial communication is widely used in power, industry, and other fields, covering aspects such as equipment control, equipment networking, and system integration. Many devices, such as relay protection devices, PLCs, industrial robots, and sensors, require serial communication to complete data acquisition and processing. Serial communication plays a crucial role between these devices and between devices and control systems, ensuring coordinated and efficient operation. With the development of the Internet of Things (IoT), the number of devices requiring serial communication in power, industry, and other fields is increasing, sometimes even requiring a single device to communicate with multiple devices simultaneously, such as a relay protection device connecting to multiple sensor devices.

[0003] Currently, UART (Universal Asynchronous Receiver Transmitter) is widely used as the serial port on CPU chips in existing technologies; for example... Figure 1 As shown, the basic UART serial communication circuit includes one serial transceiver chip and one CPU chip. The UART's receive pin RXD in the CPU is connected to the RO (Receive Output) pin of the serial transceiver chip, the UART's transmit pin TXD is connected to the DI (Data Input) pin of the serial transceiver chip, and the CPU's general-purpose I / O pins are connected to the DE (Data Enable) pin of the serial transceiver chip. (Receiver Enable) pin; the data enable pin DE is the transmit enable pin of the serial transceiver chip, active high; the receive enable pin... This is the receive enable pin for the serial transceiver chip; it is active low. When the serial data lines are idle, the UART receive pin RXD is high. The serial communication frame format is as follows: Figure 2 As shown, when the serial port starts receiving data, the UART receive pin RXD drops from high to low to indicate a start bit; followed by data bits, which can be configured to be 6, 7, or 8 bits as needed; after the data bits, there is a configurable parity bit; and finally, there is a high-level stop bit.

[0004] Because the UART serial communication resources on the CPU chip are limited, typically about 2 to 4 UARTs, they cannot meet the actual field serial communication requirements.

[0005] To address the limited resources of UART serial communication, existing technologies primarily employ two solutions: ① Expanding serial communication using dedicated chips, such as the CH9434 chip, which allows the CPU to extend four UART channels via SPI (Serial Peripheral Interface). ② Simulating the registers and other mechanisms in the serial port configuration module through FPGA reprogramming to deframe and store the received data. However, both methods have significant drawbacks: Method ①, using the expensive CH9434 chip, adds substantial costs and occupies limited space in the device; while Method ②, using high-performance chips like FPGA modules, involves high prices, complex algorithms, and difficult development, significantly increasing the costs of product design, development, and maintenance. Summary of the Invention

[0006] The purpose of this invention is to provide a control device with serial communication capabilities, thereby solving the problems of high design difficulty and high cost associated with adding UART serial communication to a CPU.

[0007] To achieve the above objectives, the present invention includes:

[0008] The control device with serial communication of the present invention includes a main control module and serial transceiver chips. The number of serial transceiver chips is n, which is the number of serial communication channels to be expanded. n IO pins in the main control module are used for serial port reception and are called serial port receive IO pins. The other n IO pins are used for transmit and receive enable and are called transmit and receive enable IO pins.

[0009] The enable pins of different serial transceiver chips are connected to different transmit / receive enable IO pins of the main control module, so that the main control module can change the transmit and receive states of the serial transceiver chips.

[0010] The DI pin of each serial transceiver chip is connected to the TXD pin of the main control module. Together with the transmit / receive enable IO pin, the corresponding serial transceiver chip is put into the transmit state, so that the TXD pin can send data through the corresponding serial transceiver chip.

[0011] The RO pins of different serial transceiver chips are connected to different serial port receive IO pins and corresponding timer channel pins of the main control module, so that the serial port receive IO pins store the data received by the serial transceiver chip in the receive state in the register corresponding to the serial port receive IO pin.

[0012] Furthermore, the RO pins of different serial transceiver chips are also connected to different timer channel pins of the main control module. The counting period of the timer is the time length for one data bit to be transmitted or received via the serial port. The comparison trigger value of the timer is less than this time length. One timer corresponds to one DMA channel. The timer is used to restart counting when the calculation period is reached, and it is also used to trigger the DMA channel corresponding to the timer to read the data in the data register of the serial port receive IO pin that is in the receiving state and put it into the buffer array corresponding to the data register when the comparison trigger value is reached.

[0013] Furthermore, the timer's comparison trigger value is half of the stated time length.

[0014] Furthermore, the DMA has a bus arbitration mechanism, which is as follows: when at least two DMA channels receive a trigger at the same time, the DMA will process each DMA channel in priority order according to the set priority.

[0015] Furthermore, each DMA channel is in cyclic mode, and the number of data read in one cycle is the sum of 2, the number of data bits, and the number of parity bits; when a parity bit is configured, the number of parity bits is 1, and when no parity bit is configured, the number of parity bits is 0.

[0016] Furthermore, the check bit is a parity check bit.

[0017] Furthermore, the serial transceiver chip used is the TPT487L1 serial transceiver chip.

[0018] Furthermore, the CPU is used as the main control module.

[0019] The beneficial effects of this invention are as follows:

[0020] The control device with serial communication of the present invention expands the serial communication circuit through a main control module and serial transceiver chips. The number of serial transceiver chips is n, which represents the number of serial communication ports to be expanded. Expansion based on serial transceiver chips is easy and highly expandable, and the related serial transceiver chips are inexpensive. n IO pins in the main control module for expanding serial communication are used as serial receive IO pins, and another n IO pins are used as transmit / receive enable IO pins and connected to the enable pins of the corresponding serial transceiver chips. This allows the main control module to switch the transmit / receive state of the corresponding serial transceiver chips through the transmit / receive enable IO pins, enabling real-time switching of the operating state of the serial transceiver chips as needed, and the switching process is relatively convenient. Each serial transceiver chip's DI pin is connected to the main control module's TXD pin. During data reception, the main control module connects the RO pins of different serial transceiver chips to the main control module's different serial port receive I / O pins and corresponding timer channel pins. This allows the serial transceiver I / O pins to store the data received by the receiving serial transceiver chip in the register corresponding to that pin. When the main control module needs to send data, it uses the transmit / receive enable I / O pin to put the corresponding serial transceiver chip into transmit mode. Data can then be sent externally via the TXD pin through the corresponding serial transceiver chip. The entire data reception / transmission process is simple and convenient, and based on the reliability of the main control module and the serial transceiver chips themselves, the data reception and transmission process is relatively safe. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the basic serial communication circuit in existing technology;

[0022] Figure 2 This is a schematic diagram of the serial communication frame format in the basic serial communication circuit of the prior art;

[0023] Figure 3 This is a schematic diagram showing the connection between multiple serial transceiver chips and CPU pins in the control device with serial communication of the present invention.

[0024] Figure 4 This is a schematic diagram of the data flow in the control device with serial communication according to the present invention;

[0025] Figure 5 This is a schematic diagram showing the connection between the CPU and four serial transceiver chips in the control device with serial communication of the present invention.

[0026] Figure 6 This is a schematic diagram of the data flow in the control device with serial communication of the present invention when the CPU is connected to four serial transceiver chips. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings.

[0028] The present invention is based on a serial communication control device comprising a main control module and a serial transceiver chip, extending serial communication based on a CPU and the serial transceiver chip. n IO pins in the main control module are used for serial reception and are referred to as serial receive IO pins, while another n IO pins are used for transmit / receive enable and are referred to as transmit / receive enable IO pins. The enable pin of the serial transceiver chip is connected to the corresponding transmit / receive enable IO pin of the main control module. The main control module switches the transmit / receive state of the serial transceiver chip according to its own data reception / transmission needs. The RO pins of different serial transceiver chips are connected to the corresponding serial receive IO pins and corresponding timer channel pins of the main control module. When receiving data, the serial transceiver IO pin stores the data received by the serial transceiver chip in the receive state in the register corresponding to that serial transceiver IO pin. The DI pin of each serial transceiver chip is connected to the TXD pin of the main control module. When transmitting data, the corresponding serial transceiver chip is put into the transmit state in conjunction with the transmit / receive enable IO pin, and the corresponding serial transceiver chip transmits data through the TXD pin.

[0029] An embodiment of a control device equipped with serial communication:

[0030] The CPU's built-in hardware DMA (Direct Memory Access) is characterized by its independent operation and non-CPU execution time. DMA is used to directly transfer data between CPU peripherals and memory. During the data transfer process, the data source address is set to a fixed address, and the destination address is set to the first address of the cache array. It can be set to automatic increment and first-end loop mode. The DMA interrupt can be triggered when the transfer is completed. It also has the characteristics of multi-channel conflict arbitration mechanism.

[0031] The CPU's built-in Timer has features such as a configurable timing period, the ability to be triggered by CPU pin I / O ports, and the ability to trigger DMA transfers via timer comparison events.

[0032] Based on Direct Memory Access (DMA), Timer, and combination Figure 1 , Figure 2 The description of the characteristics of UART serial communication, such as... Figure 3As shown, in this embodiment, the CPU's general-purpose I / O pins IO1 to IOn of the UART serial communication extension system based on timers and DMA are connected together (which can be considered as a parallel connection) with the corresponding timer1 to Timern pins of each I / O pin. These are then connected to the RO pins of multiple serial transceiver chips. The I / O pins IO1 to IOn are used for serial port reception and are referred to as the serial port receive pins, i.e., RXD1 to RXDn. The serial transceiver chips interact with external devices through pins A and B. The transmit enable pin DE and receive enable pin of the serial transceiver chip are connected... After being connected together (which can be considered a parallel connection), they are respectively connected to the CPU's general-purpose I / O pins IO11-IOn1. Pins IO11 to IOn1 are used as OE1 to OEn (Output Enable) pins (also known as transmit / receive enable I / O pins). After connecting the DI pins of multiple serial transceiver chips together (which can be considered a parallel connection), they are connected to the CPU's only UART transmit pin TXD (i.e., ... Figure 3 The UART TXD connection is used.

[0033] Simultaneously, the counting period of each timer is set to T, where T equals the time length for transmitting and receiving one data bit via the serial port; the comparison trigger value of each timer is set to t, where 0 < t < T, such as... Figure 4 As shown. Each DMA channel (DMACH1~DMA CHn) is set to cyclic mode, with N data reads, where N = 1 + X + Y + 1 (1 start bit, 1 stop bit), X is the configured number of data bits, and Y is the number of parity bits. Y = 1 when a parity bit is configured, and Y = 0 when no parity bit is configured. The source address for each DMA channel is set to the address of the data register on pins IO1~IOn, and this is a fixed address. The destination address for each DMA channel is set to the first address in arrays Buffer 1~Buffer n, and this is an auto-incrementing, first-position cyclic mode. An interrupt is triggered upon completion of the DMA transfer.

[0034] As a preferred implementation, the comparison trigger value t is set to T / 2.

[0035] The serial transceiver chip connects to the communication pins RS485_P and RS485_N of the external device via pins A and B, respectively, and reads the signals from them, namely RS485_1_P to RS485_n_P and RS485_1_N to RS485_n_N. After parsing, the serial transceiver chip sends the corresponding data stream to the CPU.

[0036] Under normal conditions, the transmit enable pin DE of the serial transceiver chip is at a low level, and the receive enable pin... When the serial transceiver is in a low-level state, meaning it's in receive mode and the data lines are idle, a falling edge of the start bit triggers a timer. When the timer reaches the comparison trigger value t, it triggers the DMA to read the corresponding CPU I / O port data register into the first bit of the corresponding buffer array. The DMA channel's destination address then automatically increments by one bit, pointing to the next bit in the buffer. After timer T, it restarts. When the timer reaches the comparison trigger value t again, it triggers the DMA to read the corresponding CPU I / O port data register into the corresponding buffer array again. This cycle of triggering the DMA continues until the DMA completes N data stream reads, triggering a DMA transfer completion interrupt. The interrupt function disables the timer and processes the data buffered in the buffer. At this point, the serial transceiver is in receive mode, the data lines are idle, and the DMA destination address is restored, pointing to the first bit of the buffer array. When data reception resumes, the falling edge of the start bit will again trigger the timer, and data will be buffered via DMA until the current data reception is complete.

[0037] In addition, DMA has a bus arbitration mechanism, which means that when multiple triggers are received at the same time, DMA will process them according to priority. For example, if the priorities of DMA CH1 to DMA CH4 are set to 0, 1, 2, and 3 respectively, the data in the DMA channel will be processed in the order of DMA CH1, DMA CH2, DMA CH3, and DMA CH4, so there is no need to worry about the problem of multiple channels receiving data at the same time.

[0038] When data needs to be sent, select the corresponding serial transceiver chip and set the corresponding transmit / receive enable pin OE of the CPU connected to that chip to a high level. At this time, the transmit enable pin DE of the serial transceiver chip is at a high level, and the receive enable pin... When the CPU's transceiver pin is high, it puts the serial transceiver chip in transmit mode, while the transmit / receive enable pins of other serial transceiver chips remain unchanged. Data is then sent to the serial transceiver chip via the CPU's UART transmit pin TXD and the serial transceiver chip's DI pin. The serial transceiver chip can then send the data to the external device normally. After transmission is complete, the CPU's transmit / receive enable pin OE changes from high to low, thus changing the serial transceiver chip from transmit mode to receive mode.

[0039] As one specific implementation, four UART serial ports are added to the CPU. The serial transceiver chip is model TPT487L1 and the number is set to four. The CPU uses a 32-bit microcontroller GD32F450. The transmission signal is set to 8 data bits, 1 even parity bit, and the signal baud rate is set to 19200.

[0040] like Figure 5 As shown, the receive pins RO of four TPT487L1 serial transceiver chips are connected to the IO pins PA1, PA2, PA3, and PA4 of the 32-bit microcontroller GD32F450, respectively, and then connected to the channel pins of Timer1, Timer2, Timer3, and Timer4, respectively. The transmit and receive enable pins of the TPT487L1 serial transceiver chips are connected to the IO pins PB1, PB2, PB3, and PB4 of the 32-bit microcontroller GD32F450, respectively. The transmit pins DI of the TPT487L1 serial transceiver chips are connected in parallel and then connected to the transmit pin TXD of UART1. Set IO pins PA1 to PA4 to input mode and IO pins PB1 to PB4 to output mode; set DMA to timer comparison event trigger, loop mode, read data number 11, that is, 1 start bit, 1 stop bit, 8 data bits, 1 parity bit; enable transmission completion interrupt, source address is fixed to the data register of pin PA, target address is set to auto-increment, and its first address is the address of the corresponding buffer array Buffer1[0], Buffer2[0], Buffer3[0], Buffer4[0].

[0041] Pins A and B of the four TPT487L1 serial port chips can also read the RS485_1_P~RS485_4_P signals and RS485_1_P~RS485_4_P signals input from external devices and parse them into data streams.

[0042] like Figure 6As shown, all timers are set to external trigger mode, with a timing period of 208us and a comparison duration of 104us. When the first serial transceiver chip TPT487L1 starts receiving data stream, the first falling edge on the receive pin RO triggers timer1 to start timing. When the counting duration reaches 125us, the timer triggers a comparison event, which triggers DMA channel 1 to read the data register of the PA pin and store the data in Buffer1[0]. Subsequently, the target address of DMA channel 1 automatically increments to point to Buffer1[1]. When the counting duration reaches 208us, timer1 is cleared and restarts timing. When the counting duration reaches 104us again, the data on the receive pin RO of the serial transceiver chip TPT487L1 has already become the data of the first data bit, and the timer triggers a comparison event again. This event then triggers DMA channel 1 to read the data register of the PA pin and store the data in Buffer1[1]. Subsequently, the target address of DMA channel 1 automatically increments to point to Buffer1[2]. Repeat the above steps until the DMA channel 1 transmits data to Buffer1

[10] for the 11th time, triggering a DMA transmission completion interrupt. In the interrupt function, Timer1 is turned off and the data in Buffer1[0] to Buffer1

[10] is processed. The target address of DMA channel 1 will also be redirected to Buffer1[0] due to the DMA's cyclic mode setting. After that, when the TPT487L1 serial transceiver chip detects a falling edge on the receive pin RO again, Timer1 will be triggered again, and the above process will be repeated until the reception of new data is completed.

[0043] Similarly, the data reception process of the other three TPT487L1 serial transceiver chips is the same as the data reception process described above, and will not be repeated here.

[0044] When multiple triggers are received simultaneously, the DMA will process the data in the DMA channel according to priority, so there is no need to worry about the problem of multiple channels receiving data at the same time.

[0045] When the 32-bit microcontroller GD32F450 needs to send data to an external device via a serial transceiver chip, taking the first TPT487L1 serial transceiver chip as an example: Set the transmit / receive enable pin PB1 of the 32-bit microcontroller GD32F450 connected to the first TPT487L1 serial transceiver chip to a high level, i.e., change from receive to transmit mode. At this time, the transmit enable pin DE on the first TPT487L1 serial transceiver chip is at a high level, and the receive enable pin... When the signal is high, the chip is in transmit mode, and the data input pin DI can receive data. Meanwhile, the other TPT487L1 serial transceiver chips have transmit enable pins DE and receive enable pins... The voltage level remains unchanged. At this time, data can only be sent through a serial transceiver chip with the transmit / receive enable pin PB1 in transmit mode, and then data can be sent through the conventional UART transmit pin TXD; after the transmission is completed, the transmit / receive enable pin PB1 changes from transmit mode to receive mode.

[0046] Similarly, the data transmission process of the other three TPT487L1 serial transceiver chips is the same as the data transmission process described above, and will not be repeated here.

[0047] The control device with serial communication of the present invention utilizes the characteristics of existing resources such as CPU and serial transceiver chip, and receives / sends data by connecting the serial port of CPU and serial transceiver chip, thereby extending UART serial communication, making full use of CPU and serial transceiver chip, and has the advantages of simple, stable and reliable implementation process, without adding extra cost.

Claims

1. A control device with serial communication capability, comprising a main control module and a serial transceiver chip, characterized in that, The number of serial transceiver chips is n, which is required to expand the number of serial communication channels; n IO pins in the main control module are used for serial port reception and are called serial port receive IO pins, and the other n IO pins are used for transmit / receive enable and are called transmit / receive enable IO pins; The enable pins of different serial transceiver chips are connected to different transmit / receive enable IO pins of the main control module, so that the main control module can change the transmit and receive states of the serial transceiver chips. The DI pin of each serial transceiver chip is connected to the TXD pin of the main control module. Together with the transmit / receive enable IO pin, the corresponding serial transceiver chip is put into the transmit state, so that the TXD pin can send data through the corresponding serial transceiver chip. The RO pins of different serial transceiver chips are connected to different serial port receive IO pins and corresponding timer channel pins of the main control module, so that the serial port receive IO pins store the data received by the serial transceiver chip in the receive state in the register corresponding to the serial port receive IO pin.

2. The control device with serial communication capability according to claim 1, characterized in that, The RO pins of different serial transceiver chips are also connected to different timer channel pins of the main control module. The counting period of the timer is the time length for one data bit to be transmitted or received via the serial port. The comparison trigger value of the timer is less than this time length. One timer corresponds to one DMA channel. The timer is used to restart counting when the calculation period is reached. It is also used to trigger the DMA channel corresponding to the timer to read the data from the data register of the serial port receive IO pin in the receiving state and put it into the buffer array corresponding to the data register when the comparison trigger value is reached.

3. The control device with serial communication capability according to claim 2, characterized in that, The timer's comparison trigger value is half of the stated time length.

4. The control device with serial communication capability according to claim 2, characterized in that, DMA has a bus arbitration mechanism, which is as follows: when at least two DMA channels receive a trigger at the same time, the DMA will process each DMA channel in priority order according to the set priority.

5. The control device with serial communication capability according to claim 4, characterized in that, Each DMA channel operates in cyclic mode, and the number of data read in a cycle is the sum of 2, the number of data bits, and the number of parity bits. When a parity bit is configured, the number of parity bits is 1; when no parity bit is configured, the number of parity bits is 0.

6. The control device with serial communication capability according to claim 5, characterized in that, The check bit is a parity check bit.

7. The control device with serial communication according to claims 1 to 6, characterized in that, The serial transceiver chip used is the TPT487L1.

8. The control device with serial communication according to claims 1 to 6, characterized in that, The CPU is used as the main control module.

Images