A signal layer exchange structure optimization method, device, medium and product suitable for a DDR5 printed circuit board

Abstract

The application discloses a signal layer exchange structure optimization method and device suitable for a DDR5 printed circuit board, equipment, medium and product, relates to the signal layer exchange structure optimization field, and the method comprises the following steps: obtaining the signal layer exchange structure of the DDR5 printed circuit board and target impedance values corresponding to surface layer traces and inner layer traces in the signal layer exchange structure; establishing an equivalent transmission line model according to basic structure parameters of the signal layer exchange structure in the vertical direction of the printed circuit board; performing time-domain reflection impedance simulation on the equivalent transmission line model in a transient solution mode to obtain actual impedance values; and adjusting the layer exchange conductor width in the signal layer exchange structure and the parallel distance between the layer exchange conductor and the vertical GND reference layer according to the difference between the actual impedance values and the target impedance values to obtain an optimized signal layer exchange structure. The application can improve the quality, stability and transmission characteristics of signal transmission.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of signal layer change structure optimization, in particular to a signal layer change structure optimization method, device, medium and product suitable for a DDR5 printed circuit board. BACKGROUND

[0002] Signal layer change technology is widely used in printed circuit board design. The traditional signal layer change structure adopts the principle of "similar coaxial cable". The signal line is introduced from the surface pad, connected to the inner layer pad by the via metal column, and then introduced to the inner layer trace, thereby realizing the layer change function of the signal on the transmission link. Although the traditional signal layer change technology makes it easier for engineers to work on device layout, interconnection design, link optimization, etc. However, due to the limitation of via structure, the traditional layer change structure is prone to cause capacitive and inductive effects in actual engineering applications, which affects the impedance of the link signal in the layer change area and affects the transmission quality.

[0003] In order to weaken the influence of impedance fluctuation, the traditional signal layer change structure usually optimizes the additional capacitive or inductive part by deleting non-functional pads, adjusting the size of the back pad and via metal column, using back drilling technology (removing the influence of via stub), adding reflow ground holes, etc., so as to reduce the impedance change range.

[0004] However, due to the existence of many highly dense signal layer change areas in high-speed printed circuit board design such as DDR5 (Memory Technology Overview), and the dense signal traces, the wiring space is very tight, so the above-mentioned traditional layer change structure has certain limitations, and its impedance adjustment method will also be limited.

[0005] In order to meet the requirements of JEDEC related protocol standards (JESD-308, JESD79-5) for DDR signal impedance, combined with the development trend of future DDR technology of higher speed, larger capacity, smaller size, etc., it is necessary to study the area with serious signal link impedance mutation (signal layer change).

[0006] Therefore, based on the above problems, it is necessary to provide a signal layer change structure that can improve the limitations of traditional signal vias, so that the signal realizes low impedance fluctuation and excellent transmission characteristics (Return Loss, Insertion Loss) in the vertical direction of the PCB, thereby realizing high-speed signal transmission with high quality. SUMMARY

[0007] The purpose of the present application is to provide a signal layer change structure optimization method, device, medium and product suitable for a DDR5 printed circuit board, which can improve the quality, stability and transmission characteristics of signal transmission.

[0008] To achieve the above object, the application provides the following scheme.

[0009] In a first aspect, the application provides a signal layer-changing structure optimization method suitable for a DDR5 printed circuit board, which comprises the following steps:

[0010] obtaining a signal layer-changing structure of a DDR5 printed circuit board and a target impedance value corresponding to a surface layer trace and an inner layer trace in the signal layer-changing structure;

[0011] establishing an equivalent transmission line model according to basic structural parameters of the signal layer-changing structure in a vertical direction of the printed circuit board;

[0012] performing time-domain reflection impedance simulation on the equivalent transmission line model in a transient solution mode to obtain an actual impedance value; the actual impedance value is a layer-changing impedance of a layer-changing conductor from the surface layer trace to the inner layer trace;

[0013] adjusting a width of the layer-changing conductor and a parallel distance between the layer-changing conductor and a vertical GND reference layer in the signal layer-changing structure according to a difference between the actual impedance value and the target impedance value to obtain an optimized signal layer-changing structure.

[0014] Optionally, the basic structural parameters specifically include a trace and layer-changing conductor connection pad radius, layer-changing conductor width and thickness, parallel distance between the layer-changing conductor and the vertical GND reference layer, transverse and longitudinal distances of a filling medium, vertical distances of the vertical GND reference layer from the signal trace at both ends and both sides arc radii, and medium chamfer arc radii.

[0015] Optionally, the step of establishing the equivalent transmission line model according to the basic structural parameters of the signal layer-changing structure in the vertical direction of the printed circuit board specifically comprises:

[0016] establishing the equivalent transmission line model by using a three-dimensional full-wave electromagnetic simulation software HFSS according to the basic structural parameters of the signal layer-changing structure in the vertical direction of the printed circuit board.

[0017] Optionally, the step of adjusting the width of the layer-changing conductor and the parallel distance between the layer-changing conductor and the vertical GND reference layer in the signal layer-changing structure according to the difference between the actual impedance value and the target impedance value to obtain the optimized signal layer-changing structure specifically comprises:

[0018] when 0 determining the layer-changing impedance Z of the layer-changing conductor from the surface layer trace to the inner layer trace by using a formula

[0019] when w / d≥1, determining the layer-changing impedance Z of the layer-changing conductor from the surface layer trace to the inner layer trace by using a formula

[0020] wherein, ε​ex equivalent dielectric constant of the medium filling each layer in the vertical direction, w is the width of the layer-changing conductor, and d is the parallel distance between the layer-changing conductor and the vertical GND reference layer.

[0021] In a second aspect, the present application provides a signal layer-changing structure optimization device suitable for a DDR5 printed circuit board, the signal layer-changing structure optimization device suitable for the DDR5 printed circuit board comprising:

[0022] a data acquisition module configured to acquire a signal layer-changing structure of a DDR5 printed circuit board and a target impedance value corresponding to a surface layer trace and an inner layer trace in the signal layer-changing structure;

[0023] an equivalent transmission line model determination module configured to establish an equivalent transmission line model according to basic structural parameters of the signal layer-changing structure in the vertical direction of the printed circuit board;

[0024] an actual impedance value determination module configured to perform time-domain reflected impedance simulation on the equivalent transmission line model in a transient solution mode to obtain an actual impedance value; the actual impedance value is a layer-changing impedance of a segment from the surface layer trace to the inner layer trace;

[0025] a structure optimization module configured to adjust a width of a layer-changing conductor and a parallel distance between the layer-changing conductor and a vertical GND reference layer in the signal layer-changing structure according to a difference between the actual impedance value and the target impedance value to obtain an optimized signal layer-changing structure.

[0026] In a third aspect, the present application provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the signal layer-changing structure optimization method suitable for the DDR5 printed circuit board.

[0027] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program is executable by a processor to implement the signal layer-changing structure optimization method suitable for the DDR5 printed circuit board.

[0028] In a fifth aspect, the present application provides a computer program product comprising a computer program, wherein the computer program is executable by a processor to implement the signal layer-changing structure optimization method suitable for the DDR5 printed circuit board.

[0029] According to the embodiments provided in the present application, the present application has the following technical effects:

[0030] The application provides a signal layer-changing structure optimization method, device, medium and product suitable for a DDR5 printed circuit board, the width of a layer-changing conductor in the signal layer-changing structure and the parallel distance between the layer-changing conductor and a vertical GND reference layer are adjusted to match a target impedance value, and the signal layer-changing structure is more compact, the application can improve the signal layer-changing structure limited by traditional signal vias, so that the signal realizes low impedance fluctuation and excellent transmission characteristics in the vertical direction of the DDR5 printed circuit board, thereby realizing high-quality transmission of higher-rate signals. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0032] Figure 1 The flowchart of the signal layer-changing structure optimization method suitable for the DDR5 printed circuit board in an embodiment of the present application is shown.

[0033] Figure 2 The basic structure parameter diagram of the signal layer-changing structure provided by the present application is shown.

[0034] Figure 3 The diagram of the traditional signal layer-changing structure is shown.

[0035] Figure 4 The diagram of the signal layer-changing structure provided by the present application is shown.

[0036] Figure 5 The diagram of the signal layer-changing transmission line equivalent circuit model of the present application is shown.

[0037] Figure 6 The diagram of the TDR impedance results of the layer-changing structure and the traditional layer-changing structure provided by the present application is shown. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0039] The above-mentioned purposes, features and advantages of the present application can be more obvious and easy to understand. The present application will be further described in detail below with reference to the drawings and specific embodiments.

[0040] In one exemplary embodiment, as shown in Figure 1 A signal layer change structure optimization method suitable for a DDR5 printed circuit board is provided, which comprises the following S101-S104. Among them:

[0041] S101, obtaining the signal layer change structure of the DDR5 printed circuit board and the target impedance value corresponding to the surface layer trace and the inner layer trace in the signal layer change structure;

[0042] The signal layer change structure specifically includes a surface layer trace (Microstrip), an inner layer trace (Stripline), an introduction pad, an extraction pad, other non-functional pads, a layer change conductor, a vertical GND reference layer, and a dielectric layer. The surface layer trace is connected to the vicinity of the vertical GND reference layer through the introduction pad, then connected to the extraction pad through a transmission line with a thickness t and a width w, and finally the inner layer trace starts from the extraction pad;

[0043] Among them, the target impedance value corresponding to the surface layer trace and the inner layer trace in the signal layer change structure can be directly obtained according to the JEDEC JESD308 protocol; for example, the single-ended signal Lead-in impedance is 40Ω, the Loaded impedance is 55Ω; the differential signal corresponds to a differential impedance of 54Ω. In the design of the DDR5 printed circuit board, the above impedance values remain fixed to reduce signal integrity problems.

[0044] S102, establishing an equivalent transmission line model according to the basic structural parameters of the signal layer change structure in the vertical direction of the printed circuit board; as shown in Figure 2 (a) three-dimensional view and (b) top view, the basic structural parameters specifically include: trace and layer change conductor connection pad radius r, layer change conductor width w and thickness t, parallel distance d of layer change conductor and vertical GND reference layer, transverse distance d1 and longitudinal distance d2 of filling medium, vertical distance d3 of vertical GND reference layer from both ends to signal trace, both sides arc radius r1 and medium chamfer arc radius r2.

[0045] As a specific embodiment, according to the basic structural parameters of the signal layer change structure in the vertical direction of the printed circuit board, a three-dimensional full-wave electromagnetic simulation software HFSS is used to establish a simulation model. The signal layer change region transmission line equivalent circuit model, as shown in Figure 5 is composed of a capacitor C with capacitance and an inductor L with inductance;

[0046] S103, time domain reflection impedance simulation of the equivalent transmission line model in transient solution mode is carried out to obtain the actual impedance value; the actual impedance value is the layer change impedance of the surface layer trace to the inner layer trace section; the transmission line equivalent characteristic impedance value can be obtained by Calculations show that the actual impedance of the transmission line decreases when capacitance increases, and increases when inductance increases. Therefore, impedance fluctuations can be adjusted by varying the deviation between the actual impedance value Z and the target characteristic impedance value Z0, thereby reducing signal integrity issues.

[0047] S104, adjust the width of the swap conductor and the parallel distance between the swap conductor and the vertical GND reference layer in the signal swap structure according to the difference between the actual impedance value and the target impedance value, to obtain the optimized signal swap structure.

[0048] To match the actual impedance value Z with the target impedance value Z0, the capacitive and inductive components of the signal layer-swapping structure need to be adjusted. The "quasi-coaxial principle" in the relevant signal layer-swapping structure is converted to the "microstrip transmission line principle." According to transmission line theory, the layer-swapping impedance (actual impedance value) Z of the surface layer trace to the inner layer trace segment is calculated as follows:

[0049] When 0 < w / d ≤ 1, use the formula Determine the layer switching impedance Z of the surface layer trace to the inner layer trace segment;

[0050] When w / d≥1, use the formula Determine the layer switching impedance Z of the surface layer trace to the inner layer trace segment;

[0051] Where, ε ex The equivalent dielectric constant of each layer of filling medium in the vertical direction is given. w d represents the width of the layer-swapping conductor, and d represents the parallel distance between the layer-swapping conductor and the vertical GND reference layer.

[0052] Since there are unused metal segments, i.e. stubs, in the vertical direction in addition to the layer-changing conductors on the layer-changing path, their response characteristics are capacitive, which will lower the overall impedance value of the signal layer-changing structure. Therefore, by designing the impedance value on the layer-changing path to be higher or removing the stub part to balance the capacitive response brought by the stub, the impedance fluctuation can be reduced.

[0053] like Figure 4As shown in (a) a 3D view of the single-ended signal, (b) a 3D view of the differential signal, (c) a top view of the single-ended signal, and (d) a top view of the differential signal, parametric scanning simulations were performed on the width w of the switching conductor and the parallel distance d between the switching conductor and the vertical GND reference layer in the signal switching structure using the 3D full-wave electromagnetic simulation software HFSS. The variation law is as follows: when d is a fixed value, w widens, capacitance increases, inductance decreases, and its impedance value decreases; when w is fixed, d decreases, capacitance decreases, and its impedance value increases, thus easily matching the target impedance value Z0. At the same time, the remaining structural parameters (which have a smaller impact on impedance) are further optimized, thereby achieving a compact design. The differential structure is similar in principle to the single-ended structure, the difference being that the target impedance value of the single-ended signal is ~40Ω, and the target impedance value of the differential signal is ~54Ω. Using the above method, a vertical switching structure for the signal that matches the target impedance value of the system can still be achieved, reducing impedance fluctuations and enabling high-quality transmission of higher-speed signals.

[0054] A schematic diagram of a traditional signal layer switching structure is shown below. Figure 3 As shown, Figure 3 (a) represents a single-ended signal layer change, including: surface layer traces, ground return vias, via paths, inner layer traces, and anti-pads. Figure 3 (b) is a differential signal layer change, including: surface layer traces, ground return holes, inner layer traces and via piles.

[0055] Figure 6 Part (a) is a traditional single-ended signal layer-switching structure. Figure 3 ) and the layer replacement structure provided in this application ( Figure 4 The time-domain reflection (TDR) impedance comparison results show that the TDR impedance of the layer-swapping structure provided in this application deviates less from the target impedance (~40Ω) of the DDR single-ended signal. The traditional layer-swapping structure fluctuates by about 4Ω, while the layer-swapping structure provided in this application only has 0.8Ω. Figure 6 Part (b) shows the TDR impedance results of the differential signal under two different structures. Compared with the single-ended signal, the target impedance of the DDR clock differential signal is ~54Ω. As can be seen from the comparison results, the impedance fluctuation of the structure in this application (~1Ω) is significantly lower than that of the traditional junction structure (~8Ω). Using the novel layer-swapping structure provided in this application, combined with the impedance optimization method, the rise time of higher speed signals is shorter, signal integrity problems are reduced, signal transmission is stable, and the performance of high-speed devices will be greatly improved.

[0056] As a specific example, such as Figure 5As shown, the signal introduction pad and the signal leading-out pad are equivalent to capacitors C1 and C3 respectively, the layer change path is represented by L1 and C2 circuit, and the unused layer change conductor part is represented by L2 and C4 circuit; the layer change area impedance is mainly determined by the layer change conductor width w and the distance d between the conductor and the vertical GND reference layer, when the distance d is determined, the wider the conductor width w, the smaller the L1 and the larger the C2, and the lower the impedance; when the width w is determined, the larger the distance d, the smaller the C2, and the larger the impedance value.

[0057] Based on the same inventive concept, the embodiments of the present application also provide a signal layer change structure optimization device for a DDR5 printed circuit board for implementing the above-mentioned signal layer change structure optimization method applicable to the DDR5 printed circuit board. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more signal layer change structure optimization device embodiments for a DDR5 printed circuit board provided below can be referred to the limitations of the signal layer change structure optimization method applicable to the DDR5 printed circuit board in the above, which will not be repeated here.

[0058] In one exemplary embodiment, a signal layer change structure optimization device for a DDR5 printed circuit board is provided, comprising:

[0059] A data acquisition module is configured to acquire a signal layer change structure of a DDR5 printed circuit board and a target impedance value corresponding to a surface layer trace and an inner layer trace in the signal layer change structure;

[0060] An equivalent transmission line model determination module is configured to establish an equivalent transmission line model according to basic structure parameters of the signal layer change structure in the vertical direction of the printed circuit board;

[0061] An actual impedance value determination module is configured to perform time-domain reflected impedance simulation on the equivalent transmission line model in a transient solution mode to obtain an actual impedance value; the actual impedance value is a layer change impedance of a surface layer trace to an inner layer trace segment;

[0062] A structure optimization module is configured to adjust a layer change conductor width and a parallel distance between the layer change conductor and a vertical GND reference layer in the signal layer change structure according to a difference between the actual impedance value and the target impedance value to obtain an optimized signal layer change structure.

[0063] In an example embodiment, a computer device is provided, which can be a server or a terminal. The computer device includes a processor, a memory, an input / output interface (I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is configured to exchange information between the processor and external devices. The communication interface of the computer device is configured to communicate with external terminals through network connection. The computer program is executed by the processor to implement a signal layer exchange structure optimization method for a DDR5 printed circuit board.

[0064] In an example embodiment, a computer device is provided, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0065] In an example embodiment, a computer readable storage medium is provided, which stores a computer program. The computer program is executed by a processor to implement the steps in the above method embodiments.

[0066] In an example embodiment, a computer program product is provided, which includes a computer program. The computer program is executed by a processor to implement the steps in the above method embodiments.

[0067] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant regulations.

[0068] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0069] The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a blockchain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general processor, a central processor, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0070] In the present application, all actions of obtaining signals, information or data are performed under the premise of complying with the corresponding data protection regulations and policies of the country where the device is located, and under the premise of obtaining authorization from the owner of the corresponding device.

[0071] The technical features of the above embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present application.

[0072] The principles and implementation manners of the present application are described herein by using specific examples, and the above examples are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will have changes. In conclusion, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A method for optimizing the signal layer switching structure of a DDR5 printed circuit board, characterized in that, The signal layer switching structure optimization method applicable to DDR5 printed circuit boards includes: Obtain the signal layer swapping structure of the DDR5 printed circuit board and the target impedance values ​​of the surface layer traces and inner layer traces in the signal layer swapping structure; Based on the basic structural parameters of the signal switching structure in the vertical direction of the printed circuit board, an equivalent transmission line model is established using the three-dimensional full-wave electromagnetic simulation software HFSS. In transient solution mode, time-domain reflection impedance simulation is performed on the equivalent transmission line model to obtain the actual impedance value; the actual impedance value is the layer switching impedance of the surface trace to the inner trace segment. The width of the swap conductor and the parallel distance between the swap conductor and the vertical GND reference layer in the signal swap structure are adjusted based on the difference between the actual impedance value and the target impedance value to obtain the optimized signal swap structure. The width w of the switching conductor and the parallel distance d between the switching conductor and the vertical GND reference layer in the signal switching structure were parametrically scanned and simulated using the three-dimensional full-wave electromagnetic simulation software HFSS. The variation law is as follows: when d is a fixed value, w widens, the capacitance increases, the inductance decreases, and the impedance value decreases; when w is fixed, d decreases, the capacitance decreases, and the impedance value increases, thereby matching the target impedance value.

2. The signal layer switching structure optimization method for DDR5 printed circuit boards according to claim 1, characterized in that, The basic structural parameters specifically include: the radius of the pad connecting the trace and the layer replacement conductor, the width and thickness of the layer replacement conductor, the parallel distance between the layer replacement conductor and the vertical GND reference layer, the lateral and longitudinal distances of the filling dielectric, the vertical distances from both ends of the vertical GND reference layer to the signal trace, the radius of the arcs on both sides, and the radius of the chamfered arc of the dielectric.

3. The signal layer switching structure optimization method for DDR5 printed circuit boards according to claim 1, characterized in that, The optimized signal layer swapping structure is obtained by adjusting the width of the swapping conductor and the parallel distance between the swapping conductor and the vertical GND reference layer based on the difference between the actual impedance value and the target impedance value. Specifically, this includes: When 0 < w / d ≤ 1, use the formula Determine the layer switching impedance Z of the surface layer trace to the inner layer trace segment; When w / d≥1, use the formula Determine the layer switching impedance Z of the surface layer trace to the inner layer trace segment; Where, ε ex The equivalent dielectric constant of each layer of filling medium in the vertical direction is given. w d represents the width of the layer-swapping conductor, and d represents the parallel distance between the layer-swapping conductor and the vertical GND reference layer.

4. A signal layer switching structure optimization device suitable for DDR5 printed circuit boards, characterized in that, The signal layer switching structure optimization device suitable for DDR5 printed circuit boards includes: The data acquisition module is used to acquire the signal layer switching structure of the DDR5 printed circuit board and the target impedance values ​​corresponding to the surface layer traces and inner layer traces in the signal layer switching structure. The equivalent transmission line model determination module is used to establish an equivalent transmission line model based on the basic structural parameters of the signal layer structure in the vertical direction of the printed circuit board using the three-dimensional full-wave electromagnetic simulation software HFSS. The actual impedance value determination module is used to perform time-domain reflection impedance simulation on the equivalent transmission line model in transient solution mode to obtain the actual impedance value; the actual impedance value is the layer switching impedance of the segment from the surface layer to the inner layer. The structure optimization module is used to adjust the width of the swap conductor and the parallel distance between the swap conductor and the vertical GND reference layer in the signal swap structure according to the difference between the actual impedance value and the target impedance value, so as to obtain the optimized signal swap structure. The width w of the switching conductor and the parallel distance d between the switching conductor and the vertical GND reference layer in the signal switching structure were parametrically scanned and simulated using the three-dimensional full-wave electromagnetic simulation software HFSS. The variation law is as follows: when d is a fixed value, w widens, the capacitance increases, the inductance decreases, and the impedance value decreases; when w is fixed, d decreases, the capacitance decreases, and the impedance value increases, thereby matching the target impedance value.

5. A computer device, comprising: A memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that the processor executes the computer program to implement the signal layer swapping structure optimization method for a DDR5 printed circuit board as described in any one of claims 1-3.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the signal layer swapping structure optimization method for DDR5 printed circuit boards as described in any one of claims 1-3.

7. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the signal layer swapping structure optimization method for DDR5 printed circuit boards as described in any one of claims 1-3.

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