Semiconductor device and power conversion device

Abstract

The purpose of the present invention is to sufficiently suppress electromagnetic noise in an IGBT structure. The upper layer electrode (14) and the lower layer electrode (12) inside the trench (8) are separated by an intermediate insulating film (16). The first resistor (R1) is connected between the upper layer electrode (14) and the input terminal (10). The second resistor (R2) is connected between the lower layer electrode (12) and the input terminal (10). The gate-emitter capacitance of the lower layer electrode (12) is smaller than the gate-emitter capacitance of the upper layer electrode (14).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and a power conversion device. BACKGROUND

[0002] The high speed of the switching speed effectively reduces the switching loss of an insulated gate bipolar transistor (IGBT). As a problem of the high speed, there is generation of electromagnetic noise. It is reported that the noise is related to Ic peak at low current (for example, refer to Non-Patent Literature 1). The Ic peak depends on the overshoot of the gate voltage Vge at the time of turn-on, the larger the displacement current (Idis = Cgc x dV / dt), the smaller the Cge, and the more the Vge increases. Here, Cgc is the gate-collector capacitance, and Cge is the gate-emitter capacitance. Therefore, in order to suppress the electromagnetic noise, it is necessary to reduce the Cgc / Cge ratio.

[0003] Non-Patent Literature 1: K. Nishi, T. Takahashi, and A. Narazaki, “Analysis the complex tradeoff among Eon-VCEsat-SCSOA and EMI noise through the single chip evaluation method,” in Proc. 31st Int. Symp. Power Semiconductor Devices ICs (ISPSD), May 2019, pp. 475-478

[0004] However, a configuration of an IGBT capable of sufficiently suppressing electromagnetic noise has not been proposed. SUMMARY

[0005] The present disclosure is made in order to solve the above-described problems, and aims to obtain a semiconductor device and a power conversion device capable of sufficiently suppressing electromagnetic noise.

[0006] The semiconductor device of the present disclosure includes a semiconductor substrate having a drift layer of a first conductivity type, a base layer of a second conductivity type formed on the drift layer, a source layer of the first conductivity type formed on the base layer, and a collector layer of the second conductivity type formed below the drift layer; an emitter electrode formed on an upper surface of the semiconductor substrate and connected to the base layer and the source layer; a collector formed on a lower surface of the semiconductor substrate and connected to the collector layer; a lower electrode formed inside a trench passing through the source layer and the base layer from the upper surface of the semiconductor substrate via a lower gate insulating film; an upper electrode formed inside the trench via an upper gate insulating film and disposed above the lower electrode, separated from the lower electrode by an intermediate insulating film; an input terminal; a first resistor connected between the upper electrode and the input terminal; and a second resistor connected between the lower electrode and the input terminal, the gate-emitter capacitance of the lower electrode being smaller than the gate-emitter capacitance of the upper electrode.

[0007] In the present disclosure, the upper electrode and the lower electrode are separated by the intermediate insulating film inside the trench. The first resistor is connected between the upper electrode and the input terminal. The second resistor is connected between the lower electrode and the input terminal. The gate-emitter capacitance of the lower electrode is smaller than the gate-emitter capacitance of the upper electrode. Thus, the electromagnetic noise can be sufficiently suppressed in the configuration of the IGBT. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a cross-sectional view showing the semiconductor device of Embodiment 1.

[0009] Figure 2 is a graph showing the time variation of Vce, Ic, and Vge at the time of turn-on of the semiconductor device of Embodiment 1.

[0010] Figure 3 is a graph showing the relationship between Cge2 / Cge1 and the Ic peak value.

[0011] Figure 4 is a cross-sectional view showing the relationship of the thickness of the insulating film of the semiconductor device of Embodiment 1.

[0012] Figure 5 is a graph showing the relationship between the thickness of the lower gate insulating film / thickness of the upper gate insulating film and the Cge of the lower electrode / Cge of the upper electrode.

[0013] Figure 6 is a graph showing the relationship between the thickness of the lower gate insulating film / thickness of the upper gate insulating film and the Ic peak value.

[0014] Figure 7 This is a cross-sectional view showing the relationship between the lengths of the carrier accumulation layer and the drift layer of the semiconductor device in Embodiment 1.

[0015] Figure 8 This is a cross-sectional view showing the relationship between the lengths of the lower and upper electrodes and the depth of the base layer of the semiconductor device in Embodiment 1.

[0016] Figure 9 This is a cross-sectional view showing the semiconductor device of Embodiment 2.

[0017] Figure 10 This is a top view showing the semiconductor device of Embodiment 3.

[0018] Figure 11 It means along Figure 10 Sectional views of sections I-II and III-IV.

[0019] Figure 12 This is a top view showing a modified example of the semiconductor device according to Embodiment 3.

[0020] Figure 13 It means along Figure 12 Sectional views of sections I-II and III-IV.

[0021] Figure 14 This is a diagram showing the semiconductor device of Embodiment 4.

[0022] Figure 15 This is a cross-sectional view showing the semiconductor device of Embodiment 5.

[0023] Figure 16 This is a cross-sectional view showing the semiconductor device of Embodiment 6.

[0024] Figure 17 This is a cross-sectional view showing the semiconductor device of Embodiment 7.

[0025] Figure 18 This is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 7.

[0026] Figure 19 This is a cross-sectional view showing the semiconductor device of Embodiment 8.

[0027] Figure 20 This is a top view showing the semiconductor device of Embodiment 8.

[0028] Figure 21 This is a cross-sectional view showing the semiconductor device of Embodiment 9.

[0029] Figure 22 This is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 9.

[0030] Figure 23 This is a cross-sectional view showing the semiconductor device of Embodiment 10.

[0031] Figure 24 This is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 10.

[0032] Figure 25 This is a cross-sectional view showing the semiconductor device of Embodiment 11.

[0033] Figure 26 This is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 11.

[0034] Figure 27 This is a cross-sectional view showing the semiconductor device of Embodiment 12.

[0035] Figure 28 This is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 12.

[0036] Figure 29 This is a cross-sectional view showing the semiconductor device of Embodiment 13.

[0037] Figure 30 This is a top view showing the semiconductor device of embodiment 14.

[0038] Figure 31 It means along Figure 29 Sectional views of sections I-II and III-IV.

[0039] Figure 32 This is a top view showing the semiconductor device of embodiment 15.

[0040] Figure 33 This is a cross-sectional view showing the semiconductor device of Embodiment 16.

[0041] Figure 34 This is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 16.

[0042] Figure 35 This is a graph representing the Vce dependency of Cge.

[0043] Figure 36 This is a graph showing the relationship between the CR time constant (the product of the gate-emitter capacitance and the second resistance as the lower electrode) and the CR time constant (the product of the gate-emitter capacitance and the first resistance as the upper electrode) and the peak value of Ic.

[0044] Figure 37 This is a graph showing the relationship between the ratio of the resistance value of the second resistor to the resistance value of the first resistor and the peak value of Ic.

[0045] Figure 38 It is a diagram showing the current-voltage relationship between the lower and upper electrodes when the circuit is switched on.

[0046] Figure 39 This is a block diagram showing the structure of the power conversion system of the power conversion device applied in embodiment 17.

[0047] Explanation of reference numerals in the attached figures: 1...semiconductor substrate; 2...drift layer; 3...base layer; 4...source layer; 5...collector layer; 6...carrier accumulation layer; 8...trench; 9...emitter electrode; 10...gate electrode (input terminal); 11...collector; 12...lower electrode; 13...lower gate insulating film; 14...upper electrode; 15...upper gate insulating film; 16...intermediate insulating film; 18...first gate wiring; 19...second gate wiring; 20...first gate contact; 21...second gate contact; 22...gate drive circuit; 23...dummy trench; 24...dummy lower electrode; 25...dummy upper electrode; 26...input terminal; C1...first capacitor; C2...second capacitor; D1, D1′...first diode (clamping circuit); D2, D2′...second diode (clamping circuit); D ON ...conducting-side diode; D OFF ...cutoff-side diode; D1 ON ...first conduction-side diode; D1 OFF ...first cutoff side diode; D2 ON ...second conduction-side diode; D2 OFF ...second cutoff diode; R1...first resistor; R2...second resistor; R3...gate resistor; R ON ...on-resistance; R OFF ...cutoff resistor; R1 ON ...first on-resistance; R1 OFF ...first cutoff resistor; R2 ON ...second on-resistance; R2 OFF ...Second cutoff resistor; 200...Power conversion device; 201...Main conversion circuit; 202...Control circuit. Detailed Implementation

[0048] The semiconductor device and power conversion device of the embodiments will be described with reference to the accompanying drawings. The same or corresponding components are labeled with the same reference numerals, and sometimes repeated descriptions are omitted.

[0049] Implementation Method 1

[0050] Figure 1 This is a cross-sectional view showing the semiconductor device according to Embodiment 1. The semiconductor substrate 1 has at least: a drift layer 2 of a first conductivity type, a base layer 3 of a second conductivity type formed on the drift layer 2, a source layer 4 of a first conductivity type formed on a portion of the base layer 3, and a collector layer 5 of a second conductivity type formed below the drift layer 2. A carrier accumulation layer 6 of the first conductivity type is formed between the drift layer 2 and the base layer 3. A buffer layer 7 of the first conductivity type is formed between the drift layer 2 and the collector layer 5. The impurity concentration of the carrier accumulation layer 6 and the buffer layer 7 is higher than that of the drift layer 2. For example, the first conductivity type is n-type and the second conductivity type is p-type, but the opposite is also possible. A plurality of trenches 8 are formed side by side, penetrating the source layer 4 and the base layer 3 from the upper surface of the semiconductor substrate 1.

[0051] An emitter electrode 9 is formed on the upper surface of the semiconductor substrate 1 and is connected to the base layer 3 and the source layer 4. A gate electrode 10 is also formed on the upper surface of the semiconductor substrate 1. A collector electrode 11 is formed on the lower surface of the semiconductor substrate 1 and is connected to the collector layer 5. A lower electrode 12 is formed inside the trench 8 via a lower gate insulating film 13. An upper electrode 14 is formed inside the trench 8 via an upper gate insulating film 15 and is disposed above the lower electrode 12, separated from the lower electrode 12 by an intermediate insulating film 16. An interlayer insulating film 17 is formed on the upper electrode 14, separating the upper electrode 14 from the emitter electrode 9.

[0052] As described above, the upper electrode 14 and the lower electrode 12 are separated inside the trench 8 by an intermediate insulating film 16, thus enabling the gate-emitter capacitance Cge of the two electrodes to be different. Although the upper electrode 14 is opposite to the base layer 3 connected to the emitter electrode 9 and has a large Cge, the lower electrode 12 is not opposite to the base layer 3 and therefore has a small Cge.

[0053] Furthermore, a first resistor R1 is connected between the upper electrode 14 and the gate electrode 10, and a second resistor R2 is connected between the lower electrode 12 and the gate electrode 10. This allows the voltages of the upper electrode 14 and the lower electrode 12 to be controlled independently via their respective gate capacitances. Therefore, by adjusting the thickness of the gate oxide film of each electrode, the voltage Cge of the lower electrode 12 is made smaller than that of the upper electrode 14. This results in faster charging of the capacitor at the lower electrode 12.

[0054] Figure 2This is a graph showing the time changes of Vce, Ic, and Vge when the semiconductor device of Embodiment 1 is turned on. As described above, the capacitor of the lower electrode 12 charges quickly, therefore, during the current increase period when the device is turned on, there is a period in which the voltage of the lower electrode 12 is higher than the voltage of the upper electrode 14. During the Miller period following the current increase period, there is a period in which the voltage of the lower electrode 12 is lower than the voltage of the upper electrode 14.

[0055] When the voltage of the lower electrode 12 increases, the potential of the mesa sandwiched laterally by the adjacent lower electrode 12 of the trench 8 also increases. Cgc is the series connection of the capacitance of the gate oxide film and the capacitance of the depletion layer; as the potential increases and the depletion layer extends, Cgc decreases. Therefore, the displacement current to the upper electrode 14 can be reduced, thus the peak value of Ic decreases. As a result, electromagnetic noise can be sufficiently suppressed in the IGBT structure.

[0056] Furthermore, electromagnetic noise is a major cause of increased displacement current due to holes and an increase in the peak value of Ic, a problem that arises in IGBTs with a large flow of holes. On the other hand, in MOSFETs, there is no significant increase in the peak value of Ic; therefore, even if the structure of this embodiment is applied to MOSFETs, a sufficient reduction in the peak value of Ic cannot be obtained.

[0057] Figure 3 This is a graph showing the relationship between Cge2 / Cge1 and the peak value of Ic. The horizontal axis is the ratio (Cge2 / Cge1) of the gate-emitter capacitance Cge2 of the electrode connected to the second resistor R2 to the gate-emitter capacitance Cge1 of the electrode connected to the first resistor R1. The inventors have discovered that the smaller Cge2 / Cge1 is, the lower the peak value of Ic can be. By setting Cge2 / Cge1 to 0.5 or less, the peak value of Ic can be reduced by more than 30%, and by setting Cge2 / Cge1 to 0.2 or less, the peak value of Ic can be reduced by more than 40%. Therefore, in this embodiment, it is preferable to set the ratio of Cge of the electrode connected to the lower electrode 12 to Cge of the upper electrode 14 to 0.5 or less, and more preferably 0.2 or less.

[0058] Furthermore, during the Miller period following the current increase period upon turn-on, there exists a period in which the voltage of the lower electrode 12 is lower than the voltage of the upper electrode 14. Since the Miller period does not affect the Ic peak value, the Ic peak value will not increase even if the voltage of the lower electrode 12 is low. By reducing the voltage of the lower electrode 12 during the Miller period, the voltage applied to the gate oxide film can be reduced. Therefore, compared to the case where the voltage of the lower electrode 12 is always high, the lifetime of the gate oxide film can be extended. On the other hand, if there is a period in the Miller period in which the voltage of the lower electrode 12 is higher than the voltage of the upper electrode 14, Cgc can be reduced.

[0059] Figure 4 This is a cross-sectional view showing the relationship between the thicknesses of the insulating films in the semiconductor device of Embodiment 1. The thickness T2 of the lower gate insulating film 13 covering the side surface of the lower electrode 12 and the thickness T4 of the lower gate insulating film 13 covering the bottom of the lower electrode 12 are thicker than the thickness T1 of the upper gate insulating film 15 covering the side surface of the upper electrode 14. As a result, the Cge of the lower electrode 12 is smaller than that of the upper electrode 14. Therefore, as described above, the charging of the capacitor of the lower electrode 12 is faster, the voltage of the lower electrode 12 can be increased, and Cgc can be reduced to suppress electromagnetic noise.

[0060] Figure 5 This is a graph showing the relationship between the thickness of the lower gate insulating film / the thickness of the upper gate insulating film and the Cge of the lower electrode / the Cge of the upper electrode. Figure 6 This is a graph showing the relationship between the thickness of the lower gate insulating film / the thickness of the upper gate insulating film and the Ic peak value. In order to suppress the Ic peak value by reducing the ratio of Cge of the lower electrode to Cge of the upper electrode, it is preferable to set the thickness of the lower gate insulating film 13 to be 1.5 times or more than the thickness of the upper gate insulating film 15, more preferably 2 times or more, and even more preferably 2.5 times or more.

[0061] Furthermore, when the potential of the lower electrode 12 increases, a potential difference is generated between the upper electrode 14 and the lower electrode 12, resulting in capacitance. Therefore, the thickness T3 of the intermediate insulating film 16 can be made thicker than the thickness T1 of the upper gate insulating film 15 on the side of the upper electrode 14. Consequently, the Cge of the lower electrode 12 decreases, and as described above, the capacitance of the lower electrode 12 charges faster, increasing the voltage of the lower electrode 12 and reducing Cgc, thereby suppressing electromagnetic noise.

[0062] Furthermore, the CR time constant formed by the gate capacitance (Cies2 = Cge + Cgc) of the lower electrode 12 and the second resistor R2 is smaller than the CR time constant formed by the gate capacitance (Cies1 = Cge + Cgc) of the upper electrode 14 and the first resistor R1. As a result, the capacitor of the lower electrode 12 charges faster, thus suppressing electromagnetic noise.

[0063] Furthermore, the resistance of the second resistor R2 is less than that of the first resistor R1. This causes the capacitor of the lower electrode 12 to charge faster, thus suppressing electromagnetic noise. On the other hand, when the resistance of the second resistor R2 is greater than that of the first resistor R1, the rise in gate voltage, determined by displacement current and resistance, increases. Therefore, the voltage of the lower electrode 12 can be higher than that of the upper electrode 14, reducing Cgc.

[0064] Furthermore, since the impurity concentration in the carrier accumulation layer 6 is higher than that in the drift layer 2, the voltage of the lower electrode 12 is more easily increased. Therefore, by forming the carrier accumulation layer 6, Cgc can be further reduced, thereby suppressing electromagnetic noise.

[0065] Figure 7 This is a cross-sectional view showing the relationship between the lengths of the carrier accumulation layer and the drift layer of the semiconductor device in Embodiment 1. The length I2 of the carrier accumulation layer 6 opposite to the lower electrode 12 is longer than the length I1 of the carrier accumulation layer 6 opposite to the upper electrode 14. By increasing the area where the lower electrode 12 faces the carrier accumulation layer 6, the voltage of the lower electrode 12 can be increased and the Cgc can be decreased. By decreasing the area where the upper electrode 14 faces the carrier accumulation layer 6, the Cgc of the upper electrode can be decreased.

[0066] Furthermore, the length I2 of the carrier accumulation layer 6 opposite to the side of the lower electrode 12 is longer than the length I3 of the drift layer 2 opposite to the side of the lower electrode 12. Since the impurity concentration in the carrier accumulation layer 6 is higher than that in the drift layer 2, it is easier to increase the voltage of the lower electrode 12. Therefore, by increasing the area of ​​the lower electrode 12 opposite to the carrier accumulation layer 6, it is possible to increase the voltage of the lower electrode 12 and reduce Cgc.

[0067] Figure 8 This is a cross-sectional view showing the relationship between the lengths of the lower and upper electrodes and the depth of the base layer in the semiconductor device of Embodiment 1. Since Cgc depends on the electrode area opposite to the drift layer 2 and the carrier accumulation layer 6, the length D1 of the upper electrode 14 extending downwards from the base layer 3 is proportional to the Cgc of the upper electrode 14, and the length L2 of the lower electrode 12 is proportional to the Cgc of the lower electrode 12. In this embodiment, the length L2 is longer than the length D1. The depth P1 of the base layer 3 is longer than the length D1.

[0068] By shortening the extension length D1 of the low-voltage upper electrode 14 in the region below the base layer 3 where the specific voltage changes, the depletion layer can be extended, thereby reducing the Cgc of the upper electrode 14 and the peak current Ic. To sufficiently reduce the Cgc of the upper electrode 14, it is preferable that the extension length D1 of the upper electrode 14 is less than half the length L2 of the lower electrode 12, and more preferably less than one-third.

[0069] Implementation Method 2

[0070] Figure 9This is a cross-sectional view showing the semiconductor device according to Embodiment 2. A plurality of trenches 8 are formed side-by-side on the semiconductor substrate 1. The width WM of the mesa between adjacent trenches 8 is narrower than the width WTR of the trench 8. This allows for an increase in the voltage across the mesa, a reduction in Cgc, and thus suppression of electromagnetic noise. Other structures and effects are the same as in Embodiment 1.

[0071] Implementation Method 3

[0072] Figure 10 This is a top view showing the semiconductor device according to Embodiment 3. A first gate wiring 18 and a resistor R1′ connect the upper electrode 14 and the gate electrode 10. A second gate wiring 19 and a resistor R2′ connect the lower electrode 12 and the gate electrode 10. The first resistor R1 is the sum of the resistances of resistor R1′ and the first gate wiring 18. The second resistor R2 is the sum of the resistances of resistor R2′ and the second gate wiring 19. The length GL2 of the second gate wiring 19 is shorter than the length GL1 of the first gate wiring 18. Therefore, even if the resistance values ​​of resistors R1′ and R2′ are the same, the resistance value of the second resistor R2 is less than the resistance value of the first resistor R1. As a result, the capacitor of the lower electrode 12 charges faster, thus suppressing electromagnetic noise.

[0073] On the other hand, when the length GL2 of the second gate wiring 19 is longer than the length GL1 of the first gate wiring 18, the resistance value of the second resistor R2 increases. Therefore, the increase in gate voltage determined by displacement current and resistance allows the voltage of the lower electrode 12 to be higher than the voltage of the upper electrode 14, thereby reducing Cgc.

[0074] Figure 11 It means along Figure 10 The cross-sectional views are shown along sections I-II and III-IV. The upper electrode 14 is connected to the first gate wiring 18 via the first gate contact 20. The lower electrode 12 is connected to the second gate wiring 19 via the second gate contact 21. Other structures and effects are the same as in Embodiment 1.

[0075] Figure 12 This is a top view showing a modified example of the semiconductor device according to Embodiment 3. Figure 13 It means along Figure 12 The diagram shows cross-sectional views along sections I-II and III-IV. The upper electrode 14 is connected to the first gate wiring 18 via a plurality of first gate contacts 20. The lower electrode 12 is connected to the second gate wiring 19 via a plurality of second gate contacts 21. Furthermore, by doubly forming the first gate wiring 18 and the second gate wiring 19 on both the outer periphery and inner side of the substrate, the contact points with the upper electrode 14 or the lower electrode 12 can be increased. This allows gate operation to be performed without in-chip gate delay.

[0076] Implementation Method 4

[0077] Figure 14 This diagram illustrates the semiconductor device according to Embodiment 4. The gate drive circuit 22 supplies a gate signal to the gate electrode 10. A gate resistor R3 is connected between the gate drive circuit 22 and the gate electrode 10 to adjust the switching speed. The gate resistor R3 has a larger resistance value than both the first resistor R1 and the second resistor R2. When a large resistance is formed inside the chip, the conduction area shrinks, increasing conduction losses, device size, and manufacturing cost. Therefore, the gate resistor R3 is formed on the outside of the semiconductor substrate 1. This reduces the resistive area within the substrate, thereby reducing conduction losses, device size, and manufacturing cost. Other structures and effects are the same as in Embodiment 1.

[0078] Furthermore, the gate resistor R3 can also have a smaller resistance value than the first resistor R1 and the second resistor R2. Therefore, compared to the case where the gate resistor R3 has a large resistance value, the current flowing through the first resistor R1 and the second resistor R2 can be increased. Thus, the increase in the voltage of the upper electrode 14 and the lower electrode 12 can be independently controlled by their respective gate capacitances, the first resistor R1, and the second resistor R2, making it easier to control to the optimal voltage value and further reducing electromagnetic noise. Moreover, by adjusting the gate current using the gate resistor R3 connected between the gate drive circuit 22 and the semiconductor element, the switching speed can be finely adjusted according to the application of the device or peripheral devices, reducing switching losses while decreasing electromagnetic noise that negatively impacts peripheral components.

[0079] Implementation Method 5

[0080] Figure 15 This is a cross-sectional view showing the semiconductor device according to Embodiment 5. A plurality of trenches 8 and a plurality of dummy trenches 23 are formed side-by-side on the semiconductor substrate 1. The dummy trenches 23, like the trenches 8, extend from the upper surface of the semiconductor substrate 1 through the source layer 4 and the base layer 3. The depth and width of the dummy trenches 23 are the same as those of the trenches 8.

[0081] A dummy lower electrode 24 is formed inside the dummy trench 23 via a lower gate insulating film 13. The dummy lower electrode 24 is connected to the emitter electrode 9. The material, length, and width of the dummy lower electrode 24 are the same as those of the lower electrode 12. The upper electrode 14 is formed inside the dummy trench 23 via an upper gate insulating film 15 and is disposed above the dummy lower electrode 24, and is separated from the dummy lower electrode 24 by an intermediate insulating film 16.

[0082] By forming a dummy lower electrode 24, the proportion of lower electrodes 12 connected to the gate electrode 10 is reduced, while the proportion of dummy lower electrodes 24 connected to the emitter electrode 9 is increased, across the plurality of trenches including trench 8 and dummy trench 23. Therefore, the gate capacitance parasitic on the lower electrode 12 can be reduced. Consequently, the charging of the capacitance of the lower electrode 12 becomes faster, the voltage of the lower electrode 12 can be increased, and Cgc can be reduced. Other structures and effects are the same as in Embodiment 1.

[0083] Implementation Method 6

[0084] Figure 16 This is a cross-sectional view of the semiconductor device according to Embodiment 6. A dummy upper electrode 25 is formed inside the dummy trench 23 via an upper gate insulating film 15. The material, length, and width of the dummy upper electrode 25 are the same as those of the upper electrode 14. A lower electrode 12 is formed inside the dummy trench 23 via a lower gate insulating film 13 and is disposed below the dummy upper electrode 25, separated from the dummy upper electrode 25 by an intermediate insulating film 16. By forming the dummy upper electrode 25, a coupling capacitance Cge is generated between the upper electrode 14 and the dummy upper electrode 25. This coupling capacitance can reduce the increase in the gate voltage of the upper electrode 14, thereby suppressing electromagnetic noise. Other structures and effects are the same as in Embodiment 5.

[0085] Implementation Method 7

[0086] Figure 17 This is a cross-sectional view of the semiconductor device according to Embodiment 7. A dummy lower electrode 24 (as in Embodiment 5) and a dummy upper electrode 25 (as in Embodiment 6) are formed in the dummy trench 23. In Embodiment 5, Cge parasitizes between the upper electrode 14 and the dummy lower electrode 24. On the other hand, in this embodiment, by providing dummy electrodes both above and below, Cge can be reduced, thus reducing the gate capacitance parasitized at the lower electrode 12 compared to Embodiment 5. Therefore, the capacitance of the lower electrode 12 charges faster, increasing the voltage of the lower electrode 12 and reducing Cgc. Other structures and effects are the same as in Embodiment 5.

[0087] In addition, the corner of the bottom surface of the dummy upper electrode 25 becomes a concentrated area of ​​electric field in shape, which may sometimes reduce the withstand voltage. Figure 18This is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 7. A dummy electrode 24b is formed inside the dummy trench 23 via a lower gate insulating film 13. The dummy electrode 24b is connected to the emitter electrode 9. By not dividing the dummy electrode 24b vertically, there is no corner of the bottom surface of the dummy upper electrode 25, thus improving the withstand voltage. Furthermore, the insulating film covering the dummy electrode 24b can also be an upper gate insulating film 15. However, by using a thicker lower gate insulating film 13, insulation film damage can be suppressed.

[0088] Implementation Method 8

[0089] Figure 19 This is a cross-sectional view showing the semiconductor device according to Embodiment 8. Instead of the gate electrode 10 of Embodiment 1, a first gate electrode 10a and a second gate electrode 10b are independently formed on the upper surface of the semiconductor substrate 1. The first gate electrode 10a is connected to the upper electrode 14. The second gate electrode 10b is connected to the lower electrode 12. On the outside of the semiconductor substrate 1, a first resistor R1 is connected between the first gate electrode 10a and the input terminal 26, and a second resistor R2 is connected between the second gate electrode 10b and the input terminal 26. The gate drive circuit 22 supplies a gate signal to the input terminal 26 according to a signal from the microcomputer.

[0090] Furthermore, the semiconductor chip, first resistor R1, second resistor R2, and gate drive circuit 22, including the semiconductor substrate 1, are mounted on the circuit board and integrated therein. The first gate electrode 10a and the second gate electrode 10b are respectively wire-connected to pads on the circuit board. These structures are connected by wiring on the circuit board.

[0091] In this embodiment, the first resistor R1 is connected between the upper electrode 14 and the input terminal 26, and the second resistor R2 is connected between the lower electrode 12 and the input terminal 26. Furthermore, similar to Embodiment 1, the Cge of the lower electrode 12 is smaller than the Cge of the upper electrode 14. Therefore, similar to Embodiment 1, electromagnetic noise can be sufficiently suppressed in the IGBT construction.

[0092] Furthermore, conventionally, two gate drive circuits are connected to the first gate electrode 10a and the second gate electrode 10b respectively to independently control the voltages of the upper electrode 14 and the lower electrode 12. In contrast, in this embodiment, the voltages of the upper electrode 14 and the lower electrode 12 can be independently controlled by a single gate drive circuit 22, thereby reducing costs.

[0093] Furthermore, the input terminal 26, the first resistor R1, and the second resistor R2 are formed on the outer side of the semiconductor substrate 1. This reduces the resistive region within the substrate, thereby lowering conduction losses, component size, and manufacturing costs. Additionally, the first resistor R1 and the second resistor R2 can be resistors that connect the resistance within the substrate in series with the resistance outside the substrate. This further reduces the resistive region within the substrate.

[0094] Furthermore, the resistance value of the second resistor R2 is preferably less than that of the first resistor R1. This allows for faster charging of the capacitor in the lower electrode 12, thus suppressing electromagnetic noise. On the other hand, when the resistance value of the second resistor R2 is greater than that of the first resistor R1, the increase in gate voltage, determined by displacement current and resistance, increases. Therefore, the voltage of the lower electrode 12 can be made higher than that of the upper electrode 14, reducing Cgc.

[0095] Figure 20 This is a top view showing the semiconductor device according to Embodiment 8. A first gate wiring 18 and a resistor R1′ connect the upper electrode 14 and the input terminal 26. A second gate wiring 19 and a resistor R2′ connect the lower electrode 12 and the input terminal 26. The first resistor R1 is the sum of the resistances of resistor R1′ and the first gate wiring 18. The second resistor R2 is the sum of the resistances of resistor R2′ and the second gate wiring 19. Furthermore, if the length GL2 of the second gate wiring 19 is shorter than the length GL1 of the first gate wiring 18, then even if the resistance values ​​of resistors R1′ and R2′ are the same, the resistance value of the second resistor R2 is less than the resistance value of the first resistor R1.

[0096] Implementation Method 9

[0097] Figure 21 This is a cross-sectional view showing the semiconductor device of Embodiment 9. A first capacitor C1 is connected between the upper electrode 14 and the emitter. A second capacitor C2 is connected between the lower electrode 12 and the emitter. The first capacitor C1 and the second capacitor C2 are formed on the outer side of the semiconductor substrate 1. The second capacitor C2 is smaller than the first capacitor C1. Therefore, the sum of the capacitance values ​​of the lower electrode 12 and the second capacitor C2 is less than the sum of the capacitance values ​​of the upper electrode 14 and the first capacitor C1. Other structures are the same as in Embodiment 1. Alternatively, only one of the first capacitor C1 and the second capacitor C2 may be provided.

[0098] By adding a first capacitor C1 and a second capacitor C2 in addition to the gate capacitances parasitic on the upper electrode 14 and the lower electrode 12, the voltages of the upper electrode 14 and the lower electrode 12 can be independently controlled not only through their respective gate capacitances but also through the added first capacitor C1 and second capacitor C2. Therefore, the voltage control range is expanded, which can further reduce electromagnetic noise.

[0099] Furthermore, since the displacement current can be split into components flowing in the gate capacitances parasitic on the upper electrode 14 and the lower electrode 12, and components flowing in the first capacitor C1 and the second capacitor C2, the displacement current flowing in the gate-emitter capacitances parasitic on the upper electrode 14 and the lower electrode 12 can be reduced. This reduces the voltage overshoot of the upper electrode 14, decreases Icp, and thus reduces electromagnetic noise.

[0100] Figure 22 This is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 9. A first capacitor C1 is connected between the first gate electrode 10a and the emitter. A second capacitor C2 is connected between the second gate electrode 10b and the emitter. The first capacitor C1 and the second capacitor C2 are formed on the outer side of the semiconductor substrate 1. Other structures are the same as in Embodiment 8. Even in this case, the aforementioned effects can be obtained.

[0101] Implementation Method 10

[0102] Figure 23 This is a cross-sectional view showing the semiconductor device of Embodiment 10. A first capacitor C1 is connected between the upper electrode 14 and the collector electrode. A second capacitor C2 is connected between the lower electrode 12 and the collector electrode. The first capacitor C1 and the second capacitor C2 are formed on the outer side of the semiconductor substrate 1. Other structures are the same as in Embodiment 1. Alternatively, only one of the first capacitor C1 and the second capacitor C2 may be provided.

[0103] By adding a first capacitor C1 and a second capacitor C2 in addition to the gate capacitances parasitic on the upper electrode 14 and the lower electrode 12, the voltages of the upper electrode 14 and the lower electrode 12 can be controlled independently not only through their respective gate capacitances but also through the added first capacitor C1 and second capacitor C2. Therefore, the voltage control amplitude is expanded, further reducing electromagnetic noise. In particular, by adding a gate-collector capacitance related to dV / dt, dV / dt is mitigated and the generation of displacement current is suppressed, thereby reducing electromagnetic noise.

[0104] Figure 24 This is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 10. A first capacitor C1 is connected between the first gate electrode 10a and the collector electrode. A second capacitor C2 is connected between the second gate electrode 10b and the collector electrode. The first capacitor C1 and the second capacitor C2 are formed on the outer side of the semiconductor substrate 1. Other structures are the same as in Embodiment 8. Even in this case, the aforementioned effects can be obtained.

[0105] Implementation Method 11

[0106] Figure 25This is a cross-sectional view showing the semiconductor device of Embodiment 11. The cathode of the first diode D1 is connected to the upper electrode 14, and the anode is connected to ground or the emitter. The cathode of the second diode D2 is connected to the lower electrode 12, and the anode is connected to ground or the emitter. The first diode D1 and the second diode D2 are formed on the outer side of the semiconductor substrate 1. Other structures are the same as in Embodiment 1. Alternatively, only one of the first diode D1 and the second diode D2 may be provided.

[0107] By adding a first diode D1 and a second diode D2, parasitic junction capacitances can be added to the diodes. Therefore, the voltages of the upper electrode 14 and the lower electrode 12 can be controlled by the gate capacitance and the junction capacitance. As a result, the voltage control amplitude is increased, which can further reduce the overshoot of Vge caused by displacement current and further reduce electromagnetic noise.

[0108] Figure 26 This is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 11. The cathode of the first diode D1 is connected to the first gate electrode 10a, and the anode is connected to ground or the emitter. The cathode of the second diode D2 is connected to the second gate electrode 10b, and the anode is connected to ground or the emitter. The first diode D1 and the second diode D2 are formed on the outer side of the semiconductor substrate 1. Other structures are the same as in Embodiment 8. Even in this case, the above-described effects can be obtained.

[0109] Implementation Method 12

[0110] Figure 27 This is a cross-sectional view of the semiconductor device according to Embodiment 12. In addition to the first diode D1 and the second diode D2 of Embodiment 11, a first diode D1' and a second diode D2' are also provided. The cathode of the first diode D1 is connected to the power supply of the gate drive circuit 22, and the anode is connected to the upper electrode 14. The cathode of the second diode D2' is connected to the power supply of the gate drive circuit 22, and the anode is connected to the lower electrode 12. The first diodes D1 and D1' constitute a first clamping circuit connected to the upper electrode 14, and the second diodes D2 and D2' constitute a second clamping circuit connected to the lower electrode 12. Other structures are the same as in Embodiment 1. Alternatively, only one of the first clamping circuit and the second clamping circuit may be provided.

[0111] Since the voltages of the upper electrode 14 and the lower electrode 12 are controlled separately in this disclosure, the voltage is prone to increase. Therefore, by providing the clamping circuit described above, the voltage can be limited even if an overvoltage is applied to the upper electrode 14 or the lower electrode 12. Therefore, abnormal operation is suppressed, and damage resistance can be improved.

[0112] Figure 28This is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 12. The first clamping circuit described above is connected to the first gate electrode 10a, and the second clamping circuit described above is connected to the second gate electrode 10b. Other structures are the same as in Embodiment 8. Even in this case, the aforementioned effects can be obtained.

[0113] Implementation Method 13

[0114] Figure 29 This is a cross-sectional view showing the semiconductor device of Embodiment 13. The diode D is on the conduction side. ON Cut-off side diode D OFF On-resistance R ON and cutoff resistance R OFF The diode D is disposed outside the semiconductor substrate 1 and connected to the gate electrode 10. ON The cathode and the cutoff-side diode D OFF The anode of the diode is connected to input terminal 26. The cutoff-side diode D... OFF With the conduction side diode D ON Reverse parallel connection. On-resistance R ON With the conduction side diode D ON Series connection. Cut-off resistor R OFF With the cutoff side diode D OFF Connected in series. Other structures are the same as in Implementation Method 1.

[0115] Because the gate signal's on and off signals flow together in both the first resistor R1 and the second resistor R2, it is impossible to optimize the on and off speeds separately. Therefore, the on-resistance R... ON and cutoff resistance R OFF Diodes D connected in series on the conduction side in reverse parallel connection respectively ON and the cutoff side diode D OFF Therefore, it is possible to distinguish between on and off signals. This is achieved using the on-resistance R. ON and cutoff resistance R OFF The resistance value can be adjusted to change the signal during both on and off states for optimal control.

[0116] Implementation Method 14

[0117] Figure 30 This is a top view showing the semiconductor device of embodiment 14. Figure 31 It means along Figure 30 Cross-sectional views of sections I-II and III-IV. Diode D1 on the first conducting side. ON anode and first cutoff side diode D1 OFF The cathode is connected to the gate electrode 10. The first cutoff-side diode D1 OFFWith the first conducting side diode D1 ON Reverse parallel connection. Diode D1 on the first conducting side. ON The cathode is connected to the upper electrode 14 via gate wiring 18a and contact 20a. First cutoff-side diode D1 OFF The anode is connected to the upper electrode 14 via gate wiring 18b and contact 20b. The first conduction-side diode D1 ON With the first on-resistance R1 ON Series connection. First cutoff side diode D1 OFF With the first cutoff resistor R1 OFF Series connection. When the circuit is closed, the first resistor R1 is equivalent to the first conducting resistor R1. ON The sum of the resistances of the gate wiring 18a and the gate wiring 18a is equivalent to the first cutoff resistance R1 when the gate is turned off. OFF The sum of the resistances of the gate wiring 18b.

[0118] Second conduction side diode D2 ON anode and second cutoff side diode D2 OFF The cathode is connected to the gate electrode 10. The second cutoff-side diode D2... OFF With the second conduction side diode D2 ON Connected in reverse parallel. Second conduction-side diode D2 ON The cathode is connected to the lower electrode 12 via gate wiring 19a and contact 21a. The second cutoff-side diode D2 OFF The anode is connected to the lower electrode 12 via gate wiring 19b and contact 21b. The second on-side diode D2... ON With the second on-resistance R2 ON Series connection. Second cutoff-side diode D2 OFF With the second cutoff resistor R2 OFF Connected in series. When the circuit is closed, the second resistor R2 acts as the second on-resistance R2. ON The sum of the resistances of the gate wiring 19a and the gate wiring 19a is equivalent to the second cutoff resistance R2 when the gate is turned off. OFF The sum of the resistances of the gate wiring 19b and the other components are the same as in Embodiment 1.

[0119] Because the on and off signals of the gate signal flow together in the first resistor R1 and the second resistor R2, it is impossible to optimize the on and off speeds separately. Therefore, the first on resistor R1... ON and the first cutoff resistor R1 OFF The diodes D1, connected in series with each other in reverse parallel, are on the first conducting side. ON and the first cutoff side diode D1 OFF The second on-resistor R2 ON Second cutoff resistor R2OFF The second conduction side diodes D2 are connected in series and in reverse parallel respectively. ON Second cutoff side diode D2 OFF Therefore, the gate current can be changed during turn-on and turn-off respectively. This allows for optimal control with low switching losses, reducing electromagnetic noise during turn-on and turn-off respectively.

[0120] In IGBTs, which are bipolar devices, the switching speed during conduction is typically faster than during cutoff due to the influence of holes, thus contributing to noise and being easily limited by the switching speed. Therefore, to accelerate the speed of the cutoff side, which is less affected by the switching speed, it is preferable to make the first cutoff resistor R1... OFF Less than the first on-resistance R1 ON And make the second cutoff resistor R2 OFF Less than the second on-resistance R2 ON Furthermore, by designing a structure that reduces the hole density inside the device due to factors such as a decrease in the concentration of the collector layer 5 or changes in carrier lifetime, a situation may arise where the velocity on the cutoff side is faster than the velocity on the conduction side. In this case, the first cutoff resistor R1... OFF Conversely, it is greater than the first on-resistance R1. ON This makes the second on-resistance R2 ON Greater than the second on-resistance R2 ON .

[0121] Implementation Method 15

[0122] Figure 32 This is a top view showing the semiconductor device of Embodiment 15. First conduction-side diode D1 ON Cathode and first cutoff side diode D1 OFF The anode is connected to the upper electrode 14 via the first gate electrode 10a. The first on-side diode D1... ON anode and first cutoff side diode D1 OFF The cathode is connected to input terminal 26. First cutoff-side diode D1 OFF With the first conducting side diode D1 ON Reverse parallel connection. Diode D1 on the first conducting side. ON With the first on-resistance R1 ON Series connection. First cutoff side diode D1 OFF With the first cutoff resistor R1 OFF Series connection. When the circuit is closed, the first resistor R1 is equivalent to the first conducting resistor R1. ON When turned off, it is equivalent to the first cutoff resistor R1. OFF .

[0123] Second conduction side diode D2ON Cathode and second cutoff side diode D2 OFF The anode is connected to the upper electrode 14 via the second gate electrode 10b. The second on-side diode D2... ON anode and second cutoff side diode D2 OFF The cathode is connected to input terminal 26. The second cutoff-side diode D2 OFF With the second conduction side diode D2 ON Connected in reverse parallel. Second conduction-side diode D2 ON With the second on-resistance R2 ON Series connection. Second cutoff-side diode D2 OFF With the second cutoff resistor R2 OFF Connected in series. Other structures are the same as in implementation method 8.

[0124] Because the on and off signals of the gate signal flow together in the first resistor R1 and the second resistor R2, it is impossible to optimize the on and off speeds separately. Therefore, the first on resistor R1... ON and the first cutoff resistor R1 OFF The diodes D1, connected in series with each other in reverse parallel, are on the first conducting side. ON and the first cutoff side diode D1 OFF The second on-resistor R2 ON Second cutoff resistor R2 OFF The second conduction side diodes D2 are connected in series and in reverse parallel respectively. ON Second cutoff side diode D2 OFF Therefore, the gate current can be changed during turn-on and turn-off respectively. This allows for optimal control with low switching losses, reducing electromagnetic noise during turn-on and turn-off respectively.

[0125] Implementation Method 16

[0126] Figure 33 This is a cross-sectional view showing the semiconductor device of Embodiment 16. The semiconductor device of this embodiment is an RC (Reverse Conducting)-IGBT comprising an IGBT region including a collector layer 5 of a second conductivity type and a diode region including a cathode layer 5b of a first conductivity type formed beneath the drift layer 2. In an RC-IGBT, holes flowing in the diode region sometimes flow into the IGBT region during recovery operation, generating displacement current, increasing Icp, and deteriorating noise. By applying the structure disclosed herein, noise can be suppressed even in an RC-IGBT. Figure 34 This is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 16. A dummy trench 23 is disposed in the diode region instead of the trench 8. This reduces the gate capacitance.

[0127] In embodiments 1 to 16 described above, the first resistor R1 and the second resistor R2 can be units that create a difference in the magnitude of the gate current, that is, units that create a difference in the speed (mobility) of charge flow. For example, the first resistor R1 and the second resistor R2 can be ICs in the gate drive circuit, or they can be the on-resistance of MOSFETs in the gate drive circuit.

[0128] When multiple semiconductor devices are connected in parallel, differences in gate wiring length and other parameters arise due to chip configuration, resulting in uneven wiring inductance. This leads to an imbalance in current distribution during switching, which can easily generate noise. By applying the above-described implementation method, noise can be reduced even when multiple semiconductor devices are connected in parallel.

[0129] Preferably, the semiconductor substrate 1 and the input terminal 26, the first resistor R1, the second resistor R2, and the gate drive circuit 22 on the outside of the substrate are integrated on the circuit board. This enables the miniaturization of the semiconductor device. In addition, by reducing the number of components and simplifying the design, the parasitic inductive component that affects electromagnetic noise can be reduced, thereby reducing electromagnetic noise.

[0130] Figure 35 This is a graph showing the Vce dependence of Cge. Vge = 0V. Although the gate capacitance varies with Vce, Cge in this disclosure is the gate-emitter capacitance under the condition of Vce = 10V and Vge = 0V, which is typically used in IGBT product datasheets. The same applies to Cies and Cgc.

[0131] Figure 36 This graph shows the relationship between the CR time constant (the product of the gate-emitter capacitance and the second resistor of the lower electrode) and the CR time constant (the product of the gate-emitter capacitance and the first resistor of the upper electrode), and the peak value of Ic. The smaller the ratio of the CR time constant (Cge2×R2) of the gate-emitter capacitance Cge2 and the second resistor R2 of the lower electrode 12 to the CR time constant (Cge1×R1) of the gate-emitter capacitance Cge1 and the first resistor R1 of the upper electrode 14, the lower the peak value of Ic. The peak value of Ic decreases by decreasing this ratio, gradually decreasing from 0.13 to 0.1, then sharply decreasing from 0.1 to 0.05, and further decreasing even below 0.05. By keeping this ratio below 0.13, the capacitor of the lower electrode 12 can be charged faster, thus reducing electromagnetic noise. It is preferable to keep this ratio below 0.1, and more preferably below 0.05. Furthermore, the relationship between Cge2×R2′ / Cge1×R1′ and the peak value of Ic is also similar.

[0132] The upper limit of the resistance values ​​of the first resistor R1 and the second resistor R2 is, for example, 10000Ω or less, preferably 1000Ω or less, and more preferably 100Ω or less. This shortens the charging period of the upper electrode 14 and the lower electrode 12, thereby reducing switching losses and noise. Furthermore, the lower limit of the resistance values ​​of the first resistor R1 and the second resistor R2 is, for example, 0Ω or more, preferably 1Ω or more, and more preferably 10Ω or more. This allows adjustment of the gate current flowing in the upper electrode 14 and the lower electrode 12, thereby reducing switching losses and noise.

[0133] Figure 37 This is a graph showing the relationship between the ratio of the resistance value of the second resistor to the resistance value of the first resistor and the peak value of Ic. By making the ratio of this resistor 1.8 or less, the capacitor of the lower electrode 12 can be charged quickly, thus reducing electromagnetic noise. The peak value of Ic decreases by decreasing the ratio, gradually decreasing from 1.8 to 1.5, then sharply decreasing from 1.5 to 0.7, and further decreasing even below 0.3. Therefore, by making the ratio 1.5 or less, electromagnetic noise can be further reduced. Preferably, the ratio is 0.7 or less, and more preferably 0.3 or less. In addition, to reduce the ratio, the resistance value of the second resistor R2 can be 1Ω or less, or even 0Ω. When the resistance value of the second resistor R2 is 0Ω, the value of the gate current is controlled by the resistance of the second gate wiring 19 or the wiring resistance of the lower electrode 12 itself. Furthermore, the relationship between the ratio of the resistance value of resistor R2′ to the resistance value of resistor R1′ and the peak value of Ic is also the same.

[0134] Figure 38 This is a current-voltage diagram showing the lower and upper electrodes when the circuit is turned on. During the initial period of gate voltage increase upon turn-on, there is a period during which the current in the lower electrode 12 is higher than the current in the upper electrode 14. Therefore, the lower electrode 12 can be charged quickly, and electromagnetic noise is reduced.

[0135] Furthermore, the semiconductor substrate 1 is not limited to being formed of silicon; it can also be formed of a wide-bandgap semiconductor with a larger bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride-based materials, or diamond. Semiconductor chips formed from such wide-bandgap semiconductors exhibit high voltage withstand capability and allowable current density, thus enabling miniaturization. By using this miniaturized semiconductor chip, semiconductor devices assembled with it can also be miniaturized and highly integrated. Additionally, due to the high heat resistance of the semiconductor chip, the heat sink can be miniaturized, and the water-cooling section can be air-cooled, further miniaturizing the semiconductor device. Furthermore, the low power loss and high efficiency of the semiconductor chip enable high efficiency in semiconductor devices.

[0136] Implementation Method 17

[0137] This embodiment applies the semiconductor devices described in Embodiments 1 to 16 to a power conversion device, thereby constructing a power conversion system including the power conversion device. This disclosure is not limited to a specific power conversion device, but an example of a three-phase inverter will be described below.

[0138] Figure 39 This is a block diagram illustrating the structure of a power conversion system according to embodiment 17. The power conversion system includes a power source 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source, supplying DC power to the power conversion device 200. The power source 100 can be composed of various components, such as a DC system, solar cells, a battery, or a rectifier circuit or AC / DC converter connected to an AC system. Alternatively, the power source 100 can be composed of a DC / DC converter that converts DC power output from a DC system into a specified power.

[0139] The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, which converts the DC power supplied from the power supply 100 into AC power and supplies AC power to the load 300. The power conversion device 200 includes: a main conversion circuit 201, which converts DC power into AC power and outputs it; a gate drive circuit 22, which outputs drive signals to drive each switching element of the main conversion circuit 201; and a control circuit 202, which outputs control signals to control the gate drive circuit 22.

[0140] Load 300 is a three-phase electric motor driven by AC power supplied from power conversion device 200. Furthermore, load 300 is not limited to a specific application, but is an electric motor mounted on various electrical equipment, such as those used in hybrid vehicles, electric vehicles, railway vehicles, elevators, or for air conditioning equipment.

[0141] The power conversion device 200 will now be described in detail. The main conversion circuit 201 includes switching elements and circulating diodes (not shown). By switching the switching elements, it converts the DC power supplied from the power source 100 into AC power and supplies it to the load 300. Although the specific circuit structure of the main conversion circuit 201 can vary, the main conversion circuit 201 in this embodiment is a two-level three-phase full-bridge circuit, which can be constructed from six switching elements and six circulating diodes connected in anti-parallel to each switching element. The semiconductor devices described in any of the embodiments 1 to 16 above are used for each switching element of the main conversion circuit 201. In the six switching elements, every two switching elements are connected in series to form upper and lower branches, and each upper and lower branch constitutes a phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower branch, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0142] In order to increase the current that the power conversion device 200 can handle, the main conversion circuit 201 has multiple switching elements, in other words, multiple semiconductor devices, which can be connected in parallel in the main conversion circuit 201.

[0143] Here, if the semiconductor devices of embodiments 1 to 16 described above are used for all of the preferred switching elements, the noise generated from the power conversion device can be reduced. RC (Reverse Conducting) IGBTs, which function as circulating diodes, can also be used for the switching elements.

[0144] The gate drive circuit 22 generates drive signals to drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, based on the control signal from the control circuit 202 (described later), drive signals that turn the switching elements on and off are output to the control electrodes of each switching element. When the switching element is held on, the drive signal is a voltage signal above the threshold voltage of the switching element (on signal); when the switching element is held off, the drive signal is a voltage signal below the threshold voltage of the switching element (off signal).

[0145] Control circuit 202 controls the switching elements of main conversion circuit 201 to supply the desired power to load 300. Specifically, based on the power to be supplied to load 300, the time (on-time) during which each switching element of main conversion circuit 201 should be in the on state is calculated. For example, main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching elements according to the voltage to be output. Moreover, control commands (control signals) are output to gate drive circuit 22, causing on signals to be output to the switching elements that should be in the on state at each time, and off signals to be output to the switching elements that should be in the off state.

[0146] The gate drive circuit 22 outputs a turn-on signal or a turn-off signal to the control electrode of each switching element as a drive signal according to the control signal.

[0147] In the power conversion device 200 of this embodiment, the semiconductor device of embodiments 1 to 16 is used as the switching element of the main conversion circuit 201, thus enabling the power conversion device 200 to achieve low loss and improved reliability of high-speed switching.

[0148] In this embodiment, an example of applying this disclosure to a 2-level three-phase inverter has been described, but this disclosure is not limited to this and can be applied to various power conversion devices 200. Although this embodiment describes a 2-level power conversion device 200, it can also be a 3-level or multi-level power conversion device 200. Furthermore, this invention can be applied to a single-phase inverter when supplying power to a single-phase load. Additionally, this disclosure can be applied to a DC / DC converter or an AC / DC converter when supplying power to a DC load, etc.

[0149] Furthermore, the application of the power conversion device 200 disclosed herein is not limited to the case where the load 300 is an electric motor. For example, it can also be used as a power supply device for an electrical discharge machining machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and it can also be used as a power regulator for a solar power generation system or an energy storage system.

[0150] While the preferred embodiments have been described in detail above, the invention is not limited to these embodiments. Various modifications and substitutions can be made to the embodiments without departing from the scope of the claims. Hereinafter, various aspects of this disclosure will be described as appendices.

[0151] (Note 1) A semiconductor device, characterized in that it comprises:

[0152] A semiconductor substrate having a drift layer of a first conductivity type, a base layer of a second conductivity type formed on the drift layer, a source layer of the first conductivity type formed on the base layer, and a collector layer of the second conductivity type formed below the drift layer.

[0153] An emitter electrode is formed on the upper surface of the semiconductor substrate and connected to the base layer and the source layer;

[0154] A collector electrode is formed on the lower surface of the semiconductor substrate and connected to the collector layer;

[0155] The lower electrode is formed via a lower gate insulating film inside a trench that extends from the upper surface of the semiconductor substrate through the source layer and the base layer;

[0156] The upper electrode is formed inside the trench via an upper gate insulating film and disposed on the lower electrode, and is separated from the lower electrode by an intermediate insulating film;

[0157] Input terminals;

[0158] A first resistor is connected between the upper electrode and the input terminal; and

[0159] The second resistor is connected between the lower electrode and the input terminal.

[0160] The gate-emitter capacitance of the lower electrode is smaller than that of the gate-emitter capacitance of the upper electrode.

[0161] (Note 2) The semiconductor device according to Note 1 is characterized in that,

[0162] The input terminal is a gate electrode formed on the upper surface of the semiconductor substrate.

[0163] (Note 3) The semiconductor device according to Note 1 is characterized in that,

[0164] The input terminal, the first resistor, and the second resistor are formed on the outer side of the semiconductor substrate.

[0165] (Appendix 4) The semiconductor device according to any one of Appendices 1 to 3, characterized in that,

[0166] During the period of increased current upon connection, there exists a period in which the voltage of the lower electrode is higher than the voltage of the upper electrode.

[0167] (Appendix 5) The semiconductor device according to any one of Appendices 1 to 4, characterized in that,

[0168] During the initial period of gate voltage increase upon turn-on, there is a period during which the current of the lower electrode is higher than the current of the upper electrode.

[0169] (Appendix 6) The semiconductor device according to any one of Appendices 1 to 5, characterized in that,

[0170] The ratio of the gate-emitter capacitance of the lower electrode to the gate-emitter capacitance of the upper electrode is less than 0.5.

[0171] (Appendix 7) The semiconductor device according to any one of Appendices 1 to 5, characterized in that,

[0172] The ratio of the gate-emitter capacitance of the lower electrode to the gate-emitter capacitance of the upper electrode is 0.2 or less.

[0173] (Appendix 8) The semiconductor device according to any one of Appendices 1 to 7, characterized in that,

[0174] During the Miller period when the circuit is turned on, there is a period in which the voltage of the lower electrode is lower than the voltage of the upper electrode.

[0175] (Appendix 9) The semiconductor device according to any one of Appendices 1 to 8, characterized in that,

[0176] The thickness of the lower gate insulating film covering the sides and bottom of the lower electrode is greater than the thickness of the upper gate insulating film covering the sides of the upper electrode.

[0177] (Note 10) The semiconductor device according to Note 9 is characterized in that,

[0178] The thickness of the lower gate insulating film is more than 1.5 times the thickness of the upper gate insulating film.

[0179] (Note 11) The semiconductor device according to Note 9 is characterized in that,

[0180] The thickness of the lower gate insulating film is more than twice the thickness of the upper gate insulating film.

[0181] (Note 12) The semiconductor device according to Note 9 is characterized in that,

[0182] The thickness of the lower gate insulating film is more than 2.5 times the thickness of the upper gate insulating film.

[0183] (Note 13) The semiconductor device according to any one of Notes 1 to 12, characterized in that,

[0184] The thickness of the intermediate insulating film is greater than the thickness of the upper gate insulating film on the side of the upper electrode.

[0185] (Note 14) The semiconductor device according to any one of Notes 1 to 14, characterized in that,

[0186] The CR time constant formed by the gate capacitance of the lower electrode and the second resistor is less than the CR time constant formed by the gate capacitance of the upper electrode and the first resistor.

[0187] (Note 15) The semiconductor device according to any one of Notes 1 to 14, characterized in that,

[0188] The CR time constant, which is the product of the gate-emitter capacitance of the lower electrode and the second resistor, is 0.13 or less relative to the CR time constant, which is the product of the gate-emitter capacitance of the upper electrode and the first resistor.

[0189] (Note 16) The semiconductor device according to any one of Notes 1 to 15, characterized in that,

[0190] The resistance value of the second resistor is less than the resistance value of the first resistor.

[0191] (Note 17) The semiconductor device according to any one of Notes 1 to 15, characterized in that,

[0192] The resistance value of the second resistor is greater than the resistance value of the first resistor.

[0193] (Note 18) The semiconductor device according to any one of Notes 1 to 15, characterized in that,

[0194] The ratio of the resistance value of the second resistor to the resistance value of the first resistor is less than 1.8.

[0195] (Note 19) The semiconductor device according to any one of Notes 1 to 18 is characterized in that,

[0196] It also has a carrier accumulation layer of a first conductivity type, which is formed between the drift layer and the base layer, and the impurity concentration is higher than that of the drift layer.

[0197] (Note 20) The semiconductor device according to Note 19 is characterized in that,

[0198] The length of the carrier accumulation layer opposite the side of the lower electrode is longer than the length of the carrier accumulation layer opposite the side of the upper electrode.

[0199] (Note 21) The semiconductor device according to Note 19 is characterized in that,

[0200] The length of the carrier accumulation layer opposite to the side of the lower electrode is longer than the length of the drift layer opposite to the side of the lower electrode.

[0201] (Note 22) The semiconductor device according to any one of Notes 1 to 21, characterized in that,

[0202] The length of the lower electrode is longer than the length of the upper electrode that extends downward from the base layer.

[0203] (Note 23) The semiconductor device according to any one of Notes 1 to 22, characterized in that,

[0204] The depth of the base layer is greater than the length of the upper electrode extending downward from the base layer.

[0205] (Note 24) The semiconductor device according to any one of Notes 1 to 23 is characterized in that,

[0206] Multiple trenches are formed side-by-side on the semiconductor substrate.

[0207] The width of the platform between adjacent grooves is narrower than the width of the groove.

[0208] (Note 25) The semiconductor device according to Note 2 is characterized in that it further comprises:

[0209] A first gate wiring connects the upper electrode to the gate electrode; and

[0210] A second gate wiring connects the lower electrode to the gate electrode.

[0211] The length of the second gate wiring is shorter than the length of the first gate wiring.

[0212] (Note 26) The semiconductor device according to Note 2 is characterized in that it further comprises:

[0213] A first gate wiring connects the upper electrode to the gate electrode; and

[0214] A second gate wiring connects the lower electrode to the gate electrode.

[0215] The length of the second gate wiring is longer than the length of the first gate wiring.

[0216] (Note 27) The semiconductor device according to Note 25 is characterized in that,

[0217] The upper electrode is connected to the first gate wiring via the first gate contact.

[0218] The lower electrode is connected to the second gate wiring via the second gate contact.

[0219] (Note 28) The semiconductor device according to Note 2 is characterized in that,

[0220] It also includes a gate resistor, which is disposed outside the semiconductor substrate and connected to the gate electrode.

[0221] The gate resistor has a resistance value larger than that of the first resistor and the second resistor, and is formed on the outer side of the semiconductor substrate.

[0222] (Note 29) The semiconductor device according to Note 2 is characterized in that,

[0223] It also includes a gate resistor, which is disposed outside the semiconductor substrate and connected to the gate electrode.

[0224] The gate resistor has a resistance value smaller than that of the first resistor and the second resistor, and is formed on the outside of the semiconductor substrate.

[0225] (Note 30) The semiconductor device according to any one of Notes 1 to 29 is characterized in that,

[0226] It also includes a dummy lower electrode, which is formed via the lower gate insulating film inside a dummy trench extending from the upper surface of the semiconductor substrate through the source layer and the base layer, and is connected to the emitter electrode.

[0227] The upper electrode is formed inside the dummy trench via the upper gate insulating film and is disposed above the dummy lower electrode, and is separated from the dummy lower electrode by the intermediate insulating film.

[0228] (Note 31) The semiconductor device according to any one of Notes 1 to 29 is characterized in that,

[0229] It also includes a dummy upper electrode, which is formed via the upper gate insulating film inside a dummy trench extending from the upper surface of the semiconductor substrate through the source layer and the base layer, and is connected to the emitter electrode.

[0230] The lower electrode is formed inside the dummy trench via the lower gate insulating film and is disposed below the dummy upper electrode, and is separated from the dummy upper electrode by the intermediate insulating film.

[0231] (Note 32) The semiconductor device according to any one of Notes 1 to 29 is characterized in that it further comprises:

[0232] A dummy lower electrode is formed via the lower gate insulating film within a dummy trench extending from the upper surface of the semiconductor substrate through the source layer and the base layer, and is connected to the emitter electrode; and

[0233] A dummy upper electrode is formed inside the dummy trench via the upper gate insulating film and disposed above the dummy lower electrode, and is separated from the dummy lower electrode by the intermediate insulating film.

[0234] (Note 33) The semiconductor device according to any one of Notes 1 to 29 is characterized in that,

[0235] It also includes a dummy electrode, which is formed via a gate insulating film inside a dummy trench that extends from the upper surface of the semiconductor substrate through the source layer and the base layer, and is connected to the emitter electrode.

[0236] (Note 34) The semiconductor device according to any one of Notes 1 to 33 is characterized in that,

[0237] It includes at least one of a first capacitor connected between the upper electrode and the emitter, and a second capacitor connected between the lower electrode and the emitter.

[0238] (Note 35) The semiconductor device according to Note 34 is characterized in that,

[0239] The sum of the gate-emitter capacitance of the lower electrode and the second capacitance is less than the sum of the gate-emitter capacitance of the upper electrode and the first capacitance.

[0240] (Note 36) The semiconductor device according to any one of Notes 1 to 33 is characterized in that,

[0241] It includes at least one of a first capacitor connected between the upper electrode and the collector, and a second capacitor connected between the lower electrode and the collector.

[0242] (Note 37) The semiconductor device according to any one of Notes 1 to 36 is characterized in that,

[0243] The device includes at least one of a first diode and a second diode, wherein the cathode of the first diode is connected to the upper electrode and the anode is connected to ground or the emitter, and the cathode of the second diode is connected to the lower electrode and the anode is connected to ground or the emitter.

[0244] (Note 38) The semiconductor device according to any one of Notes 1 to 36 is characterized in that,

[0245] It has a clamping circuit connected to the upper electrode or the lower electrode.

[0246] (Note 39) The semiconductor device according to any one of Notes 1 to 38 is characterized in that it further comprises:

[0247] A diode on the conduction side, the cathode of which is connected to the input terminal;

[0248] The cutoff diode has its anode connected to the input terminal and is connected in reverse parallel with the on-side diode;

[0249] The on-resistance is connected in series with the on-side diode; and

[0250] A cutoff resistor, which is connected in series with the cutoff-side diode.

[0251] (Note 40) The semiconductor device according to any one of Notes 1 to 39, characterized in that it comprises:

[0252] The first conduction-side diode has its anode connected to the input terminal and its cathode connected to the upper electrode;

[0253] The first on-resistance is connected in series with the first on-side diode;

[0254] The first cutoff diode has its cathode connected to the input terminal, its anode connected to the upper electrode, and is connected in reverse parallel with the first on-side diode.

[0255] The first cutoff resistor is connected in series with the first cutoff-side diode;

[0256] The second conduction-side diode has its anode connected to the input terminal and its cathode connected to the lower electrode;

[0257] The second on-resistor is connected in series with the second on-side diode;

[0258] The second cutoff diode has its cathode connected to the input terminal and its anode connected to the lower electrode, and is connected in reverse parallel with the second on-side diode; and

[0259] The second cutoff resistor is connected in series with the second cutoff-side diode.

[0260] The first resistor has either the first on-resistance or the first off-resistance.

[0261] The second resistor has the second on-resistance or the second off-resistance.

[0262] (Note 41) The semiconductor device according to Note 40 is characterized in that,

[0263] The first cutoff resistance is less than the first on-resistance.

[0264] The second cutoff resistor is less than the second on-resistance.

[0265] (Note 42) The semiconductor device according to any one of Notes 1 to 41 is characterized in that,

[0266] It comprises: an IGBT region including the collector layer, and a diode region including a cathode layer of a first conductivity type formed beneath the drift layer.

[0267] (Appendix 43) A semiconductor device, characterized in that,

[0268] Multiple semiconductor devices described in any of Appendices 1 to 42 are connected in parallel.

[0269] (Note 44) The semiconductor device according to any one of Notes 1 to 43 is characterized in that,

[0270] The semiconductor substrate, the input terminal, the first resistor, and the second resistor are integrated into one unit.

[0271] (Note 45) The semiconductor device according to any one of Notes 1 to 44 is characterized in that,

[0272] The semiconductor substrate is formed of a wide-bandgap semiconductor.

[0273] (Note 46) The semiconductor device according to any one of Notes 1 to 45 is characterized in that,

[0274] It also includes a gate drive circuit that supplies a gate signal to the input terminal.

[0275] (Appendix 47) A power conversion device, characterized in that it comprises:

[0276] A main conversion circuit having a semiconductor device as described in any one of Appendices 1 to 46, which converts and outputs the input power;

[0277] A driving circuit that outputs a driving signal to the semiconductor device; and

[0278] The control circuit outputs control signals to the drive circuit.

Claims

1. A semiconductor device, characterized in that, have: A semiconductor substrate having a drift layer of a first conductivity type, a base layer of a second conductivity type formed on the drift layer, a source layer of the first conductivity type formed on the base layer, and a collector layer of the second conductivity type formed below the drift layer. An emitter electrode is formed on the upper surface of the semiconductor substrate and connected to the base layer and the source layer; A collector electrode is formed on the lower surface of the semiconductor substrate and connected to the collector layer; The lower electrode is formed via a lower gate insulating film inside a trench that extends from the upper surface of the semiconductor substrate through the source layer and the base layer; The upper electrode is formed inside the trench via an upper gate insulating film and disposed on the lower electrode, and is separated from the lower electrode by an intermediate insulating film; Input terminals; A first resistor is connected between the upper electrode and the input terminal; as well as The second resistor is connected between the lower electrode and the input terminal. The gate-emitter capacitance of the lower electrode is smaller than that of the gate-emitter capacitance of the upper electrode.

2. The semiconductor device according to claim 1, characterized in that, The input terminal is a gate electrode formed on the upper surface of the semiconductor substrate.

3. The semiconductor device according to claim 1, characterized in that, The input terminal, the first resistor, and the second resistor are formed on the outer side of the semiconductor substrate.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, During the period of increased current upon connection, there exists a period in which the voltage of the lower electrode is higher than the voltage of the upper electrode.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that, During the initial period of gate voltage increase upon turn-on, there is a period during which the current of the lower electrode is higher than the current of the upper electrode.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that, The ratio of the gate-emitter capacitance of the lower electrode to the gate-emitter capacitance of the upper electrode is less than 0.

5.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that, The ratio of the gate-emitter capacitance of the lower electrode to the gate-emitter capacitance of the upper electrode is 0.2 or less.

8. The semiconductor device according to any one of claims 1 to 3, characterized in that, During the Miller period when the circuit is turned on, there is a period in which the voltage of the lower electrode is lower than the voltage of the upper electrode.

9. The semiconductor device according to any one of claims 1 to 3, characterized in that, The thickness of the lower gate insulating film covering the sides and bottom of the lower electrode is greater than the thickness of the upper gate insulating film covering the sides of the upper electrode.

10. The semiconductor device according to claim 9, characterized in that, The thickness of the lower gate insulating film is more than 1.5 times the thickness of the upper gate insulating film.

11. The semiconductor device according to claim 9, characterized in that, The thickness of the lower gate insulating film is more than twice the thickness of the upper gate insulating film.

12. The semiconductor device according to claim 9, characterized in that, The thickness of the lower gate insulating film is more than 2.5 times the thickness of the upper gate insulating film.

13. The semiconductor device according to any one of claims 1 to 3, characterized in that, The thickness of the intermediate insulating film is greater than the thickness of the upper gate insulating film on the side of the upper electrode.

14. The semiconductor device according to any one of claims 1 to 3, characterized in that, The CR time constant formed by the gate capacitance of the lower electrode and the second resistor is less than the CR time constant formed by the gate capacitance of the upper electrode and the first resistor.

15. The semiconductor device according to any one of claims 1 to 3, characterized in that, The CR time constant, which is the product of the gate-emitter capacitance of the lower electrode and the second resistor, is 0.13 or less relative to the CR time constant, which is the product of the gate-emitter capacitance of the upper electrode and the first resistor.

16. The semiconductor device according to any one of claims 1 to 3, characterized in that, The resistance value of the second resistor is less than the resistance value of the first resistor.

17. The semiconductor device according to any one of claims 1 to 3, characterized in that, The resistance value of the second resistor is greater than the resistance value of the first resistor.

18. The semiconductor device according to any one of claims 1 to 3, characterized in that, The ratio of the resistance value of the second resistor to the resistance value of the first resistor is less than 1.

8.

19. The semiconductor device according to any one of claims 1 to 3, characterized in that, It also has a carrier accumulation layer of a first conductivity type, which is formed between the drift layer and the base layer, and the impurity concentration is higher than that of the drift layer.

20. The semiconductor device according to claim 19, characterized in that, The length of the carrier accumulation layer opposite the side of the lower electrode is longer than the length of the carrier accumulation layer opposite the side of the upper electrode.

21. The semiconductor device according to claim 19, characterized in that, The length of the carrier accumulation layer opposite to the side of the lower electrode is longer than the length of the drift layer opposite to the side of the lower electrode.

22. The semiconductor device according to any one of claims 1 to 3, characterized in that, The length of the lower electrode is longer than the length of the upper electrode that extends downward from the base layer.

23. The semiconductor device according to any one of claims 1 to 3, characterized in that, The depth of the base layer is greater than the length of the upper electrode extending downward from the base layer.

24. The semiconductor device according to any one of claims 1 to 3, characterized in that, Multiple trenches are formed side-by-side on the semiconductor substrate. The width of the platform between adjacent grooves is narrower than the width of the groove.

25. The semiconductor device according to claim 2, characterized in that, It also has: A first gate wiring connects the upper electrode to the gate electrode; and A second gate wiring connects the lower electrode to the gate electrode. The length of the second gate wiring is shorter than the length of the first gate wiring.

26. The semiconductor device according to claim 2, characterized in that, It also has: A first gate wiring connects the upper electrode to the gate electrode; and A second gate wiring connects the lower electrode to the gate electrode. The length of the second gate wiring is longer than the length of the first gate wiring.

27. The semiconductor device according to claim 25, characterized in that, The upper electrode is connected to the first gate wiring via the first gate contact. The lower electrode is connected to the second gate wiring via the second gate contact.

28. The semiconductor device according to claim 2, characterized in that, It also includes a gate resistor, which is disposed outside the semiconductor substrate and connected to the gate electrode. The gate resistor has a resistance value larger than that of the first resistor and the second resistor, and is formed on the outer side of the semiconductor substrate.

29. The semiconductor device according to claim 2, characterized in that, It also includes a gate resistor, which is disposed outside the semiconductor substrate and connected to the gate electrode. The gate resistor has a resistance value smaller than that of the first resistor and the second resistor, and is formed on the outside of the semiconductor substrate.

30. The semiconductor device according to any one of claims 1 to 3, characterized in that, It also includes a dummy lower electrode, which is formed via the lower gate insulating film inside a dummy trench extending from the upper surface of the semiconductor substrate through the source layer and the base layer, and is connected to the emitter electrode. The upper electrode is formed inside the dummy trench via the upper gate insulating film and is disposed above the dummy lower electrode, and is separated from the dummy lower electrode by the intermediate insulating film.

31. The semiconductor device according to any one of claims 1 to 3, characterized in that, It also includes a dummy upper electrode, which is formed via the upper gate insulating film inside a dummy trench extending from the upper surface of the semiconductor substrate through the source layer and the base layer, and is connected to the emitter electrode. The lower electrode is formed inside the dummy trench via the lower gate insulating film and is disposed below the dummy upper electrode, and is separated from the dummy upper electrode by the intermediate insulating film.

32. The semiconductor device according to any one of claims 1 to 3, characterized in that, It also has: A dummy lower electrode is formed via the lower gate insulating film inside a dummy trench that extends from the upper surface of the semiconductor substrate through the source layer and the base layer, and is connected to the emitter electrode. and A dummy upper electrode is formed inside the dummy trench via the upper gate insulating film and disposed above the dummy lower electrode, and is separated from the dummy lower electrode by the intermediate insulating film.

33. The semiconductor device according to any one of claims 1 to 3, characterized in that, It also includes a dummy electrode, which is formed via a gate insulating film inside a dummy trench that extends from the upper surface of the semiconductor substrate through the source layer and the base layer, and is connected to the emitter electrode.

34. The semiconductor device according to any one of claims 1 to 3, characterized in that, It includes at least one of a first capacitor connected between the upper electrode and the emitter, and a second capacitor connected between the lower electrode and the emitter.

35. The semiconductor device according to claim 34, characterized in that, The sum of the gate-emitter capacitance of the lower electrode and the second capacitance is less than the sum of the gate-emitter capacitance of the upper electrode and the first capacitance.

36. The semiconductor device according to any one of claims 1 to 3, characterized in that, It includes at least one of a first capacitor connected between the upper electrode and the collector, and a second capacitor connected between the lower electrode and the collector.

37. The semiconductor device according to any one of claims 1 to 3, characterized in that, The device includes at least one of a first diode and a second diode, wherein the cathode of the first diode is connected to the upper electrode and the anode is connected to ground or the emitter, and the cathode of the second diode is connected to the lower electrode and the anode is connected to ground or the emitter.

38. The semiconductor device according to any one of claims 1 to 3, characterized in that, It has a clamping circuit connected to the upper electrode or the lower electrode.

39. The semiconductor device according to any one of claims 1 to 3, characterized in that, It also has: A diode on the conduction side, the cathode of which is connected to the input terminal; The cutoff diode has its anode connected to the input terminal and is connected in reverse parallel with the on-side diode; The on-resistance is connected in series with the on-side diode; and A cutoff resistor, which is connected in series with the cutoff-side diode.

40. The semiconductor device according to any one of claims 1 to 3, characterized in that, have: The first conduction-side diode has its anode connected to the input terminal and its cathode connected to the upper electrode; The first on-resistance is connected in series with the first on-side diode; The first cutoff diode has its cathode connected to the input terminal, its anode connected to the upper electrode, and is connected in reverse parallel with the first on-side diode. The first cutoff resistor is connected in series with the first cutoff-side diode; The second conduction-side diode has its anode connected to the input terminal and its cathode connected to the lower electrode; The second on-resistor is connected in series with the second on-side diode; The second cutoff diode has its cathode connected to the input terminal and its anode connected to the lower electrode, and is connected in reverse parallel with the second on-side diode; and The second cutoff resistor is connected in series with the second cutoff-side diode. The first resistor has either the first on-resistance or the first off-resistance. The second resistor has the second on-resistance or the second off-resistance.

41. The semiconductor device according to claim 40, characterized in that, The first cutoff resistance is less than the first on-resistance. The second cutoff resistor is less than the second on-resistance.

42. The semiconductor device according to any one of claims 1 to 3, characterized in that, It comprises: an IGBT region including the collector layer, and a diode region including a cathode layer of a first conductivity type formed beneath the drift layer.

43. A semiconductor device, characterized in that, Multiple semiconductor devices according to any one of claims 1 to 3 are connected in parallel.

44. The semiconductor device according to claim 3, characterized in that, The semiconductor substrate, the input terminal, the first resistor, and the second resistor are integrated into one unit.

45. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor substrate is formed of a wide-bandgap semiconductor.

46. ​​The semiconductor device according to any one of claims 1 to 3, characterized in that, It also includes a gate drive circuit that supplies a gate signal to the input terminal.

47. A power conversion device, characterized in that, have: A main conversion circuit having a semiconductor device as described in any one of claims 1 to 3, which converts and outputs the input power; A driving circuit that outputs a driving signal to the semiconductor device; as well as The control circuit outputs control signals to the drive circuit.

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