Front-side-bonded heterogeneous integrated chip and preparation method thereof

Abstract

The invention provides a front-side-bonded heterogeneous integrated chip and a preparation method thereof. A silicon nitride waveguide layer of the heterogeneous integrated chip is arranged on a silicon waveguide layer and is coupled with the silicon waveguide layer; the lithium niobate waveguide layer is arranged on one side, deviating from the silicon waveguide layer, of the silicon nitride waveguide layer and is coupled with the silicon nitride waveguide layer; the lithium niobate waveguide layer comprises a first sub-waveguide layer and a second sub-waveguide layer which are connected with each other, the second sub-waveguide layer is arranged on one side of the silicon nitride waveguide layer, orthographic projections of the second sub-waveguide layer and the silicon nitride waveguide layer on the silicon waveguide layer are mutually overlapped, and the first sub-waveguide layer is arranged on one side, deviating from the silicon nitride waveguide layer, of the second sub-waveguide layer; the silicon nitride waveguide layer is used as an intermediate coupling layer, and the silicon waveguide layer and the lithium niobate waveguide layer are integrated on the same chip, so that the chip has the advantages of a silicon optical chip and lithium niobate; and moreover, the lithium niobate waveguide can be allowed to adopt a contact type photoetching process with a larger line width, so that the etching difficulty and the equipment cost can be reduced.

Description

Technical Field

[0001] This application belongs to the field of optoelectronic chip technology, and in particular relates to a heterogeneous integrated chip with front bonding and its fabrication method. Background Technology

[0002] As a core component of optical communication and optoelectronic integrated systems, the performance of optoelectronic chips directly affects the efficiency of high-speed signal transmission in scenarios such as data centers and 5G networks. As transmission rates evolve towards 1.6T and higher, optoelectronic chips based on a single material system can hardly meet the requirements of high bandwidth, low power consumption, and integration density simultaneously.

[0003] In related technologies, optoelectronic chips include silicon photonic chips and lithium niobate chips. Silicon photonic chips rely on mature CMOS (Complementary Metal-Oxide-Semiconductor) compatible processes and have significant advantages in device integration and mass production capabilities. However, their electro-optic modulation performance is limited by carrier dispersion effects, making it difficult to meet the requirements of higher transmission rates. Lithium niobate chips, with their high electro-optic coefficient and fast response characteristics, have outstanding potential in the field of high-speed modulation. However, due to the difficulty of material etching and the complexity of integration with lasers / detectors, it is difficult to independently build a complete optoelectronic system.

[0004] Therefore, there is an urgent need for an optoelectronic chip that combines the advantages of silicon photonics chips and lithium niobate chips. Summary of the Invention

[0005] The purpose of this application is to provide a heterogeneous integrated chip with front bonding and its fabrication method, which aims to solve the problem of low performance of optoelectronic chips in traditional technologies.

[0006] A first aspect of this application provides a front-bonded heterogeneous integrated chip, the front-bonded heterogeneous integrated chip comprising:

[0007] Silicon waveguide layer;

[0008] A silicon nitride waveguide layer is disposed on the silicon waveguide layer and spaced apart from the silicon waveguide layer, wherein the silicon waveguide layer and the silicon nitride waveguide layer are coupled.

[0009] A lithium niobate waveguide layer is disposed on the side of the silicon nitride waveguide layer away from the silicon waveguide layer and is spaced apart from the silicon nitride waveguide layer; the lithium niobate waveguide layer is coupled to the silicon nitride waveguide layer.

[0010] The lithium niobate waveguide layer includes a first sub-waveguide layer and a second sub-waveguide layer that are interconnected. The second sub-waveguide layer is disposed on one side of the silicon nitride waveguide layer, and the orthographic projection of the second sub-waveguide layer on the silicon waveguide layer overlaps with the orthographic projection of the silicon nitride waveguide layer on the silicon waveguide layer. The first sub-waveguide layer is disposed on the side of the second sub-waveguide layer that is away from the silicon nitride waveguide layer.

[0011] In some embodiments of this application, the second sub-waveguide layer includes a first separated waveguide segment, and the silicon nitride waveguide layer includes a first strip waveguide segment. The orthographic projection of the first separated waveguide segment on the silicon waveguide layer overlaps with the orthographic projection of the first strip waveguide segment on the silicon waveguide layer. The first separated waveguide segment and the first strip waveguide segment are intersected, and a portion of the first separated waveguide segment extends outside the area where the first strip waveguide segment is located.

[0012] In some embodiments of this application, the second sub-waveguide layer further includes a first tapered waveguide segment connected to the first separated waveguide segment, and the silicon nitride waveguide layer further includes a second tapered waveguide segment connected to the first strip waveguide segment; the orthographic projection of the first tapered waveguide segment on the silicon waveguide layer and the orthographic projection of the second tapered waveguide segment on the silicon waveguide layer overlap each other;

[0013] The first tapered waveguide segment is configured to have a gradually expanding structure along the direction away from the first separated waveguide segment; the second tapered waveguide segment is configured to have a gradually contracting structure along the direction away from the first strip waveguide segment.

[0014] In some embodiments of this application, the second sub-waveguide layer further includes a second strip waveguide segment connected to the end of the first tapered waveguide segment away from the first separated waveguide segment; the silicon nitride waveguide layer further includes a second separated waveguide segment connected to the end of the second tapered waveguide segment away from the first strip waveguide segment;

[0015] The orthographic projection of the second strip waveguide segment on the silicon waveguide layer overlaps with the orthographic projection of the second separated waveguide segment on the silicon waveguide layer;

[0016] The second separated waveguide segment is intersected with the second strip waveguide segment, and part of the second separated waveguide segment extends outside the area where the second strip waveguide segment is located.

[0017] In some embodiments of this application, the second sub-waveguide layer further includes a first bent dissipative waveguide segment, which is connected to the end of the first separated waveguide segment away from the first tapered waveguide segment. The first bent dissipative waveguide segment and the first separated waveguide segment are intersected, and the width of the first bent dissipative waveguide segment is smaller than the width of the first separated waveguide segment.

[0018] And / or, the silicon nitride waveguide layer further includes a second bent dissipative waveguide segment, the second bent dissipative waveguide segment being connected to the end of the second separated waveguide segment away from the second tapered waveguide segment, the second bent dissipative waveguide segment being intersected with the second separated waveguide segment, and the width of the second bent dissipative waveguide segment being smaller than the width of the second separated waveguide segment.

[0019] In some embodiments of this application, the first sub-waveguide layer includes a third separated waveguide segment, the orthographic projection of which overlaps with the second strip waveguide segment on the silicon waveguide layer; the third separated waveguide segment and the second strip waveguide segment are intersected, and a portion of the third separated waveguide segment extends beyond the region where the second strip waveguide segment is located; the second separated waveguide segment and the third separated waveguide segment extend to different sides of the second strip waveguide segment, respectively.

[0020] The first sub-waveguide layer further includes a third tapered waveguide segment, which is connected to the third separated waveguide segment; the second sub-waveguide layer further includes a fourth tapered waveguide segment, which is connected to the end of the second strip waveguide segment away from the first tapered waveguide segment; the orthographic projection of the third tapered waveguide segment on the silicon waveguide layer falls within the orthographic projection of the fourth tapered waveguide segment on the silicon waveguide layer;

[0021] The third tapered waveguide segment is configured to gradually expand in a direction away from the third separated waveguide segment; and / or, the fourth tapered waveguide segment is configured to gradually expand in a direction away from the second strip waveguide segment.

[0022] In some embodiments of this application, the first sub-waveguide layer further includes a third strip waveguide segment connected to the end of the third tapered waveguide segment away from the third separated waveguide segment, and the second sub-waveguide layer further includes a fourth strip waveguide segment connected to the end of the fourth tapered waveguide segment away from the second strip waveguide segment;

[0023] The orthographic projection of the third strip waveguide segment onto the silicon waveguide layer falls within the orthographic projection of the fourth strip waveguide segment onto the silicon waveguide layer, and the third strip waveguide segment and the fourth strip waveguide segment constitute a lithium niobate ridge waveguide structure.

[0024] In some embodiments of this application, the silicon nitride waveguide layer is configured as at least one layer. In the case where there are at least two silicon nitride waveguide layers, the orthogonal projections of the silicon waveguide layer and the two silicon nitride waveguide layers closest to the silicon waveguide layer on the substrate layer overlap each other.

[0025] A second aspect of this application also provides a method for fabricating a heterogeneous integrated chip with front-side bonding, the method comprising:

[0026] A pre-fabricated silicon photonic chip is provided, the pre-fabricated silicon photonic chip comprising a silicon waveguide layer and a silicon nitride waveguide layer as described above;

[0027] A prefabricated lithium niobate chip is provided, the lithium niobate chip comprising a lithium niobate layer;

[0028] The prefabricated lithium niobate chip is bonded to the prefabricated silicon photonic chip, and the lithium niobate layer is disposed close to the silicon nitride waveguide layer.

[0029] The lithium niobate layer is etched to obtain the lithium niobate waveguide layer as described above.

[0030] In some embodiments of this application, the preparation method satisfies at least one of the following:

[0031] The provision of a pre-fabricated silicon photonic chip includes:

[0032] A silicon photonics chip middleware is provided, the silicon photonics chip middleware comprising a silicon waveguide layer and a silicon nitride waveguide layer as described above;

[0033] A first silicon dioxide layer is deposited on one side of the silicon photonic chip intermediate where the silicon nitride waveguide layer is disposed, and the first silicon dioxide layer is chemically and mechanically polished.

[0034] The first silicon dioxide layer is surface activated;

[0035] The provision of a prefabricated lithium niobate chip includes:

[0036] A lithium niobate chip middleware is provided, the lithium niobate chip middleware including a lithium niobate layer;

[0037] A second silicon dioxide layer is deposited on one side of the lithium niobate chip intermediate where the lithium niobate layer is disposed, and the second silicon dioxide layer is chemically and mechanically polished.

[0038] The second silicon dioxide layer is surface activated;

[0039] Etching the lithium niobate layer to obtain the lithium niobate waveguide layer as described above includes:

[0040] Remove the substrate layer on the side of the lithium niobate layer away from the pre-fabricated silicon photonic chip to expose the lithium niobate layer;

[0041] The lithium niobate layer is etched at least twice to obtain a first sub-waveguide layer and a second sub-waveguide layer, resulting in the lithium niobate waveguide layer as described above.

[0042] The beneficial effects of this invention embodiment compared with the prior art are as follows: In the above-described heterogeneous integrated chip and fabrication method with front bonding, the heterogeneous integrated chip includes a silicon waveguide layer, a silicon nitride waveguide layer, and a lithium niobate waveguide layer; the silicon nitride waveguide layer is disposed on the silicon waveguide layer and spaced apart from it; the lithium niobate waveguide layer is disposed on the side of the silicon nitride waveguide layer away from the silicon waveguide layer and spaced apart from it, and the lithium niobate waveguide layer is coupled to the silicon nitride waveguide layer; the lithium niobate waveguide layer includes a first sub-waveguide layer and a second sub-waveguide layer interconnected, the second sub-waveguide layer is disposed on one side of the silicon nitride waveguide layer, and the second... The orthographic projection of the sub-waveguide layer onto the silicon waveguide layer overlaps with the orthographic projection of the silicon nitride waveguide layer onto the silicon waveguide layer. The first sub-waveguide layer is disposed on the side of the second sub-waveguide layer away from the silicon nitride waveguide layer. This application uses the silicon nitride waveguide layer as an intermediate coupling layer to integrate the silicon waveguide layer and the lithium niobate waveguide layer on the same chip, enabling the chip to combine the advantages of silicon photonics chips and lithium niobate. Furthermore, the orthographic projection of the second sub-waveguide layer of the lithium niobate waveguide layer overlaps with the silicon nitride waveguide layer, which allows the lithium niobate waveguide to use a contact lithography process with a larger linewidth, avoiding the requirements of traditional high-precision lithography, and helping to reduce etching difficulty and equipment cost. Attached Figure Description

[0043] Figure 1 A cross-sectional view of a heterogeneous integrated chip with front bonding provided in an embodiment of this application;

[0044] Figure 2 A top view of a heterogeneous integrated chip with front bonding provided in an embodiment of this application;

[0045] Figure 3 A schematic diagram illustrating the steps of a method for fabricating a front-bonded heterogeneous integrated chip according to an embodiment of this application;

[0046] Figure 4 A schematic diagram of the steps of a silicon-based chip middleware preprocessing method for a front-bonded heterogeneous integrated chip provided in an embodiment of this application;

[0047] Figure 5 A schematic diagram of the steps of a lithium niobate chip intermediate preprocessing method for a front-bonded heterogeneous integrated chip provided in an embodiment of this application;

[0048] Figure 6A schematic diagram of the steps in a method for fabricating a lithium niobate chip structure of a front-bonded heterogeneous integrated chip according to an embodiment of this application;

[0049] Figure 7 A process flow diagram of a method for fabricating a front-bonded heterogeneous integrated chip according to an embodiment of this application;

[0050] Figure 8 A schematic diagram illustrating the relationship between transmittance and alignment error provided in an embodiment of this application;

[0051] Figure 9 This is a schematic diagram illustrating the relationship between transmittance and the tip width of the lithium niobate waveguide layer, provided as an embodiment of this application.

[0052] Specific element symbol explanations: 10-Silicon photonic chip intermediate, 20-Lithium niobate chip intermediate, 30-Chemical mechanical polishing, 100-Silicon waveguide layer, 200-Silicon nitride waveguide layer, 210-First strip waveguide segment, 220-Second tapered waveguide segment, 230-Second split waveguide segment, 240-Second bending dissipation waveguide segment, 300-Lithium niobate waveguide layer, 310-Second sub-waveguide layer, 311-First split waveguide segment, 312-First tapered waveguide segment, 313-Second strip waveguide segment, 314-First bending dissipation waveguide segment, 315-Fourth tapered waveguide segment, 316-Fourth strip waveguide segment, 321-Third split waveguide segment, 322-Third tapered waveguide segment, 323-Third strip waveguide segment, 320-First sub-waveguide layer, 400-SOI wafer, a-First direction. Detailed Implementation

[0053] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0054] It should be noted that when a component is referred to as being "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0055] It should be understood that the terms "length", "width", "upper", "lower", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0056] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0057] It's important to understand that optoelectronic chips, as core components of optical communication and optoelectronic integrated systems, directly impact the efficiency of high-speed signal transmission in scenarios such as data centers and 5G networks. With the iterative upgrades of artificial intelligence and intelligent computing technologies, data centers are placing stringent demands on the communication speeds of chips and switches, with transmission rates evolving from the current 400G / 800G to 1.6T and higher. Against this backdrop, optoelectronic chips based on single-material systems face significant technical bottlenecks: achieving a balance between high bandwidth (such as ultra-high frequency modulation corresponding to speeds above 1.6T), low power consumption, and integration density is challenging, prompting the industry to explore heterogeneous integration technologies.

[0058] In related technologies, optoelectronic chips are mainly divided into two major systems: silicon photonic chips and lithium niobate chips. Silicon photonic chips, relying on mature processes compatible with CMOS (Complementary Metal-Oxide-Semiconductor), have irreplaceable advantages in device integration and large-scale mass production capabilities. 400G / 800G optoelectronic modules based on the silicon-on-insulator (SOI) platform have entered the small-batch mass production stage, encompassing various proven device structures such as edge couplers (EC), grating couplers (GC), and multimode interference couplers (MMI). However, the electro-optic modulation performance of silicon photonic chips is limited by the carrier dispersion effect mechanism, and its 3dB modulation bandwidth typically only reaches 40GHz, making it difficult to meet the high-speed signal processing requirements of 1.6T and higher speed optoelectronic modules.

[0059] Lithium niobate chips, with their high electro-optic coefficient (~32 pm / V), sub-picosecond response speed, and wide optical transparency window (0.35-5.2 μm), have shown significant potential in optoelectronic modules with speeds of 1.6T / 3.2T and higher. In particular, recent technological breakthroughs based on the lithium niobate-on-insulator (LNOI) platform have further promoted its application in high-speed modulation. However, this platform faces inherent technical challenges: First, lithium niobate itself lacks light emission and photodetection capabilities, making heterogeneous integration with optoelectronic devices such as lasers and detectors difficult; second, lithium niobate is a difficult-to-etch material, and the processing precision of fine structures is affected by factors such as etching tilt angle, making high-density photolithography and etching difficult to achieve; third, because the refractive index of lithium niobate is lower than that of silicon, LNOI devices are typically larger than SOI devices, resulting in limited integration density.

[0060] Based on this, this application improves the related front-bonded heterogeneous integrated chips and their fabrication methods.

[0061] Please see Figure 1 and Figure 2 , Figure 1 This illustration shows a cross-sectional view of the heterogeneous integrated chip with front bonding provided in this embodiment. The heterogeneous integrated chip with front bonding in this embodiment includes a silicon waveguide layer 100, a silicon nitride waveguide layer 200, and a lithium niobate waveguide layer 300. The silicon nitride waveguide layer 200 is disposed on the silicon waveguide layer 100 and spaced apart from it; the silicon waveguide layer 100 and the silicon nitride waveguide layer 200 are coupled. The lithium niobate waveguide layer 300 is disposed on the side of the silicon nitride waveguide layer 200 away from the silicon waveguide layer 100 and is coupled to the silicon nitride waveguide layer 200. The lithium niobate waveguide layer 300 and the silicon nitride waveguide layer 200 are coupled with zero spacing. The lithium niobate waveguide layer 300 includes a first sub-waveguide layer 320 and a second sub-waveguide layer 310 that are connected to each other. The second sub-waveguide layer 310 is disposed on one side of the silicon nitride waveguide layer 200, and the orthographic projection of the second sub-waveguide layer 310 on the silicon waveguide layer 100 overlaps with the orthographic projection of the silicon nitride waveguide layer 200 on the silicon waveguide layer 100. The first sub-waveguide layer 320 is disposed on the side of the second sub-waveguide layer 310 that is away from the silicon nitride waveguide layer 200.

[0062] It needs to be explained that front-bonded heterogeneous integrated chips refer to the integration of materials with different physical properties (such as silicon, silicon nitride, and lithium niobate) into the same chip architecture through specific processes to achieve optoelectronic integrated devices with comprehensive performance that cannot be achieved by a single material. The silicon waveguide layer 100 is a waveguide structure layer based on silicon, relying on mature CMOS technology to realize optical signal transmission and device integration. The silicon nitride waveguide layer 200 is an intermediate coupling layer disposed above the silicon waveguide layer 100, realizing optical signal transmission with the upper and lower waveguides through the optical evanescent wave effect. The lithium niobate waveguide layer 300 is a waveguide structure layer made of lithium niobate, utilizing its high electro-optic coefficient characteristics to achieve high-speed optical modulation, and is coupled to the silicon nitride waveguide layer 200. The first sub-waveguide layer 320 and the second sub-waveguide layer 310 are layered structures of the lithium niobate waveguide layer 300, and are spatially connected to form a waveguide conversion path; wherein the orthographic projection of the second sub-waveguide layer 310 on the silicon waveguide layer 100 overlaps with the orthographic projection of the silicon nitride waveguide layer 200.

[0063] It is understood that, by setting a silicon nitride waveguide layer 200 as an intermediate coupling layer, the silicon waveguide layer 100 and the lithium niobate waveguide layer 300 are integrated into the same chip. This allows the chip to combine the advantages of mature silicon photonics chip technology and high device integration with the characteristics of high electro-optic coefficient and fast response speed of lithium niobate material. Furthermore, the design of the second sub-waveguide layer 310 of the lithium niobate waveguide layer 300 overlapping with the silicon nitride waveguide layer 200 through orthogonal projection relaxes the etching precision requirements of the lithium niobate waveguide, allowing the use of contact lithography process. This avoids the dependence of traditional high-precision lithography on high-end equipment, reduces etching difficulty and equipment cost, and the structure is tolerant to process alignment errors, adapting to process fluctuations in mass production and improving device yield and production feasibility.

[0064] In some embodiments, the minimum linewidth of the lithium niobate waveguide layer 300 is 800 nm, and the photolithography process can be completed using a contact lithography machine.

[0065] In some embodiments of this application, please refer to Figure 2 , Figure 2 A schematic diagram of the structure of the heterogeneous integrated chip with front bonding provided in this embodiment is shown. The second sub-waveguide layer 310 of this embodiment includes a first separated waveguide segment 311, and the silicon nitride waveguide layer 200 includes a first strip waveguide segment 210. The orthographic projection of the first separated waveguide segment 311 on the silicon waveguide layer 100 and the orthographic projection of the first strip waveguide segment 210 on the silicon waveguide layer 100 overlap each other. The first separated waveguide segment 311 and the first strip waveguide segment 210 are intersected, and part of the first separated waveguide segment 311 extends outside the area where the first strip waveguide segment 210 is located.

[0066] It should be explained that the second sub-waveguide layer 310 is one of the layered structures of the lithium niobate waveguide layer 300, located on one side of the silicon nitride waveguide layer 200, and connected to the first sub-waveguide layer 320 to form a waveguide transmission path. The first separated waveguide segment 311 is a waveguide structure unit in the second sub-waveguide layer 310, separated from the main waveguide at an angular offset, used for optical field coupling and mode conversion. The first strip waveguide segment 210 is a linear waveguide unit in the silicon nitride waveguide layer 200, serving as the main transmission path for optical signals. Orthographic projection overlap refers to the overlapping area between the projections of the first separated waveguide segment 311 and the first strip waveguide segment 210 on the plane of the silicon waveguide layer 100, forming the basis for spatial coupling.

[0067] It is understood that the overlapping of the first separated waveguide segment 311 and the silicon nitride waveguide layer 200 in this application is beneficial to expanding the optical coupling area between waveguides, enabling the light field to be transmitted efficiently in the overlapping area through the evanescent wave effect, and avoiding the decrease in coupling efficiency caused by insufficient alignment accuracy in traditional methods. The structure of the cross-set and partially extended strip waveguide segment area forms a gradient light field guiding path, which on the one hand reduces the requirements for the etching accuracy of lithium niobate waveguides, allowing the use of contact lithography to adapt to mass production, and on the other hand, the extended design of the separated waveguide segment effectively dissipates the reflected signal in the light transmission, improving signal integrity. Furthermore, the heterogeneous integrated chip with front bonding in the embodiments of this application has tolerance for process alignment errors.

[0068] Please refer to the embodiments described in this application. Figure 2 In this embodiment, the second sub-waveguide layer 310 further includes a first tapered waveguide segment 312, which is connected to the first separated waveguide segment 311. The silicon nitride waveguide layer 200 also includes a second tapered waveguide segment 220, which is connected to the first strip waveguide segment 210. The orthographic projection of the first tapered waveguide segment 312 on the silicon waveguide layer 100 and the orthographic projection of the second tapered waveguide segment 220 on the silicon waveguide layer 100 overlap. The first tapered waveguide segment 312 is configured to have a gradually expanding structure along the direction away from the first separated waveguide segment 311, and the second tapered waveguide segment 220 is configured to have a gradually contracting structure along the direction away from the first strip waveguide segment 210.

[0069] It should be explained that the first tapered waveguide segment 312 is a strip waveguide structure in the second sub-waveguide layer 310 connected to the first separated waveguide segment 311, used for optical field mode conversion and transmission. The second tapered waveguide segment 220 is a tapered waveguide structure in the silicon nitride waveguide layer 200 connected to the first strip waveguide segment 210, forming a coupling relationship with the first tapered waveguide segment 312. The expanding structure is a design where the waveguide width of the first tapered waveguide segment 312 gradually increases along the direction away from the first separated waveguide segment 311. The contracting structure is a design where the waveguide width of the second tapered waveguide segment 220 gradually decreases along the direction away from the first strip waveguide segment 210.

[0070] It is understood that in this embodiment of the application, the overlapping of the orthographic projections of the first separated waveguide segment 311 and the first strip waveguide segment 210 is beneficial to expanding the optical field interaction area. The cross-set and extended regions form a gradually changing guiding path. Furthermore, the conical structure with the opposite trend forms a gradually changing optical mode matching region at the waveguide interface. When the optical signal enters the coupling region from the silicon nitride waveguide, the tapered silicon nitride waveguide compresses the optical field, while the gradually expanding lithium niobate waveguide provides an extension space for the optical field. The synergistic effect of the two causes the optical field to gradually squeeze from the silicon nitride waveguide into the lithium niobate waveguide, reducing the transmission loss caused by mode mismatch.

[0071] Please refer to the embodiments described in this application. Figure 2 In this embodiment, the second sub-waveguide layer 310 further includes a second strip waveguide segment 313, which is connected to the end of the first tapered waveguide segment 312 away from the first separated waveguide segment 311; the silicon nitride waveguide layer 200 further includes a second separated waveguide segment 230, which is connected to the end of the second tapered waveguide segment 220 away from the first strip waveguide segment 210; the orthographic projection of the second strip waveguide segment 313 on the silicon waveguide layer 100 overlaps with the orthographic projection of the second separated waveguide segment 230 on the silicon waveguide layer 100; the second separated waveguide segment 230 and the second strip waveguide segment 313 are intersected, and a portion of the second separated waveguide segment 230 extends outside the area where the second strip waveguide segment 313 is located.

[0072] It should be explained that the second strip waveguide segment 313 is a linear waveguide structure in the second sub-waveguide layer 310, connected to the end of the first tapered waveguide segment 312 away from the first separated waveguide segment 311, serving as the main optical transmission path of the lithium niobate waveguide layer 300 to maintain the stability of the optical field mode. The second separated waveguide segment 230 is a separated waveguide structure in the silicon nitride waveguide layer 200, connected to the end of the second tapered waveguide segment 220 away from the first strip waveguide segment 210, overlapping and intersecting with the second strip waveguide segment 313 in orthographic projection, with part of the structure extending outside the main waveguide region for optical field coupling and reflection dissipation.

[0073] Understandably, the cross-extension structure of the second separated waveguide segment 230 and the second strip waveguide segment 313 in this application expands the optical field coupling region from linear contact to surface overlap, allowing the lithium niobate waveguide to use contact lithography (e.g., linewidth ≥ 600nm), avoiding reliance on high-precision lithography equipment. The spatial redundancy of the overlapping region provides a buffer for alignment errors within ±800nm, ensuring that process fluctuations during mass production do not affect device performance, resulting in a significant improvement in yield. The second strip waveguide segment 313 is connected to the end of the gradually expanding first tapered waveguide segment 312, and its width matches the main transmission mode of the lithium niobate waveguide; the second separated waveguide segment 230 is connected to the end of the gradually narrowing second tapered waveguide segment 220, and the two achieve a smooth transition of the optical field through the gradual change in width of the tapered structure. The separated waveguide segment extending out of the main waveguide region can be connected to a dissipative structure, effectively reducing back reflection and ensuring the transmission stability of high-speed optical signals.

[0074] Please refer to the embodiments described in this application. Figure 2The second sub-waveguide layer 310 in this embodiment also includes a first bent dissipative waveguide segment 314, which is connected to the end of the first separated waveguide segment 311 away from the first tapered waveguide segment 312. The first bent dissipative waveguide segment 314 and the first separated waveguide segment 311 are arranged intersectingly, and the width of the first bent dissipative waveguide segment 314 is smaller than the width of the first separated waveguide segment 311.

[0075] It should be explained that the first curved dissipative waveguide segment 314 is a curved waveguide structure in the second sub-waveguide layer 310, connected to the end of the first separated waveguide segment 311 away from the first tapered waveguide segment 312. Its cross-sectional width is smaller than that of the first separated waveguide segment 311, and it is used to dissipate reflected signals in optical transmission and improve signal integrity.

[0076] Understandably, the first curved dissipative waveguide segment 314 is connected to the end of the first separated waveguide segment 311. Its curved structure and gradually changing width design (width smaller than the first separated waveguide segment 311) can guide the reflected light during optical transmission to the outside of the waveguide, where it is naturally dissipated through bending loss. This structure avoids signal distortion caused by reflected light returning to the main transmission path.

[0077] Please refer to the embodiments described in this application. Figure 2 The silicon nitride waveguide layer 200 in this embodiment also includes a second bent dissipative waveguide segment 240, which is connected to the end of the second separated waveguide segment 230 away from the second tapered waveguide segment 220. The second bent dissipative waveguide segment 240 and the second separated waveguide segment 230 are arranged intersectingly, and the width of the second bent dissipative waveguide segment 240 is smaller than the width of the second separated waveguide segment 230.

[0078] It should be explained that the second curved dissipative waveguide section 240 is a curved waveguide structure in the silicon nitride waveguide layer 200, connected to the end of the second separated waveguide section 230 away from the second tapered waveguide section 220. Its cross-sectional width is smaller than that of the second separated waveguide section 230, and it is used to dissipate reflected signals in optical transmission and improve the stability of optical signal transmission.

[0079] Understandably, the second curved dissipative waveguide segment 240 is connected to the end of the second separated waveguide segment 230. Its curved structure and gradually changing width design (width smaller than the second separated waveguide segment 230) can guide the return reflection in optical transmission to the outside of the waveguide, where it is naturally dissipated through bending loss. This structure avoids reflected light interfering with the main transmission path and can reduce return loss in high-speed optical communication scenarios.

[0080] Please refer to the embodiments described in this application. Figure 2In this embodiment, the first sub-waveguide layer includes a third separated waveguide segment 321. The orthographic projection of the third separated waveguide segment 321 on the silicon waveguide layer 100 overlaps with the second strip waveguide segment 313 on the silicon waveguide layer. The third separated waveguide segment 321 and the second strip waveguide segment 313 are intersected, and part of the third separated waveguide segment 321 extends outside the area where the second strip waveguide segment 313 is located. The second separated waveguide segment 230 and the third separated waveguide segment 321 extend to different sides of the second strip waveguide segment 313, respectively.

[0081] It needs to be explained that, Figure 2 The first sub-waveguide layer 320 and the second sub-waveguide layer 310 represent two photolithographic patterns in the fabrication process, and their overlapping portion together forms the pattern of the lithium niobate ridge waveguide.

[0082] It should be explained that the third separated waveguide segment 321 is a separated waveguide structure in the first sub-waveguide layer. It overlaps and intersects with the second strip waveguide segment 313 in orthographic projection. Part of the structure extends outside the area where the second strip waveguide segment 313 is located, and is used for optical field conversion and reflection dissipation.

[0083] It is understood that in this embodiment, the orthographic overlap of the third separated waveguide segment 321 and the second strip waveguide segment 313 reduces structural abrupt changes. Combined with the intersecting three-dimensional layout, this allows for effective mode field conversion and reduced reflection in the overlapping region when the light field passes through. Furthermore, the intersecting structure allows the third separated waveguide segment 321 to be processed using contact lithography (linewidth ≥ 600nm), eliminating the need for high-precision DUV lithography. The double-sided extension layout provides a dual tolerance buffer for alignment errors within ±800nm—even if there is an alignment deviation on one side of the waveguide, the extension structure on the other side can still maintain light field coupling, ensuring that process fluctuations during mass production do not affect device performance.

[0084] Please refer to the embodiments described in this application. Figure 2In this embodiment, the first sub-waveguide layer further includes a third tapered waveguide segment 322, which is connected to the third separated waveguide segment 321. The second sub-waveguide layer further includes a fourth tapered waveguide segment 315, which is connected to the end of the second strip waveguide segment 313 away from the first tapered waveguide segment 312. The orthographic projection of the third tapered waveguide segment 322 onto the silicon waveguide layer 100 falls within the orthographic projection of the fourth tapered waveguide segment 315 onto the silicon waveguide layer 100. The third tapered waveguide segment 322 is configured to gradually expand along a direction away from the third separated waveguide segment 321. It should be explained that the third tapered waveguide segment 322 is a ridge waveguide ridge structure in the first sub-waveguide layer, connected to the third separated waveguide segment 321, and its orthographic projection onto the silicon waveguide layer 100 falls entirely within the projection range of the fourth tapered waveguide segment 315, gradually expanding along a direction away from the third separated waveguide segment 321. The fourth tapered waveguide segment 315 is a ridge-shaped waveguide plate structure in the second sub-waveguide layer, connected to the end of the second strip waveguide segment 313 away from the first tapered waveguide segment 312, forming a projected nesting relationship with the third tapered waveguide segment 322. This projected nesting structure allows the third tapered waveguide segment 322 and the fourth tapered waveguide segment 315 to be fabricated using contact lithography (linewidth ≥ 600 nm) without the need for high-precision alignment. Even with an alignment error of ±800 nm, the spatial redundancy of the nested region still ensures effective thermally adiabatic transmission of the light field. Furthermore, the gradient width variation of the expanding structure is adapted to the dry etching process of lithium niobate material, avoiding nanoscale precision machining. Simultaneously, the expanding shape of the third tapered waveguide segment 322 and the expanding shape of the fourth tapered waveguide segment 315 form a tapered coupling region, through which the light field is transmitted.

[0085] In some embodiments, please continue reading Figure 2 In this embodiment, the fourth tapered waveguide segment 315 is configured to gradually expand along a direction away from the second strip waveguide segment 313.

[0086] Understandably, the fourth tapered waveguide segment 315 gradually expands away from the second strip waveguide segment 313. This gradual width design allows the optical field to expand progressively as it enters the tapered waveguide from the second strip waveguide segment 313, avoiding mode mismatch caused by abrupt changes in the optical field. This structure, together with the gradually expanding third tapered waveguide segment 322, forms a dual-gradient path, which helps reduce the transmission loss of the optical field within the lithium niobate waveguide layer 300.

[0087] Please refer to the embodiments described in this application. Figure 2In this embodiment, the first sub-waveguide layer further includes a third strip waveguide segment 323, which is connected to the end of the third tapered waveguide segment 322 away from the third separated waveguide segment 321. The second sub-waveguide layer further includes a fourth strip waveguide segment 316, which is connected to the end of the fourth tapered waveguide segment 315 away from the second strip waveguide segment 313. The orthographic projection of the third strip waveguide segment 323 on the silicon waveguide layer 100 falls within the orthographic projection of the fourth strip waveguide segment 316 on the silicon waveguide layer 100, and the third strip waveguide segment 323 and the fourth strip waveguide segment 316 constitute a lithium niobate ridge waveguide structure.

[0088] It should be explained that the third strip waveguide segment 323 and the fourth strip waveguide segment 316 are lithium niobate ridge straight waveguide structures, connected to the end of the third strip waveguide segment 322 and the fourth tapered waveguide segment 315 away from the second strip waveguide segment 313, forming the optical transmission end of the lithium niobate waveguide layer 300.

[0089] In some embodiments, the first strip waveguide segment 210, the second strip waveguide segment 313, the third strip waveguide segment 323 and the fourth strip waveguide segment 316 are all extended along the first direction a.

[0090] In some embodiments, the first tapered waveguide segment 312, the second tapered waveguide segment 220, the third tapered waveguide segment 322, and the fourth tapered waveguide segment 315 also extend along the first direction a.

[0091] Please refer to the embodiments described in this application. Figure 1 In this embodiment, the silicon nitride waveguide layer is set to at least one layer. When there are at least two silicon nitride waveguide layers 200, the orthogonal projections of the silicon waveguide layer 100 and the two silicon nitride waveguide layers 200 closest to the silicon waveguide layer 100 on the substrate layer overlap with each other.

[0092] It should be explained that optical coupling is formed with the upper and lower waveguides by means of a design that is spaced at least two silicon nitride waveguide layers 200 apart.

[0093] It is understood that in this embodiment, by setting the silicon nitride waveguide layer 200 as at least one layer, when the silicon nitride waveguide layer 200 is two layers, the orthographic projections of the two silicon nitride waveguides on the silicon waveguide layer 100 overlap to form a double-layer coupling structure, thereby expanding the optical field interaction area and improving the evanescent wave coupling efficiency. At the same time, the optical field mode matching is optimized by the refractive index gradient of the double-layer silicon nitride waveguide, thereby reducing cross-layer transmission loss.

[0094] In some embodiments, the silicon nitride layer may be configured as multiple layers, with the uppermost layer of the multilayer silicon nitride layer coupled to the lithium niobate waveguide layer 300, and the lowermost layer of the multilayer silicon nitride layer coupled to the silicon waveguide layer 100.

[0095] Furthermore, to better implement the heterogeneous integrated chip with front bonding in any of the above embodiments, please refer to [reference needed] based on the aforementioned heterogeneous integrated chip with front bonding. Figure 3 , Figure 3 The illustration shows a schematic diagram of the fabrication method provided in this embodiment; this application embodiment also provides a method for fabricating a front-side bonded heterogeneous integrated chip, the fabrication method including:

[0096] S100: Provide a pre-fabricated silicon photonic chip, which includes a silicon waveguide layer 100 and a silicon nitride waveguide layer 200 as described above; specifically, the pre-fabricated silicon photonic chip requires the silicon waveguide layer 100 and the silicon nitride waveguide layer 200 to be pre-fabricated on a chip substrate.

[0097] S200: Provides a pre-fabricated lithium niobate chip, the lithium niobate chip including a lithium niobate layer;

[0098] S300: The pre-fabricated lithium niobate chip is bonded to the pre-fabricated silicon photonic chip, with the lithium niobate layer positioned close to the silicon nitride waveguide layer 200. Specifically, the bonding process is a process that connects the pre-fabricated lithium niobate chip and the pre-fabricated silicon photonic chip through interfacial physicochemical interactions, ensuring that the lithium niobate layer and the silicon nitride waveguide layer 200 are positioned close to each other.

[0099] S400: The lithium niobate layer is etched to obtain the lithium niobate waveguide layer as described above.

[0100] Understandably, the independent fabrication of pre-fabricated silicon photonic chips can utilize mature mass production processes in silicon photonic production lines (such as SOI etching and PECVD deposition) to avoid process conflicts when co-processing heterogeneous materials and ensure the performance stability of each layer structure.

[0101] In some embodiments of this application, please refer to Figure 4 , Figure 4 This illustration shows a schematic diagram of the preprocessing method provided in this embodiment. Step S100 of this embodiment includes:

[0102] S110: Provide a silicon photonics chip middleware 10, the silicon photonics chip middleware 10 including the silicon waveguide layer 100 and the silicon nitride waveguide layer 200 as described above;

[0103] S120: A first silicon dioxide layer is deposited on the side of the silicon photonic chip intermediate 10 where the silicon nitride waveguide layer 200 is disposed, and the first silicon dioxide layer is subjected to chemical mechanical polishing 30; specifically, the surface of the first silicon dioxide layer is planarized by chemical mechanical polishing 30 process to construct a smooth bonding interface, avoid light scattering loss and reduction of mechanical strength of bonding interface caused by surface roughness, and provide a uniform physical support surface for bonding of pre-fabricated lithium niobate chip.

[0104] S130: Surface activation of the first silicon dioxide layer. Specifically, the surface of the silicon dioxide layer is subjected to plasma or chemical activation treatment to enhance the interfacial chemical activity, strengthen the bonding force with the pre-fabricated lithium niobate chip, ensure the mechanical strength and optical transmittance of the bonding interface, and provide a reliable physical connection basis for cross-material optical signal transmission.

[0105] Understandably, the polishing of the silica layer improves the flatness of the bonding interface, avoiding light scattering and bonding voids; surface activation enhances the interfacial adhesion, achieving low-temperature and high-efficiency bonding.

[0106] In some embodiments of this application, please refer to Figure 5 , Figure 5 This illustration shows a schematic diagram of the preprocessing method provided in this embodiment. Step S200 of this embodiment includes:

[0107] S210: Provide a lithium niobate chip middleware 20, the lithium niobate chip middleware 20 including the lithium niobate layer as described above;

[0108] S220: A second silicon dioxide layer is deposited on the side of the lithium niobate chip intermediate 20 where the lithium niobate layer is provided, and the second silicon dioxide layer is chemically mechanically polished 30; specifically, the surface is flattened by the chemically mechanical polishing 30 process, the etching residue or material defects are eliminated, a smooth bonding interface is constructed, and the physical adhesion and optical transmission quality are ensured when bonding with the silicon photonics chip intermediate 10.

[0109] S230: Surface activation of the second silicon dioxide layer. Specifically, the surface of the second silicon dioxide layer is activated (e.g., by plasma treatment) to increase the number of surface active groups, enhance interfacial chemical activity, strengthen the bonding force with the silicon photonic chip intermediate 10, ensure the mechanical strength and optical transmission stability of the bonding interface, and avoid signal loss due to poor interfacial bonding.

[0110] In some embodiments of this application, please refer to Figure 6 , Figure 6 This embodiment shows a schematic diagram of the preparation method steps provided. Step S400 of this embodiment includes:

[0111] S410: Remove the substrate layer on the side of the lithium niobate layer away from the pre-fabricated silicon photonic chip to expose the lithium niobate layer.

[0112] S420: The lithium niobate layer is etched at least twice to obtain a first sub-waveguide layer 320 and a second sub-waveguide layer 310. Specifically, the first etching forms the second sub-waveguide layer 310, and the second etching forms the first sub-waveguide layer 320 on the second sub-waveguide layer 310. This layered structure enables functions such as optical field coupling and mode conversion. Furthermore, during the photolithography process, the overlapping structure of the photolithographic structure and the pre-fabricated silicon photonic chip allows for alignment errors within ±800nm, eliminating the need for high-precision photolithography alignment equipment.

[0113] In the embodiments of this application, please refer to Figure 7 , Figure 7 A process flow diagram of the preparation method provided in this embodiment is shown. Figure 7 As shown, Si is the silicon waveguide layer 100, SiO2 is the dielectric layer, LN is the lithium niobate waveguide layer 300, CMP is chemical mechanical polishing 30, SiN is the silicon nitride waveguide layer 200, and -OH is surface activation. In this embodiment, an SOI wafer 400 (corresponding to silicon photonic chip intermediate 10) with a silicon waveguide layer 100 and a silicon nitride waveguide layer 200 is first provided, and the silicon nitride waveguide layer 200 has already been coupled. Then, CMP is performed on the silicon dioxide on the surface of the SOI wafer 400 to polish the silicon dioxide to the designed thickness of the silicon nitride, followed by surface activation to obtain a pre-fabricated silicon photonic chip. Simultaneously, an LNOI wafer (corresponding to a pre-fabricated lithium niobate chip) with a lithium niobate waveguide layer 300 is also provided. Then, a layer of silicon dioxide is deposited on the LNOI wafer and polished to the designed thickness using CMP, followed by surface activation to obtain a pre-fabricated lithium niobate chip.

[0114] After obtaining the pre-fabricated silicon photonic chip and the pre-fabricated lithium niobate chip, the pre-fabricated lithium niobate chip is flipped and bonded to the pre-fabricated silicon photonic chip. The substrate on the original pre-fabricated lithium niobate chip is thinned and removed to expose the lithium niobate waveguide layer 300. Then, the lithium niobate waveguide layer 300 is etched twice to form the first sub-waveguide layer 320 and the second sub-waveguide layer 310 mentioned above.

[0115] In some embodiments, the silicon nitride waveguide layer 200 has a thickness of 300 nm, the lithium niobate waveguide layer 300 has a thickness of 200 nm, and the spacing between the silicon nitride waveguide layer 200 and the lithium niobate waveguide layer 300 is 600 nm. The maximum distance between the first separated waveguide segment 311 extending into the region where the first strip waveguide segment 210 is located and the region where the first strip waveguide segment 210 is located is 3 μm, and the length of the first separated waveguide segment 311 is 100 μm. The width of the first tapered waveguide segment 312 gradually decreases from 2 μm to 0.8 μm, and the width of the second tapered waveguide segment 220 gradually increases from 0.8 μm to 1.2 μm. The lengths of the first tapered waveguide segment 312 and the second tapered waveguide segment 220 are 130 μm. In this embodiment, the coupling transmittance between the silicon nitride waveguide layer 200 and the lithium niobate waveguide layer 300 is 99.4% at a wavelength of 1550 nm.

[0116] When the end edge of the third separated waveguide segment 321 in the first sub-waveguide layer 320 deviates from the edge of the second strip waveguide segment 313 by 1.15 μm and the length of the third separated waveguide segment 321 is 125 μm, the width of the third tapered waveguide segment 322 gradually increases from 0.8 μm to 1.2 μm, the width of the fourth tapered waveguide segment 315 gradually increases from 1.2 μm to 5 μm, and the lengths of the third tapered waveguide segment 322 and the fourth tapered waveguide segment 315 are 150 μm, the transmittance from the first sub-waveguide layer 320 to the second sub-waveguide layer 310 is 99.2%, and the combined transmittance of the silicon nitride waveguide layer 200 and the lithium niobate waveguide layer 300 obtained above is 99.4%, that is, the total transmittance is 98.6%.

[0117] Please see Figure 8 , Figure 8 A schematic diagram illustrating the relationship between transmittance and alignment error provided in this embodiment is shown; specifically, alignment errors are prone to occur when the lithium niobate strip waveguide and the silicon nitride waveguide are perpendicular to the propagation direction. For example... Figure 8 As shown, within an alignment error of ±800 nm, the transmittance of the coupled structure is greater than 97.2%. Please refer to [link / reference]. Figure 9 , Figure 9 A schematic diagram illustrating the relationship between transmittance and the tip width of the lithium niobate waveguide layer 300 provided in this embodiment is shown. It can be seen that when the tip width of the lithium niobate waveguide varies, the transmittance remains greater than 98.3% within the range of 100nm–1000nm. Therefore, throughout the entire etched structure of lithium niobate, the minimum feature size of lithium niobate can be maintained above 600nm, significantly reducing the etching precision requirements for lithium niobate, allowing for the use of relatively inexpensive contact lithography machines.

[0118] In some embodiments, the aforementioned front-bonded heterogeneous integrated chips can be applied in data centers and 5G data backhaul as well as optical communication transmission.

[0119] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0120] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0121] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0122] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0123] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A heterogeneous integrated chip with front-side bonding, characterized in that, The heterogeneous integrated chip includes: Silicon waveguide layer; A silicon nitride waveguide layer is disposed on the silicon waveguide layer and spaced apart from the silicon waveguide layer, wherein the silicon waveguide layer and the silicon nitride waveguide layer are coupled. A lithium niobate waveguide layer is disposed on the side of the silicon nitride waveguide layer away from the silicon waveguide layer and is spaced apart from the silicon nitride waveguide layer; the lithium niobate waveguide layer is coupled to the silicon nitride waveguide layer. The lithium niobate waveguide layer includes a first sub-waveguide layer and a second sub-waveguide layer that are interconnected. The second sub-waveguide layer is disposed on one side of the silicon nitride waveguide layer, and the orthographic projection of the second sub-waveguide layer on the silicon waveguide layer overlaps with the orthographic projection of the silicon nitride waveguide layer on the silicon waveguide layer. The first sub-waveguide layer is disposed on the side of the second sub-waveguide layer that is away from the silicon nitride waveguide layer.

2. The heterogeneous integrated chip with front bonding according to claim 1, characterized in that, The second sub-waveguide layer includes a first separated waveguide segment, and the silicon nitride waveguide layer includes a first strip waveguide segment. The orthographic projection of the first separated waveguide segment on the silicon waveguide layer overlaps with the orthographic projection of the first strip waveguide segment on the silicon waveguide layer. The first separated waveguide segment and the first strip waveguide segment are intersected, and a portion of the first separated waveguide segment extends outside the area where the first strip waveguide segment is located.

3. The heterogeneous integrated chip with front bonding according to claim 2, characterized in that, The second sub-waveguide layer further includes a first tapered waveguide segment connected to the first separated waveguide segment. The silicon nitride waveguide layer further includes a second tapered waveguide segment connected to the first strip waveguide segment. The orthographic projection of the first tapered waveguide segment on the silicon waveguide layer and the orthographic projection of the second tapered waveguide segment on the silicon waveguide layer overlap each other. The first tapered waveguide segment is configured to have a gradually expanding structure along the direction away from the first separated waveguide segment; the second tapered waveguide segment is configured to have a gradually contracting structure along the direction away from the first strip waveguide segment.

4. The heterogeneous integrated chip with front bonding according to claim 3, characterized in that, The second sub-waveguide layer further includes a second strip waveguide segment, which is connected to the end of the first tapered waveguide segment away from the first separated waveguide segment; the silicon nitride waveguide layer further includes a second separated waveguide segment, which is connected to the end of the second tapered waveguide segment away from the first strip waveguide segment; The orthographic projection of the second strip waveguide segment on the silicon waveguide layer overlaps with the orthographic projection of the second separated waveguide segment on the silicon waveguide layer; The second separated waveguide segment is intersected with the second strip waveguide segment, and part of the second separated waveguide segment extends outside the area where the second strip waveguide segment is located.

5. The heterogeneous integrated chip with front bonding according to claim 4, characterized in that, The second sub-waveguide layer further includes a first bent dissipative waveguide segment, which is connected to the end of the first separated waveguide segment away from the first tapered waveguide segment. The first bent dissipative waveguide segment and the first separated waveguide segment are intersected, and the width of the first bent dissipative waveguide segment is smaller than the width of the first separated waveguide segment. And / or, the silicon nitride waveguide layer further includes a second bent dissipative waveguide segment, the second bent dissipative waveguide segment being connected to the end of the second separated waveguide segment away from the second tapered waveguide segment, the second bent dissipative waveguide segment being intersected with the second separated waveguide segment, and the width of the second bent dissipative waveguide segment being smaller than the width of the second separated waveguide segment.

6. The heterogeneous integrated chip with front bonding according to claim 4, characterized in that, The first sub-waveguide layer includes a third separated waveguide segment, the orthographic projection of which overlaps with the second strip waveguide segment on the silicon waveguide layer; the third separated waveguide segment and the second strip waveguide segment are intersected, and a portion of the third separated waveguide segment extends beyond the region where the second strip waveguide segment is located; the second separated waveguide segment and the third separated waveguide segment extend to different sides of the second strip waveguide segment, respectively. The first sub-waveguide layer further includes a third tapered waveguide segment, which is connected to the third separated waveguide segment; the second sub-waveguide layer further includes a fourth tapered waveguide segment, which is connected to the end of the second strip waveguide segment away from the first tapered waveguide segment; the orthographic projection of the third tapered waveguide segment on the silicon waveguide layer falls within the orthographic projection of the fourth tapered waveguide segment on the silicon waveguide layer; The third tapered waveguide segment is configured to gradually expand in a direction away from the third separated waveguide segment; and / or, the fourth tapered waveguide segment is configured to gradually expand in a direction away from the second strip waveguide segment.

7. The heterogeneous integrated chip with front bonding according to claim 6, characterized in that, The first sub-waveguide layer further includes a third strip waveguide segment, which is connected to the end of the third tapered waveguide segment away from the third separated waveguide segment. The second sub-waveguide layer further includes a fourth strip waveguide segment, which is connected to the end of the fourth tapered waveguide segment away from the second strip waveguide segment. The orthographic projection of the third strip waveguide segment onto the silicon waveguide layer falls within the orthographic projection of the fourth strip waveguide segment onto the silicon waveguide layer, and the third strip waveguide segment and the fourth strip waveguide segment constitute a lithium niobate ridge waveguide structure.

8. The heterogeneous integrated chip with front bonding according to any one of claims 1 to 7, characterized in that, The silicon nitride waveguide layer is configured as at least one layer. When the silicon nitride waveguide layer is configured as at least two layers, the orthogonal projections of the silicon waveguide layer and the two silicon nitride waveguide layers closest to the silicon waveguide layer on the substrate layer overlap each other.

9. A method for fabricating a heterogeneous integrated chip with front-side bonding, characterized in that, The preparation method includes: A pre-fabricated silicon photonic chip is provided, the pre-fabricated silicon photonic chip comprising a silicon waveguide layer and a silicon nitride waveguide layer as described in any one of claims 1 to 8; A prefabricated lithium niobate chip is provided, the lithium niobate chip comprising a lithium niobate layer; The prefabricated lithium niobate chip is bonded to the prefabricated silicon photonic chip, and the lithium niobate layer is disposed close to the silicon nitride waveguide layer; The lithium niobate layer is etched to obtain the lithium niobate waveguide layer as described in any one of claims 1 to 8.

10. The preparation method according to claim 9, characterized in that, The preparation method satisfies at least one of the following: The provision of a pre-fabricated silicon photonic chip includes: A silicon photonics chip middleware is provided, the silicon photonics chip middleware comprising a silicon waveguide layer and a silicon nitride waveguide layer as described in any one of claims 1 to 8; A first silicon dioxide layer is deposited on one side of the silicon photonic chip intermediate where the silicon nitride waveguide layer is disposed, and the first silicon dioxide layer is chemically and mechanically polished. The first silicon dioxide layer is surface activated; The provision of a prefabricated lithium niobate chip includes: A lithium niobate chip middleware is provided, the lithium niobate chip middleware including a lithium niobate layer; A second silicon dioxide layer is deposited on one side of the lithium niobate chip intermediate where the lithium niobate layer is disposed, and the second silicon dioxide layer is chemically and mechanically polished. The second silicon dioxide layer is surface activated; Etching the lithium niobate layer to obtain the lithium niobate waveguide layer as described in any one of claims 1 to 8 comprises: Remove the substrate layer on the side of the lithium niobate layer away from the pre-fabricated silicon photonic chip to expose the lithium niobate layer; The lithium niobate layer is etched at least twice to obtain a first sub-waveguide layer and a second sub-waveguide layer, thereby obtaining the lithium niobate waveguide layer as described in any one of claims 1 to 8.

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