Cache division method and device, equipment and storage medium
By obtaining the bit error rate of a four-bit storage block on the hard disk and converting it into a single-bit storage block, the problem of performance and wear imbalance in cache partitioning is solved, achieving wear leveling and performance improvement.
Patent Information
- Application Number
- CN202511075102.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-31
- Publication Date
- 2025-11-21
AI Technical Summary
Existing technologies cannot effectively balance performance and wear in cache partitioning. Static methods result in uneven wear between four-bit and single-bit storage units, while dynamic methods affect solid-state drive performance.
By obtaining the bit error rate of each four-bit storage block in the hard disk, the target four-bit storage block with the highest bit error rate is found, converted into a single-bit storage block, and the current cache block is released. The cache blocks are dynamically adjusted to achieve wear leveling.
Achieving a balance between cache performance and block wear, avoiding high error rate blocks from impacting performance, and improving storage resource utilization and data read/write speed.
Smart Images
Figure CN120994127A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage technology, and in particular to cache partitioning methods, apparatus, devices and storage media. Background Technology
[0002] With the continuous advancement of manufacturing technology, the storage density of NAND flash memory has increased from the early single-level cell (SLC) and multi-level cell (MLC) to the current triple-level cell (TLC) and quad-level cell (QLC), reducing storage costs.
[0003] To meet storage demands, some technologies employ static methods for cache allocation, fixing a portion of four-bit storage areas as single-bit storage areas for long-term cache use. While these techniques can improve storage performance, they can lead to uneven wear between four-bit and single-bit storage units. Other technologies use dynamic methods, setting a portion of four-bit storage units as single-bit storage units based on certain indicators. While this improves flexibility and storage resource utilization, dynamic switching may impact SSD performance, indicating insufficient optimization mechanisms. Therefore, effectively achieving performance and wear balance in cache partitioning has become a pressing issue. Summary of the Invention
[0004] This application provides a cache partitioning method, a data storage device, an electronic device, a computer-readable storage medium, and a computer program product to at least solve the problem of performance and wear imbalance in cache partitioning in related technologies.
[0005] This application provides a cache partitioning method, including:
[0006] Obtain the bit error rate of each four-bit storage block in the hard disk, and find the target four-bit storage block with the highest bit error rate, wherein each four-bit storage block is used to store four bits of data;
[0007] The target four-bit storage block is converted into a first single-bit storage block;
[0008] Release the second single-bit storage block currently used as a cache in the hard disk, and use the first single-bit storage block as a cache for the hard disk, wherein each single-bit storage block is used to store one bit of data.
[0009] This application also provides a cache partitioning device, including:
[0010] Bit error rate acquisition module: used to acquire the bit error rate of each bit storage block in the hard disk, including acquiring the bit error rate of each flash page, and taking the maximum or average value as the bit error rate of the block;
[0011] Target block lookup module: used to find the target four-bit storage block with the highest bit error rate. It sorts the blocks in each logical storage unit according to the bit error rate and takes the block with the highest bit error rate in each unit as the target block.
[0012] Block conversion module: used to convert a target four-bit storage block into a first single-bit storage block, and also used to convert at least one four-bit storage block into a third single-bit storage block when the hard drive is first powered on.
[0013] Cache switching module: used to release the second single-bit storage block currently being used as cache, and to use the first single-bit storage block as cache. It is also used to release the first single-bit storage block and use the fourth single-bit storage block as cache when the hard drive is idle.
[0014] Initial cache configuration module: Used to set the third single-bit storage block as the initial cache of the hard drive when it is first powered on.
[0015] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing any of the above-described cache partitioning methods when executing the computer program.
[0016] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described cache partitioning methods.
[0017] In some embodiments of this application, based on the bit error rate of each four-bit storage block in the hard disk, the target four-bit storage block with the highest bit error rate is found, converted into a first single-bit storage block, and the second single-bit storage block currently used as cache in the hard disk is released. The first single-bit storage block is then used as the hard disk cache. This allows for dynamic adjustment of cache blocks based on the bit error rate of the four-bit storage blocks. For example, converting the four-bit storage block with the highest bit error rate into a single-bit storage block for cache avoids performance degradation due to its high bit error rate. Releasing the original cache block allows for a more balanced wear distribution across blocks. Thus, a balance can be achieved between cache performance and block wear, solving the problem of unbalanced performance and wear in cache partitioning in some technologies. Attached Figure Description
[0018] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 A flowchart illustrating a cache partitioning method provided for some embodiments of this application;
[0020] Figure 2 Schematic diagram of a data storage device provided for some embodiments of this application;
[0021] Figure 3 A schematic diagram of the modules of an electronic device provided for some embodiments of this application. Detailed Implementation
[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.
[0023] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.
[0024] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0025] In the architecture of NAND flash memory, from the smallest storage unit to the entire solid-state drive (SSD), there are multiple hierarchical concepts. Their relationship can be understood as a structure of "from small to large, gradually forming together." The basic concepts are as follows:
[0026] 1) Single-Level Cell (SLC): Each storage cell stores only 1 bit of data (2 states, i.e., 0 or 1).
[0027] 2) Multi-Level Cell (MLC): Each storage cell stores 2 bits of data (4 states, namely 00 / 01 / 10 / 11).
[0028] 3) Triple-Level Cell (TLC): Each storage cell stores 3 bits of data (8 states).
[0029] 4) Quad-Level Cell (QLC): Each cell stores 4 bits of data (16 states).
[0030] 5) Flash Page: The smallest unit for reading and writing. A flash page typically contains thousands of four-bit storage cells. A four-bit storage block (QLC Multi-BLK) contains multiple four-bit blocks (QLC BLK), and each four-bit block contains multiple flash pages. Read and write operations must be performed on a page-by-page basis; it is not possible to operate on a single four-bit storage cell.
[0031] 6) Quad-block (QLC BLK, Block): Composed of multiple flash memory pages, it is the basic unit of data erasure. Due to the characteristics of NAND flash memory, the corresponding area must be erased before writing data, and erasure can only be performed in units of quad-blocks.
[0032] 7) Quad-bit storage block (QLC Multi-BLK): This is a collection of multiple quad-bit blocks. Each quad-bit storage block is used to store four bits of data. It is mainly used to improve wear leveling and cache allocation performance. It is the basic unit of state transition, such as switching from quad-bit storage mode to single-bit storage mode.
[0033] 8) Logical Unit Number (LUN): A hard disk can be divided into at least one logical unit, and each logical unit includes at least one four-bit storage block.
[0034] 9) Die: A die is an independent functional unit within a single NAND flash memory chip. It contains a large number of four-bit storage blocks. Logical storage units can be divided based on the die, and the four-bit storage blocks within each logical storage unit can be independently sorted and managed.
[0035] 10) Single-Level Cell Block (SLC BLK): Converted from a four-bit cell block, each single-bit cell block is used to store one bit of data and can be used as a cache for the hard drive. When the single-bit cell block used as a cache is released, it can be converted back to a four-bit cell block.
[0036] 11) NAND Flash: A type of flash memory technology, consisting of a hierarchical structure of four-bit storage cells, flash pages, four-bit blocks, and four-bit storage areas. It is the core storage medium of solid-state drives and provides the physical basis for data storage.
[0037] 12) Solid-State Drive (SSD): Composed of multiple dies, a controller, and other components, it is the final storage device for users. The controller is responsible for managing the underlying hierarchical structure, implementing functions such as data allocation, read / write scheduling, and cache partitioning, and providing stable storage services.
[0038] The hierarchical relationship of the above basic concepts is as follows: four-bit storage cells form a flash memory page, multiple flash memory pages form a four-bit block, and multiple four-bit blocks form a four-bit storage block; the four-bit storage block is integrated within the die, the die is divided into multiple logical cells, and the die can be further divided into multiple logical storage cells, each logical storage cell containing at least one four-bit storage block; multiple dies containing logical cells together constitute NAND flash memory, and NAND flash memory, as the core storage medium, together with components such as the controller, constitutes a solid-state drive.
[0039] A four-bit storage block can be converted into a single-bit storage block for caching, and a single-bit storage block can also be converted back into a four-bit storage block. Here, the four-bit storage unit is the foundation of storage, the flash page is the unit of read / write, the four-bit block is the basic unit of erasure, the four-bit storage block is the basic unit of conversion and management, logical storage units and logical cells are the units of management and parallel operation, NAND flash memory is the core storage medium of a solid-state drive (SSD), and the SSD is a complete storage device.
[0040] In some technical solutions, static cache allocation schemes are used, fixing a portion of four-bit storage areas as single-bit storage areas for long-term cache. While this can improve storage performance, it leads to uneven wear between four-bit and single-bit storage units, affecting the lifespan of the solid-state drive (SSD). Dynamic cache allocation schemes, which dynamically set some four-bit storage units as single-bit storage units based on certain indicators, improve the flexibility of storage resource utilization, but dynamic switching may affect SSD performance, indicating insufficient optimization mechanisms. Therefore, how to achieve an effective balance between performance and wear in cache partitioning has become an urgent problem to be solved.
[0041] In view of this, this application provides a cache partitioning method that can solve the above problems. The cache partitioning method can be applied to electronic devices. Electronic devices may include, but are not limited to, tablet computers, laptops, desktop computers, servers, etc. (See also...) Figure 1 This is a flowchart illustrating a cache partitioning method provided in some embodiments of this application. Figure 1 In this context, the cache partitioning method includes the following steps:
[0042] Step S101: Obtain the bit error rate of each four-bit storage block in the hard disk, and find the target four-bit storage block with the highest bit error rate. Each four-bit storage block is used to store four bits of data.
[0043] Specifically, a hard drive is a solid-state drive (SSD) with NAND flash memory as its core storage medium. It includes components such as a controller and is responsible for managing operations such as reading, writing, erasing, and cache allocation of four-bit storage blocks.
[0044] A 4-bit storage block is a storage unit built based on 4-bit storage cells. Each 4-bit storage block can store four bits of data and is the carrier for data storage operations in NAND flash memory. When updating or erasing stored data, the entire 4-bit storage block must be erased before new data can be written. Furthermore, the bit error rate, wear parameters, and other performance characteristics of the 4-bit storage block directly affect the overall performance of the solid-state drive (SSD).
[0045] Bit error rate (BER) refers to the ratio of the number of erroneous bits in a four-bit storage block to the total number of bits during data storage. A higher BER indicates a greater probability of errors occurring in the stored data, signifying a gradual decline in storage performance. When the BER of a four-bit storage block increases, it indicates a decrease in the accuracy of the stored data. Converting it to a single-bit storage block as a cache can mitigate the performance drawbacks under high BER conditions while leveraging the advantages of single-bit storage in data read / write speeds, thus achieving efficient utilization of storage resources.
[0046] After obtaining the bit error rate (BER) of all four-bit storage blocks, it is necessary to identify the target four-bit storage block with the highest BER. Specifically, the BER of each four-bit storage block is compared one by one, and one or more four-bit storage blocks with the highest BER values are selected from all four-bit storage blocks. Since the target four-bit storage block with the highest BER may have an increased probability of errors during data storage, continuing to use it as a regular storage block could affect the reliability of data storage and overall performance. Identifying it as the target four-bit storage block prepares for subsequent mode conversion and can optimize hard drive storage efficiency.
[0047] Of course, it is understandable that the frequency and range of obtaining the bit error rate can be adjusted according to actual needs, and this application does not impose any restrictions on this.
[0048] Step S102: Convert the target four-bit storage block into the first single-bit storage block.
[0049] Specifically, a single-bit storage block is a storage unit built based on a single-bit storage cell. Each cell stores only 1 bit of data, and its storage density is much lower than that of a four-bit storage cell.
[0050] The storage mode parameters of this block can be adjusted via the hard disk controller, changing the voltage state configuration that originally supported four-bit data storage to a voltage state configuration that only supports single-bit data storage. During this process, the controller sends specific voltage signals to the storage cells within the block, redefining the electrical characteristics of the cells so that they can only represent two stable voltage states, corresponding to a single bit "0" and "1".
[0051] Step S103: Release the second single-bit storage block currently used as cache on the hard disk, and use the first single-bit storage block as cache on the hard disk, wherein each single-bit storage block is used to store one bit of data.
[0052] Specifically, the second single-bit storage block is the single-bit storage area currently serving as a cache, while the first single-bit storage block is a single-bit storage area that has just been converted from a four-bit storage block.
[0053] The hard drive controller manages the state of cache blocks. When a cache block needs to be replaced, it first performs a release operation on the second single-bit storage block. After processing the data within it, it is removed from the cache state. After releasing the second single-bit storage block, it can be converted into a four-bit storage block for use, thus improving storage space utilization; alternatively, it can continue to be used as a single-bit storage block, thereby improving data read and write speeds.
[0054] Simultaneously, the first single-bit storage block is converted to cache state, enabling it to begin fulfilling its caching responsibilities. This ensures the continuous stability of the caching function while allowing for the rational allocation of cache resources through block replacement. It prevents a single block from becoming excessively worn out due to prolonged cache use, while allowing the new single-bit storage block to leverage its advantages in high-speed access, thus improving overall cache performance.
[0055] In summary, in some embodiments of this application, based on the bit error rate of each four-bit storage block in the hard disk, the target four-bit storage block with the highest bit error rate is found, converted into a first single-bit storage block, and the second single-bit storage block currently used as cache in the hard disk is released. The first single-bit storage block is then used as the hard disk cache. This allows for dynamic adjustment of cache blocks based on the bit error rate of the four-bit storage blocks. Converting the four-bit storage block with the highest bit error rate into a single-bit storage block for cache avoids performance degradation due to its high bit error rate. Releasing the original cache block allows for a more balanced wear distribution across blocks. Thus, a balance can be achieved between cache performance and block wear, resolving the problem of unbalanced performance and wear in cache partitioning in some technologies.
[0056] In some embodiments, each four-bit storage block in step S101 includes a plurality of flash memory pages;
[0057] Obtain the bit error rate of each four-bit storage block in the hard disk, including:
[0058] For any four-bit storage block, obtain the bit error rate of each memory page in the four-bit storage block, and take the maximum bit error rate as the bit error rate of the four-bit storage block, or calculate the average bit error rate of the obtained bit error rates and take the average bit error rate as the bit error rate of the four-bit storage block.
[0059] Specifically, obtaining the bit error rate (BER) of each four-bit storage block in the hard drive is a crucial prerequisite for cache partitioning. Since each four-bit storage block consists of multiple flash pages, the BER of a single flash page directly affects the storage performance of the entire block. Therefore, it is necessary to determine the overall BER of the four-bit storage block by evaluating the BER of each flash page within the block.
[0060] For ease of understanding, assume that four-bit storage block A includes flash pages A1, A2, and A3; four-bit storage block B includes flash pages B1, B2, B3, and B4; and four-bit storage block C includes flash pages C1 and C2. In practice, the following operations can be performed:
[0061] 1) For a four-bit storage block A, which includes flash pages A1, A2, and A3. If the bit error rate (BER) of flash page A1 is 0.05%, the BER of flash page A2 is 0.08%, and the BER of flash page A3 is 0.06%, then when the maximum BER is used as the BER of this four-bit storage block, the BER of four-bit storage block A is 0.08%. Thus, the flash page with the highest BER in this four-bit storage block, i.e., the worst storage performance, can be identified, providing a basis for subsequent cache partitioning.
[0062] 2) For a four-bit storage block B, which includes flash pages B1, B2, B3, and B4. If the bit error rate (BER) of flash page B1 is 0.03%, the BER of flash page B2 is 0.05%, the BER of flash page B3 is 0.04%, and the BER of flash page B4 is 0.06%, then when the obtained BER rates are averaged, the BER of the four-bit storage block B is (0.03% + 0.05% + 0.04% + 0.06%) / 4 = 0.045%. This provides a comprehensive reflection of the overall BER of the four-bit storage block, avoiding excessive influence from individual extreme BER values.
[0063] 3) For a four-bit storage block C, which includes flash pages C1 and C2, if the bit error rate (BER) of flash page C1 is 0.02% and the BER of flash page C2 is 0.09%, either 0.09% can be chosen as the BER of the four-bit storage block C, or it can be calculated as (0.02% + 0.09%) / 2 = 0.055%. Thus, the method of calculating the BER can be determined according to the actual storage requirements to ensure that the obtained BER accurately serves subsequent operations such as cache partitioning.
[0064] In the above embodiments, when obtaining the bit error rate of a four-bit storage block, the bit error rate of each flash page in the four-bit storage block is also taken into account, and the bit error rate of the four-bit storage block is determined by taking the maximum bit error rate or the average bit error rate, which can improve the accuracy and comprehensiveness of the bit error rate assessment of the four-bit storage block.
[0065] In some embodiments, obtaining the bit error rate of each memory page of a four-bit storage block includes:
[0066] Write test data for detecting the bit error rate into each memory page;
[0067] Within a preset time period after the test data is written, data is read from each flash memory page, where the preset time period is less than the time threshold.
[0068] The read data is compared with the test data, and the error rate of each memory page is determined based on the comparison results.
[0069] Specifically, the preset duration refers to the time interval between writing the test data and reading the data, and the duration threshold is the critical value for judging whether the preset duration is reasonable.
[0070] Test data is written to each memory page. Within a preset time interval after the test data writing is complete, the data is read and compared with the test data. The number of error bits is counted, and the bit error rate (BER) is calculated for each memory page based on the ratio of error bits to the total number of bits. For example, after performing the above operation on memory page A, the BER of memory page A can be calculated based on the number of error bits and the total number of bits stored in that memory page. This process is repeated for other memory pages to obtain the BER of each memory page.
[0071] In the above embodiments, when obtaining the bit error rate of each memory page in a four-bit storage block, the accuracy of memory page bit error rate detection can be improved by writing test data to the memory page and reading and comparing the data within a preset time period, thus providing a more accurate basis for subsequent cache partitioning.
[0072] In some embodiments, the hard disk in step S101 is divided into at least one logical storage unit, and each logical storage unit includes at least one four-bit storage block.
[0073] Find the target four-bit storage block with the highest bit error rate, including:
[0074] According to the bit error rate, the four-bit storage blocks in each logical storage unit are sorted to obtain the sorting result;
[0075] Based on the sorting results, the four-bit storage block with the highest bit error rate in each logical storage unit is selected as the target four-bit storage block.
[0076] Specifically, by dividing the hard drive into multiple logical storage units and independently evaluating the four-bit storage blocks within each logical storage unit, it is possible to more accurately locate the storage areas that need optimization. Each logical storage unit contains multiple four-bit storage blocks, and their bit error rate reflects the reliability of that block. By sorting the four-bit storage blocks within each logical storage unit according to their bit error rates, the worst-performing target four-bit storage blocks can be identified first, providing a basis for subsequent cache optimization.
[0077] Referring to Table 1, similar operations can be performed in practice:
[0078] Table 1. Ranking of Bit Error Rate of Four-Bit Storage Blocks
[0079]
[0080] 1) For example, a hard drive is divided into 4 logical storage units, including logical storage unit 0, logical storage unit 1, logical storage unit 2, and logical storage unit 3. Each logical storage unit includes 4 four-bit storage blocks, namely four-bit storage block 0, four-bit storage block 1, four-bit storage block 2, and four-bit storage block 3.
[0081] 2) For logical storage cell 0, the bit error rate (BER) of the four-bit storage block 0 is 0, the BER of the four-bit storage block 1 is 1, the BER of the four-bit storage block 2 is 2, and the BER of the four-bit storage block 3 is 3. If the BERs are sorted from highest to lowest as follows: four-bit storage block 3 > four-bit storage block 1 > four-bit storage block 2 > four-bit storage block 0, then four-bit storage block 3 is selected as the target four-bit storage block for this cell.
[0082] 3) For logical storage unit 1, the bit error rates of its four-bit storage blocks 0 to 3 also correspond to bit error rates 0, 1, 2, and 3 in the table. If the bit error rates are sorted from high to low as four-bit storage block 0 > four-bit storage block 2 > four-bit storage block 1 > four-bit storage block 3, then four-bit storage block 0 is taken as the target four-bit storage block for this unit.
[0083] 4) For logical storage unit 2, the bit error rates of its four-bit storage blocks 0 to 3 also correspond to bit error rates 0, 1, 2, and 3 in the table. If the bit error rates are sorted from high to low as four-bit storage block 1 > four-bit storage block 3 > four-bit storage block 0 > four-bit storage block 2, then four-bit storage block 1 is taken as the target four-bit storage block for this unit.
[0084] 5) For logical storage unit 3, the bit error rates of its four-bit storage blocks 0 to 3 also correspond to bit error rates 0, 1, 2, and 3 in the table. If the bit error rates are sorted from high to low as four-bit storage block 1 > four-bit storage block 2 > four-bit storage block 3 > four-bit storage block 0, then four-bit storage block 1 is taken as the target four-bit storage block for this unit.
[0085] In the above embodiments, when searching for the target four-bit storage block with the highest bit error rate, sorting the four-bit storage blocks in each logical storage unit according to the bit error rate and taking the four-bit storage block with the highest bit error rate in each logical storage unit as the target four-bit storage block can improve the accuracy of the target four-bit storage block selection based on the highest bit error rate and provide a clearer target for subsequent cache partitioning operations.
[0086] In some embodiments, step S103 further includes, in response to the hard disk being powered on for the first time, converting at least one four-bit storage block in the hard disk into a third single-bit storage block, and using the third single-bit storage block as the initial cache of the hard disk.
[0087] Specifically, when a hard drive is first powered on, it does not yet have an effective caching mechanism and cannot quickly respond to the host's data access requests. At this time, at least one four-bit storage block on the hard drive can be converted into a third single-bit storage block and used as the hard drive's initial cache, enabling the hard drive to have complete data interaction capabilities from the initial stage.
[0088] For example, when the hard drive is powered on for the first time, the controller detects that there is no available cache. It then selects a four-bit storage block A from multiple four-bit storage blocks. The controller first clears the original data in the four-bit storage block A, and then adjusts its storage mode parameters so that it can only store single-bit data, that is, it is converted into a third single-bit storage block.
[0089] In the above embodiments, when the hard disk is powered on for the first time, by converting at least one four-bit storage block into a third single-bit storage block and using the third single-bit storage block as the initial cache of the hard disk, the data interaction capability of the hard disk during the boot phase can be improved, laying the foundation for subsequent dynamic adjustment of cache partitioning.
[0090] In some embodiments, after the first single-bit storage block is used as a cache on the hard disk in step S103, the method further includes:
[0091] In response to the hard disk being idle, the bit error rate of each four-bit storage block in the hard disk is retrieved again, and the target four-bit storage block with the highest bit error rate is searched again.
[0092] The target four-bit storage block that was re-found is converted into a fourth single-bit storage block;
[0093] Release the first single-bit storage block and use the fourth single-bit storage block as a cache for the hard drive.
[0094] Specifically, after the first single-bit storage area has been used as a cache for a period of time, the bit error rate of each four-bit storage block in the hard drive may change due to factors such as frequent read / write operations and long storage times. When the hard drive is idle, readjusting the cache will not affect the host's data access efficiency. At this time, re-acquiring the bit error rate of the four-bit storage block and replacing the cache can optimize the hard drive's storage performance.
[0095] For example, when the hard drive enters an idle state, the controller triggers a re-detection command to recalculate the bit error rate (BER) of all four-bit storage blocks. It finds that four-bit storage block A, which previously had a low BER, now has the highest BER and becomes the new target four-bit storage block. The controller then performs a conversion operation on four-bit storage block A, transforming it into a fourth single-bit storage block. At this point, the first single-bit storage block, which was originally used as cache, is released and restored to normal cache, while the fourth single-bit storage block is converted into a new cache.
[0096] In the above embodiments, after the first single-bit storage block is used as a hard disk cache, the bit error rate is reacquired in the hard disk idle state, the new target four-bit storage block is converted into the fourth single-bit storage block, and the original cache is released. This method can improve the performance stability of the hard disk cache and provide more reliable storage support for subsequent data read and write operations.
[0097] In some embodiments, after releasing the first single-bit storage block and the second single-bit storage block, the method further includes:
[0098] Convert the first and second single-bit storage blocks into four-bit storage blocks.
[0099] Specifically, when the first and second single-bit storage areas are used as caches, they operate in single-bit storage mode to ensure efficient read and write responses. Once released, they cease their caching function and are converted back to four-bit storage blocks to restore their high storage density and improve the overall storage space utilization of the hard drive.
[0100] For example, after the first and second single-bit storage blocks have completed their caching function and been released, the hard disk controller performs a mode switching operation. First, it erases the data, clearing the cached data. Then, it adjusts the storage parameters of the first and second single-bit storage blocks, switching them from a mode that only supports single-bit data storage to a mode that can store four bits of data. In this way, these two single-bit storage blocks can be reused as high-capacity storage units to store more data.
[0101] In the above embodiments, after releasing the first single-bit storage block and the second single-bit storage block, converting them into four-bit storage blocks can improve the overall storage space utilization of the hard disk and provide more sufficient storage space for subsequent data storage operations.
[0102] Corresponding to the cache partitioning method, this application also provides a cache partitioning apparatus. (See also...) Figure 2 This is a schematic diagram of a cache partitioning device provided in some embodiments of this application. Figure 2 In this context, the cache partitioning device includes:
[0103] Bit error rate acquisition module 201: used to acquire the bit error rate of each bit storage block in the hard disk, including acquiring the bit error rate of each flash page, and taking the maximum or average value as the bit error rate of the block;
[0104] Target block lookup module 202: used to find the target four-bit storage block with the highest bit error rate, sort the blocks in each logical storage unit according to the bit error rate, and take the block with the highest bit error rate in each unit as the target block;
[0105] Block conversion module 203: used to convert a target four-bit storage block into a first single-bit storage block, and also used to convert at least one four-bit storage block into a third single-bit storage block when the hard disk is powered on for the first time;
[0106] Cache switching module 204: used to release the second single-bit storage block currently being used as cache and use the first single-bit storage block as cache; also used to release the first single-bit storage block and use the fourth single-bit storage block as cache when the hard disk is in an idle state.
[0107] Initial cache configuration module 205: used to set the third single-bit storage block as the initial cache of the hard disk when it is first powered on.
[0108] In some embodiments, the bit error rate acquisition module 201 is specifically used for:
[0109] Obtain the bit error rate of each four-bit storage block in the hard disk, including:
[0110] For any four-bit storage block, obtain the bit error rate of each memory page in the four-bit storage block, and take the maximum bit error rate as the bit error rate of the four-bit storage block, or calculate the average bit error rate of the obtained bit error rates and take the average bit error rate as the bit error rate of the four-bit storage block.
[0111] In some embodiments, the bit error rate acquisition module 201 is specifically used for:
[0112] Write test data for detecting the bit error rate into each memory page;
[0113] Within a preset time period after the test data is written, data is read from each flash memory page, where the preset time period is less than the time threshold.
[0114] The read data is compared with the test data, and the error rate of each memory page is determined based on the comparison results.
[0115] In some embodiments, the target block lookup module 202 is specifically used for:
[0116] Find the target four-bit storage block with the highest bit error rate, including:
[0117] According to the bit error rate, the four-bit storage blocks in each logical storage unit are sorted to obtain the sorting result;
[0118] Based on the sorting results, the four-bit storage block with the highest bit error rate in each logical storage unit is selected as the target four-bit storage block.
[0119] In some embodiments, the initial cache configuration module 205 and the block conversion module 203 are specifically used for:
[0120] In response to the hard drive being powered on for the first time, at least one four-bit storage block in the hard drive is converted into a third single-bit storage block, and the third single-bit storage block is used as the initial cache of the hard drive.
[0121] In some embodiments, the cache switching module 204 and the block conversion module 203 are specifically used for:
[0122] In response to the hard disk being idle, the bit error rate of each four-bit storage block in the hard disk is retrieved again, and the target four-bit storage block with the highest bit error rate is searched again.
[0123] The target four-bit storage block that was re-found is converted into a fourth single-bit storage block;
[0124] Release the first single-bit storage block and use the fourth single-bit storage block as a cache for the hard drive.
[0125] In some embodiments, the cache switching module 204 and the block conversion module 203 are specifically used for:
[0126] Convert the first and second single-bit storage blocks into four-bit storage blocks.
[0127] For a description of the features in the embodiment corresponding to the data storage device, please refer to the relevant description in the embodiment corresponding to the sample data processing method, which will not be repeated here.
[0128] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.
[0129] See also Figure 3 The embodiments of this application also provide an electronic device, including a memory 10 and a processor 20, wherein the memory 10 stores a computer program and the processor 20 is configured to run the computer program to perform the steps in any of the above-described cache partitioning method embodiments.
[0130] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described cache partitioning method embodiments at runtime.
[0131] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.
[0132] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described cache partitioning method embodiments.
[0133] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described cache partitioning method embodiments.
[0134] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0135] The foregoing has provided a detailed description of a cache partitioning method, apparatus, device, and storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.
Claims
1. A cache partitioning method, characterized in that, The method includes: Obtain the bit error rate of each four-bit storage block in the hard disk, and find the target four-bit storage block with the highest bit error rate, wherein each four-bit storage block is used to store four bits of data; The target four-bit storage block is converted into a first single-bit storage block; Release the second single-bit storage block currently used as a cache in the hard disk, and use the first single-bit storage block as a cache for the hard disk, wherein each single-bit storage block is used to store one bit of data.
2. The method according to claim 1, characterized in that, Each of the four-bit storage blocks includes multiple flash memory pages; The process of obtaining the bit error rate of each four-bit storage block in the hard disk includes: For any of the four-bit storage blocks, the bit error rate of each memory page of the four-bit storage block is obtained, and the maximum bit error rate among the obtained bit error rates is taken as the bit error rate of the four-bit storage block, or the obtained bit error rates are averaged and the average bit error rate is taken as the bit error rate of the four-bit storage block.
3. The method according to claim 2, characterized in that, The step of obtaining the bit error rate of each memory page of the four-bit storage block includes: Test data for detecting the bit error rate is written into each of the memory pages; Within a preset time period after the test data writing is completed, data is read from each of the flash memory pages, wherein the preset time period is less than a time threshold. The read data is compared with the test data, and the error rate of each memory page is determined based on the comparison results.
4. The method according to claim 1 or 2, characterized in that, The hard disk is divided into at least one logical storage unit, and each logical storage unit includes at least one four-bit storage block; The search for the target four-bit storage block with the highest bit error rate includes: According to the bit error rate, the four-bit storage blocks in each of the logical storage units are sorted to obtain the sorting result; Based on the sorting results, the four-bit storage block with the highest bit error rate in each of the logical storage units is taken as the target four-bit storage block.
5. The method according to claim 1, characterized in that, The method further includes: In response to the hard disk being powered on for the first time, at least one of the four-bit storage blocks in the hard disk is converted into a third single-bit storage block, and the third single-bit storage block is used as the initial cache of the hard disk.
6. The method according to claim 1, characterized in that, After using the first single-bit storage block as a cache for the hard disk, the method further includes: In response to the hard disk being in an idle state, the bit error rate of each of the four-bit storage blocks in the hard disk is reacquired, and the target four-bit storage block with the highest bit error rate is searched again. The target four-bit storage block that was re-found is converted into a fourth single-bit storage block; Release the first single-bit storage block and use the fourth single-bit storage block as a cache for the hard disk.
7. The method according to claim 6, characterized in that, After releasing the first single-bit storage block and the second single-bit storage block, the method further includes: The first single-bit storage block and the second single-bit storage block are converted into four-bit storage blocks.
8. A cache partitioning device, characterized in that, The device includes: Bit error rate acquisition module: used to acquire the bit error rate of each bit storage block in the hard disk, including acquiring the bit error rate of each flash page, and taking the maximum or average value as the bit error rate of the block; Target Block Lookup Module: Used to find the target four-bit storage block with the highest bit error rate. It sorts the blocks in each logical storage unit according to their bit error rate and takes the block with the highest bit error rate in each unit as the target block. Block conversion module: used to convert a target four-bit storage block into a first single-bit storage block, and also used to convert at least one four-bit storage block into a third single-bit storage block when the hard drive is powered on for the first time; Cache switching module: used to release the second single-bit storage block currently being used as cache and use the first single-bit storage block as cache. It is also used to release the first single-bit storage block and use the fourth single-bit storage block as cache when the hard disk is idle. Initial cache configuration module: Used to set the third single-bit storage block as the initial cache of the hard drive when it is first powered on.
9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the cache partitioning method as described in any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the cache partitioning method as described in any one of claims 1 to 7.