HEMT chip preparation method and system

Abstract

The invention discloses an HEMT (High Electron Mobility Transistor) chip preparation method and system, and the method comprises the steps: carrying out the longitudinal etching on an epitaxial layer on an epitaxial wafer based on a first etching method, forming a plurality of physical isolation grooves, and dividing the epitaxial layer into a tube core array comprising a plurality of independent tube core units through the physical isolation grooves; for any tube core unit, epitaxially etching a step-shaped structure on the side surface of the tube core unit based on a second etching method; and bombarding the surface of the step-shaped structure by adopting ion current with strong electronegativity, so that active plasma in the ion current is combined with dangling bonds on the surface of the step-shaped structure to form a bonding layer so as to passivate the surface of the step-shaped structure. According to the method, the stable chemical bonding layer is formed, dangling bonds on the external delay surface are directly neutralized, surface state trapped charges are reduced, an electron migration path is blocked, and leakage current is greatly reduced; in addition, based on the formed bonding layer, the electric field distribution on the surface of the stepped structure can be effectively optimized, so that the breakdown voltage is improved.

Description

Technical Field

[0001] This invention relates to the field of chip manufacturing technology, and in particular to a method and system for fabricating HEMT chips. Background Technology

[0002] HEMT chips have significant advantages in high-frequency and high-power applications due to the presence of a two-dimensional electron gas (2DEG) at the AlGaN / GaN heterojunction interface. However, dry etching processes in chip manufacturing (such as MESA mesa etching) expose sidewalls, leading to dangling bonds and surface state trap charges, forming parasitic leakage paths, significantly increasing the off-state leakage current (IDSS) and reducing the breakdown voltage (BVDSS).

[0003] Current technologies for suppressing sidewall leakage mainly include: 1. Wet chemical passivation (such as sulfide treatment): It only acts on the surface, which is insufficient for repairing deep defects and has poor thermal stability; 2. Dielectric layer deposition (e.g.) Coverage): Physical isolation cannot eliminate dangling keys, and interface stress can easily induce new defects; The above methods are insufficient to simultaneously address leakage current suppression, breakdown voltage improvement, and low damage requirements, thus limiting the reliability and performance upgrades of HEMT chips. Summary of the Invention

[0004] The purpose of this invention is to provide a method and system for fabricating HEMT chips based on atomic-level bonding repair passivation process to prevent side leakage of the chip, thereby solving the above-mentioned technical problems.

[0005] To achieve the above objectives, the present invention provides a method for fabricating a HEMT chip, comprising: Based on the first etching method, longitudinal etching is performed on the epitaxial layer on the epitaxial wafer to form several physical isolation trenches. With the help of the physical isolation trenches, the epitaxial layer is divided into a die array including several independent die units. For any of the die units, a stepped structure is epitaxially etched on its side surface using the second etching method; The surface of the stepped structure is bombarded with a highly electronegative ion stream, causing the active ions in the ion stream to bond with the dangling bonds on the surface of the stepped structure to form a bonding layer, thereby passivating the surface of the stepped structure.

[0006] Preferably, before bombarding the surface of the stepped structure with an ion beam, the surface of the stepped structure is first activated and pretreated with oxygen ions.

[0007] Preferably, the active ion is a fluoride ion, and the method for generating the fluoride ion includes: In the plasma generator, The gas decomposes into fluoride ions and sulfur ions.

[0008] Preferably, an inert gas is also introduced into the plasma generator, wherein... The gas flow rate is 5-20 sccm for the gas and 10-30 sccm for the inert gas.

[0009] Preferably, the temperature of the ion stream is less than or equal to 150°C.

[0010] Preferably, the ion stream bombards the stepped structure for 30-120 seconds.

[0011] Preferably, the penetration depth of the ion flow in the stepped structure is controlled to be 5-20 nm.

[0012] Preferably, after the ion beam bombardment of the stepped structure surface is completed, the stepped structure is annealed in a nitrogen atmosphere at a temperature of 300-400°C for 1-5 minutes.

[0013] Preferably, after passivating the surface of the stepped structure with an ion stream, a deposition is also made on the surface of the stepped structure. or Passivation layer.

[0014] This invention also provides an HEMT chip fabrication system, which fabricates HEMT chips based on the HEMT chip fabrication method described above.

[0015] Compared with the prior art, the chip fabrication method provided by the above-mentioned technical solution of the present invention firstly bombards the surface of the stepped structure with a strong electronegative ion current, so that the active ions combine with dangling bonds to form a stable chemical bonding layer. The bonding layer directly neutralizes the surface dangling bonds, reduces surface state trap charges, blocks electron migration paths, and significantly reduces leakage current. Moreover, the chemical bonding layer has higher thermal stability and can maintain low leakage current characteristics even at high temperature. In addition, based on the formed bonding layer, the electric field distribution on the surface of the stepped structure can be effectively optimized, thereby improving the breakdown voltage. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the planar structure of the die unit after one etching step in an embodiment of the present invention.

[0017] Figure 2 This is a schematic diagram of the planar structure of the die unit after secondary etching in an embodiment of the present invention.

[0018] Figure 3 This is a flowchart of the chip fabrication method in an embodiment of the present invention. Detailed Implementation

[0019] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0020] This embodiment discloses a method for fabricating HEMT (High Electron Mobility Transistor) chips. Figure 3 The preparation method includes the following steps: S1: For the entire wafer, longitudinal etching is performed on the epitaxial layer on the epitaxial wafer using the first etching method to form several physical isolation trenches. These physical isolation trenches divide the epitaxial layer into several independent die units (such as…). Figure 1 ) of die array.

[0021] The epitaxial layers include a buffer layer, a C-GaN layer (intentionally doped layer), an i-GaN layer (unintentionally doped layer), and a barrier layer located above the sapphire substrate.

[0022] S2: For any die unit, based on the second etching method, a stepped structure is epitaxially etched on its side surface, such as... Figure 2 .

[0023] S3: A highly electronegative ion stream bombards the surface of the stepped structure, causing the active ions in the ion stream to combine with the dangling bonds on the surface of the stepped structure to form a bonding layer, thereby passivating the surface of the stepped structure.

[0024] The core of the HEMT chip fabrication method of this invention lies in the passivation treatment of the sidewalls of the HEMT epitaxial layer.

[0025] First, a series of physical isolation trenches are formed by longitudinal etching on the epitaxial layer of the epitaxial wafer using a first etching method. These physical isolation trenches divide the epitaxial layer into independent die units, ensuring electrical isolation between the chips.

[0026] Next, for each individual die unit, a second etching method is used to epitaxially etch a stepped structure on its side. This stepped structure is used to clearly delineate the active region (the region containing the source, drain, and gate) and the non-active region, and to provide a better contact interface for subsequent ion beam bombardment.

[0027] Finally, a highly electronegative ion beam is used to bombard the surface of the stepped structure. The active ions in the ion beam can chemically bond with the dangling bonds generated by etching on the surface of the stepped structure, forming a stable bonding layer.

[0028] The chip fabrication method provided by the above-mentioned technical solution of the present invention firstly generates a bonding layer that directly neutralizes surface dangling bonds, significantly reduces surface state trap charges, and blocks electron migration paths, thereby greatly reducing leakage current.

[0029] Secondly, due to the higher thermal stability of the chemical bonding layer, it can maintain low leakage current characteristics even at high temperatures, thus improving the reliability of the device.

[0030] Furthermore, dangling bonds would normally generate high-density surface states, trapping electrons and forming space charge regions that interfere with the electric field distribution and intensify the local electric field strength, leading to a decrease in the breakdown threshold. By forming a bonding layer, the surface state density is significantly reduced (by 1-2 orders of magnitude), thereby suppressing the interference of surface charges on the electric field. This mechanism directly reduces electric field inhomogeneity and improves the chip's breakdown voltage.

[0031] Finally, the 2DEG in HEMT originates from the polarization effect of the heterojunction. Exposed sidewalls can cause an imbalance of polarization charges or interface positive charges, leading to uneven electric field distribution. However, when the active ion is bonded to the dangling bond, it can introduce negative fixed charges, partially compensating for these polarization charges or interface positive charges, modulating the 2DEG concentration, and optimizing the electric field distribution, thereby further improving the breakdown voltage.

[0032] In the above embodiments, the first etching method can employ inductively coupled plasma (ICP) dry etching to achieve high aspect ratio physical isolation trenches. The second etching method can employ reactive ion etching (RIE) or atomic layer etching (ALE) to precisely control the sidewall morphology and angles of the stepped structure.

[0033] The generation of highly electronegative ion currents can be achieved using equipment such as plasma-enhanced chemical vapor deposition (PECVD) or ion beam sputtering. In addition to fluoride ions, active ionizers can also be other halide ions such as chloride and bromide ions, which possess strong electronegativity and can effectively bind to dangling bonds.

[0034] Furthermore, during ion bombardment, the energy and density of the ion flow can be controlled by adjusting parameters such as radio frequency power, gas flow rate, and chamber pressure, thereby optimizing the formation effect of the bonding layer.

[0035] On the other hand, before bombarding the surface of the stepped structure with an ion beam, the surface of the stepped structure is first activated and pretreated with oxygen ions.

[0036] When oxygen ions bombard the surface of a stepped structure, they can react with impurities such as hydrocarbons on the surface to generate volatile products, thereby achieving surface cleaning. At the same time, oxygen ions can also introduce more active sites or slight surface roughness into the surface, which helps to increase the contact area and reactivity between the active ions and the surface dangling bonds in the subsequent passivation ion stream, promotes the uniform formation of the bonding layer, and enhances the bonding strength.

[0037] Therefore, by pre-treating the stepped structure surface with oxygen ions before ion beam bombardment, this invention can significantly improve passivation efficiency and bonding layer quality. Firstly, the oxygen ion pretreatment effectively removes surface contaminants and weak bonding layers, allowing subsequent active ions to bind more directly and fully to dangling bonds, thus improving bonding efficiency and ensuring the uniformity and density of the bonding layer.

[0038] Secondly, the active sites introduced by the pretreatment on the surface enhance the surface's adsorption and reaction capabilities for active ions, making the bonding layer more robust and thus further reducing leakage current.

[0039] Furthermore, the optimized bonding layer can more effectively suppress surface state trapped charges, reduce electric field distortion, and thus improve the breakdown voltage of the device.

[0040] This pretreatment mechanism provides better surface conditions for atomic-level bonding repair without introducing additional thermal budget, thereby improving the performance and reliability of the overall passivation process.

[0041] In the above embodiments, oxygen ions can be generated through oxygen plasma treatment or ozone treatment. Oxygen plasma treatment is typically carried out in a vacuum chamber, where oxygen is excited by radio frequency (RF) or microwave (MW) energy, causing it to decompose into oxygen ions and reactive oxygen free radicals. The treatment time is generally 10 to 60 seconds, and the power range is around 50W to ensure surface activation without causing damage.

[0042] Furthermore, the concentration and energy of oxygen ion pretreatment can be adjusted according to the specific conditions of the stepped surface structure. For example, for samples with heavy surface contamination, the treatment time and power can be appropriately increased.

[0043] On the other hand, the active ion is a fluoride ion, and the methods for generating fluoride ions include: In the plasma generator, The gas decomposes into fluoride ions and sulfur ions.

[0044] In a plasma environment, through excitation by radio frequency (RF) or microwave (MW) energy, The molecule undergoes ionization and decomposition, producing various reactive species, including fluoride radicals (F·), negatively charged fluoride ions (F-), and sulfide ions (S+), and may also produce a small amount of positively charged fluoride ions (F+). Fluoride radicals (F·) and negatively charged fluoride ions (F-) can react chemically with dangling bonds, therefore these two types of ions are the target fluoride ions.

[0045] In this process, the plasma generator provides high-energy electrons and ions, which interact with... Molecular collisions break them apart and form the desired fluoride ions. This is achieved through precise control of the plasma generator's operating parameters, such as radio frequency power, chamber pressure, and... Gas flow rate can optimize the yield and purity of fluoride ions, ensuring that they meet the requirements of subsequent passivation treatment.

[0046] By using plasma generator The gas decomposes into fluoride and sulfur ions to generate fluoride ions, achieving a highly efficient and controllable fluoride ion source. Firstly, The gas has a high fluorine content, which can generate a high concentration of fluorine ions after plasma decomposition, ensuring a sufficient supply of active ions during the passivation process.

[0047] Secondly, plasma decomposition This method offers excellent process controllability. By adjusting parameters such as RF power, gas flow rate, and chamber pressure, the energy and quantity of fluoride ions can be precisely controlled, thereby optimizing the passivation effect. This stable fluoride ion generation method helps ensure the uniformity and density of the bonding layer, further reducing leakage current and increasing breakdown voltage.

[0048] In the above embodiments, the plasma generator can be of various types, such as inductively coupled plasma (ICP) sources, electron cyclotron resonance (ECR) sources, or parallel-plate radio frequency (RF) plasma sources. Among them, ICP sources have advantages in fluoride ion generation because they can generate high-density plasma and independently control ion energy. The purity of the gas should reach semiconductor grade (typically 99.999% or higher) to avoid introducing impurities.

[0049] Furthermore, an inert gas is introduced into the plasma generator. The gas flow rate is 5-20 sccm (standard cubic centimeters per minute) for gaseous gases and 10-30 sccm for inert gases.

[0050] The main purpose of introducing inert gas is to stabilize the plasma and act as a diluent. Inert gas will not react with... While chemical reactions occur, the atoms of the inert gas, after being ionized in the plasma, can provide additional electrons and ions, helping to maintain the stability and homogeneity of the plasma. Simultaneously, the inert gas, acting as a carrier gas, can help... Molecules diffuse more evenly into the plasma region and are diluted. The decomposition products are reduced, and the interactions between active species are decreased, thereby optimizing the yield of fluoride ions.

[0051] Therefore, the introduction of inert gas significantly improves the stability of the plasma and reduces its inhomogeneity, thereby making the generation of fluoride ions more stable and controllable, and ensuring the consistency of the passivation treatment.

[0052] Secondly, inert gases, as diluents, can effectively regulate... The decomposition rate of the gas and the concentration of fluoride ions should be considered to avoid [further factors]. Excessive concentration can lead to over-etching or damage, while ensuring a sufficient concentration of active fluoride ions for passivation. Precise control of the gas flow rate (5-20 sccm) and the inert gas flow rate (10-30 sccm) optimizes the generation efficiency of fluoride ions, enabling them to effectively bond with dangling bonds and form a uniform and dense bonding layer. This further reduces leakage current and increases breakdown voltage. This optimized gas ratio ensures passivation effectiveness while also improving process stability and repeatability.

[0053] In the above embodiments, the inert gas is preferably argon (Ar) because it has a high ionization energy and low chemical reactivity, and will not react with... Or its decomposition products may undergo adverse reactions.

[0054] The inert gas flow rate can be fine-tuned depending on the specific model of the plasma generator, the cavity volume, and the required fluoride ion concentration. For example, in some high-density plasma sources, a higher inert gas flow rate may be required to maintain plasma stability. The flow rates of the gas and inert gas can be precisely controlled using a mass flow controller (MFC) to ensure flow stability and repeatability. In practice, the optimal gas flow rate combination can be determined through experimental optimization to achieve the highest fluoride ion yield and best passivation effect.

[0055] On the other hand, the temperature of the ion flow is less than or equal to 150°C.

[0056] During ion bombardment, although ions have a certain kinetic energy, the temperature of the chip surface can be effectively maintained below 150°C by precisely controlling the power of the plasma source, the cavity pressure, and the substrate cooling system.

[0057] By controlling the ion flow temperature to less than or equal to 150°C, the passivation effect of the HEMT chip was ensured. Firstly, the low thermal budget passivation process effectively avoids material degradation, interface diffusion, and lattice damage that can be caused by high temperatures, thus protecting the original structural integrity and electrical performance of the HEMT device and ensuring high reliability. Secondly, the low-temperature treatment reduces thermal stress, lowering the risk of film cracking or peeling due to thermal expansion coefficient mismatch and improving the stability of the bonding layer. Most importantly, under low-temperature conditions, the active ion can still effectively combine with dangling bonds to form a stable bonding layer, significantly reducing leakage current and increasing breakdown voltage, achieving effective passivation of heat-sensitive devices without sacrificing device performance.

[0058] In the above embodiments, various technical measures can be taken to control the temperature of the ion flow below 150°C. For example, the power and pulse mode of the plasma source can be optimized, and low-power or pulsed plasma can be used to reduce the thermal load on the substrate. In actual operation, an infrared thermometer or thermocouple can be used to monitor the sample surface temperature in real time to ensure that the temperature is controlled within the set range.

[0059] On the other hand, the ion stream bombards the stepped structure for 30-120 seconds.

[0060] This optimized time window ensures that the active ion has sufficient time to fully bond with the dangling bonds on the stepped surface structure, forming a uniform and dense bonding layer. This effectively neutralizes surface-state trapped charges, significantly reducing off-state leakage current and improving device reliability. Secondly, by avoiding excessively long ion bombardment, this invention minimizes physical damage to the HEMT chip, such as increased surface roughness or the introduction of lattice defects, thereby protecting the original electrical performance of the device. Furthermore, within this time frame, process repeatability and stability are guaranteed, facilitating mass production. Precise timing control achieves an optimal balance in passivation, effectively suppressing leakage current and increasing breakdown voltage while minimizing damage to the device.

[0061] In practice, the specific bombardment time can be further optimized by performing electrical performance tests (such as leakage current and breakdown voltage) and surface analyses (such as XPS and AFM) on samples at different bombardment times.

[0062] On the other hand, the penetration depth of the ion flow in the stepped structure is controlled to be 5-20 nm.

[0063] This penetration depth range is designed to ensure that the active plasma can penetrate deep into the areas of the stepped structure surface where dangling bonds and surface state defects exist due to etching, and form a bonding layer therewith to achieve the best passivation effect, while maximizing the protection of the active areas of the HEMT chip.

[0064] Specifically, this precise penetration depth ensures that the active ion can effectively reach and neutralize the dangling bonds and surface state trap charges generated by etching on the stepped structure surface, thereby significantly reducing off-state leakage current and improving device reliability. Secondly, by avoiding excessive ion penetration, this invention maximizes the protection of the active layer and two-dimensional electron gas (2DEG) channels inside the HEMT chip, preventing a decrease in carrier mobility or the introduction of new defects due to ion damage, thus maintaining the device's excellent electrical performance. Furthermore, precise control of the penetration depth helps form a uniform and stable bonding layer, improving the consistency and repeatability of the passivation effect.

[0065] In the above embodiments, methods for controlling the penetration depth of the ion current include, but are not limited to, adjusting the energy of the ion current, the bombardment time of the ion current, the chamber pressure, and the incident angle of the ion current. Generally, the higher the ion energy, the greater the penetration depth; the longer the bombardment time, the greater the penetration depth. The penetration depth can be reduced by lowering the ion energy (e.g., by reducing the radio frequency power or bias voltage). For example, controlling the ion energy in the range of tens to hundreds of electron volts (eV) can achieve nanometer-scale penetration depths.

[0066] On the other hand, although the surface dangling bonds of the HEMT chip are effectively neutralized after ion bombardment passivation, the newly formed bonding layer may have certain bonding stress or an unstable structure. To further optimize the quality of the bonding layer, enhance the durability of the passivation effect, and repair any minor damage caused by ion bombardment, annealing is required. Specifically, after ion bombardment of the stepped structure surface, the stepped structure is annealed in a nitrogen atmosphere at a temperature of 300-400°C for 1-5 minutes.

[0067] Annealing in a nitrogen atmosphere effectively prevents surface oxidation at high temperatures, protecting the integrity of the bonding layer. An annealing temperature of 300-400°C provides sufficient energy for the atoms in the bonding layer to rearrange, forming a more stable and denser structure, thus enhancing bonding strength, while also preventing excessive thermal stress or lattice damage to the HEMT chip.

[0068] Within this temperature range, the chemical bonds formed between the active ion and the dangling bond are further strengthened, and minor defects introduced during ion bombardment may be repaired. An annealing time of 1-5 minutes ensures sufficient stabilization of the bonded layer while avoiding negative effects that may be caused by prolonged high temperatures (such as interfacial diffusion or ohmic contact degradation).

[0069] In the above embodiments, the annealing equipment can be a rapid thermal annealing (RTA) furnace or a tube furnace. RTA furnaces, due to their rapid heating and cooling capabilities, allow for more precise control of annealing time and temperature, making them particularly suitable for heat-sensitive HEMT devices. Nitrogen gas should be of semiconductor grade purity (typically 99.999% or higher) to ensure an inert annealing atmosphere.

[0070] During the annealing process, the RTA annealing equipment cavity can be preheated to ensure temperature uniformity within the cavity. The specific selection of annealing temperature and time can be fine-tuned based on the material and thickness of the bonding layer and the specific structure of the HEMT device. For example, a thicker bonding layer may require a longer annealing time. After annealing, the chip should be slowly cooled to room temperature to avoid defects caused by thermal stress. Furthermore, the performance of the annealed bonding layer and device can be analyzed using characterization techniques such as XPS, AFM, and PL (photoluminescence) to evaluate the annealing effect.

[0071] On the other hand, after passivating the surface of the stepped structure with ion flow, a deposition process is also performed on the surface of the stepped structure. or Passivation layer.

[0072] This additional dielectric layer deposition step is performed after the formation of the atomic-level bonding layer. (Silicon nitride) and Alumina possesses a high dielectric constant, good chemical stability, and mechanical strength. These dielectric layers can be deposited using techniques such as plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).

[0073] The layer provides excellent passivation, reduces surface charge, and has good water and oxygen barrier properties. The layer, due to its high dielectric constant and good compatibility with the GaN interface, can effectively suppress surface traps.

[0074] In this embodiment, this dual passivation structure combines the advantages of atomic-level bonding repair (eliminating dangling bonds) with the advantages of dielectric layer passivation (physical isolation and electric field modulation), achieving more comprehensive and durable suppression of surface defects. The bonding layer fundamentally solves the dangling bond problem, while the outer layer... or This provides additional protection against the effects of environmental factors (such as moisture and oxygen) on device performance, significantly reducing off-state leakage current and increasing breakdown voltage. Secondly, the dielectric layer further stabilizes the surface electric field of the device, reducing interference from surface states on the electric field distribution, thereby improving the device's stability under high voltage operation. Furthermore, or The layer also provides protection for subsequent metallization and packaging processes, enhancing the mechanical strength and environmental adaptability of HEMT chips, and significantly improving the long-term reliability and market competitiveness of the devices.

[0075] In another preferred embodiment of the present invention, an HEMT chip fabrication system is also disclosed, which fabricates HEMT chips based on the above-described HEMT chip fabrication method.

[0076] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A method for fabricating an HEMT chip, characterized in that, include: Based on the first etching method, longitudinal etching is performed on the epitaxial layer on the epitaxial wafer to form several physical isolation trenches. With the help of the physical isolation trenches, the epitaxial layer is divided into a die array including several independent die units. For any of the die units, a stepped structure is epitaxially etched on its side surface using the second etching method; The surface of the stepped structure is bombarded with a highly electronegative ion stream, causing the active ions in the ion stream to bond with the dangling bonds on the surface of the stepped structure to form a bonding layer, thereby passivating the surface of the stepped structure.

2. The HEMT chip fabrication method according to claim 1, characterized in that, Before bombarding the surface of the stepped structure with an ion beam, the surface of the stepped structure is first activated and pretreated with oxygen ions.

3. The HEMT chip fabrication method according to claim 1, characterized in that, The active ion is a fluoride ion, and the method for generating the fluoride ion includes: In the plasma generator, The gas decomposes into fluoride ions and sulfur ions.

4. The HEMT chip fabrication method according to claim 3, characterized in that, An inert gas is also introduced into the plasma generator. The gas flow rate is 5-20 sccm for the gas and 10-30 sccm for the inert gas.

5. The HEMT chip fabrication method according to claim 1, characterized in that, The temperature of the ion stream is less than or equal to 150°C.

6. The HEMT chip fabrication method according to claim 1, characterized in that, The ion stream bombards the stepped structure for 30-120 seconds.

7. The HEMT chip fabrication method according to claim 1, characterized in that, The penetration depth of the ion flow in the stepped structure is controlled to be 5-20 nm.

8. The HEMT chip fabrication method according to claim 1, characterized in that, After the ion beam bombardment of the stepped structure surface is completed, the stepped structure is annealed in a nitrogen atmosphere at a temperature of 300-400°C for 1-5 minutes.

9. The HEMT chip fabrication method according to claim 1, characterized in that, After passivating the surface of the stepped structure with an ion flow, deposition is also performed on the surface of the stepped structure. or Passivation layer.

10. A HEMT chip fabrication system, characterized in that, The fabrication system fabricates HEMT chips based on the HEMT chip fabrication method according to any one of claims 1 to 9.

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