Manufacturing method of printed circuit board with embedded passive device

Abstract

The invention relates to the technical field of circuit board processing, and discloses a manufacturing method of a printed circuit board with an embedded passive device, which comprises the following steps of: preparing a combined structure body which comprises a temporary carrier and a printed circuit board outer layer pattern formed on the temporary carrier; combining the passive device body with the outer layer pattern in a specific area of the combined structure body by adopting an attaching mode to form a composite structure body containing the passive device; and overlapping the composite structural body containing the passive device, a film, a printed circuit board with an inner layer structure and a copper foil according to a preset sequence to form an overlapped assembly. According to the manufacturing method of the printed circuit board with the embedded passive device, impedance abrupt change caused by poor interlayer contact is effectively eliminated, the power supply integrity and the signal integrity are greatly improved, and the quick response requirement of a high-integration-level chip in a high-speed switching transient state can be met.

Description

Technical Field

[0001] This invention relates to the field of circuit board processing technology, specifically to a method for manufacturing a printed circuit board with embedded passive components. Background Technology

[0002] As the demand for increased computing power grows, chip integration is constantly improving. This makes the timeliness and integrity of chip power supply increasingly important, as it has become a key factor in reducing switching noise. By ensuring power supply stability, the disruption of signal integrity by switching noise during high-speed transmission can be avoided, thereby reducing the bit error rate of signal transmission. At the same time, the increased chip integration leads to a greater number of passive components required, posing challenges to printed circuit board layout design.

[0003] In existing surface mount technologies, the distance between the power and signal ports of the chip or multi-chip package and passive components is relatively large, which easily generates parasitic capacitance and inductance, resulting in poor signal integrity and making it difficult to meet the signal quality requirements of high-speed transmission scenarios. For embedded structures, although the distance between passive components and chip ports is closer than in traditional surface mount methods, optimal layout is still not achieved, and the negative impact of parasitic parameters cannot be completely eliminated, resulting in limited improvement in signal and power integrity. Furthermore, both existing technologies struggle to efficiently arrange a large number of passive components within a limited PCB space, limiting the integration capabilities of high-performance, highly integrated chips and failing to meet the stringent requirements for extreme signal integrity, power integrity, and high-density wiring in scenarios such as high-performance AI computing units and high-speed data communication systems. Summary of the Invention

[0004] The purpose of this invention is to solve the above-mentioned problems by proposing a method for manufacturing a printed circuit board with embedded passive devices.

[0005] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: A method for manufacturing a printed circuit board with embedded passive components includes the following steps: S10. Prepare an assembly structure, which includes a temporary carrier and an outer layer pattern of a printed circuit board formed on the temporary carrier. S20. In a specific area of ​​the combined structure, the passive device body is attached to the outer pattern to form a composite structure containing passive devices. S30. The composite structure containing passive components, the film, the printed circuit board with the inner layer structure, and the copper foil are stacked in a preset order to form a stacked assembly, wherein the composite structure containing passive components is located between the film and the printed circuit board with the inner layer structure, and the copper foil is located on the side away from the composite structure. S40. Perform a hot pressing process on the stacked components to bond and solidify the outer layer pattern, film, passive component body, printed circuit board with inner layer structure and copper foil into one piece to form a preliminary composite board. S50. Separate the preliminary composite plate from the temporary carrier to obtain an intermediate with inner and outer layer structures; S60. Drill holes in the intermediate body to form VIA holes, metallize the VIA holes, and create an outer layer pattern on the side of the intermediate body away from the original temporary carrier to obtain a printed circuit board with embedded passive devices.

[0006] Based on the above technical solution, the present invention can be further improved as follows.

[0007] Furthermore, the temporary carrier in S10 is a peelable carrier, and its material is selected from one of polyimide film, polyester film or aluminum foil, with a thickness of 25-100μm; the outer layer pattern of the printed circuit board is formed by photolithography etching process, and its pattern accuracy is controlled within ±0.02mm. The surface roughness of the PAD area in the outer layer pattern used to bond with the passive device body is 0.8-1.2μm.

[0008] Furthermore, in S20, the bonding method is to use an organic polymer conductive adhesive for bonding. The organic polymer conductive adhesive is an epoxy resin-based conductive adhesive with a solid content of 60-80%, and the conductive particles are silver powder or copper powder with a particle size of 1-5μm and a coating thickness of 10-30μm. The passive device body includes at least one of a capacitor, a resistor, and an inductor, wherein the capacitor is a high dielectric constant ceramic capacitor with a dielectric constant ≥1000, the resistor is a thin film resistor with an accuracy ≤±1%, and the inductor is a wire-wound inductor or a multilayer inductor with a Q value ≥50.

[0009] Furthermore, the film in S30 is a modified epoxy resin film with a thickness of 50-150μm, a melt viscosity of 500-1500cP, a curing temperature of 160-180℃, and a curing time of 60-90min; the printed circuit board with the inner layer structure is a multilayer board, with the line width and spacing of the inner layer lines being 30 / 30μm-50 / 50μm, the interlayer dielectric thickness being 80-120μm, and the inner layer having a power layer and a ground layer, with a spacing of 50-80μm between the power layer and the ground layer.

[0010] Furthermore, the parameters for the hot pressing process in S40 are: hot pressing temperature 170-190℃, pressure 20-30 kgf / cm². 2 The heating rate is 5-10℃ / min, the holding time is 90-120min, and the cooling rate is ≤5℃ / min.

[0011] Furthermore, the separation method in S50 is either mechanical peeling or chemical corrosion peeling. Mechanical peeling uses a special peeling tool, with the peeling angle controlled at 30°-60° and the peeling speed at 5-10 mm / s. Chemical corrosion peeling uses a 5-10% sodium hydroxide solution, which is soaked at 50-60°C for 10-20 minutes before peeling.

[0012] Furthermore, in S60, the drilling process employs either laser drilling or mechanical drilling. Laser drilling produces holes with a diameter of 50-150 μm and a positional accuracy of ±5 μm, while mechanical drilling produces holes with a diameter of 200-500 μm and a positional accuracy of ±10 μm. The VIA hole metallization process includes deburring, desmearing, chemical copper plating, and electrolytic copper plating. The chemical copper plating layer has a thickness of 0.5-1 μm, and the electrolytic copper plating layer has a thickness of 15-25 μm. After metallization, the VIA hole's on-resistance is ≤5 mΩ.

[0013] Furthermore, the printed circuit board with embedded passive devices is one of Anylayer board, traditional blind via board, high-density printed circuit board, or coreless board; when it is an HDI board, it has 6-12 layers, the outermost layer line width and spacing is 20 / 20μm-30 / 30μm, the embedded passive device is located in the inner layer 1-3 layers away from the surface, and the distance between it and the power port of the BGA packaged chip on the HDI board is ≤0.5mm.

[0014] Furthermore, in S20, the position of the passive device body corresponds to the signal output port or power output port of the active device package subsequently assembled on the printed circuit board, and the straight-line distance between the two is ≤1mm; the active device package is a single-chip package or a multi-chip integrated package, and its pin pitch is 0.4-1mm.

[0015] Furthermore, the method also includes S70: performing reliability testing on the completed printed circuit board with embedded passive devices, including temperature cycling test, damp heat test and vibration test; after the test, the bonding strength between the embedded passive device body and the printed circuit board is ≥5N, and the on-resistance change rate of the VIA hole is ≤10%.

[0016] Compared with the prior art, the technical solution of this application has the following beneficial technical effects: This invention achieves the embedding of passive components within the PCB by directly integrating the passive component body with the outer layer pattern and then laminating it between the film and the inner circuit board. This significantly shortens the physical distance between the passive component and the chip's power and signal ports, fundamentally reducing parasitic capacitance and inductance. Addressing the shortcomings of existing embedded structures with poor layout and limited improvement, this invention uses a hot-pressing process to tightly bond and solidify the outer layer pattern, film, passive component body, and inner circuit board, ensuring that the embedded passive component forms a stable whole with the surrounding structure. Combined with VIA via metallization, reliable interconnection between inner and outer layers is achieved, effectively eliminating impedance abrupt changes caused by poor interlayer contact, and significantly improving power integrity and signal integrity. It can meet the rapid response requirements of highly integrated chips under high-speed switching transients. Addressing the problem of two existing technologies that struggle to efficiently arrange a large number of passive components in a limited space, this invention embeds the passive component within the PCB inner layer, freeing up wiring space on the PCB surface and enabling more passive components to achieve high-density integration within a limited space. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the outer layer pattern and temporary carrier of a printed circuit board in the prior art; Figure 2 This is a schematic diagram of a structure in the prior art where a passive device structure is attached to an outer patterned PAD using an organic polymer adhesive. Figure 3 This is a schematic diagram of how an outer layer pattern containing passive device structures and a temporary carrier are combined with an inner layer pattern PCB using film in the prior art. Figure 4 This is a schematic diagram of a PCB structure formed by combining the outer layer pattern and temporary carrier with the inner layer pattern of a specific passive device structure through a hot-pressing process. Figure 5 This is a schematic diagram of the structure after the temporary carrier on the laminated PCB is peeled off according to the present invention.

[0018] Figure 6 This is a schematic diagram of the structure of a multilayer integrated printed circuit board with the unique reinforcement structure of this invention, which is the only one with this invention after the PCB with the embedded passive device structure has been drilled, the VIA holes have been metallized and the pattern on the other side has been etched. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] The present invention discloses a method for manufacturing a printed circuit board with embedded passive devices, comprising the following steps: S10. Prepare an assembly structure, which includes a temporary carrier and an outer layer pattern of a printed circuit board formed on the temporary carrier. S20. In a specific area of ​​the composite structure, the passive device body is attached to the outer pattern to form a composite structure containing passive devices. S30. The composite structure containing passive components, the film, the printed circuit board with the inner layer structure, and the copper foil are stacked in a preset order to form a stacked assembly, wherein the composite structure containing passive components is located between the film and the printed circuit board with the inner layer structure, and the copper foil is located on the side away from the composite structure. S40. Perform hot pressing process on the stacked components to bond and solidify the outer layer pattern, film, passive component body, printed circuit board with inner layer structure and copper foil into one piece to form a preliminary composite board. S50. Separate the preliminary composite plate from the temporary carrier to obtain an intermediate with inner and outer layer structures; S60. Drill holes in the intermediate body to form VIA holes, metallize the VIA holes, and create an outer layer pattern on the side of the intermediate body away from the original temporary carrier to obtain a printed circuit board with embedded passive devices.

[0021] The temporary carrier in S10 is a peelable carrier, and its material is selected from one of polyimide film, polyester film or aluminum foil, with a thickness of 25-100μm; the outer layer pattern of the printed circuit board is formed by photolithography etching process, and its pattern accuracy is controlled within ±0.02mm. The surface roughness of the PAD area in the outer layer pattern used to bond with the passive device body is 0.8-1.2μm to enhance the bonding force during subsequent attachment. Using such temporary carriers not only facilitates subsequent separation steps and avoids damage to the surface of the initial composite board, but also provides stable support for the outer layer pattern during lamination and hot pressing, ensuring the integrity of the pattern structure. Meanwhile, the PAD areas with specific roughness can improve the mechanical bonding strength between the passive device body and the outer layer pattern, reducing the risk of separation due to vibration or temperature changes during later use. The peelable carrier provides stable support during hot pressing, preventing deformation of the outer layer pattern and ensuring efficient utilization of wiring space. The high-precision pattern and rough PAD areas enhance the mechanical interlocking between the passive device and the outer layer pattern, reducing the risk of separation due to vibration or temperature changes, laying the foundation for high-density placement of passive devices.

[0022] In the temporary carrier, polyimide film has a temperature resistance of ≥200℃ and can withstand subsequent hot pressing processes at 170-190℃ without deformation; polyester film has excellent flexibility and is suitable for the fabrication of thin PCBs. In the photolithography etching process, positive photoresist such as AZ4620 is used, and the exposure dose is controlled at 120-150mJ / cm². 2 A development time of 60-90 seconds achieves a pattern accuracy of ±0.02mm; the roughness of the PAD area is achieved through a micro-etching process, specifically using a 120g / L ammonium persulfate solution at 30℃ for 10-15 seconds to form a uniform micro-uneven structure, increasing the contact area between the conductive adhesive and the PAD by more than 30%, further enhancing the bonding strength.

[0023] The S20 is attached using an organic polymer conductive adhesive, which is an epoxy resin-based conductive adhesive with a solid content of 60-80%. The conductive particles are silver or copper powder with a particle size of 1-5μm and a coating thickness of 10-30μm. The passive device body includes at least one of a capacitor, a resistor, and an inductor. The capacitor is a high dielectric constant ceramic capacitor with a dielectric constant ≥1000. The resistor is a thin film resistor with an accuracy ≤±1%. The inductor is a wire-wound inductor or a multilayer inductor with a Q value ≥50 (at 1MHz). Using organic polymer conductive adhesive not only achieves mechanical fixation between passive components and outer layer patterns, but its conductivity also ensures reliable electrical connections between them, avoiding problems such as cold solder joints and solder bridging that may occur in traditional soldering processes. Furthermore, selecting high-performance passive components ensures signal and power integrity on the embedded printed circuit board in high-frequency, high-speed scenarios, meeting the demands of high-end applications such as AI high-computing units. Epoxy resin-based conductive adhesive achieves reliable connections between passive components and outer layer patterns, avoiding the defects of traditional soldering. The conductivity of the conductive adhesive ensures reliable electrical connections, while high-performance components operate stably in high-frequency scenarios, meeting the stringent signal transmission quality requirements of AI high-computing units.

[0024] Adding 1.5-2% silane coupling agent to epoxy resin-based conductive adhesive can improve interfacial adhesion with copper PADs. Its curing process uses "120℃ / 20min pre-curing + 160℃ / 40min full curing," ensuring compatibility with subsequent hot-pressing processes and eliminating the risk of secondary melting. The high-dielectric-constant ceramic capacitor uses BaTiO3-TiO2 composite ceramic material, with 0.5% La2O3 doping optimizing the grain size, resulting in a dielectric constant fluctuation of ≤5% at 1MHz. The thin-film resistor uses NiCr alloy material with a temperature coefficient ≤±25ppm / ℃, ensuring a resistance change of ≤0.5% within the range of -55℃ to 125℃, thus improving circuit stability.

[0025] The S30 film is a modified epoxy resin film with a thickness of 50-150μm, a melt viscosity of 500-1500cP (at 120℃), a curing temperature of 160-180℃, and a curing time of 60-90min. The printed circuit board with the inner layer structure is a multilayer board with a line width and spacing of 30 / 30μm-50 / 50μm for the inner layer circuits, an interlayer dielectric thickness of 80-120μm, and the inner layer has a power layer and a ground layer, with a spacing of 50-80μm between the power layer and the ground layer. Modified epoxy resin film possesses excellent flowability and adhesion, effectively filling the gaps between passive components and the inner circuit board during hot pressing to form a dense insulating layer, preventing interlayer bubbles or voids. The parameter design of the inner layer structure provides a suitable operating environment for the embedded passive components. In particular, the optimal spacing between the power and ground layers, combined with the high-dielectric-constant dielectric layer, forms an efficient decoupling structure, further improving power integrity. The modified epoxy resin film effectively fills the gaps between passive components and the inner circuit board during hot pressing, preventing voids. Simultaneously, the optimized spacing between the inner power and ground layers, working in conjunction with the high-dielectric-constant dielectric layer, forms an efficient decoupling structure, overcoming the limitation of limited power integrity improvement caused by poor embedded layouts. The film's dense insulating layer and optimal inner layer parameters provide a suitable environment for passive components, enhancing power response speed.

[0026] Adding 8-10% nano-Al2O3 particles (80nm in diameter) to the modified epoxy resin film can improve melt flowability by 20% while reducing curing shrinkage to ≤0.5%, thus preventing interlayer cracking. The inner layer circuitry uses electrolytic copper foil, achieving 30 / 30μm linewidth and spacing through a negative etching process, with an edge roughness ≤5μm. The interlayer dielectric is glass fiber reinforced epoxy resin with a dielectric constant of 4.2±0.2. The power layer employs a hybrid design of "grid + solid area," with a grid linewidth of 50μm and a spacing of 200μm, ensuring current transmission while reducing parasitic coupling with the ground plane.

[0027] The parameters for the hot pressing process in S40 are: hot pressing temperature 170-190℃, pressure 20-30 kgf / cm². 2The heating rate is 5-10℃ / min, the holding time is 90-120min, and the cooling rate is ≤5℃ / min. These hot-pressing parameters are determined based on the curing characteristics of the film and the temperature resistance of the passive components. Higher temperatures and pressures ensure the film fully melts and bonds tightly to each layer, while preventing performance degradation of the passive components due to excessively high temperatures. Slow heating and cooling rates reduce thermal stress within the laminated assembly, lowering the risk of warping or cracking and ensuring dimensional stability of the printed circuit board. This is particularly suitable for high-density, thin PCB products. By ensuring the film fully melts and bonds tightly to each layer through hot-pressing parameters, the defects of poor interlayer adhesion are solved. Simultaneously, controlling the heating and cooling rates reduces thermal stress in the laminated assembly, preventing PCB warping or cracking and ensuring structural reliability of the product in high-speed scenarios.

[0028] The hot-pressing process employs a three-stage heating phase: 120℃ / 30min (initial softening of the film), followed by 150℃ / 30min (gradual filling of gaps), and finally 180℃ / 60min (complete curing). This prevents localized overheating and decomposition of the film due to sudden heating. The hot-pressing equipment uses zoned pressure control to ensure uniform pressure around passive components and prevent damage from pressure. During the cooling phase, dry nitrogen gas is introduced at a flow rate of 8L / min to prevent oxidation of the copper layer at high temperatures and to ensure the conductivity of the plating.

[0029] In S50, the separation methods are mechanical peeling or chemical etching peeling. Mechanical peeling uses a specialized peeling tool, with the peeling angle controlled between 30° and 60° and the peeling speed between 5 and 10 mm / s. Chemical etching peeling uses a 5-10% sodium hydroxide solution, soaked at 50-60°C for 10-20 minutes before peeling. Mechanical peeling is suitable for scenarios where the adhesion between the temporary carrier and the initial composite board is moderate. By controlling the peeling angle and speed, scratches to the outer layer pattern can be avoided. Chemical etching peeling is suitable for situations with strong adhesion. The sodium hydroxide solution can selectively etch the temporary carrier (such as aluminum foil) without damaging the copper layer of the outer layer pattern, ensuring that the surface smoothness and electrical properties of the intermediate are not affected after separation. The two methods can be flexibly selected according to the material characteristics of the temporary carrier. Mechanical peeling is suitable for scenarios with moderate adhesion, while chemical peeling is for carriers with strong adhesion, selectively etching the carrier without damaging the copper layer, ensuring the surface smoothness and electrical properties of the intermediate.

[0030] The blade of the mechanical peeling tool is coated with 0.1mm thick polytetrafluoroethylene, with a friction coefficient ≤0.05, which reduces frictional scratches with the temporary carrier. For the aluminum foil carrier, after chemical etching and peeling, a process of "deionized water ultrasonic cleaning (200W power, 3min), followed by neutralization with 5% dilute sulfuric acid for 10s, and finally a second ultrasonic cleaning" is used to thoroughly remove residual sodium hydroxide and prevent alkaline corrosion of the copper layer. After separation, the surface flatness is checked using a laser profilometer to ensure Ra≤0.5μm, meeting the requirements for subsequent pattern fabrication.

[0031] Drilling in S60 can be done using laser drilling or mechanical drilling. Laser drilling produces holes with a diameter of 50-150μm and a positional accuracy of ±5μm, while mechanical drilling produces holes with a diameter of 200-500μm and a positional accuracy of ±10μm. The metallization process for VIA holes includes deburring, desmearing, electroless copper plating, and electrolytic copper plating. The electroless copper plating layer has a thickness of 0.5-1μm, and the electrolytic copper plating layer has a thickness of 15-25μm. After metallization, the on-resistance of the VIA hole is ≤5mΩ. Laser drilling is suitable for processing small-diameter holes, meeting the needs of high-density interconnect (HDI) boards, while mechanical drilling is suitable for larger diameter holes and is less expensive. The multi-step metallization process ensures that a uniform and dense copper layer is formed on the inner wall of the VIA hole, guaranteeing reliable conductive connection between the inner and outer layers. Low on-resistance reduces signal transmission loss and improves the integrity of high-speed signals. Laser drilling meets the requirements of high-density interconnect, while mechanical drilling is suitable for larger diameter holes and reduces costs. The VIA hole metallization process forms a uniform copper layer, and the multi-step metallization process ensures the reliability of conductive connection between the inner and outer layers and improves the integrity of high-speed signals.

[0032] Laser drilling utilizes a UV pulsed laser, controlling hole diameter accuracy through "5-8 pulse superpositions," achieving a hole wall roughness ≤3μm. The deburring step employs a diamond wheel with an 800-mesh grit for light grinding, removing copper shavings from the hole opening to prevent short circuits. Plasma activation is performed before chemical copper plating to increase the hydrophilicity of the hole wall, achieving a contact angle ≤10°, ensuring uniform copper plating coverage. Electrolytic copper plating uses an acidic copper sulfate solution with a current density of 2A / dm³. 2 This ensures that the coating thickness deviation is ≤1μm, reducing fluctuations in resistance consistency.

[0033] The printed circuit board with embedded passive components is one of the following: Anylayer board, traditional blind via board, high-density printed circuit board (HDI), or coreless board; when it is an HDI board, it has 6-12 layers, the outermost layer line width and spacing is 20 / 20μm-30 / 30μm, the embedded passive components are located in the inner layer 1-3 layers away from the surface, and the distance between them and the power port of the BGA packaged chip on the HDI board is ≤0.5mm. This method is applicable to various types of printed circuit boards, especially HDI boards. By embedding passive components in the inner layer close to the chip's power port, the power loop path can be significantly shortened, reducing the equivalent series inductance (ESL) to below 1nH. Compared with traditional surface mount methods, it can respond more quickly to the chip's ns / ps level switching current requirements, effectively suppress power ripple noise, and improve the working stability of highly integrated processors. Specifically, in HDI boards, passive components are located in the inner layer 1-3 layers from the surface, with a distance of ≤0.5mm from the chip's power port. The shortened power loop path reduces ESL to below 1nH, effectively suppressing power ripple and improving the working stability of highly integrated processors.

[0034] In Anylayer boards, passive components are embedded using an "any-layer interconnect" design, achieving direct connections to each layer via laser-drilled blind vias, reducing intermediate paths. Traditional blind via boards embed passive components in the bottom area of ​​the blind vias, utilizing the short-path characteristics of blind vias to reduce parasitic parameters. In HDI boards, the areas where passive components are embedded are equipped with heat dissipation microchannels, connected to the outer heat sink via inner copper foil, controlling the device operating temperature to ≤70℃ and preventing performance degradation caused by high temperatures.

[0035] In S20, the passive device body is positioned corresponding to the signal output port or power output port of the active device package subsequently assembled on the printed circuit board, with a straight-line distance between them ≤1mm. The active device package is a single-chip package or a multi-chip integrated package, with a pin pitch of 0.4-1mm. Placing the passive device body near the signal or power port of the active device package can minimize parasitic parameters on the signal transmission path (such as parasitic capacitance ≤0.1pF, parasitic inductance ≤0.5nH), avoid signal reflection and attenuation caused by impedance abrupt changes, improve the signal integrity (SI) of the high-speed data communication system by more than 20%, and reduce the bit error rate to 10%. -12 The following design is particularly suitable for scenarios with stringent signal transmission quality requirements, such as 5G communication and AI training chips. The close-range layout ensures parasitic capacitance ≤0.1pF and inductance ≤0.5nH, avoiding impedance abrupt changes and improving signal integrity of high-speed data communication systems by over 20%, while reducing the bit error rate to 10%. -12 The following chips meet the requirements for 5G communication and artificial intelligence training.

[0036] The position of passive components is calibrated against the pin coordinates of active component packages using an AOI vision positioning system to ensure a distance deviation of ≤0.1mm. For multi-chip integrated packages with a pin pitch of 0.4mm, passive components are housed in ultra-small 01005 packages, and a "vacuum nozzle + elastic pressing" mounting process is used to avoid pin interference caused by mounting misalignment. Passive components at the signal output port and transmission lines employ an "impedance matching design," with the resistance value equal to the characteristic impedance of the transmission line, further reducing signal reflection.

[0037] It also includes S70: performing reliability testing on the completed printed circuit board with embedded passive components, including temperature cycling test (-55℃ to 125℃, 1000 cycles), damp heat test (85℃ / 85% RH, 1000 hours), and vibration test (10-2000Hz, 10g acceleration, 8 hours in each direction); after the test, the bonding strength between the embedded passive component and the printed circuit board is ≥5N, and the on-resistance change rate of the VIA via is ≤10%. Through rigorous reliability testing, this printed circuit board can be ensured to operate stably even in extreme environments, meeting the long lifespan and high reliability requirements of automotive electronics, industrial control, and other fields. Its embedded structure has a vibration resistance performance that is more than 30% higher than that of traditional surface-mount passive components, significantly reducing the risk of system failure due to component detachment. Through temperature cycling, damp heat, and vibration tests, it is ensured that the bonding strength of the embedded components is ≥5N and the resistance change rate of the VIA holes is ≤10%. The vibration resistance performance of the structure after testing is improved by more than 30%, meeting the long lifespan requirements of automotive electronics, industrial control, and other fields, and reducing the risk of system failure.

[0038] Temperature cycling tests consist of a cycle of "-55℃ / 30min to room temperature / 5min to 125℃ / 30min to room temperature / 5min". After each cycle, the temperature distribution of the device is detected using an infrared thermal imager to ensure no localized overheating. Vibration testing is followed by X-ray inspection to check the interface between the device and the PCB, ensuring the delamination area is ≤3%. Damp heat testing is performed to measure insulation resistance, avoiding the risk of leakage due to moisture. Long-term reliability assessment also includes 1000 hours of power-on aging, monitoring VIA via resistance changes to ≤5%, verifying product lifespan.

[0039] First, a composite structure containing a peelable temporary carrier and a high-precision outer pattern is fabricated. The temporary carrier provides stable support and facilitates subsequent separation. The outer pattern is etched using photolithography to ensure an accuracy of ±0.02mm, and its PAD area is micro-etched to achieve a roughness of 0.8-1.2μm, laying the foundation for reliable bonding of passive components. Subsequently, epoxy resin-based conductive adhesive is used to bond high-dielectric-constant capacitors, high-precision resistors, and other passive components to the outer pattern PAD. The conductive adhesive serves both mechanical fixing and electrical connection functions, avoiding the defects of traditional welding. AOI (Automated Optical Inspection) is then used to further bond the components. Positioning ensures that the distance between passive components and subsequent active component ports is ≤1mm, minimizing parasitic parameters. Next, the composite structure containing passive components, modified epoxy resin film, inner multilayer boards, and copper foil are sequentially stacked. The film fully fills the gaps during hot pressing, and the inner structure works with the passive components to form an efficient decoupling structure. A three-stage hot pressing process bonds and cures each layer, with slow heating and cooling to reduce thermal stress and prevent warping or bubbles. Temporary carriers are separated by mechanical peeling or chemical etching to ensure a smooth intermediate surface. Finally, VIA holes are created using laser / mechanical drilling, followed by deburring, chemical copper plating, and electrolytic copper plating for metallization. The outer layer pattern is then fabricated to complete the PCB. Simultaneously, reliability is verified through temperature cycling, damp heat, and vibration testing. The overall process significantly reduces equivalent series inductance and improves signal and power integrity by shortening the distance between passive components and chip ports and optimizing material and process parameters, meeting the stringent requirements of high-performance AI units and high-speed data communication scenarios.

[0040] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0041] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a printed circuit board with embedded passive components, characterized in that, Includes the following steps: S10. Prepare an assembly structure, which includes a temporary carrier and an outer layer pattern of a printed circuit board formed on the temporary carrier. S20. In a specific area of ​​the combined structure, the passive device body is attached to the outer pattern to form a composite structure containing passive devices. S30. The composite structure containing passive components, the film, the printed circuit board with the inner layer structure, and the copper foil are stacked in a preset order to form a stacked assembly, wherein the composite structure containing passive components is located between the film and the printed circuit board with the inner layer structure, and the copper foil is located on the side away from the composite structure. S40. Perform a hot pressing process on the stacked components to bond and solidify the outer layer pattern, film, passive component body, printed circuit board with inner layer structure and copper foil into one piece to form a preliminary composite board. S50. Separate the preliminary composite plate from the temporary carrier to obtain an intermediate with inner and outer layer structures; S60. Drill holes in the intermediate body to form VIA holes, metallize the VIA holes, and create an outer layer pattern on the side of the intermediate body away from the original temporary carrier to obtain a printed circuit board with embedded passive devices.

2. The method for manufacturing a printed circuit board with embedded passive components according to claim 1, characterized in that, The temporary carrier in S10 is a peelable carrier, and its material is selected from one of polyimide film, polyester film or aluminum foil, with a thickness of 25-100μm; the outer layer pattern of the printed circuit board is formed by photolithography etching process, and its pattern accuracy is controlled within ±0.02mm. The surface roughness of the PAD area in the outer layer pattern used to bond with the passive device body is 0.8-1.2μm.

3. The method for manufacturing a printed circuit board with embedded passive components according to claim 1, characterized in that, The attachment method in S20 is to use an organic polymer conductive adhesive for bonding. The organic polymer conductive adhesive is an epoxy resin-based conductive adhesive with a solid content of 60-80%. The conductive particles are silver powder or copper powder with a particle size of 1-5μm and a coating thickness of 10-30μm. The passive device body includes at least one of a capacitor, a resistor, and an inductor. The capacitor is a high dielectric constant ceramic capacitor with a dielectric constant ≥1000. The resistor is a thin film resistor with an accuracy ≤±1%. The inductor is a wire-wound inductor or a multilayer inductor with a Q value ≥50.

4. The method for manufacturing a printed circuit board with embedded passive components according to claim 1, characterized in that, The film in S30 is a modified epoxy resin film with a thickness of 50-150μm, a melt viscosity of 500-1500cP, a curing temperature of 160-180℃, and a curing time of 60-90min. The printed circuit board with the inner layer structure is a multilayer board with a line width and spacing of 30 / 30μm-50 / 50μm for the inner layer circuits, an interlayer dielectric thickness of 80-120μm, and a power layer and a ground layer in the inner layer, with a spacing of 50-80μm between the power layer and the ground layer.

5. A method for manufacturing a printed circuit board with embedded passive components according to claim 1, characterized in that, The parameters for the hot pressing process in S40 are: hot pressing temperature 170-190℃, pressure 20-30 kgf / cm². 2 The heating rate is 5-10℃ / min, the holding time is 90-120min, and the cooling rate is ≤5℃ / min.

6. A method for manufacturing a printed circuit board with embedded passive components according to claim 1, characterized in that, The separation method in S50 is either mechanical peeling or chemical corrosion peeling. Mechanical peeling uses a special peeling tool with a peeling angle controlled between 30° and 60° and a peeling speed of 5-10 mm / s. Chemical corrosion peeling uses a 5-10% sodium hydroxide solution, which is soaked at 50-60°C for 10-20 minutes before peeling.

7. A method for manufacturing a printed circuit board with embedded passive components according to claim 1, characterized in that, The drilling process in S60 uses laser drilling or mechanical drilling. The diameter of the laser-drilled hole is 50-150μm with a hole position accuracy of ±5μm, while the diameter of the mechanically drilled hole is 200-500μm with a hole position accuracy of ±10μm. The metallization process of the VIA hole includes deburring, desmearing, chemical copper plating, and electrolytic copper plating. The thickness of the chemical copper plating layer is 0.5-1μm, and the thickness of the electrolytic copper plating layer is 15-25μm. After metallization, the conduction resistance of the VIA hole is ≤5mΩ.

8. A method for manufacturing a printed circuit board with embedded passive components according to claim 6, characterized in that, The printed circuit board with embedded passive components is one of Anylayer board, traditional blind via board, high-density printed circuit board, or coreless board; when it is an HDI board, it has 6-12 layers, the outermost layer line width and spacing is 20 / 20μm-30 / 30μm, the embedded passive components are located in the inner layer 1-3 layers away from the surface, and the distance between them and the power port of the BGA packaged chip on the HDI board is ≤0.5mm.

9. A method for manufacturing a printed circuit board with embedded passive components according to claim 3, characterized in that, In step S20, the position of the passive device body corresponds to the signal output port or power output port of the active device package subsequently assembled on the printed circuit board, and the straight-line distance between the two is ≤1mm; the active device package is a single-chip package or a multi-chip integrated package, and its pin pitch is 0.4-1mm.

10. A method for manufacturing a printed circuit board with embedded passive devices according to any one of claims 1 to 9, characterized in that, The method also includes S70: performing reliability testing on the completed printed circuit board with embedded passive devices, including temperature cycling test, damp heat test and vibration test; after the test, the bonding strength between the embedded passive device body and the printed circuit board is ≥5N, and the on-resistance change rate of the VIA hole is ≤10%.

Images