Packaging chip failure detection method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a packaged chip failure detection method and device, electronic equipment and a storage medium, relates to the technical field of integrated circuit packaging, and is convenient for analyzing the influence of a packaging process on the electrical performance of a circuit. The method comprises the steps of designing a test path based on testability, and detecting a packaging interface of an independent chip before packaging so as to determine whether a transmitting end circuit, a receiving end circuit and a non-working state circuit of the chip before packaging are invalid or not; designing a test path based on testability, and detecting a packaging interface of the packaged interconnected chips so as to determine whether the transmitting end circuit, the receiving end circuit and the non-working state circuit of the packaged chips fail or not; and comparing the chip detection result before packaging with the chip detection result after packaging, positioning a failure position and evaluating the influence of packaging on the circuit. The method and the device are suitable for the scene of failure detection of the packaged chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit packaging, and in particular to a packaged chip failure detection method and device, an electronic device and a storage medium. BACKGROUND

[0002] In three-dimensional (3D) packaging technology, a through-silicon via (TSV) structure is a key technology for realizing vertical interconnection between chips, and the yield thereof directly affects the performance and reliability of the chips. However, under the current 3D packaging process, the yield of the TSV is only about 99%, and a single central processing unit (CPU) or graphics processing unit (GPU) chip usually contains a large number of TSVs, which means that some TSVs may be open-circuited, thereby affecting the function of the chip. Therefore, how to efficiently detect the yield of the packaged circuit has become an important issue for chip design and packaging process optimization.

[0003] The prior art usually drives the TSV by a unidirectional transmitting end (Tx) and transmits the signal to a receiving end (Rx), wherein the Tx and the Rx can be located on a top die (Top Die) or a bottom die (Base Die), the interface located on the top die is referred to as a BPVIO, and the interface located on the bottom die is referred to as a TSVIO, the two interfaces realize high-speed data transmission through the TSV, and if the TSV is open-circuited or damaged, the signal cannot reach the Rx end, and the system may report an error. However, the prior art cannot distinguish the specific position of the circuit failure, it is difficult to evaluate the influence of 3D packaging on the circuit, and it is impossible to accurately locate the fault source to optimize the design. SUMMARY

[0004] Therefore, the embodiments of the present application provide a packaged chip failure detection method and device, an electronic device and a storage medium, which facilitate analysis of the influence of the packaging process on the electrical performance of the circuit.

[0005] In a first aspect, the embodiments of the present application provide a packaged chip failure detection method, which comprises: detecting the packaging interface of an independent chip before packaging based on a test access of a testability design, to determine whether the transmitting end circuit, the receiving end circuit and the non-working state circuit of the chip before packaging are failed; detecting the packaging interface of the interconnected chip after packaging based on the test access of the testability design, to determine whether the transmitting end circuit, the receiving end circuit and the non-working state circuit of the chip after packaging are failed; and comparing the detection results of the chip before packaging and the chip after packaging, to locate the failure position and evaluate the influence of the packaging on the circuit.

[0006] According to a specific implementation manner of the embodiment of the present application, the detection on the packaging interface of the independent chip before packaging to determine whether the sending end circuit, the receiving end circuit and the non-working state circuit of the chip before packaging are invalid comprises: configuring a preset test mode for the packaging interface of the independent chip before packaging, the preset test mode comprising a sending end loopback mode, a receiving end loopback mode and a non-working mode; in the sending end loopback mode, inputting a first random test signal from a test signal input end, detecting the integrity of the sending end circuit through a random test signal output end, and determining whether the sending end circuit is invalid; in the receiving end loopback mode, inputting a second random test signal from the test signal input end, detecting the integrity of the receiving end circuit through a main path output end, and determining whether the receiving end circuit is invalid; in the non-working mode, determining whether the non-working state circuit is invalid according to the voltage and current of a test path output end.

[0007] According to a specific implementation manner of the embodiment of the present application, the detection on the packaging interface of the interconnected chip after packaging to determine whether the sending end circuit, the receiving end circuit and the non-working state circuit of the interconnected chip after packaging are invalid comprises: configuring a preset test mode for the packaging interface of the interconnected chip after packaging, the preset test mode comprising a sending end loopback mode, a receiving end loopback mode and a non-working mode; in the sending end loopback mode, inputting a third random test signal from a test signal input end, detecting the integrity of the sending end circuit through a random test signal output end, and determining whether the sending end circuit is invalid; in the receiving end loopback mode, inputting a fourth random test signal from the test signal input end, detecting the integrity of the receiving end circuit through a main path output end, and determining whether the receiving end circuit is invalid; in the non-working mode, determining whether the non-working state circuit is invalid according to the voltage and current of a test path output end.

[0008] According to a specific implementation manner of the embodiment of the present application, the detection on the integrity of the sending end circuit or the receiving end circuit comprises: comparing the output signal with the random test signal sequence bit by bit to judge the logic consistency; and detecting the output signal delay, jitter or eye diagram quality to evaluate the high frequency characteristics; wherein the random test signal is generated by a built-in test signal generator.

[0009] According to a specific implementation manner of the embodiment of the present application, the preset test mode further comprises a function mode; in the function mode, a detection circuit is connected to the main path output end of the receiving end circuit to monitor whether the output signal is consistent with the sending end input signal, or the overall working state of the interconnected chip after packaging is verified through a system-level function test.

[0010] According to a specific implementation manner of the embodiment of the present application, the detection on the packaging interface of the packaged interconnected chip based on the test access of the design for test includes: configuring the packaging interface of the packaged interconnected chip to enter a reverse test mode; inputting a first test signal from a test signal input end of the receiving end circuit, transmitting the first test signal through the through-silicon via structure, and outputting the first test signal from a test signal output end of the sending end circuit; and determining whether the through-silicon via structure is failed by comparing an output signal of the test signal output end of the sending end circuit with an input signal of the test signal input end of the receiving end circuit.

[0011] According to a specific implementation manner of the embodiment of the present application, the determination of whether the through-silicon via structure is failed by comparing the output signal of the test signal output end of the sending end circuit with the input signal of the test signal input end of the receiving end circuit includes: if the output signal is consistent with the input signal, determining that the through-silicon via structure is normally connected; and if the output signal is inconsistent with the input signal, determining that the through-silicon via structure is failed, and there is an open circuit or an abnormal impedance.

[0012] In a second aspect, the embodiment of the present application provides a packaged chip failure detection device, including: a pre-packaging chip detection unit configured to detect a packaging interface of a pre-packaging independent chip based on a test access of a design for test, to determine whether a sending end circuit, a receiving end circuit and a non-working state circuit of the pre-packaging chip are failed; a post-packaging chip detection unit configured to detect a packaging interface of a post-packaging interconnected chip based on the test access of the design for test, to determine whether the sending end circuit, the receiving end circuit and the non-working state circuit of the post-packaging chip are failed; and a comparison unit configured to compare a detection result of the pre-packaging chip and a detection result of the post-packaging chip, to locate a failure position and to evaluate an influence of packaging on the circuit.

[0013] According to a specific implementation manner of the embodiment of the present application, the post-packaging chip detection unit includes: a first configuration module configured to configure the packaging interface of the post-packaging interconnected chip to enter a reverse test mode; an input-output module configured to input a first test signal from a test signal input end of the receiving end circuit, transmit the first test signal through the through-silicon via structure, and output the first test signal from a test signal output end of the sending end circuit; and a first judgment module configured to determine whether the through-silicon via structure is failed by comparing an output signal of the test signal output end of the sending end circuit with an input signal of the test signal input end of the receiving end circuit.

[0014] According to a specific implementation manner of the embodiment of the present application, the first judging module comprises: a first judging submodule, configured to judge that the through silicon via structure is in normal communication if the output signal is consistent with the input signal; and a second judging submodule, configured to judge that the through silicon via structure is in failure, i.e., there is an open circuit or abnormal impedance, if the output signal is inconsistent with the input signal.

[0015] According to a specific implementation manner of the embodiment of the present application, the pre-packaging chip detection unit comprises: a second configuration module, configured to configure a preset test mode for the packaging interface of the pre-packaging independent chip, the preset test mode comprising a sending end loopback mode, a receiving end loopback mode and a non-working mode; a first determination module, configured to input a first random test signal from a test signal input end in the sending end loopback mode, detect the integrity of the sending end circuit through the random test signal output end, and determine whether the sending end circuit is in failure; a second determination module, configured to input a second random test signal from the test signal input end in the receiving end loopback mode, detect the integrity of the receiving end circuit through the main path output end, and determine whether the receiving end circuit is in failure; and a third determination module, configured to determine whether the non-working state circuit is in failure according to the voltage and current of the test path output end in the non-working mode.

[0016] According to a specific implementation manner of the embodiment of the present application, the post-packaging chip detection unit comprises: a third configuration module, configured to configure a preset test mode for the packaging interface of the post-packaging interconnected chip, the preset test mode comprising a sending end loopback mode, a receiving end loopback mode and a non-working mode; a fourth determination module, configured to input a third random test signal from a test signal input end in the sending end loopback mode, detect the integrity of the sending end circuit through the random test signal output end, and determine whether the sending end circuit is in failure; a fifth determination module, configured to input a fourth random test signal from the test signal input end in the receiving end loopback mode, detect the integrity of the receiving end circuit through the main path output end, and determine whether the receiving end circuit is in failure; and a sixth determination module, configured to determine whether the non-working state circuit is in failure according to the voltage and current of the test path output end in the non-working mode.

[0017] According to a specific implementation manner of the embodiment of the present application, the detection of the integrity of the sending end circuit or the receiving end circuit comprises: comparing the output signal with the random test signal sequence bit by bit to judge the logic consistency; and detecting the output signal delay, jitter or eye diagram quality to evaluate the high frequency characteristics; wherein the random test signal is generated by a built-in test signal generator.

[0018] According to a specific implementation manner of the embodiment of the present application, the preset test mode further comprises a function mode; in the function mode, a detection circuit is connected to an output end of a main path of the receiving end circuit, and it is monitored whether the output signal is consistent with the input signal of the sending end, or the overall working state of the interconnected chip after packaging is verified through system-level function test.

[0019] In a third aspect, the embodiment of the present application provides an electronic device, which comprises a shell, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is arranged inside a space enclosed by the shell, the processor and the memory are arranged on the circuit board; the power supply circuit is used for supplying power to each circuit or device of the electronic device; the memory is used for storing executable program codes; the processor runs programs corresponding to the executable program codes by reading the executable program codes stored in the memory, and is used for executing the packaging chip failure detection method provided by any of the embodiments of the present application.

[0020] In a fourth aspect, the embodiment of the present application provides a computer readable storage medium, which stores one or more computer programs, and when the one or more computer programs are executed by one or more processors, the packaging chip failure detection method in any of the first aspect is implemented.

[0021] The packaging chip failure detection method, device, electronic device and storage medium provided by the embodiment of the present application can determine whether the sending end circuit, the receiving end circuit and the non-working state circuit are failed, directly locate the failure position, and evaluate the influence of packaging on the circuit by comparing the detection results of the chips before packaging and the chips after packaging, so as to optimize the packaging process and the circuit design. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiment or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0023] Figure 1 A flow chart of the packaging chip failure detection method provided by the embodiment of the present application is provided. Figure 2 A packaging chip test circuit schematic diagram provided by the embodiment of the present application is provided. Figure 3This is a schematic diagram of test signal transmission in reverse test mode of the packaged chip provided in an embodiment of this application; Figure 4 A schematic diagram of test signal transmission in loopback mode at the chip transmitter after packaging, provided in an embodiment of this application; Figure 5 This is a schematic diagram of signal transmission in loopback mode at the packaged chip receiver provided in an embodiment of this application; Figure 6 This is a schematic diagram of signal transmission in the functional mode of the packaged chip provided in an embodiment of this application; Figure 7 This is a schematic block diagram of the architecture of the packaged chip failure detection device provided in the embodiments of this application; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0024] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0025] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0026] In a first aspect, embodiments of this application provide a method for detecting packaged chip failure, which can locate the specific location of packaged chip failure, assess the impact of packaging on circuits, and thereby optimize packaging processes and circuit design.

[0027] like Figure 1 As shown, an embodiment of this application provides a method for detecting packaged chip failure, including: S11, based on testability design test path, tests the packaging interface of the independent chip before packaging to determine whether the transmitting circuit, receiving circuit and non-working state circuit of the chip before packaging are faulty. Before implementing 3D packaging technology, it is necessary to perform integrity testing on the packaging interface circuit of the independent chip to achieve the following testing objectives: verify whether the driving capability and signal integrity of the transmitting circuit Tx meet the requirements; confirm whether the signal reception and processing functions of the receiving circuit Rx are normal; and check whether there are leakage or abnormal conduction problems in the non-working circuit.

[0028] Figure 2 This is a schematic diagram of the packaged chip test circuit provided in the embodiments of this application, such as... Figure 2To achieve the above detection goal, the embodiment of the application adds a design for testability (DFT) test path in the independent chip packaging interface, wherein the independent chip includes a Top Die and a Base Die. In terms of the sending end test path, three key modules are newly added: a test signal selector (IN SEL) for switching between a main input (IN0) and a test input (IN1), a test output end (DFT OUT) for looping a Tx output signal to a detection circuit, and a test enable signal (DFT EN TX) for independently controlling the switching state of the test path. In the test mode, the signal is input through IN1, processed by the driving circuit, and finally output from DFT OUT, so as to realize closed-loop detection by bypassing the TSV which has not been connected. Similarly, in the receiving end Rx test path, a test input end (DFT IN) is newly added for directly injecting a test signal into the Rx internal logic, and a test enable signal (DFT EN RX) is newly added for controlling the connection of the test signal and the main path. In the test mode, the signal is input from DFT IN, processed by the Rx processing circuit, and finally output from the OUT port, so as to realize independent detection of the receiving end circuit.

[0029] S12, detecting the packaging interface of the packaged chip which has been interconnected based on the design for testability test path, to determine whether the sending end circuit, the receiving end circuit and the non-working state circuit of the packaged chip are failed; After the 3D packaging process is completed, the packaging interface of the chip which has been interconnected by TSV needs to be comprehensively detected, mainly including four key detection goals: firstly, verifying whether the sending end circuit Tx still maintains normal driving capability and signal integrity after packaging; secondly, confirming whether the signal receiving and processing function of the receiving end circuit Rx is abnormal due to the influence of the packaging process; and finally, checking whether the non-working state circuit has leakage or abnormal conduction phenomenon introduced by the packaging process.

[0030] To achieve the packaging chip detection requirement, refer to Figure 2 ​, the test signal can be input through the dedicated test port IN1 or DFT IN of the sending end Tx or the receiving end Rx, or can be looped back to the detection circuit from the corresponding test port DFT OUT or OUT, so that the cross-chip signal tracking is realized. Through the flexible configuration of the enable signal, the test signal can be selectively allowed to flow through the TSV or the complete signal chain, and from the Tx to the TSV and then to the Rx, and in combination with the comparison of the test results before and after packaging, the failure problems caused by the packaging process, such as damage to the interface circuit, can be accurately located. At the same time, by closing all the enable signals and detecting the static current change, whether the packaging causes the leakage current to increase can be effectively judged.

[0031] S13, comparing the chip detection results before packaging and the chip detection results after packaging, locating the failure position and evaluating the influence of packaging on the circuit.

[0032] In the whole-process quality control of the 3D packaging process, by systematically comparing the chip detection results before packaging and the chip detection results after packaging, the accurate positioning of the failure position and the comprehensive evaluation of the influence of the packaging process on the circuit can be realized.

[0033] First, a benchmark database is established to record the key parameters of the Tx driving circuit, the Rx receiving circuit and the static power consumption before packaging; the same test conditions are used for repeated detection after packaging, and the changes of the parameters such as Tx driving capability, Rx receiving sensitivity and static leakage current are analyzed through an automatic comparison algorithm. In the aspect of failure positioning, for example, when the Tx parameter is abnormal and the Rx is normal, it can be determined that the Tx circuit is damaged, when the Rx sensitivity decreases and the Tx is normal, it points to the Rx circuit or the interconnection micro-bump problem, and if both of them are deteriorated, the power supply network needs to be checked. Finally, intelligent diagnosis is realized through a machine learning algorithm, an automatic report containing failure analysis and process suggestion is formed, and the results are fed back to the process parameter adjustment, so as to build a closed-loop optimization system of design, manufacturing and testing, thereby significantly improving the yield and reliability of 3D packaging.

[0034] By quantifying the data difference before and after packaging, the specific influence of the packaging process on the circuit can be evaluated, different fault types such as Tx or Rx circuit failure and packaging-induced parasitic effect can be accurately distinguished, and the design of the test path is completely compatible with the normal working mode of the chip, which can perfectly support the automation demand of production test.

[0035] The packaging chip failure detection method provided by the embodiment of the application can determine whether the sending end circuit, the receiving end circuit and the non-working state circuit are failed, directly locate the failure position, and evaluate the influence of packaging on the circuit by comparing the chip detection results before packaging and the chip detection results after packaging, so as to optimize the packaging process and the circuit design.

[0036] In some embodiments, the test path based on the design for testability tests the package interface of the post-packaged interconnected chip, including: configuring the package interface of the post-packaged interconnected chip into a reverse test mode; inputting a first test signal from a test signal input end of the receiving end circuit, transmitting through the through-silicon via structure, and outputting from a test signal output end of the sending end circuit; and judging whether the through-silicon via structure is failed by comparing the output signal of the test signal output end of the sending end circuit with the input signal of the test signal input end of the receiving end circuit.

[0037] The present application can realize accurate detection of the through-silicon via structure in the 3D packaged chip through the test path based on the design for testability.

[0038] Referring to Table 1, the package interface of the post-packaged interconnected chip is configured to work in the reverse test mode, and in some examples, TX EN=0, DFT EN TX=1, RX EN=0, and DFT EN RX=1 can be configured, so that the test signal is directly transmitted to the DFT OUT output through the TSV after being input through the DFT IN, completely bypassing the main path circuit of the Tx and the Rx, and realizing independent detection of the TSV connectivity. Specifically, Figure 3 The schematic diagram for test signal transmission of the post-packaged chip in the reverse test mode is as follows, Figure 3 The test signal is first injected from the dedicated test signal input end DFT IN of the receiving end Rx, then transmitted through the TSV structure, and finally output from the test signal output end DFT OUT of the sending end Tx. The main functional circuit of the Tx and the Rx is bypassed, and independent detection of the TSV interconnection structure is realized.

[0039] In the test process, the waveform characteristics of the input signal and the output signal are captured in real time by a high-precision signal acquisition system, and advanced digital signal processing algorithms are used for time domain and frequency domain comparison and analysis to judge whether the TSV structure is failed.

[0040] In some examples, the detection resolution of the through-silicon via structure detection reaches the micron level, which can accurately identify typical defects such as open circuit, short circuit, and impedance mismatch of the TSV, and effectively distinguish between TSV failure and chip circuit failure, providing reliable test data support for optimization of the 3D packaging process.

[0041]

[0042] In some embodiments, the determining whether the TSV structure is failed by comparing the output signal of the test signal output end of the sending end circuit with the input signal of the test signal input end of the receiving end circuit comprises: if the output signal is consistent with the input signal, determining that the TSV structure is in normal communication; and if the output signal is inconsistent with the input signal, determining that the TSV structure is failed, and there is an open circuit or abnormal impedance.

[0043] The TSV communication detection method in the application adopts an innovative multi-dimensional signal analysis technology, and realizes high-precision failure determination through a reverse test mode.

[0044] In the test process, the system first injects a standard test signal sequence into the receiving end DFT IN port, and simultaneously monitors the response signal of the sending end DFT OUT port. In some examples, a dedicated signal analysis module comprehensively evaluates from three dimensions of time domain, frequency domain and digital integrity. In the time domain, the signal rising or falling time and propagation delay are detected; in the frequency domain, the frequency spectrum characteristics are analyzed through fast Fourier transform (FFT), and whether the high-frequency component attenuation exceeds a preset critical value is focused on; and in the digital level, strict bit-by-bit comparison and bit error rate calculation are performed.

[0045] In some embodiments, the detecting the packaging interface of the independent chip before packaging to determine whether the sending end circuit, the receiving end circuit and the non-working state circuit of the chip before packaging are failed comprises: configuring a preset test mode for the packaging interface of the independent chip before packaging, the preset test mode comprising a sending end loopback mode, a receiving end loopback mode and a non-working mode; in the sending end loopback mode, inputting a first random test signal from the test signal input end, detecting the integrity of the sending end circuit through the random test signal output end, and determining whether the sending end circuit is failed; in the receiving end loopback mode, inputting a second random test signal from the test signal input end, detecting the integrity of the receiving end circuit through the main path output end, and determining whether the receiving end circuit is failed; and in the non-working mode, determining whether the non-working state circuit is failed according to the voltage and current of the test path output end.

[0046] The packaging interface of the independent chip before packaging can work in three preset test modes to realize comprehensive detection by configuration. In some examples, the three preset test modes are respectively a sending end loopback mode, a receiving end loopback mode and a non-working mode.

[0047] Table 2 is a packaging port configuration table of the independent chip before packaging. Referring to Table 2, the sending end main path TX EN=1 and the test path DFT EN TX=1 are configured to be enabled, and the receiving end enable signal RX EN=0 is closed. DFT EN RX=0, makes the pre-packaged independent chip work in the sending end loopback mode, inputs the pseudo-random binary sequence (PRBS) as the first test signal from the test signal input end IN1, and judges whether the sending end circuit is invalid by monitoring the signal integrity of the test signal output end DFT OUT.

[0048] Referring to Table 2, the sending end enable signal is turned off, that is, TX EN=0, DFT EN TX=0, the receiving end main channel is turned on, RX EN=1 and the test channel DFT EN RX=1 are configured, the pre-packaged independent chip works in the receiving end loopback mode, the second random test signal is injected from the test signal input end DFT IN, and the receiving end circuit function is evaluated by analyzing the signal response of the main channel output end OUT.

[0049] Referring to Table 2, all enable signals are turned off by configuring TX EN=0, DFT EN TX=0, RX EN=0, DFT EN RX=0, the pre-packaged independent chip works in the non-working mode, and whether the non-working state circuit exists abnormal conduction or leakage failure is judged by precisely measuring the leakage current and residual voltage of the test channel output end.

[0050] The three modes are quickly switched through dedicated enable signals, the test time of each mode is controlled within the preset time, and the integrity of each functional module of the pre-packaged chip can be comprehensively evaluated.

[0051]

[0052] In some embodiments, the package interface of the interconnected post-packaged chip is detected to determine whether the sending end circuit, the receiving end circuit and the non-working state circuit of the post-packaged chip are invalid, comprising: configuring a preset test mode for the package interface of the interconnected post-packaged chip, the preset test mode comprising a sending end loopback mode, a receiving end loopback mode and a non-working mode; in the sending end loopback mode, a third random test signal is input from the test signal input end, the integrity of the sending end circuit is detected through the random test signal output end, and whether the sending end circuit is invalid is determined; in the receiving end loopback mode, a fourth random test signal is input from the test signal input end, the integrity of the receiving end circuit is detected through the main channel output end, and whether the receiving end circuit is invalid is determined; in the non-working mode, whether the non-working state circuit is invalid is determined according to the voltage and current of the test channel output end.

[0053] The package interface of the interconnected chip after packaging can work in a preset test mode for detection by configuration. In some examples, the preset test mode includes a sending end loopback mode, a receiving end loopback mode and a non-working mode.

[0054] Referring to Table 1, in the sending end loopback mode, the sending end main channel is configured to enable TX EN = 1 and the test channel is configured to enable DFT EN TX = 1, while the receiving end function is disabled, i.e. RX EN = 0 is set, DFT EN RX = 0. Figure 4 A schematic diagram of signal transmission of the chip in the sending end loopback mode after packaging is shown in FIG. 2. Figure 4 A third group of PRBS random sequences is injected from a dedicated test input port IN1 as a third random test signal, and a response signal of the test signal output end DFT OUT is collected by high-precision collection, and time domain analysis and bit error rate detection are combined to determine whether the sending end circuit maintains complete functions after packaging.

[0055] Referring to Table 1, in the receiving end loopback mode, the receiving end main channel RX EN = 1 and the test channel DFT EN RX = 1 are enabled, while the sending end test channel of the opposite chip is enabled DFT EN TX = 1, but the main channel is disabled TX EN = 0. Figure 5 A schematic diagram of signal transmission of the chip in the receiving end loopback mode after packaging is shown in FIG. 3. Figure 5 A fourth group of characteristic test signals is input from the test input end DFT IN as a fourth random test signal, and the signal integrity of the main channel output end OUT is analyzed to evaluate the performance of the receiving end circuit. Referring to Table 1, in the non-working mode, all the enable signals are globally turned off, i.e. TX EN = 0, DFT EN TX = 0, RX EN = 0, DFT EN RX = 0, and a nano-ampere current probe and a micro-volt meter are used to measure the residual parameters of the test channel output end, and the reliability of the non-working state circuit is verified by requiring that the static current and the floating voltage are less than a preset threshold.

[0056] In some examples, each test mode supports automatic switching, and a single complete test cycle can be completed within a preset time, and a diagnostic report containing failure positioning information is generated.

[0057] In some embodiments, the detection of the integrity of the sending end circuit or the receiving end circuit includes: comparing the output signal with the random test signal sequence bit by bit to judge the logic consistency; and detecting the output signal delay, jitter or eye diagram quality to evaluate the high frequency characteristics; wherein the random test signal is generated by a built-in test signal generator.

[0058] The test strategy adopted in the embodiment of the application is applicable to interface detection of independent chips before packaging and interconnected chips after packaging.

[0059] In some examples, for integrity verification of the transmitting end Tx and the receiving end Rx circuit, the system generates a high-precision PRBS random test sequence through a built-in built-in self-test (BIST) signal generator, and the random test sequence is injected through a local test input port IN1 or DFT IN of the chip before packaging; or the random test sequence is transmitted through a cross-chip path after packaging. In the detection process, for high-speed digital interface testing, such as a pseudo-random binary sequence or a fixed pattern test signal, a strict bit-by-bit comparison is first performed, and the error rate is required to be lower than a preset threshold to ensure the absolute consistency of the digital signal; or the output signal waveform is captured through a high-speed sampling module, and key time domain parameters including transmission delay, timing jitter, and eye diagram quality and other high-frequency characteristic indexes are analyzed.

[0060] In this way, the correct transmission of the digital signal can be ensured, the analog signal integrity can be effectively evaluated, and the detection results before and after packaging have direct comparability through a unified test standard, thereby providing a quantitative basis for process improvement. In some examples, the entire test process is automatically completed by on-chip control logic, and supports fast screening of defective products in mass production testing.

[0061] In some embodiments of the application, the preset test mode further includes a functional mode; in the functional mode, a detection circuit is connected to an output end of a main path of the receiving end circuit to monitor whether the output signal is consistent with the input signal of the transmitting end, or the overall working state of the interconnected chip after packaging is verified through system-level functional testing.

[0062] The packaging interface of the interconnected chip after packaging works in a preset test mode, and in some examples, the preset test mode further includes a functional mode.

[0063] Referring to Table 1, in the functional mode, the system enables the transmitting end main path TX EN=1 and the receiving end main path RX EN=1 at the same time, and disables the test path, that is, sets DFT EN TX=0 and DFT EN RX=0, at this time, the chip is in a normal working state.

[0064] Figure 6 For a signal transmission schematic diagram of the chip after packaging in the functional mode, as shown in Figure 6 The main input IN0 signal of the transmitting end first enters the transmitting end driving circuit for processing, then is transmitted through the TSV interconnection structure to realize cross-chip transmission, and then is analyzed and shaped by the receiving end processing circuit, and finally is output from the main path output end OUT of the receiving end.

[0065] In some cases, a high-speed detection circuit can be connected to the OUT port of the receiver to compare the matching degree between the output signal and the IN0 input signal of the transmitter in three dimensions: timing, amplitude, and logic content, in real time to determine whether the cross-chip transmission function is normal. Alternatively, the chip can be connected to the actual system environment and standard test programs can be run to verify system-level indicators such as data processing correctness and effective throughput to determine whether the cross-chip transmission function is normal.

[0066] The functional mode fully preserves the signal path when the chip is working normally, and can complete the detection within a preset time without affecting the system operation. It also supports seamless switching with other test modes.

[0067] Secondly, embodiments of this application provide a packaged chip failure detection device that can locate the specific location of the packaged chip failure, assess the impact of packaging on the circuit, and thereby optimize the packaging process and circuit design.

[0068] like Figure 7 As shown, embodiments of this application also provide a packaged chip failure detection device, including a pre-packaging chip detection unit 31, a post-packaging chip detection unit 32, and a comparison unit 33.

[0069] Among them, the pre-packaging chip detection unit 31 is used to design test paths based on testability and detect the packaging interface of the independent chip before packaging, so as to determine whether the transmitting end circuit, receiving end circuit and non-working state circuit of the chip before packaging are faulty.

[0070] The packaged chip testing unit 32 is used to design test paths based on testability and test the package interface of the interconnected packaged chips to determine whether the transmitting end circuit, receiving end circuit and non-working state circuit of the packaged chip are faulty.

[0071] The comparison unit 33 is used to compare the chip inspection results before packaging with the chip inspection results after packaging, locate the failure location, and evaluate the impact of packaging on the circuit.

[0072] The packaged chip failure detection device provided in this application embodiment, by designing test paths based on testability, detects the packaging interface of the independent chip before packaging, and detects the packaging interface of the interconnected chip after packaging. It can determine whether the transmitting circuit, receiving circuit and non-working circuit have failed, directly locate the failure location, and by comparing the chip detection results before packaging and the chip detection results after packaging, it can evaluate the impact of packaging on the circuit, thereby optimizing the packaging process and circuit design.

[0073] In some embodiments, the packaged chip testing unit includes: a first configuration module for configuring the packaged interconnected chip interface to enter a reverse test mode; an input / output module for inputting a first test signal from the test signal input terminal of the receiving circuit, transmitting it through a through-silicon via (TSV) structure, and outputting it from the test signal output terminal of the transmitting circuit; and a first judgment module for determining whether the TSV structure is faulty by comparing the output signal of the test signal output terminal of the transmitting circuit with the input signal of the test signal input terminal of the receiving circuit.

[0074] In some embodiments, the first determination module includes: a first determination submodule, configured to determine that the through-silicon via structure is normally connected if the output signal is consistent with the input signal; and a second determination submodule, configured to determine that the through-silicon via structure is faulty and has an open circuit or abnormal impedance if the output signal is inconsistent with the input signal.

[0075] In some embodiments, the pre-packaging chip testing unit includes: a second configuration module, configured to configure a preset test mode for the packaging interface of the pre-packaging independent chip, the preset test mode including a transmitting loopback mode, a receiving loopback mode, and a non-operating mode; a first determination module, configured to input a first random test signal from a test signal input terminal in the transmitting loopback mode, and detect the integrity of the transmitting circuit through the random test signal output terminal to determine whether the transmitting circuit is faulty; a second determination module, configured to input a second random test signal from a test signal input terminal in the receiving loopback mode, and detect the integrity of the receiving circuit through the main path output terminal to determine whether the receiving circuit is faulty; and a third determination module, configured to determine whether the non-operating circuit is faulty based on the voltage and current at the test path output terminal in the non-operating mode.

[0076] In some embodiments, the packaged chip testing unit includes: a third configuration module, configured to configure a preset test mode for the package interface of the packaged interconnected chip, the preset test mode including a transmitting loopback mode, a receiving loopback mode, and a non-operating mode; a fourth determination module, configured to input a third random test signal from a test signal input terminal in the transmitting loopback mode, and detect the integrity of the transmitting circuit through the random test signal output terminal to determine whether the transmitting circuit has failed; a fifth determination module, configured to input a fourth random test signal from a test signal input terminal in the receiving loopback mode, and detect the integrity of the receiving circuit through the main path output terminal to determine whether the receiving circuit has failed; and a sixth determination module, configured to determine whether the non-operating circuit has failed based on the voltage and current at the test path output terminal in the non-operating mode.

[0077] In some embodiments, detecting the integrity of the transmitting or receiving circuit includes: comparing the output signal bit by bit with the random test signal sequence to determine logical consistency; and detecting output signal delay, jitter, or eye diagram quality to evaluate high-frequency characteristics; wherein the random test signal is generated by a built-in test signal generator.

[0078] In some embodiments, the preset test mode further includes a functional mode; in the functional mode, a detection circuit is connected to the main path output terminal of the receiving circuit to monitor whether the output signal is consistent with the input signal of the transmitting end, or, through system-level functional testing, to verify the overall working status of the packaged interconnected chips.

[0079] Thirdly, embodiments of this application also provide an electronic device capable of locating the specific location of a packaged chip failure, assessing the impact of packaging on the circuit, thereby optimizing the packaging process and circuit design.

[0080] like Figure 8 As shown, the electronic device provided in the embodiments of this application may include: a housing 51, a processor 52, a memory 53, a circuit board 54, and a power supply circuit 55, wherein the circuit board 54 is disposed inside the space enclosed by the housing 51, and the processor 52 and the memory 53 are disposed on the circuit board 54; the power supply circuit 55 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 53 is used to store executable program code; the processor 52 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 53, for executing the packaged chip failure detection method provided in any of the foregoing embodiments.

[0081] For details on the specific execution process of the above steps by the processor 52 and the steps further executed by the processor 52 by running executable program code, please refer to the description of the foregoing embodiments, which will not be repeated here.

[0082] Fourthly, embodiments of this application also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the packaged chip failure detection methods provided in the foregoing embodiments, thus achieving the corresponding technical effects. This has been described in detail above and will not be repeated here.

[0083] The packaging interface testing technology proposed in this application has significant multi-dimensional advantages. First, through an innovative DFT testing architecture, dedicated test paths are set at both ends of the TSV and a reverse transmission mode is adopted, enabling independent and accurate detection of TSV connectivity. This allows packaging process engineers to quantitatively calculate the actual TSV yield and evaluate the impact of the packaging process on the circuit. Second, this application supports comparative testing before and after packaging, clearly distinguishing between damage introduced by the packaging process and inherent defects. This provides chip designers with key data to optimize redundant TSV layout and automatic signal repair mechanisms. Simultaneously, the test results can accurately pinpoint transistor-level failures, significantly accelerating the design iteration cycle. For testers, this application provides a standardized testing process, enabling fault location and path configuration to be completed within a preset time. This application also has universal scalability, applicable not only to TSV interfaces but also to various packaging forms, providing a unified yield testing solution for advanced packaging, thereby comprehensively improving the reliability design and manufacturing level of 3D packaged products.

[0084] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0085] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0086] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0087] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this application, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0088] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0089] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for detecting failure of a packaged chip, the method comprising: The method comprises the following steps: detecting the packaging interface of the independent chip before packaging based on the test path of the design for testability to determine whether the transmitting end circuit, the receiving end circuit and the non-working state circuit of the chip before packaging are failed; detecting the packaging interface of the interconnected chip after packaging based on the test path of the design for testability to determine whether the transmitting end circuit, the receiving end circuit and the non-working state circuit of the chip after packaging are failed; comparing the detection results of the chip before packaging and the chip after packaging to locate the failure position and evaluate the influence of packaging on the circuit.

2. The method of claim 1, wherein, The method of detecting the packaging interface of the independent chip before packaging to determine whether the transmitting end circuit, the receiving end circuit and the non-working state circuit of the chip before packaging are failed comprises the following steps: configuring a preset test mode for the packaging interface of the independent chip before packaging, wherein the preset test mode comprises a transmitting end loopback mode, a receiving end loopback mode and a non-working mode; in the transmitting end loopback mode, inputting a first random test signal from a test signal input end, detecting the integrity of the transmitting end circuit through a random test signal output end, and determining whether the transmitting end circuit is failed; in the receiving end loopback mode, inputting a second random test signal from a test signal input end, detecting the integrity of the receiving end circuit through a main path output end, and determining whether the receiving end circuit is failed; in the non-working mode, determining whether the non-working state circuit is failed according to the voltage and current of the test path output end.

3. The method of claim 1, wherein the method further comprises: The method of detecting the packaging interface of the interconnected chip after packaging to determine whether the transmitting end circuit, the receiving end circuit and the non-working state circuit of the chip after packaging are failed comprises the following steps: configuring a preset test mode for the packaging interface of the interconnected chip after packaging, wherein the preset test mode comprises a transmitting end loopback mode, a receiving end loopback mode and a non-working mode; in the transmitting end loopback mode, inputting a third random test signal from a test signal input end, detecting the integrity of the transmitting end circuit through a random test signal output end, and determining whether the transmitting end circuit is failed; in the receiving end loopback mode, inputting a fourth random test signal from a test signal input end, detecting the integrity of the receiving end circuit through a main path output end, and determining whether the receiving end circuit is failed; in the non-working mode, determining whether the non-working state circuit is failed according to the voltage and current of the test path output end.

4. The method of claim 2 or 3, wherein The method of detecting the integrity of the transmitting end circuit or the receiving end circuit comprises the following steps: comparing the output signal with the random test signal sequence bit by bit to judge the logic consistency; and detecting the output signal delay, jitter or eye diagram quality to evaluate the high frequency characteristics; wherein the random test signal is generated by a built-in test signal generator.

5. The method of claim 3, wherein the step of detecting a failure of the packaged chip comprises the steps of: determining whether the packaged chip is operating normally; and determining whether the packaged chip is operating abnormally. The preset test mode further comprises a function mode; in the function mode, a detection circuit is connected to the main path output end of the receiving end circuit to monitor whether the output signal is consistent with the transmitting end input signal, or the overall working state of the interconnected chip after packaging is verified through a system-level function test.

6. The method of claim 1, wherein, The method of detecting the packaging interface of the interconnected chip after packaging based on the test path of the design for testability comprises the following steps: configure the packaging after the interconnected chip packaging interface into a reverse test mode; input a first test signal from a test signal input end of the receiving end circuit, transmit through the through silicon via structure, and output from a test signal output end of the sending end circuit; determine whether the through silicon via structure is failed by comparing the output signal of the test signal output end of the sending end circuit with the input signal of the test signal input end of the receiving end circuit.

7. The method of claim 6, wherein the step of detecting a failure of the packaged chip comprises the step of: The method comprises the following steps: if the output signal is consistent with the input signal, it is determined that the through silicon via structure is connected normally; if the output signal is inconsistent with the input signal, it is determined that the through silicon via structure is failed, and there is an open circuit or abnormal impedance.

8. A packaged chip failure detection apparatus, comprising: The method comprises the following steps: a pre-packaging chip detection unit is configured to detect the packaging interface of a pre-packaging independent chip based on a testability design test path to determine whether the sending end circuit, the receiving end circuit and the non-working state circuit of the pre-packaging chip are failed; a post-packaging chip detection unit is configured to detect the packaging interface of a post-packaging interconnected chip based on a testability design test path to determine whether the sending end circuit, the receiving end circuit and the non-working state circuit of the post-packaging chip are failed; a comparison unit is configured to compare the pre-packaging chip detection result and the post-packaging chip detection result to locate the failure position and evaluate the influence of packaging on the circuit.

9. The packaged chip failure detection apparatus of claim 8, wherein, The post-packaging chip detection unit comprises: a first configuration module configured to configure the packaging after the interconnected chip packaging interface into a reverse test mode; an input and output module configured to input a first test signal from a test signal input end of the receiving end circuit, transmit through the through silicon via structure, and output from a test signal output end of the sending end circuit; a first judgment module configured to determine whether the through silicon via structure is failed by comparing the output signal of the test signal output end of the sending end circuit with the input signal of the test signal input end of the receiving end circuit.

10. An electronic device, comprising: The electronic device comprises a housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is arranged inside a space enclosed by the housing, the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to each circuit or device of the electronic device; the memory is used to store executable program codes; the processor runs programs corresponding to the executable program codes by reading the executable program codes stored in the memory, and is used to execute the packaging chip failure detection method in any one of the preceding claims 1 to 7.

11. A computer readable storage medium, characterized in that, The computer readable storage medium stores one or more programs, which can be executed by one or more processors to implement the packaging chip failure detection method in any one of the preceding claims 1 to 7.

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