Chip verification method and device, electronic equipment and storage medium

Abstract

The invention provides a chip verification method and device, electronic equipment and a storage medium, and relates to the technical field of chip design verification, and the method comprises the steps: synchronously operating a to-be-verified chip design and a chip verification model to execute a preset cache line processing method; respectively acquiring a first output signal and first additional information of the to-be-verified chip design, and a second output signal and second additional information of the chip verification model; the first additional information is used for representing intermediate state information of a cache line in the design of the to-be-verified chip; the second additional information is used for representing intermediate state information of a cache line in the chip verification model; and determining a function verification result of the to-be-verified chip design. According to the method and the device provided by the invention, the output signal and the additional information are compared, so that the design defect can be found in time in the early stage of deviation of the internal logic state of the chip, the verification completeness and accuracy are greatly improved, and the overall verification efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of chip design verification technology, and in particular to a chip verification method, apparatus, electronic device and storage medium. Background Technology

[0002] Functional verification is a crucial step in ensuring the correctness of chip designs. When performing functional verification on complex chip designs, related technologies typically employ the construction of a high-level language reference model (such as a System Verilog model) that exhibits functional behavior consistent with the Design Under Test (DUT) for comparative verification.

[0003] This verification method is essentially an end-to-end black-box test. The verification platform can only observe the final output of the DUT, but cannot monitor the intermediate states of its internal logic units. Logical errors may have occurred within the DUT, but these errors may not be immediately reflected in the final output signal, or may even be masked by subsequent logical operations, leading to the omission of potential design flaws and insufficient verification coverage. Furthermore, to accurately locate design problems, engineers need to generate and analyze massive amounts of log files, significantly extending the debugging cycle and reducing debugging efficiency.

[0004] Therefore, how to verify the intermediate states inside the chip and improve the completeness of chip verification and debugging efficiency has become a technical problem that the industry urgently needs to solve. Summary of the Invention

[0005] This application provides a chip verification method, apparatus, electronic device, and storage medium to solve the technical problem of how to verify the intermediate state inside a chip and improve the completeness and debugging efficiency of chip verification.

[0006] This application provides a chip verification method, including: A preset cache line processing method is executed synchronously on the chip design to be verified and the chip verification model; the chip verification model is consistent with the chip design to be verified in terms of function and behavior. The first output signal and first additional information of the chip design to be verified, and the second output signal and second additional information of the chip verification model are obtained respectively; the first additional information is used to characterize the intermediate state information of the cache line in the chip design to be verified; the second additional information is used to characterize the intermediate state information of the cache line in the chip verification model. Based on the comparison results of the first output signal and the second output signal, and the comparison results of the first additional information and the second additional information, the functional verification result of the chip design to be verified is determined.

[0007] In some embodiments, the first additional information includes at least one of cache line priority information, cache line dirty data information, and cache line access time information of the chip design to be verified. The second additional information includes at least one of the following: cache line priority information, cache line dirty data information, and cache line access time information of the chip verification model.

[0008] In some embodiments, the preset cache line processing method includes an automatic cache line degradation method and / or an automatic cache line dirty data removal method.

[0009] In some embodiments, when the preset cache line processing method is a cache line automatic degradation method, the synchronous execution of the preset cache line processing method on the chip design to be verified and the chip verification model includes: If the count value of the first timer reaches its maximum value, perform the following steps: If the cache line access time information of all cache lines is in the first state, stop the degradation operation and clear the count value of the first timer to zero; Alternatively, if the cache line access time information of all cache lines includes the third state, select one cache line from the cache lines whose cache line access time information is in the third state, perform a downgrade operation, and clear the count value of the first timer to zero. Alternatively, if the cache line access time information of all cache lines includes the first state and the second state, select one cache line from the cache lines whose cache line access time information is in the second state, perform a degradation operation, and clear the count value of the first timer to zero. The access time of the cache line in the first state is less than the access time of the cache line in the second state; the access time of the cache line in the second state is less than the access time of the cache line in the third state.

[0010] In some embodiments, when the preset cache line processing method is an automatic cache line dirty data removal method, the synchronous execution of the preset cache line processing method on the chip design to be verified and the chip verification model includes: If the count value of the second timer reaches its maximum value, perform the following steps: If there are no cache lines storing dirty data, stop performing dirty data eviction and clear the count value of the second timer to zero; Alternatively, if a cache line storing dirty data exists, poll to select a cache line storing dirty data, perform a dirty data eviction operation, and reset the counter value of the second timer to zero.

[0011] In some embodiments, the method further includes: If the functional verification result of the chip design to be verified fails, a first preset signal is extracted from the chip design to be verified based on the first debugging virtual interface, and a second preset signal is extracted from the chip verification model based on the second debugging virtual interface. Based on at least one of the simulation waveform file of the first preset signal, the simulation waveform file of the second preset signal, the first debugging record file of the chip design to be verified, and the second debugging record file of the chip verification model, the fault location of the chip design to be verified is performed.

[0012] In some embodiments, the first preset signal includes cache line priority information and / or cache line dirty data information of the chip design to be verified; The second preset signal includes the cache line priority information and / or cache line dirty data information of the chip verification model.

[0013] This application provides a chip verification device, including: The runtime module is used to synchronously run the chip design to be verified and the chip verification model to execute a preset cache line processing method; the chip verification model is consistent with the chip design to be verified in terms of function and behavior. The acquisition module is used to acquire the first output signal and first additional information of the chip design to be verified, and the second output signal and second additional information of the chip verification model, respectively; the first additional information is used to characterize the intermediate state information of the cache line in the chip design to be verified; the second additional information is used to characterize the intermediate state information of the cache line in the chip verification model. The verification module is used to determine the functional verification result of the chip design to be verified based on the comparison result of the first output signal and the second output signal, and the comparison result of the first additional information and the second additional information.

[0014] This application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the chip verification method described above.

[0015] This application provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the chip verification method described above.

[0016] The chip verification method, apparatus, electronic device, and storage medium provided in this application, based on output signal comparison, add comparison of additional information that can characterize the intermediate state of the internal cache line, upgrading chip verification from a black-box mode to a white-box mode. By comparing the output signal and the additional information, potential design defects can be detected in a timely manner at an early stage when the internal logic state of the chip deviates but has not yet caused the final output signal to malfunction. This greatly improves the completeness and accuracy of verification, enables earlier and more accurate problem location, significantly shortens the debugging cycle of complex chip designs, and improves the overall verification efficiency. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating the chip verification method provided in this application.

[0020] Figure 2 This is a framework diagram for debugging the chip verification model provided in this application.

[0021] Figure 3 This is a flowchart of the verification process for automatic cache line degradation provided in this application.

[0022] Figure 4 This is a flowchart of the verification process for automatically removing dirty data from cache lines provided in this application.

[0023] Figure 5 This is a schematic diagram of the chip verification device provided in this application.

[0024] Figure 6 This is a schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0026] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps, units, or modules is not necessarily limited to those explicitly listed, but may include other steps, units, or modules not explicitly listed or inherent to such processes, methods, products, or devices.

[0027] ‌ Figure 1 This is a flowchart illustrating the chip verification method provided in this application, as shown below. Figure 1 As shown, the method includes steps 110, 120 and 130.

[0028] Step 110: Simultaneously run the chip design to be verified and the chip verification model to execute the preset cache line processing method; the chip verification model and the chip design to be verified are consistent in function and behavior.

[0029] Specifically, the chip verification method provided in this application is executed by a chip verification device. This device can be implemented in software, such as a chip verification program; or it can be a device that executes the chip verification method, such as a mobile terminal, tablet computer, desktop computer, or server.

[0030] A design under test (DUT) is a digital circuit design of a chip implemented in a hardware description language (such as Verilog, VHDL, etc.) that has not yet been finalized or requires functional correctness verification. A DUT must include at least a level 2 cache.

[0031] A chip verification model is a software model used for reference and comparison. This model maintains functional consistency with the chip design under test; that is, for the same input stimuli, its output and the trajectory of changes in internal critical states should be identical to the functionally correct chip design under test. This chip verification model is also known as a reference model. In practical verification environments, this chip verification model can be built using a high-level verification language (such as SystemVerilog) combined with standardized verification methodologies (such as UVM) to achieve high flexibility and reusability. Chip verification models built using SystemVerilog are also called SV Models.

[0032] Synchronous operation refers to running the chip design to be verified and the chip verification model on the same verification platform, receiving the same clock signal, reset signal and input stimulus sequence, to ensure that the two are strictly aligned in time and perform the same operation process.

[0033] Pre-defined cache line processing methods refer to the automated processing logic for cache lines inherent within the chip design under test. This processing logic does not require intervention from external real-time instructions but is executed automatically according to pre-defined rules. For example, in L2 cache design, some internal automated processing logic is usually designed to optimize cache performance.

[0034] In this application embodiment, the chip design to be verified and the chip verification model are simultaneously triggered and executed by a preset cache line processing method. For example, an internal timer can be set, and when the timer reaches a certain preset value, the chip design to be verified and the chip verification model will synchronously execute the preset cache line processing method.

[0035] Step 120: Obtain the first output signal and first additional information of the chip design to be verified, and the second output signal and second additional information of the chip verification model respectively; the first additional information is used to characterize the intermediate state information of the cache line in the chip design to be verified; the second additional information is used to characterize the intermediate state information of the cache line in the chip verification model.

[0036] Specifically, during the synchronous operation of the chip design and chip verification model, two types of information need to be extracted for subsequent comparison.

[0037] The first category is output signals, which refer to the signals output by the standard functional interface of the chip design to be verified or the chip verification model (interface out signal, intf out sig). The first output signal is the signal output by the standard functional interface of the chip design to be verified; the second output signal is the signal output by the standard functional interface of the chip verification model. Output signals can include data bus signals after a read operation is completed, acknowledgement signals for write operations, request or confirmation signals sent to higher or lower level modules, etc.

[0038] The second category is additional information, which refers to the additional information output by the interface of the chip design to be verified or the chip verification model. The first additional information is used to characterize the intermediate state information of the cache line in the chip design to be verified; the second additional information is used to characterize the intermediate state information of the cache line in the chip verification model.

[0039] Unlike conventional output signals, this additional information is typically not directly exposed on the chip's external interface, but rather resides within the design's internal logic state, reflecting internal changes during the execution of the preset cache line processing method. The first additional information can be probed or extracted from the internal nodes of the chip design to be verified (such as registers, state machine variables, etc.). The second additional information can be obtained from the internal member variables or state variables of the chip verification model.

[0040] Intermediate state information of a cache line refers to data that reflects the attributes of a cache line at a specific point in time. This may include a priority value (prio) to indicate the replacement priority of the cache line, a dirty flag to indicate whether the cache line data has been modified, and a count value (age) to record the number of clock cycles elapsed since the cache line was last accessed.

[0041] Additional information allows us to see the internal workings of the chip design under test, rather than just observing its final external output.

[0042] Step 130: Based on the comparison results of the first output signal and the second output signal, and the comparison results of the first additional information and the second additional information, determine the functional verification results of the chip design to be verified.

[0043] Specifically, when verifying the functional correctness of the chip design to be verified, the following operations are performed: First, the first output signal and the second output signal are compared. If they are inconsistent, it indicates that the chip design to be verified has a functional error. Second, the first additional information and the second additional information are compared. If they are inconsistent, it also indicates that the chip design to be verified has a functional error.

[0044] The functional verification of the chip design under test can only be considered successful (passed) at the current moment if both the comparison results of the output signal and the comparison results of the additional information are consistent. If any comparison is inconsistent, the functional verification result is considered a failure (not passed).

[0045] In the above process, additional information can be compared by checking whether the intermediate state information of the cache lines of the chip design to be verified matches that of the chip verification model. If they do not match, the additional information can also be used to locate faults in the logic modules or functional units of the chip design to be verified.

[0046] The chip verification method provided in this application, based on output signal comparison, adds comparison of additional information that can characterize the intermediate state of the internal cache line, upgrading chip verification from a black-box mode to a white-box mode. By comparing the output signal and the additional information, potential design defects can be detected in a timely manner at an early stage when the internal logic state of the chip deviates but has not yet caused the final output signal to malfunction. This greatly improves the completeness and accuracy of verification, enables earlier and more accurate problem location, significantly shortens the debugging cycle of complex chip designs, and improves the overall verification efficiency.

[0047] It should be noted that each implementation method of this application can be freely combined, rearranged, or executed individually, and does not need to rely on or depend on a fixed execution order.

[0048] In some embodiments, the first additional information includes at least one of cache line priority information, cache line dirty data information, and cache line access time information of the chip design to be verified; The second additional information includes at least one of the following: cache line priority information, cache line dirty data information, and cache line access time information of the chip verification model.

[0049] Specifically, cache line priority information refers to information related to the priority of each cache line. Cache line priority refers to the priority at which each cache line in the cache (such as L2 Cache) is evicted. The chip system maintains a priority value (prio) for each cache line and selects the cache line with the highest priority for eviction.

[0050] In this embodiment of the application, by comparing cache line priority information as additional information, inconsistencies can be detected the instant that an error occurs in the priority update logic (e.g., a downgrade is not performed when it should be downgraded, or the downgrade value is incorrect), without having to wait until the incorrect priority causes an incorrect cache line eviction operation before the problem is discovered.

[0051] Cache line dirty data information refers to information related to dirty data stored in each cache line. Dirty data refers to data in a cache line that has been modified. Cache line dirty data information can be used to identify data in a cache line that has been modified but has not yet been written back to the next level of storage (such as main memory). If the data in a cache line has been modified, the cache line is said to be dirty; otherwise, it is clean. Cache line dirty data information is also known as the dirty bit.

[0052] In the embodiments of this application, by comparing the dirty data information of each cache line in the chip design to be verified and the chip verification model, the correctness of the dirty bit setting can be verified immediately after the write operation occurs, or the correctness of the dirty bit clearing can be verified immediately after the data is written back, thereby achieving precise monitoring of the data consistency management logic.

[0053] Cache line access time information refers to information related to the access time of each cache line. Cache line access time refers to the elapsed time since a cache line was last used (accessed), and can represent the storage duration of data in the cache line.

[0054] In this embodiment, the correctness of the cache line replacement algorithm directly affects system performance. By comparing cache line access time information, it can be ensured that the cache line usage logic inside the chip design to be verified is completely consistent with the reference implementation in the chip verification model, thereby guaranteeing the logical correctness of its replacement algorithm and avoiding erroneous cache line replacement behavior due to timing errors.

[0055] One or more of the following can be selected as additional information for comparison: cache line priority information, cache line dirty data information, and cache line access time information, in order to achieve more comprehensive internal status monitoring of the chip design under verification.

[0056] The chip verification method provided in this application, by specifying additional information as internal state information such as cache line priority, dirty state, and access time, enables the verification of the internal logic units of the chip. It can discover logic defects that traditional testing methods cannot reach, thereby greatly improving the completeness and accuracy of verification.

[0057] In some embodiments, the preset cache line processing method includes an automatic cache line degradation method and / or an automatic cache line dirty data removal method.

[0058] Specifically, to implement an efficient cache replacement strategy, a priority is associated with each or each group of cache lines in the chip design. This priority is used to determine which cache line should be replaced first when a cache miss occurs and an existing cache line needs to be replaced. Generally, cache lines with higher priority are more likely to be replaced.

[0059] Automatic cache line degradation refers to a mechanism within the cache controller of a chip design that automatically lowers the priority of certain cache lines according to preset rules without external instruction intervention. For example, this method can be implemented based on an internal timer.

[0060] In one specific embodiment, both the chip design to be verified and the chip verification model are configured with timers. When the timer starts counting from 0 and reaches a preset value, the automatic degradation method is triggered synchronously. At this time, the chip design to be verified and the chip verification model simultaneously scan all or part of their internal cache lines and automatically reduce the priority value of cache lines that meet specific conditions.

[0061] In a write-back cache, when the chip performs a write operation on a cache line, the data in that cache line will be inconsistent with the data in main memory. At this point, the cache line is called dirty data. This dirty data must be written back to main memory at some point in the future; this process is called evict or write-back.

[0062] The automatic eviction of dirty cache lines refers to the cache controller automatically selecting one or more dirty cache lines and writing their data back to main memory based on internal preset logic, thereby cleaning them up or directly replacing them. The triggering conditions for this automatic eviction operation can be various, such as an internal timer reaching a preset value, the number of dirty data in the cache reaching a certain threshold, or a dirty data not being accessed for a long time.

[0063] You can choose at least one of the following methods to verify the chip design: automatic cache line degradation method and automatic cache line dirty data removal method.

[0064] The chip verification method provided in this application specifies the verification target as two key internal automated operations: automatic cache line degradation and automatic removal of dirty data in cache lines. This enables chip design verification to delve into the core logic of cache management, greatly improving the completeness and accuracy of the verification.

[0065] In some embodiments, the method further includes: If the functional verification result of the chip design to be verified fails, a first preset signal is extracted from the chip design to be verified based on the first debug virtual interface, and a second preset signal is extracted from the chip verification model based on the second debug virtual interface. Based on at least one of the following: a simulation waveform file of a first preset signal, a simulation waveform file of a second preset signal, a first debugging record file of the chip design to be verified, and a second debugging record file of the chip verification model, fault location is performed on the chip design to be verified.

[0066] Specifically, the Virtual Interface (VIF) is a logical interface designed specifically for debugging purposes and existing in a simulation verification environment. It differs from the standard functional interface of the chip design itself; its sole purpose is to expose signals deep within the design that are normally invisible to the verification engineer.

[0067] The first debug virtual interface can connect to the internal nodes of the chip design to be verified. The second debug virtual interface can connect to the internal variables of the chip verification model; for example, a SystemVerilog interface named "model_debug vif" can be defined in the chip verification model.

[0068] Preset signals refer to one or more sets of internal signals that are critical to debugging, selected in advance based on the functional characteristics and potential error modes of the chip design to be verified. These signals are typically strongly logically related to additional information or output signals that may cause errors.

[0069] By extracting preset signals through the debugging virtual interface, key debugging information can be transmitted directionally from the complex internal design to the top level of the verification environment, preparing for subsequent fault location.

[0070] Fault localization refers to the process of identifying the logic unit that caused the functional verification to fail (the functional verification result is failure), that is, finding out which specific part of the logic implementation in the chip design to be verified does not conform to expectations.

[0071] Simulation waveform files are graphical representations that record the changes of all signal values ​​over time during the simulation process. The format of simulation waveform files can be Fast Signal Database (FSDB). Since the first and second preset signals have been extracted to the debug virtual interface, verification engineers can display the first preset signal from the chip design under test and the second preset signal from the chip verification model side-by-side in waveform analysis tools. When an error occurs, verification engineers can visually see on the waveform graph at the precise point in time when the values ​​of the two signals begin to deviate, and can trace back along the logical driving relationship of the signals to the source logic causing the deviation, thereby quickly locating the fault.

[0072] Debug log files are text files generated during simulation from the printed statements within the chip design or chip verification model. These files can record detailed transaction-level information, the sequence of events, and the values ​​of internal variables printed by the software. Although analyzing these large text files can be very time-consuming, they provide macroscopic process information and software-level state records that are difficult to display in waveform diagrams, serving as an important supplement to waveform analysis.

[0073] A combination of simulation waveform files and debug log files can be used to locate faults in the chip design to be verified. In a specific embodiment, the time point and signal of the error can be quickly found by comparing the waveforms of the first preset signal and the second preset signal. Then, the debug log files generated by the chip design and the chip verification model before and after that time point can be consulted to obtain richer contextual information, thereby comprehensively understanding the cause and effect of the error and finally completing the fault location.

[0074] The chip verification method provided in this application, by setting up a debugging virtual interface and extracting preset signals, enables verification engineers to directly perform visual waveform comparison analysis of internal signals from the chip design to be verified and the chip verification model when verification fails, thereby greatly reducing the reliance on cumbersome and inefficient log files. In addition, waveform comparison analysis and log file analysis can be combined to improve the intuitiveness and efficiency of fault location, greatly shorten the debugging cycle, and reduce the verification cost of complex chip designs.

[0075] In some embodiments, the first preset signal includes cache line priority information and / or cache line dirty data information of the chip design to be verified; The second preset signal includes cache line priority information and / or cache line dirty data information of the chip verification model.

[0076] Specifically, the preset signal may include cache line priority information and / or cache line dirty data information.

[0077] Cacheline priority information (cacheline priority info) not only represents the final value of the cacheline priority, but also broadly includes all internal signals related to the calculation, updating, and use of that priority. When functional verification fails due to a mismatch in additional priority-related information, the aforementioned first preset signal (from the chip design under test) and second preset signal (from the chip verification model) can be extracted simultaneously through the debug virtual interface and compared on the simulation waveform. Verification engineers can clearly observe which step caused the deviation in the final priority value.

[0078] The dirty data information in the cache line not only includes the dirty bit that identifies whether the data is "dirty", but can also include richer information related to the dirty data processing flow, such as write-back dirty data information (wb dirty data info).

[0079] Figure 2 This is a framework diagram of the chip verification model debugging provided in this application, such as... Figure 2 As shown, the first output signal (dut intf out sig) and the first additional information (dut additional info) of the chip design to be verified (DUT), as well as the second output signal (model intf out sig) and the second additional information (modeladditional info) of the chip verification model (SV Model) are input into the L2 cache adapter (L2 Adapter). The output result of the L2 cache adapter is sent to the comparator (comp), and the comparator determines the functional verification result of the chip design to be verified.

[0080] In the event of a functional verification failure, the first debug log file of the chip design to be verified is obtained through the log file collection component of the verification platform, and the first preset signal is extracted from the chip design through the first debug virtual interface. The second debug log file (model debug log) of the chip verification model is obtained, and the second preset signal (wb dirty datainfo and cacheline prio info) is extracted from the chip verification model through the second debug virtual interface (model debug vif).

[0081] By analyzing the simulation waveforms of the first and second preset signals, and combining the first debugging record file of the chip design to be verified with the second debugging record file of the chip verification model, fault location can be performed on the chip design to be verified.

[0082] The chip verification method provided in this application determines the cache line priority information and cache line dirty data information that are directly related to the core verification target as preset signals, making the fault location process more targeted, improving the efficiency and accuracy of debugging, and significantly shortening the verification iteration cycle of complex chip designs.

[0083] In some embodiments, when the preset cache line processing method is an automatic cache line degradation method, the preset cache line processing method is executed synchronously on the chip design to be verified and the chip verification model, including: If the count value of the first timer reaches its maximum value, perform the following steps: If the cache line access time information of all cache lines is in the first state, stop the degradation operation and clear the count value of the first timer to zero; Alternatively, if the cache line access time information of all cache lines includes the third state, poll among the cache lines whose cache line access time information is in the third state to select one cache line to perform a downgrade operation, and clear the count value of the first timer to zero; Alternatively, if the cache line access time information of all cache lines includes the first state and the second state, select one cache line from the cache lines whose cache line access time information is in the second state, perform a degradation operation, and clear the count value of the first timer to zero. The access time for a cache line in the first state is less than the access time for a cache line in the second state; the access time for a cache line in the second state is less than the access time for a cache line in the third state.

[0084] Specifically, the cacheline age of all cached lines can be determined based on their access duration. This cacheline age includes three states: a first state, a second state, and a third state. The access duration of a cacheline in the first state is less than that of a cacheline in the second state; the access duration of a cacheline in the second state is less than that of a cacheline in the third state. For example, the first state could be "young" (most recently accessed), the second state could be "normal" (most recently accessed), and the third state could be "old" (least recently accessed).

[0085] Understandably, cache lines in the first state have low priority and do not need to be downgraded; cache lines in the third state have high priority and need to be downgraded first; cache lines in the second state have medium priority and are only downgraded when no higher priority cache lines are replaced.

[0086] Since the chip design to be verified and the chip verification model are identical in functional behavior, the automatic cache line degradation method executed by the chip design to be verified is the same as that of the chip verification model. Therefore, the automatic cache line degradation method will be explained below using the chip verification model as an example.

[0087] The chip verification model can be configured with a first timer to time the execution of the automatic cache line degradation method. When the count value of the first timer reaches its maximum value (the maximum value can be set as needed), a cache line that meets the conditions is selected to perform the degradation operation.

[0088] In the first case, if the cache line access time information of all cache lines in the cache is in the first state (indicating that the cache line priority of all cache lines is low), then the degradation operation will be stopped and the count value of the first timer will be cleared.

[0089] In the second scenario, if the cache line access time information of all cache lines includes a third state (indicating the existence of a cache line with a high priority), select one cache line from among the multiple cache lines with the third state in the cache line access time information, perform a degradation operation, and clear the count value of the first timer to zero.

[0090] For example, in the L2 cache, cache lines whose access time information is in the second or third state can be selected to form a cache line set. Multiple cache lines can be combined into a cache line set list. From the cache line set list, a cache line set can be selected (using a round-robin approach). It is then checked whether there is a cache line in the third state in that cache line set. If one or more exist, a cache line is selected in a round-robin fashion to perform a degradation operation, which can update it from the third state to the first state, reducing its priority from high to low.

[0091] In the third scenario, if the cache line access time information of all cache lines includes the first state and the second state (indicating that there are cache lines with medium and low priority, but no cache lines with high priority), then select one cache line from the cache lines with the second state in a round-robin fashion to perform a downgrade operation, and clear the count value of the first timer to zero.

[0092] Accordingly, cache line priority information can be used as a preset signal. When functional verification fails due to mismatch of additional priority-related information, the first preset signal (from the chip design to be verified) and the second preset signal (from the chip verification model) can be extracted simultaneously through the debugging virtual interface and compared on the simulation waveform. Verification engineers can clearly observe which link caused the deviation of the final priority value.

[0093] Figure 3 This is a flowchart of the verification process for automatic cache line degradation provided in this application, such as... Figure 3 As shown, the Design Under Test (DUT) and the SV Model can generate an inter-auto downgrade request when their respective first timer counts reach their maximum values, triggering the execution of the cache line auto-downgrade method. This request is an internal request and requires no external input.

[0094] The first output signal (dut intf out sig) and the first additional information (dut additional info) of the chip design to be verified (DUT), and the second output signal (model intfout sig) and the second additional information (model additional info) of the chip verification model (SV Model) are compared and input to the L2 cache adapter. The output result of the L2 cache adapter is sent to the comparator (comp), and the comparator determines the functional verification result of the chip design to be verified.

[0095] The output signals may include: req_id (request ID), req_addr (request address), req_set_index (index of the requested cache line group), req_way_index (index of the cache line that needs to be downgraded), timer_cnt (count value of the first timer), etc.

[0096] Additional information may include: req_cacheline_prio (the level of cache line downgrade), l2_prio_young_all_set (cache lines in the L2 cache whose access time information is in the first state), l2_prio_old_all_set (cache lines in the L2 cache whose access time information is in the third state), l2_prio_nml_all_set (cache lines in the L2 cache whose access time information is in the second state), etc.

[0097] The first debug log file (DUT debug log) of the chip design to be verified is obtained through the DUT monitor and is ultimately input into the log collection component (log collect) in the verification environment. The second debug log file (model debug log) of the chip verification model is also input into the log collection component (log collect).

[0098] In the event of a functional verification failure, the first debug log file of the chip design to be verified is obtained, and the first preset signal is extracted from the chip design through the first debug virtual interface. The second debug log file of the chip verification model is obtained, and the second preset signal (wb dirty data info and cacheline prio info) is extracted from the chip verification model through the second debug virtual interface (model debug vif).

[0099] By analyzing the simulation waveform files (FSDB format) of the first and second preset signals, and combining the first debugging record file of the chip design to be verified and the second debugging record file of the chip verification model, fault location can be performed on the chip design to be verified.

[0100] The chip verification method provided in this application specifies the verification target as an automatic cache line degradation operation, which enables chip design verification to delve into the core logic of cache management, greatly improving the completeness and accuracy of the verification.

[0101] In some embodiments, when the preset cache line processing method is an automatic cache line dirty data removal method, the preset cache line processing method is executed synchronously on the chip design to be verified and the chip verification model, including: If the count value of the second timer reaches its maximum value, perform the following steps: If there are no cache lines storing dirty data, stop performing dirty data eviction and clear the counter value of the second timer to zero; Alternatively, if a cache line storing dirty data exists, poll to select one of the cache lines storing dirty data, perform a dirty data eviction operation, and reset the counter value of the second timer to zero.

[0102] Specifically, since the chip design to be verified and the chip verification model are identical in functional behavior, the automatic eviction method for dirty data in cache lines performed by the chip design to be verified is the same as that of the chip verification model. Therefore, the following explanation uses the chip verification model as an example to illustrate the automatic eviction method for dirty data in cache lines.

[0103] The chip verification model can be configured with a second timer to time the execution of the automatic dirty data eviction method for cache lines. When the count value of the second timer reaches its maximum value (the maximum value can be set as needed), cache lines that meet the conditions are selected to perform dirty data eviction.

[0104] In the first case, if there is no cache line storing dirty data, stop the dirty data eviction operation and clear the counter value of the second timer to zero.

[0105] In the second scenario, if there is a cache line storing dirty data, poll to select a cache line storing dirty data, perform a dirty data eviction operation, and clear the counter value of the second timer to zero.

[0106] For example, cache lines can be selected in the L2 cache to form a cache line set, and multiple cache lines can be combined into a cache line set list. A cache line set is selected from the cache line set list (which can be done by round-robin), and it is checked whether there is a cache line storing dirty data in the cache line set. If one or more exist, a cache line is selected in round-robin to perform a dirty data eviction operation (storing the data from the cache line to main memory).

[0107] Correspondingly, the dirty data information of the cache line can be used as a preset signal. When the functional verification fails due to the mismatch of additional information related to the dirty data, the first preset signal (from the chip design to be verified) and the second preset signal (from the chip verification model) can be extracted simultaneously through the debugging virtual interface and compared on the simulation waveform. The verification engineer can clearly observe which link caused the dirty data information of the cache line to be not removed and thus cause the failure.

[0108] Figure 4 This is a flowchart illustrating the verification process for automatically removing dirty data from cache lines provided in this application. Figure 4 As shown, the Design Under Test (DUT) and the SV Model can generate an inter auto cacheline evict request when their respective second timer counts reach their maximum values, triggering the execution of the cacheline auto-evict method. This request is an internal request and requires no external input.

[0109] The first output signal (dut intf out sig) and the first additional information (dut additional info) of the chip design to be verified (DUT), and the second output signal (model intfout sig) and the second additional information (model additional info) of the chip verification model (SV Model) are compared and input to the L2 cache adapter. The output result of the L2 cache adapter is sent to the comparator (comp), and the comparator determines the functional verification result of the chip design to be verified.

[0110] The output signals may include: req_id (request ID), req_addr (request address), req_set_index (index of the cache line group of the request), req_way_index (index of the cache line that needs to be evictioned), timer_cnt (count value of the second timer), etc.

[0111] Additional information may include: l2_dirty_way_all_set (cache lines in the L2 cache that store dirty data), l2_clean_way_all_set (cache lines in the L2 cache that do not store dirty data), l2_clean_valid_all_set (cache lines in the L2 cache that are valid), etc.

[0112] The first debug log file (DUT debug log) of the chip design to be verified is obtained through the DUT monitor and is ultimately input into the log collection component (log collect) in the verification environment. The second debug log file (model debug log) of the chip verification model is also input into the log collection component (log collect).

[0113] In the event of a functional verification failure, the first debug log file of the chip design to be verified is obtained, and the first preset signal is extracted from the chip design through the first debug virtual interface. The second debug log file of the chip verification model is obtained, and the second preset signal (wb dirty data info and cacheline prio info) is extracted from the chip verification model through the second debug virtual interface (model debug vif).

[0114] By analyzing the simulation waveform files (FSDB format) of the first and second preset signals, and combining the first debugging record file of the chip design to be verified and the second debugging record file of the chip verification model, fault location can be performed on the chip design to be verified.

[0115] The chip verification method provided in this application specifies the verification target as the automatic removal of dirty data in the cache line, which enables chip design verification to delve into the core logic of cache management, greatly improving the completeness and accuracy of the verification.

[0116] The apparatus provided in the embodiments of this application is described below. The apparatus described below can be referred to in correspondence with the method described above.

[0117] Figure 5 This is a schematic diagram of the chip verification device provided in this application, as shown below. Figure 5 As shown, the device includes: The running module 510 is used to synchronously run the chip design to be verified and the chip verification model to execute a preset cache line processing method; the chip verification model is consistent with the chip design to be verified in terms of function and behavior; The acquisition module 520 is used to acquire the first output signal and first additional information of the chip design to be verified, and the second output signal and second additional information of the chip verification model, respectively; the first additional information is used to characterize the intermediate state information of the cache line in the chip design to be verified; the second additional information is used to characterize the intermediate state information of the cache line in the chip verification model. The verification module 530 is used to determine the functional verification result of the chip design to be verified based on the comparison result of the first output signal and the second output signal, and the comparison result of the first additional information and the second additional information.

[0118] The chip verification apparatus provided in this application, based on output signal comparison, adds comparison of additional information that can characterize the intermediate state of the internal cache line, upgrading chip verification from a black-box mode to a white-box mode. By comparing the output signal and the additional information, potential design defects can be detected in a timely manner at an early stage when the internal logic state of the chip deviates but has not yet caused the final output signal to malfunction. This greatly improves the completeness and accuracy of verification, enables earlier and more accurate problem location, significantly shortens the debugging cycle of complex chip designs, and improves the overall verification efficiency.

[0119] Figure 6 This is a schematic diagram of the structure of the electronic device provided in this application, such as... Figure 6 As shown, the electronic device may include: a processor 610, a communications interface 620, a memory 630, and a communications bus 640, wherein the processor, communications interface, and memory communicate with each other via the communications bus. The processor can invoke logical commands stored in the memory to execute the methods described in the above embodiments, for example: The chip design to be verified and the chip verification model are run synchronously using a preset cache line processing method; the chip verification model and the chip design to be verified are consistent in function and behavior; the first output signal and the first additional information of the chip design to be verified, and the second output signal and the second additional information of the chip verification model are obtained respectively; the first additional information is used to characterize the intermediate state information of the cache line in the chip design to be verified; the second additional information is used to characterize the intermediate state information of the cache line in the chip verification model; based on the comparison result of the first output signal and the second output signal, and the comparison result of the first additional information and the second additional information, the functional verification result of the chip design to be verified is determined.

[0120] Furthermore, when the logical commands in the aforementioned memory can be implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several commands to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0121] The processor in the electronic device provided in this application embodiment can call logical instructions in the memory to implement the above method. Its specific implementation method is the same as the aforementioned method implementation method and can achieve the same beneficial effect, which will not be repeated here.

[0122] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the methods provided in the above embodiments.

[0123] The specific implementation method is the same as the aforementioned method implementation method and can achieve the same beneficial effects, so it will not be repeated here.

[0124] This application provides a computer program product, including a computer program that, when executed by a processor, implements the method described above.

[0125] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0126] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A chip verification method characterized by, The method comprises the following steps: synchronously running a chip design to be verified and a chip verification model to execute a preset cache line processing method; the chip verification model is consistent with the chip design to be verified in functional behavior; first output signals and first additional information of the chip design to be verified are acquired, and second output signals and second additional information of the chip verification model are acquired; the first additional information is used to represent intermediate state information of a cache line in the chip design to be verified; the second additional information is used to represent intermediate state information of a cache line in the chip verification model; a functional verification result of the chip design to be verified is determined based on comparison results of the first output signals and the second output signals, and comparison results of the first additional information and the second additional information.

2. The chip verification method according to claim 1, wherein the first additional information comprises at least one of cache line priority information, cache line dirty data information and cache line access time information of the chip design to be verified; the second additional information comprises at least one of cache line priority information, cache line dirty data information and cache line access time information of the chip verification model.

3. The chip verification method of claim 1, wherein, the preset cache line processing method comprises a cache line automatic degradation method and / or a cache line dirty data automatic elimination method.

4. The chip verification method according to claim 3, wherein in the case that the preset cache line processing method is the cache line automatic degradation method, the step of synchronously running the chip design to be verified and the chip verification model to execute the preset cache line processing method comprises: in the case that a count value of a first timer reaches a maximum value, the following steps are executed: in the case that cache line access time information of all cache lines is in a first state, the degradation operation is stopped, and the count value of the first timer is cleared; or, in the case that the cache line access time information of all cache lines comprises a third state, a cache line in a cache line access time information third state is selected by polling to execute the degradation operation, and the count value of the first timer is cleared; or, in the case that the cache line access time information of all cache lines comprises a first state and a second state, a cache line in a cache line access time information second state is selected by polling to execute the degradation operation, and the count value of the first timer is cleared; the access time length of the cache line in the first state is less than that of the cache line in the second state, and the access time length of the cache line in the second state is less than that of the cache line in the third state.

5. The chip verification method according to claim 3, wherein in the case that the preset cache line processing method is the cache line dirty data automatic elimination method, the step of synchronously running the chip design to be verified and the chip verification model to execute the preset cache line processing method comprises: in the case that a count value of a second timer reaches a maximum value, the following steps are executed: in the case that there is no cache line storing dirty data, the dirty data elimination operation is stopped, and the count value of the second timer is cleared; or, in the case that there is a cache line storing dirty data, a cache line storing dirty data is selected by polling to execute the dirty data elimination operation, and the count value of the second timer is cleared.

6. The chip verification method according to any one of claims 1 to 5, characterized by, the method further comprises: In a case that the function verification result of the chip design to be verified is failure, a first preset signal is extracted from the chip design to be verified based on a first debugging virtual interface, and a second preset signal is extracted from the chip verification model based on a second debugging virtual interface; At least one of a simulation waveform file of the first preset signal, a simulation waveform file of the second preset signal, a first debugging record file of the chip design to be verified and a second debugging record file of the chip verification model is used to perform fault positioning on the chip design to be verified.

7. The chip verification method according to claim 6, wherein The first preset signal comprises cache line priority information and / or cache line dirty data information of the chip design to be verified. The second preset signal comprises cache line priority information and / or cache line dirty data information of the chip verification model.

8. A chip verification apparatus characterized by comprising: Comprise: A running module is configured to run the chip design to be verified and the chip verification model to execute a preset cache line processing method synchronously. The chip verification model is consistent with the chip design to be verified in terms of function behavior. An acquisition module is configured to acquire a first output signal and first additional information of the chip design to be verified, and a second output signal and second additional information of the chip verification model. The first additional information is used to represent intermediate state information of a cache line in the chip design to be verified. The second additional information is used to represent intermediate state information of a cache line in the chip verification model. A verification module is configured to determine a function verification result of the chip design to be verified based on a comparison result of the first output signal and the second output signal, and a comparison result of the first additional information and the second additional information.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the chip verification method in any one of claims 1 to 7. 10.A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the chip verification method in any one of claims 1 to 7.

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