Data processing method, device, electronic device, storage medium, and program product

Abstract

The present disclosure provides a data processing method, device, electronic device, storage medium and program product, relating to the technical field of chip design, the method comprising: buffering an input valid signal based on a global clock buffer corresponding to a field programmable gate array to obtain a first signal, enabling each module of a data processing device within a first time interval based on the first signal; processing the to-be-processed data based on a data grouping module and a message padding module to obtain first data, and transmitting the first data to an iterative calculation module; performing iterative operation processing on the first data based on each sub-function included in a first function in the iterative calculation module to obtain an output result corresponding to the to-be-processed data. In this way, the path of the input valid signal is optimized by the global clock buffer, which is quickly transmitted to each module of the data processing device, reduces the congestion of wiring, optimizes the timing path, and improves the operating frequency and operation performance.

Description

Technical Field

[0001] This disclosure relates to the field of chip design technology, and in particular to a data processing method, apparatus, electronic device, storage medium, and program product. Background Technology

[0002] SHA-3 is the third-generation Secure Hash Algorithm, formerly known as Keccak. It is a cryptographic hash algorithm and the latest generation of secure hash algorithms. Secure hash algorithms are also called hash algorithms. Keccak can resist attacks with a minimum complexity of 2^N, where N is the size of the hash. To date, third-party cryptanalysis shows that Keccak has no serious security flaws.

[0003] When the SHA3 algorithm is implemented on Field-Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) platforms, the complex algorithm principle and operation process of SHA3 (involving permutation, shifting, linear and nonlinear operations of large bit-width data and multidimensional arrays) result in excessively long timing paths and congested placement and routing, ultimately leading to low algorithm running frequency and low computing power. Summary of the Invention

[0004] This disclosure provides a data processing method, apparatus, electronic device, storage medium, and program product to at least solve the above-mentioned technical problems existing in the prior art.

[0005] According to a first aspect of this disclosure, a data processing method is provided, implemented based on a data processing device, wherein each module of the data processing device is implemented based on at least one partition of a field-programmable gate array (FPGA), and the data processing device includes at least a data grouping module, a message filling module, and an iterative calculation module; the method includes:

[0006] The input valid signal is buffered by the global clock buffer corresponding to the field programmable gate array to obtain a first signal. The first signal is then transmitted to each module of the data processing device, so that each module of the data processing device starts up within a first time interval based on the first signal.

[0007] The data to be processed is processed by the data grouping module and the message filling module to obtain the first data, and the first data is transmitted to the iterative calculation module.

[0008] The first data is processed iteratively based on the sub-functions included in the first function of the iterative calculation module to obtain the output result corresponding to the data to be processed;

[0009] The first function includes a first sub-function, a second sub-function, a third sub-function, a fourth sub-function, and a fifth sub-function; the first sub-function, the second sub-function, and the third sub-function are each configured with at least two registers; the registers are used to store data input to the corresponding sub-function or data output by the corresponding sub-function, so that the data input to the corresponding sub-function is input to the corresponding sub-function via the shortest path.

[0010] The method in the above scheme further includes:

[0011] Based on the source of the data to be processed, the field-programmable gate array (FPGA) partitions of the data input module included in the data processing device are determined, such that the distance between the data input module and the partition in the FPGA that receives the data to be processed is less than a first threshold.

[0012] In the above scheme, determining the field-programmable gate array partition of the data input module included in the data processing device based on the source of the data to be processed includes:

[0013] In response to the input of data to be processed from the first port of the field-programmable gate array (FPGA), it is determined that the distance between the FPGA partition implementing the data input module and the FPGA partition implementing the input is less than a first threshold.

[0014] The method in the above scheme further includes:

[0015] It is determined that the data grouping module and the data input module are implemented using the same field-programmable gate array partition;

[0016] Alternatively, determine that the distance between the field-programmable gate array partition implementing the data grouping module and the field-programmable gate array partition implementing the data input module is less than a second threshold.

[0017] In the above scheme, the distance between the field-programmable gate array partition implementing the message filling module and the field-programmable gate array partition implementing the data packet module is less than the first threshold.

[0018] In the above scheme, the data grouping module and message filling module process the data to be processed to obtain first data, and transmit the first data to the iterative calculation module, including:

[0019] In response to the activation of the data input module, data grouping module, and message filling module based on the first signal, the data input module receives the data to be processed.

[0020] The data input module transmits the data to be processed to the data grouping module, so that the data grouping module groups the data to be processed to obtain grouped data;

[0021] The data grouping data is input into the message filling module to obtain the first data;

[0022] The message block size of the first data is consistent with the processing size of the iterative calculation module.

[0023] In the above scheme, the first sub-function is used to perform an XOR operation on the bits of two adjacent columns of any bit, and then perform an XOR operation with the arbitrary bit.

[0024] The second sub-function is used to perform a cyclic shift operation on the channel;

[0025] The third sub-function is used to perform a transposition operation on the slice corresponding to the first data.

[0026] The fourth sub-function is used to perform bit combination operations on the rows in the first data;

[0027] The fifth sub-function is used to modify at least one bit in the channel.

[0028] In the above scheme, the first sub-function corresponds to at least two registers; the at least two registers store the data that the first sub-function needs to process, and the data stored in the at least two registers corresponding to the first sub-function is the same;

[0029] Based on the distance between the at least two registers and at least one input port corresponding to the first sub-function, a strategy is determined for the at least two registers to input data to at least one input port corresponding to the first sub-function.

[0030] In the above scheme, the second sub-function corresponds to at least two registers; the at least two registers store the data output by the second sub-function, and the data stored in the at least two registers corresponding to the second sub-function is the same;

[0031] Based on the distance between the at least two registers and at least one input port corresponding to the third sub-function, a strategy is determined for the at least two registers to input data to at least one input port corresponding to the third sub-function.

[0032] In the above scheme, the third sub-function corresponds to at least two registers; the at least two registers store the data output by the third sub-function, and the data stored in the at least two registers corresponding to the third sub-function is the same;

[0033] Based on the distance between the at least two registers and at least one input port corresponding to the fourth sub-function, a strategy is determined for the at least two registers to input data to at least one input port corresponding to the fourth sub-function.

[0034] In the above scheme, the fifth sub-function modifies at least one bit in the channel respectively, and transmits the modification results to the aggregation module based on the buffer respectively;

[0035] The summarization module summarizes the modification results of at least one bit buffered by the buffer and the data output by the fourth sub-function, and uses the summarization result as the input of the first sub-function in the next round of iteration calculation.

[0036] In the above scheme, if the current iteration calculation round is the last round, then at least two registers corresponding to the first sub-function are not configured, and the final result of the iteration calculation module is directly output;

[0037] Alternatively, if the current iteration is not the last iteration, then at least two registers are configured for the first sub-function, and the processing result of the fifth sub-function and the output of the fourth sub-function are stored in the at least two registers.

[0038] In the above scheme, based on performance requirement information and / or field-programmable gate array (FPGA) resource information, at least one FPGA partition for implementing the iterative computing module is determined;

[0039] If the iterative calculation module is implemented based on two field-programmable gate array (FPGA) partitions, then the two FPGA partitions are adjacent.

[0040] The method in the above scheme further includes:

[0041] In response to the iterative calculation module implemented based on two field-programmable gate array partitions, the data output by the fifth sub-function is buffered based on a global clock buffer, and all buffered data is summarized as the input of the first sub-function in the next round of iterative calculation.

[0042] The method in the above scheme further includes:

[0043] In response to the iterative calculation module being implemented based on a field-programmable gate array partition, the data output by the fifth sub-function is buffered based on a global clock buffer or a regional clock buffer, and all buffered data is summarized as the input of the first sub-function for the next round of iterative calculation.

[0044] In the above scheme, the step of performing iterative calculations on the first data based on the various sub-functions included in the first function of the iterative calculation module to obtain the output result corresponding to the data to be processed includes:

[0045] The first data is stored in at least two registers corresponding to the first sub-function, and the first data is transmitted to the first sub-function based on the strategy of inputting data to at least one input port corresponding to the first sub-function using the at least two registers.

[0046] The first sub-function processes the first data and transmits the processing result to the second sub-function. After processing by the second sub-function, the result is transmitted to at least two registers corresponding to the second sub-function.

[0047] At least two registers corresponding to the second sub-function will transfer the stored data to the third sub-function according to a strategy.

[0048] The third sub-function processes the received data and transmits the processing result to at least two registers corresponding to the third sub-function. The at least two registers corresponding to the third sub-function then transmit the stored data to the fourth sub-function according to a strategy.

[0049] The fourth sub-function will process the received data and transmit the processing result to the fifth sub-function;

[0050] The fifth sub-function modifies at least one bit of the received data and transmits the modification results to the aggregation module based on the buffer.

[0051] The summarization module summarizes the modification results of at least one bit buffered by the buffer and the data output by the fourth sub-function, and uses the summary result as the input of the first sub-function in the next round of iteration calculation.

[0052] According to a second aspect of this disclosure, a data processing apparatus is provided, the data processing apparatus comprising a data processing unit and a buffering unit, wherein each module of the data processing unit is implemented based on at least one partition of a field-programmable gate array, and the data processing unit includes at least a data grouping module, a message filling module, and an iterative calculation module; the apparatus includes:

[0053] A buffering device is used to buffer the input valid signal based on the global clock buffer corresponding to the field programmable gate array to obtain a first signal, and transmit the first signal to each module of the data processing device so that each module of the data processing device starts up based on the first signal in a first time interval.

[0054] The data grouping module and message filling module are used to process the data to be processed, obtain the first data, and transmit the first data to the iterative calculation module;

[0055] The iterative calculation module is used to perform iterative calculations on the first data based on the various sub-functions included in the first function, so as to obtain the output result corresponding to the data to be processed;

[0056] The first function includes a first sub-function, a second sub-function, a third sub-function, a fourth sub-function, and a fifth sub-function; the first sub-function, the second sub-function, and the third sub-function are each configured with at least two registers; the registers are used to store data input to the corresponding sub-function or data output by the corresponding sub-function, so that the data input to the corresponding sub-function is input to the corresponding sub-function via the shortest path.

[0057] According to a third aspect of this disclosure, an electronic device is provided, comprising:

[0058] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods of this disclosure.

[0059] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions for causing the computer to perform the methods described in this disclosure.

[0060] According to a fifth aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the methods described in this disclosure.

[0061] The data processing method disclosed herein buffers the input valid signal based on the global clock buffer corresponding to the field-programmable gate array (FPGA) to obtain a first signal. This first signal is then transmitted to each module of the data processing device, causing each module to start within a first time interval based on the first signal. The data to be processed is processed by the data grouping module and the message filling module to obtain first data, which is then transmitted to the iterative calculation module. The first data is iteratively processed by the sub-functions included in the first function of the iterative calculation module to obtain the output result corresponding to the data to be processed. The first function includes a first sub-function, a second sub-function, a third sub-function, a fourth sub-function, and a fifth sub-function. Each of the first, second, and third sub-functions is configured with at least two registers. These registers are used to store data input to or output from the corresponding sub-function, ensuring that data input to the corresponding sub-function is received via the shortest path. In this way, the path of the valid input signal is optimized by a global clock buffer, enabling it to be quickly transmitted to each module of the data processing device. At the same time, registers are added to each sub-function of the KECCAK-f function in the iterative operation processing module, so that the data transmission path between the sub-functions is not unique, reducing wiring congestion, optimizing timing paths, and improving operating frequency and computing performance.

[0062] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0063] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. Several embodiments of this disclosure are illustrated in the drawings by way of example and not limitation, in which:

[0064] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0065] Figure 1 This diagram illustrates the state array and its structure in related technologies.

[0066] Figure 2 The coordinate system of the state array is shown;

[0067] Figure 3 A schematic diagram of a first optional flow of the data processing method provided in this embodiment of the present disclosure is shown;

[0068] Figure 4 This diagram illustrates the FPGA logic resource partitioning and placement / routing.

[0069] Figure 5 This diagram illustrates the principle of setting logic fan-out values ​​and register replication optimization layout routing provided in an embodiment of this disclosure.

[0070] Figure 6 A schematic diagram of a first optional flow of the data processing method provided in this embodiment of the present disclosure is shown;

[0071] Figure 7 A schematic diagram of a second optional flow of the data processing method provided in an embodiment of this disclosure is shown;

[0072] Figure 8 This illustration shows a schematic diagram of FPGA placement and routing provided in an embodiment of this disclosure;

[0073] Figure 9 A schematic diagram of the structure of the first function provided in an embodiment of this disclosure is shown;

[0074] Figure 10 A schematic diagram of a third optional flow of the data processing method provided in this embodiment of the present disclosure is shown;

[0075] Figure 11 A schematic diagram of an optional structure of the data processing apparatus provided in an embodiment of this disclosure is shown;

[0076] Figure 12 A schematic diagram of the composition structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0077] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0078] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0079] In the following description, the terms "first" and "second" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first" and "second" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0080] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0081] It should be understood that in the various embodiments of this disclosure, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0082] The SHA-3 series consists of four cryptographic hash functions (SHA3-224, SHA3-256, SHA3-384, and SHA3-512) and two extensible output functions (SHAKE-128 and SHAKE-256). Unlike the cryptographic hash functions, SHAKE-128 and SHAKE-256 have a crucial characteristic: they can extend messages to arbitrary lengths. This property has wide applications in global hashing, random hashing, stream encryption, and message authentication.

[0083] Figure 1 This diagram illustrates the state array and its structure in related technologies. Figure 2 The coordinate system of the state array is shown.

[0084] Combination Figure 1 and Figure 2 The SHA-3 algorithm, during internal processing (especially the calculation of the F function), uses a state array composed of multidimensional arrays. Taking 1600 bits of input data as an example, the state array can be interpreted along the x, y, and z axes, and can be three-dimensional data of size 5×5×64. In the state array, the 5×64 matrix in the x0z plane is a plane, the 5×5 matrix in the x0y plane is a slice, the 5×64 matrix in the y0z plane is a sheet, the 1×5 vector in the x-axis direction is a row, the 5×1 vector in the y-axis direction is a column, and the 1×64 vector in the z-axis direction is a lane. Each element in the three-dimensional matrix is ​​1 bit.

[0085] FPGA is a highly flexible programmable logic device widely used in electronic design and development. The Global Clock Buffer (BUFG) is the most important clock buffer in an FPGA, driving the FPGA's global clock network and covering all timing resources of the entire chip. The Regional Clock Buffer (BUFR) is a regional clock buffer that can only drive logic resources within the current clock partition.

[0086] When the SHA3 algorithm is implemented on FPGA and ASIC platforms, the complex algorithm principle and operation process (involving permutation, shifting, linear and nonlinear operations of large bit-width data and multidimensional arrays) result in excessively long timing paths and congested placement and routing, ultimately leading to low algorithm running frequency and low computing power.

[0087] In related technologies, by inserting pipelines into the algorithm kernel operation process, complex calculations are completed over multiple clock cycles, thereby improving the operating frequency and computing power.

[0088] However, adding multi-stage pipelines generates a large number of registers, consumes significant hardware resources, and complicates the design. Furthermore, while multi-stage pipelines increase the operating frequency, they consume more clock cycles, resulting in relatively low final performance. Computational performance is positively correlated with frequency and negatively correlated with the number of clock cycles.

[0089] Based on the deficiencies in related technologies, this disclosure provides a data processing method that, by configuring the multidimensional array in the KECCAK-f function as a multi-register group, optimizing the critical path in the iota step using a clock buffer, and optimizing the input valid signal (data_val signal) using a clock buffer, reduces wiring congestion, optimizes timing paths, and improves operating frequency and computing performance.

[0090] Figure 3 A schematic diagram of a first alternative flow of the data processing method provided in this disclosure embodiment is shown, and the steps will be described accordingly.

[0091] In some embodiments, the present disclosure is intended to process data that needs to be compressed, verified, or computed using the SHA3 algorithm.

[0092] The input data to be compressed / verified is the raw data for SHA3 algorithm calculation. In a SOC chip, the SHA3 operation unit is generally a unit mounted on the system bus or a dedicated bus, used to obtain data from the FPGA's I / O pad port, CPU, or large-capacity memory (such as SDRAM, FLASH, etc.). The data bit width of the bus interface is generally 32 bits or 64 bits. When performing SHA3 algorithm calculation, data of length r is input each time (r can be one of 1152, 1088, 832, 576, or 1344). Therefore, after the data is input, it is necessary to first group the data.

[0093] The data grouping module is used to convert the 64-bit or 32-bit data input from the previous stage into data of length r.

[0094] After grouping the data, it is necessary to add 1 bit of 1, several bits of 0, and 1 bit of 1 to ensure that the total length of the input data and the added data is an integer multiple of r. The specific method of padding varies depending on the length of the input data. At the same time, this step is for processing large bit width (1152, 1088, 832, 576, 1344 bits) data, which has a high timing delay and consumes a lot of hardware resources.

[0095] The data after message filling is output to the iterative calculation module according to the read / write timing requirements of the subsequent stage.

[0096] The iterative calculation module uses multiple rounds of the F function (i.e., the KECCAK-f function) to iteratively compress the data, obtain the calculation results, and output the calculation results to the bus or the next-level module.

[0097] In some embodiments, the data grouping module, message filling module, and iterative calculation module are implemented based on FPGA.

[0098] Figure 4A schematic diagram of FPGA logic resource partitioning and layout routing is shown.

[0099] like Figure 4 The FPGA logic resources shown are divided into 16 partitions, with one or two partitions supporting the operation of a module.

[0100] FPGA logic resource partitioning and placement / routing, such as Figure 4 As shown, FPGAs are semi-custom devices, meaning they offer high flexibility but also have certain limitations. They are generally divided into multiple partitions of approximately the same size, such as... Figure 4 The 1-16 partitions are marked on the diagram. The number of partitions varies depending on the FPGA specifications, and the amount of hardware resources allocated to each partition also differs. Generally, (for ordinary signals) the signal transmission delay within the same partition is less than the signal transmission delay across partitions. The wire delay of signal transmission is positively correlated with the physical location of the partitions. That is, the greater the physical distance between two partitions, the greater the wire delay of signal transmission between them, the worse the timing, and the lower the computing performance.

[0101] Besides ordinary signals, clock buffer resources can also be used in FPGAs. Commonly used ones include BUFG and BUFR. Clock buffer resources were originally used to drive clocks. In digital circuits, almost all signals are driven by clocks, so the fan-out of clock signals is the largest. Therefore, dedicated routing is needed to ensure that the delay of clock signals reaching different modules is as consistent and as small as possible. In practical applications, they can also be used to optimize the layout and routing of ordinary signals to optimize timing. However, clock buffer resources are limited in FPGAs (they need to be specially designed during FPGA chip design, and the cost is very high). For example, a certain series of FPGAs only has 32 BUFG resources. Therefore, how to achieve the best timing optimization effect using limited clock buffer resources is one of the key innovations of this disclosure. The BUFG used in this disclosure can drive the FPGA global clock network and can cover all timing resources of the entire chip. That is, it can be considered that the transmission delay is very small when reaching any position on the chip. BUFR is a partitioned clock buffer, which can only drive the current clock partition (e.g., ...). Figure 4 The logical resources of the 1-16 partitions on the FPGA chip can be considered to have very low transmission latency when reaching any position within a unified partition.

[0102] Figure 5 This illustration shows a schematic diagram of the setting logic fan-out value and register copy optimization layout and routing principle provided in an embodiment of this disclosure.

[0103] like Figure 5As shown, the two dashed boxes represent two sets of data for logical operations. In the SHA3 algorithm, the basic unit of computation is the lane, so "lane" is also used to represent the data to be processed. The result of the logical operation on the two sets of data is A. By limiting the logic fan-out value (3 in this example) and copying registers, the output register A is copied into three sets: A1, A2, and A3. The values ​​in the three sets of registers are exactly the same, but their positions differ, being close to the units (or sub-functions) that will be processed later. Through this processing, path ① replaces the dashed path ②, and path ③ replaces the dashed path ④, thus reducing signal transmission line delay and optimizing timing. This method can be applied to both FPGAs and ASIC chips, which will be explained in detail later.

[0104] Figure 6 A schematic diagram of a first alternative flow of the data processing method provided in this disclosure embodiment is shown, and the steps will be described accordingly.

[0105] Step S101: Buffer the input valid signal based on the global clock buffer corresponding to the field programmable gate array to obtain a first signal, and transmit the first signal to each module of the data processing device.

[0106] In some embodiments, the apparatus for compressing or calculating the data to be processed is a data processing apparatus, which includes at least a data grouping module, a message filling module, and an iterative calculation module, wherein each module of the data processing apparatus is implemented based on at least one partition of a field-programmable gate array.

[0107] In some embodiments, the data to be processed is first transmitted to the FPGA. After determining that the data to be processed is valid, an input valid signal is generated. The input valid signal is buffered based on the BUFG corresponding to the FPGA to obtain a first signal. The first signal is transmitted to any partition of the FPGA through the global clock network, so that the module that implements the function based on the partition of the FPGA can receive the first signal and start within the first time interval.

[0108] The valid input signal includes a signal generated by the FPGA after receiving the data to be processed and confirming that the data to be processed is valid. The FPGA-implemented data processing device can compress or calculate the data to be processed. This signal is used to start the various modules included in the data processing device so that each module processes the data to be processed in a logical order after starting.

[0109] In some embodiments, the first time interval can be any preset time interval, that is, the modules included in the data processing device can be started within a similar time period based on the first signal.

[0110] Step S102: The data to be processed is processed based on the data grouping module and the message filling module to obtain the first data, and the first data is transmitted to the iterative calculation module.

[0111] In some embodiments, the data grouping module and the message filling module are activated based on a first signal.

[0112] In some embodiments, if the data to be processed is transmitted to the FPGA via a bus, since the data width of the bus interface is usually 32 bits or 64 bits, and the length of the data input each time during the SHA3 algorithm operation is one of 1152, 1088, 832, 576, or 1344, after receiving the data to be processed, the data to be processed is first grouped based on the data grouping module to make its length conform to the requirements of the SHA3 algorithm.

[0113] In some embodiments, after the data grouping module groups the input data, the message filling module fills the grouped data by adding 1 bit of 1, several bits of 0, and 1 bit of 1, so that the length of the grouped data is an integer multiple that meets the requirements of the SHA3 algorithm; the output of the message filling module is the first data.

[0114] Step S103: Based on the various sub-functions included in the first function of the iterative calculation module, perform iterative calculation on the first data to obtain the output result corresponding to the data to be processed.

[0115] In some embodiments, the first function includes a first sub-function, a second sub-function, a third sub-function, a fourth sub-function, and a fifth sub-function; the first sub-function, the second sub-function, and the third sub-function are each configured with at least two registers; the registers are used to store data input to the corresponding sub-function or data output by the corresponding sub-function, so that the data input to the corresponding sub-function is input to the corresponding sub-function via the shortest path.

[0116] In some embodiments, the first data is input to the iterative calculation module, and the first data is iteratively processed based on the order and logic between the sub-functions included in the first function to obtain the output result corresponding to the data to be processed.

[0117] Thus, the data processing method provided in this embodiment optimizes the path of the input valid signal through a global clock buffer, enabling it to be quickly transmitted to each module of the data processing device; at the same time, registers are added to each sub-function included in the KECCAK-f function in the iterative operation processing module, so that the data transmission path between each sub-function is not unique, reducing wiring congestion, optimizing timing paths, and improving operating frequency and computing performance.

[0118] Figure 7A second alternative flowchart of the data processing method provided in this disclosure embodiment is shown, and will be described according to each step.

[0119] Step S201: Determine the FPGA partitions for each module of the data processing device.

[0120] In some embodiments, the data processing apparatus includes a data input module, a data grouping module, a message filling module, and an iterative calculation module.

[0121] In some embodiments, based on the source of the data to be processed, a field-programmable gate array (FPGA) partition for implementing the data input module of the data processing apparatus is determined, such that the distance between the data input module and the partition in the FPGA that receives the data to be processed is less than a first threshold.

[0122] In specific implementation, in response to the input of data to be processed from the first port of the field-programmable gate array (FPGA), it is determined that the distance between the FPGA partition implementing the data input module and the FPGA partition implementing the input is less than a first threshold.

[0123] Alternatively, in specific implementations, if the data to be processed is obtained from the bus or memory, there is no need to constrain the position of the FPGA partition of the data input module.

[0124] The first port includes an IO PAD port. If data is input to the FPGA from the first port, the partitions corresponding to the data input module and the data grouping module are constrained to the partitions closest to the first port. That is, the distance between the FPGA partition of the data input module and the partition in the FPGA that implements the input (or the partition where the first port is located) is less than a first threshold. The distance between two regions includes the number of regions separated by the two regions; if the two regions are vertically or horizontally adjacent, the number of regions is 0; if the two regions are not vertically or horizontally adjacent, the number of regions is the number of regions that need to be traversed in the shortest path from one region to another. In some optional embodiments, the first threshold can be a positive integer; if the first threshold is 1, it indicates that the partition implementing the data input module is adjacent to the partition where the first port is located.

[0125] In some embodiments, it is determined that the data packet module and the data input module are implemented by the same field-programmable gate array (FPGA) partition; or, it is determined that the distance between the FPGA partition implementing the data packet module and the FPGA partition implementing the data input module is less than a second threshold. The second threshold can be 0, that is, the FPGA partition of the data packet module and the FPGA partition of the data input module are adjacent.

[0126] In some embodiments, the distance between the field-programmable gate array partition implementing the message filling module and the field-programmable gate array partition implementing the data packet module is less than a first threshold.

[0127] In some embodiments, at least one field-programmable gate array (FPGA) partition for implementing the iterative computing module is determined based on performance requirement information and / or FPGA resource information; wherein, if the iterative computing module is implemented based on two FPGA partitions, the two FPGA partitions are adjacent.

[0128] In practical implementation, if the performance requirement information representation requires low latency, the iterative calculation module is set up in one FPGA partition; if the performance requirement information representation requires high reliability, the iterative calculation module is set up in two FPGA partitions. If the remaining resources of the FPGA resource information representation are sufficient, the iterative calculation module is set up in two FPGA partitions; if the remaining resources of the FPGA resource information representation are insufficient, the iterative calculation module is set up in one FPGA partition. Optionally, the data processing device further includes a result output module, used to summarize the intermediate results of the first function output of the iterative calculation module for the next iteration, or to receive the final result of the first function output of the iterative calculation module.

[0129] Figure 8 A schematic diagram of FPGA placement and routing provided in an embodiment of this disclosure is shown.

[0130] like Figure 8 As shown, the data input module and the data grouping module are set in the same partition (i.e., partition 3), the message filling module is set in the partition adjacent to the partition of the data grouping module (i.e., partition 7), and the iterative calculation module is set in partitions 10 and 11; wherein partition 11 is adjacent to partition 7, so that the data output by the message filling module is transmitted to the iterative calculation module via the shortest path.

[0131] Step S202: Buffer the input valid signal based on the global clock buffer corresponding to the field programmable gate array to obtain a first signal, and transmit the first signal to each module of the data processing device.

[0132] In some embodiments, the data to be processed is first transmitted to the FPGA. After determining that the data to be processed is valid, an input valid signal is generated. The input valid signal is buffered based on the BUFG corresponding to the FPGA to obtain a first signal. The first signal is transmitted to any partition of the FPGA through the global clock network, so that the module that implements the function based on the partition of the FPGA can receive the first signal and start within the first time interval.

[0133] like Figure 8As shown, the input valid signal (Data_val) is buffered by the BUFG, and the buffered signal is transmitted to the corresponding modules of each partition of the FPGA through the global clock network.

[0134] The valid input signal includes a signal generated by the FPGA after receiving the data to be processed and confirming that the data to be processed is valid. The FPGA-implemented data processing device can compress or calculate the data to be processed. This signal is used to start the various modules included in the data processing device so that each module processes the data to be processed in a logical order after starting.

[0135] Step S203: The data to be processed is processed based on the data grouping module and the message filling module to obtain the first data.

[0136] In some embodiments, in response to the activation of the data input module, data grouping module, and message filling module based on a first signal, the data input module receives data to be processed; the data input module transmits the data to be processed to the data grouping module, so that the data grouping module groups the data to be processed to obtain grouped data; the grouped data is input to the message filling module to obtain first data; and the first data is transmitted to the iterative calculation module. The message block size of the first data conforms to the processing size of the iterative calculation module.

[0137] Step S204: Based on the various sub-functions included in the first function of the iterative calculation module, perform iterative calculation on the first data to obtain the output result corresponding to the data to be processed.

[0138] In some embodiments, the first function (KECCAK-f function) includes a first subfunction, a second subfunction, a third subfunction, a fourth subfunction, and a fifth subfunction.

[0139] Figure 9 A schematic diagram of the structure of the first function provided in an embodiment of this disclosure is shown.

[0140] like Figure 9 As shown, the first function includes the first sub-function (theta), the second sub-function (rho), the third sub-function (pi), the fourth sub-function (chi), and the fifth sub-function (iota).

[0141] The first sub-function is used to perform an XOR operation on the bits of any two adjacent columns of a bit, and then perform an XOR operation on the arbitrary bit. Taking 1600-bit data as an example, when it is input to the first function, the data to be processed is a 5×5×64 state array. The first sub-function is used to XOR the five bits of each of the two columns surrounding a certain bit, and then XOR it on the bit. The second sub-function is used to perform a cyclic shift operation on the channel. The second sub-function is used to perform a cyclic shift operation on 25 lanes. The third sub-function is used to perform a transposition operation on the slice corresponding to the first data. The third sub-function is used to perform a fixed transposition on the slice. The fourth sub-function is used to perform a bit combination operation on the rows in the first data. The fourth sub-function is used to perform a bit combination operation on the row. The fifth sub-function is used to modify at least one bit in the channel. The fifth sub-function is used to modify some bits of Lane(0,0), while other data remains unchanged.

[0142] The first function may also include a summary module for obtaining the output results of the fifth and fourth sub-functions.

[0143] In some embodiments, the first sub-function corresponds to at least two registers (e.g. Figure 9 As shown, there are three registers: Input_data1, Input_data2, and Input_data3. At least two registers store data that the first sub-function needs to process. In the first iteration, Input_data1, Input_data2, and Input_data3 store data transmitted from the message filling module to the first function. In iterations 2 to 24, Input_data1, Input_data2, and Input_data3 store data output after the previous iteration. The data stored in the at least two registers corresponding to the first sub-function are the same. Based on the distance between the at least two registers and at least one input port corresponding to the first sub-function, a strategy is determined for the at least two registers to input data to the at least one input port corresponding to the first sub-function. For example, according to the strategy of minimizing delay, the register closest to any input port is determined, and the data stored in that register is transmitted to that input port.

[0144] Optionally, if the current iteration calculation round is the last round, then at least two registers corresponding to the first sub-function are not configured, and the final result of the iteration calculation module is directly output; or, if the current iteration calculation round is not the last round, then at least two registers are configured for the first sub-function, and the processing result of the fifth sub-function and the output of the fourth sub-function are stored in the at least two registers.

[0145] In some embodiments, the second sub-function corresponds to at least two registers (e.g., Figure 9 As shown, there are three registers, namely rho_out1, rho_out2, and rho_out3; the data output by the second sub-function is stored in at least two registers, and the data stored in the at least two registers corresponding to the second sub-function is the same; based on the distance between the at least two registers and at least one input port corresponding to the third sub-function, a strategy is determined for the at least two registers to input data to at least one input port corresponding to the third sub-function.

[0146] In some embodiments, the third sub-function corresponds to at least two registers (e.g. Figure 9 (As shown, there are 3 registers, namely pi_out1, pi_out2, and pi_out3). The data output by the third sub-function is stored in at least two registers, and the data stored in the at least two registers corresponding to the third sub-function is the same. Based on the distance between the at least two registers and at least one input port corresponding to the fourth sub-function, a strategy is determined for the at least two registers to input data to at least one input port corresponding to the fourth sub-function.

[0147] In some embodiments, the fifth sub-function modifies at least one bit in the channel and transmits the modification results to the aggregation module based on the buffer. The aggregation module aggregates the modification results of at least one bit buffered by the buffer and the data output by the fourth sub-function, and uses the aggregated result as the input of the first sub-function in the next round of iteration calculation. The buffer includes BUFG or BUFR.

[0148] In specific implementation, in response to the iterative calculation module implemented based on two field-programmable gate array partitions, the data output by the fifth sub-function is buffered based on a global clock buffer, and all buffered data is summarized as the input of the first sub-function in the next round of iterative calculation.

[0149] Alternatively, in a specific implementation, in response to the iterative calculation module being implemented based on a field-programmable gate array partition, the data output by the fifth sub-function is buffered based on a global clock buffer or a regional clock buffer, and all buffered data is summarized as the input of the first sub-function for the next round of iterative calculation.

[0150] In some embodiments, the first data is stored in at least two registers corresponding to the first sub-function. Based on a strategy of inputting data to at least one input port corresponding to the first sub-function using the at least two registers, the first data is transmitted to the first sub-function. The first sub-function processes the first data and transmits the processing result to the second sub-function. After processing by the second sub-function, the data is transmitted to at least two registers corresponding to the second sub-function. The at least two registers corresponding to the second sub-function transmit the stored data to the third sub-function according to a strategy. The third sub-function processes the received data and transmits the processing result to the at least two registers corresponding to the third sub-function. The at least two registers corresponding to the third sub-function transmit the stored data to the fourth sub-function according to a strategy. The fourth sub-function processes the received data and transmits the processing result to the fifth sub-function. The fifth sub-function modifies at least one bit of the received data and transmits the modification result to the summarization module based on a buffer. The summarization module summarizes the modification result of at least one bit buffered by the buffer and the data output by the fourth sub-function, and uses the summarization result as the input to the first sub-function in the next iteration calculation.

[0151] Thus, the data processing method provided in this embodiment optimizes the path of the input valid signal through a global clock buffer, enabling it to be quickly transmitted to each module of the data processing device; at the same time, registers are added to each sub-function included in the KECCAK-f function in the iterative operation processing module, so that the data transmission path between each sub-function is not unique, reducing wiring congestion, optimizing timing paths, and improving operating frequency and computing performance.

[0152] Figure 10 A third alternative flowchart of the data processing method provided in this disclosure embodiment is shown, and will be described according to each step.

[0153] Step S301: Buffer the input valid signal based on BUFG to obtain the first signal.

[0154] In some embodiments, the valid input signal data_val is connected to the input of any BUFG, and the BUFG transmits data_val to the corresponding partition of the data processing device on the entire chip with minimal delay. Specifically, the BUFG statement can be added to the RTL code: BUFG bufg_inst (.I(data_val), .O(data_val_bufg)).

[0155] Where BUFG bufg_inst indicates that the global clock buffer has been invoked, data_val is the valid input signal, and the signal after being buffered by BUFG is the first signal, i.e., data_val_bufg. I represents the input of the statement, and O represents the output of the statement.

[0156] In some embodiments, the data_val_bufg signal can be transmitted to various modules of the data processing device. Each module of the data processing device depends on the input of valid data; that is, each module only begins calculation when valid data is input. Therefore, a valid signal is required to trigger or start each module.

[0157] Step S302: Constrain the FPGA partitions of each module that implements the data processing device.

[0158] In some embodiments, partition location constraints are added to each module of the data processing device. The constraint addition method is referenced in: INST " / module_name / "LOC = CLB_X2Y3, where CLB_X2Y3 corresponds to Figure 8 The 16 partitions in the FPGA are marked with position coordinates. Different FPGAs use different marking methods, which can be determined by referring to the relevant technical manual. `module_name` represents the name of each module in the data processing device.

[0159] In practice, if the data to be processed is input from the FPGA's IO PAD port, the data input module and data grouping module are constrained to the partition close to the chip's input IO; if the data to be processed is obtained from the bus or memory, no positional constraints are required, and the software will arrange them automatically.

[0160] In practice, multiple first functions (F functions) can be set in one or two adjacent regions according to the design performance requirements and the internal resources of the FPGA.

[0161] Step S303: Perform timing optimization within and between the first functions.

[0162] In some embodiments, the iterative calculation module is implemented based on at least one first function, such as Figure 8 As shown, the iterative calculation module is implemented based on partition 10 and partition 11, which involves four first functions.

[0163] In some embodiments, the first function can be divided into 5 sub-functions, which are functions specified by the standard protocol. The input and output are both 1600-bit data. During internal processing, the three-dimensional data set is calculated according to its function.

[0164] The first sub-function theta() represents the process of XORing the five bits of each of the two columns surrounding a given bit, and then XORing it with that bit.

[0165] The second sub-function rho() is used to perform cyclic shifting on the 25 lanes.

[0166] The third sub-function pi() is used to perform fixed transposition on the Slice.

[0167] The fourth sub-function, chi(), is used to perform bit combination on row.

[0168] The fifth subfunction, iota(), is used to modify certain bits of Lane(0,0), while other data remains unchanged.

[0169] Specifically, the fifth sub-function performs an XOR operation on bits 0, 1, 3, 7, 15, 31, and 63. RC is the round constant, which is related to the iteration rounds of the F function. SHA3 performs 24 rounds of iterative compression of each data set using the F function.

[0170] chi_out_lane(0,0)[0] ⊕RC(0) = iota_out_lane(0,0)[0]

[0171] chi_out_lane(0,0)[1] ⊕RC(1) = iota_out_lane(0,0)[1]

[0172] chi_out_lane(0,0)[3] ⊕RC(3) = iota_out_lane(0,0)[3]

[0173] chi_out_lane(0,0)[7] ⊕RC(7) = iota_out_lane(0,0)[7]

[0174] chi_out_lane(0,0)

[15] ⊕RC(15) = iota_out_lane(0,0)

[15]

[0175] chi_out_lane(0,0)

[31] ⊕RC(31) = iota_out_lane(0,0)

[31]

[0176] chi_out_lane(0,0)

[63] ⊕RC(63) = iota_out_lane(0,0)

[63]

[0177] In some embodiments, key timing paths are identified by analyzing different sub-functions, and constraints are added to these key timing paths.

[0178] The internal calculation process of Theta involves multiple sets of XOR operations on various parameters, resulting in high computational complexity. During data input, for the first round of F-function calculation, it is "configured" (by adding constraints or implementing through RTL code) to become the same three sets of registers (i.e., input_data1, input_data2, and input_data3). For rounds 2-24 of F-function calculation, input_data also consists of the same three sets, but this is achieved by configuring the output_data of the previous round of F-function. This reduces the placement and routing congestion of Theta and lowers its timing latency. The F-function is an iterative calculation, with the output_data of the previous iteration serving as the input_data of the next iteration.

[0179] The internal calculation process of pi involves multiple fixed transpositions (replacements) of slices, resulting in very high wiring delays and heavy placement and routing pressure. Therefore, during data input, it is "configured" to be converted into the same three sets of registers (i.e., rho_out1, rho_out2, and rho_out3). Since the input signal of pi is the output signal of rho, the output signal of rho can be directly "configured". During pi operation, the placement and routing congestion of pi can be reduced, and the timing delay of pi can be reduced.

[0180] The internal calculation process of chi involves bit XOR operations and combinations within row, resulting in high interconnection latency and high placement and routing pressure. Therefore, during data input, it is configured to be converted into the same three sets of registers (i.e., pi_out1, pi_out2, pi_out3) for input. Since the input signal of chi is the output signal of pi, the output signal of pi can be directly configured. During chi operation, the placement and routing congestion of chi can be reduced, and the timing delay of pi can be reduced.

[0181] For 1600 bits of data, only 7 bits are processed in the iota step, while the other data bits remain unchanged. Therefore, these 7 bits have the largest timing delay and are the critical path. It is necessary to prioritize reducing the delay of outputting these 7 bits to the next module or sub-function. Specifically, each of these bits iota_out_lane(0,0)[0,1,3,7,15,31,63] uses a BUFG or BUFR buffer. After being output through the buffer, they are gathered with other bit data (unprocessed, i.e., directly output via chi, passing through the bypass unit in the attached diagram) in the Gather unit. Then, based on the current iteration round, it is determined whether to "configure" them with the same 3 sets of registers. If the current iteration is the last of 24 iterations of compression, no "configuration" is performed, and the value is directly output to the next level module. Otherwise, they need to be "configured" with 3 sets of registers as the input value (Input_data) for the next round of F function calculation.

[0182] The buffer is determined based on the partition corresponding to the iterative calculation module, such as Figure 8 As shown, if all F functions are set in one partition (partition 11, which uses 2 hardware F function units to implement iterative calculations and outputs through path ②), then either BUFG or BUFR can be selected; if all F functions are set in adjacent partitions (partitions 10 and 11, which use 4 hardware F function units to implement iterative calculations and outputs through path ①), then the F functions that transmit signals across partitions must use BUFG, such as the F function in partition 11, while other functions can use either BUFG or BUFR.

[0183] The above "configuration" process can be implemented in two ways during the design phase, both of which are applicable to FPGA chips and ASIC chips. One approach is through constraints, which involves adding fan-out constraints and register replication constraints to the corresponding signal or data groups; the other approach is through RTL code design, which involves directly generating multiple identical sets of logic and registers through code.

[0184] Step S304: Based on the various sub-functions included in the first function of the iterative calculation module, perform iterative calculation processing on the first data to obtain the output result corresponding to the data to be processed.

[0185] The specific steps of step S304 are the same as those of step S103 or step S204, and will not be repeated here.

[0186] Thus, the data processing method provided in this embodiment optimizes the path of the input valid signal through a global clock buffer, enabling it to be quickly transmitted to each module of the data processing device; at the same time, registers are added to each sub-function included in the KECCAK-f function in the iterative operation processing module, so that the data transmission path between each sub-function is not unique, reducing wiring congestion, optimizing timing paths, and improving operating frequency and computing performance.

[0187] Figure 11 A schematic diagram of an optional structure of a data processing apparatus provided in an embodiment of this disclosure is shown, and the details will be described in terms of each part.

[0188] In some embodiments, the data processing device includes a data processing apparatus and a buffering apparatus; each module of the data processing apparatus is implemented based on at least one partition of a field-programmable gate array, and the data processing apparatus includes at least a data packetization module, a message filling module, and an iterative calculation module; the buffering apparatus includes a global clock buffer and / or a regional clock buffer.

[0189] A buffering device is used to buffer the input valid signal based on the global clock buffer corresponding to the field programmable gate array to obtain a first signal, and transmit the first signal to each module of the data processing device so that each module of the data processing device starts up based on the first signal in a first time interval.

[0190] The data grouping module and message filling module are used to process the data to be processed, obtain the first data, and transmit the first data to the iterative calculation module;

[0191] The iterative calculation module is used to perform iterative calculations on the first data based on the various sub-functions included in the first function, so as to obtain the output result corresponding to the data to be processed;

[0192] The first function includes a first sub-function, a second sub-function, a third sub-function, a fourth sub-function, and a fifth sub-function; the first sub-function, the second sub-function, and the third sub-function are each configured with at least two registers; the registers are used to store data input to the corresponding sub-function or data output by the corresponding sub-function, so that the data input to the corresponding sub-function is input to the corresponding sub-function via the shortest path.

[0193] In the above scheme, the data processing device may further include a layout and wiring device.

[0194] The layout and wiring device is used to determine the field-programmable gate array (FPGA) partition for implementing the data input module of the data processing device based on the source of the data to be processed, such that the distance between the data input module and the partition in the FPGA that receives the data to be processed is less than a first threshold.

[0195] The layout and routing device is specifically used to determine, in response to the input of data to be processed from the first port of the field-programmable gate array (FPGA), that the distance between the FPGA partition implementing the data input module and the FPGA partition implementing the input is less than a first threshold.

[0196] The layout and wiring device is used to determine that the data grouping module and the data input module are implemented by the same field-programmable gate array partition;

[0197] Alternatively, determine that the distance between the field-programmable gate array partition implementing the data grouping module and the field-programmable gate array partition implementing the data input module is less than a second threshold.

[0198] The layout and routing device is used to determine that the distance between the field-programmable gate array partition implementing the message filling module and the field-programmable gate array partition implementing the data packet module is less than a first threshold.

[0199] In some embodiments, in response to the activation of the data input module, the data grouping module, and the message filling module based on a first signal, the data input module receives the data to be processed.

[0200] The data input module transmits the data to be processed to the data grouping module, so that the data grouping module groups the data to be processed to obtain grouped data;

[0201] The data grouping data is input into the message filling module to obtain the first data;

[0202] The message block size of the first data is consistent with the processing size of the iterative calculation module.

[0203] In some embodiments, the first sub-function is used to perform an XOR operation on the bits of two adjacent columns of any bit, and then perform an XOR operation with the arbitrary bit.

[0204] The second sub-function is used to perform a cyclic shift operation on the channel;

[0205] The third sub-function is used to perform a transposition operation on the slice corresponding to the first data.

[0206] The fourth sub-function is used to perform bit combination operations on the rows in the first data;

[0207] The fifth sub-function is used to modify at least one bit in the channel.

[0208] In some embodiments, the first sub-function corresponds to at least two registers; the at least two registers store data that needs to be processed by the first sub-function, and the data stored in the at least two registers corresponding to the first sub-function is the same;

[0209] Based on the distance between the at least two registers and at least one input port corresponding to the first sub-function, a strategy is determined for the at least two registers to input data to at least one input port corresponding to the first sub-function.

[0210] In some embodiments, the second sub-function corresponds to at least two registers; the at least two registers store the data output by the second sub-function, and the data stored in the at least two registers corresponding to the second sub-function is the same;

[0211] Based on the distance between the at least two registers and at least one input port corresponding to the third sub-function, a strategy is determined for the at least two registers to input data to at least one input port corresponding to the third sub-function.

[0212] In some embodiments, the third sub-function corresponds to at least two registers; the at least two registers store the data output by the third sub-function, and the data stored in the at least two registers corresponding to the third sub-function is the same;

[0213] Based on the distance between the at least two registers and at least one input port corresponding to the fourth sub-function, a strategy is determined for the at least two registers to input data to at least one input port corresponding to the fourth sub-function.

[0214] In some embodiments, the fifth sub-function modifies at least one bit in the channel respectively, and transmits the modification results to the aggregation module based on the buffer respectively;

[0215] The summarization module summarizes the modification results of at least one bit buffered by the buffer and the data output by the fourth sub-function, and uses the summary result as the input of the first sub-function in the next round of iteration calculation.

[0216] In some embodiments, if the current iteration is the last iteration, then at least two registers corresponding to the first sub-function are not configured, and the final result of the iteration calculation module is directly output.

[0217] Alternatively, if the current iteration is not the last iteration, then at least two registers are configured for the first sub-function, and the processing result of the fifth sub-function and the output of the fourth sub-function are stored in the at least two registers.

[0218] In some embodiments, at least one field-programmable gate array (FPGA) partition for implementing the iterative computing module is determined based on performance requirement information and / or FPGA resource information.

[0219] If the iterative calculation module is implemented based on two field-programmable gate array (FPGA) partitions, then the two FPGA partitions are adjacent.

[0220] The layout and routing device is also used to respond to the iterative calculation module implemented based on two field-programmable gate array partitions, by buffering the data output of the fifth sub-function based on a global clock buffer, summarizing all buffered data, and using it as the input of the first sub-function in the next round of iterative calculation.

[0221] The layout and routing device is also used to respond to the iterative calculation module implemented based on a field-programmable gate array partition, by buffering the data output of the fifth sub-function based on a global clock buffer or a regional clock buffer, summarizing all buffered data, and using it as the input of the first sub-function in the next round of iterative calculation.

[0222] The data processing device is specifically used to store the first data into at least two registers corresponding to the first sub-function, and to transmit the first data to the first sub-function based on a strategy of inputting data to at least one input port corresponding to the first sub-function using the at least two registers.

[0223] The first sub-function processes the first data and transmits the processing result to the second sub-function. After processing by the second sub-function, the result is transmitted to at least two registers corresponding to the second sub-function.

[0224] At least two registers corresponding to the second sub-function will transfer the stored data to the third sub-function according to a strategy.

[0225] The third sub-function processes the received data and transmits the processing result to at least two registers corresponding to the third sub-function. The at least two registers corresponding to the third sub-function then transmit the stored data to the fourth sub-function according to a strategy.

[0226] The fourth sub-function will process the received data and transmit the processing result to the fifth sub-function;

[0227] The fifth sub-function modifies at least one bit of the received data and transmits the modification results to the aggregation module based on the buffer.

[0228] The summarization module summarizes the modification results of at least one bit buffered by the buffer and the data output by the fourth sub-function, and uses the summary result as the input of the first sub-function in the next round of iteration calculation.

[0229] According to embodiments of this disclosure, this disclosure also provides an electronic device and a readable storage medium.

[0230] Figure 12A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0231] like Figure 12 As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. The RAM 803 may also store various programs and data required for the operation of the electronic device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0232] Multiple components in electronic device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of displays, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows electronic device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0233] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as data processing methods. For example, in some embodiments, the data processing method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform data processing methods by any other suitable means (e.g., by means of firmware).

[0234] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0235] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0236] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0237] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0238] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0239] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0240] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0241] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0242] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, The method is implemented using a data processing device, wherein each module of the data processing device is implemented based on at least one partition of a field-programmable gate array (FPGA), and the data processing device includes at least a data grouping module, a message filling module, and an iterative calculation module; the method includes: The input valid signal is buffered by the global clock buffer corresponding to the field programmable gate array to obtain a first signal. The first signal is then transmitted to each module of the data processing device, so that each module of the data processing device starts up within a first time interval based on the first signal. The data to be processed is processed by the data grouping module and the message filling module to obtain the first data, and the first data is transmitted to the iterative calculation module. The first data is processed iteratively based on the sub-functions included in the first function of the iterative calculation module to obtain the output result corresponding to the data to be processed; The first function includes a first sub-function, a second sub-function, a third sub-function, a fourth sub-function, and a fifth sub-function; the first sub-function, the second sub-function, and the third sub-function are each configured with at least two registers; the registers are used to store data input to the corresponding sub-function or data output by the corresponding sub-function, so that the data input to the corresponding sub-function is input to the corresponding sub-function via the shortest path.

2. The method according to claim 1, characterized in that, The method further includes: Based on the source of the data to be processed, the field-programmable gate array (FPGA) partitions of the data input module included in the data processing device are determined, such that the distance between the data input module and the partition in the FPGA that receives the data to be processed is less than a first threshold.

3. The method according to claim 2, characterized in that, The determination of the field-programmable gate array partition for implementing the data input module of the data processing device based on the source of the data to be processed includes: In response to the input of data to be processed from the first port of the field-programmable gate array (FPGA), it is determined that the distance between the FPGA partition implementing the data input module and the FPGA partition implementing the input is less than a first threshold.

4. The method according to claim 2, characterized in that, The method further includes: It is determined that the data grouping module and the data input module are implemented using the same field-programmable gate array partition; Alternatively, determine that the distance between the field-programmable gate array partition implementing the data grouping module and the field-programmable gate array partition implementing the data input module is less than a second threshold.

5. The method according to claim 1, characterized in that, The distance between the field-programmable gate array partition implementing the message filling module and the field-programmable gate array partition implementing the data packet module is less than a first threshold.

6. The method according to claim 1, characterized in that, The data grouping module and message filling module process the data to be processed to obtain first data, and transmit the first data to the iterative calculation module, including: In response to the activation of the data input module, data grouping module, and message filling module based on the first signal, the data input module receives the data to be processed. The data input module transmits the data to be processed to the data grouping module, so that the data grouping module groups the data to be processed to obtain grouped data; The data grouping data is input into the message filling module to obtain the first data; The message block size of the first data is consistent with the processing size of the iterative calculation module.

7. The method according to claim 1, characterized in that, The first sub-function is used to perform an XOR operation on the bits of any two adjacent columns, and then perform an XOR operation on the arbitrary bit; The second sub-function is used to perform a cyclic shift operation on the channel; The third sub-function is used to perform a transposition operation on the slice corresponding to the first data. The fourth sub-function is used to perform bit combination operations on the rows in the first data; The fifth sub-function is used to modify at least one bit in the channel.

8. The method according to claim 1, characterized in that, The first sub-function corresponds to at least two registers; the at least two registers store the data that the first sub-function needs to process, and the data stored in the at least two registers corresponding to the first sub-function is the same; Based on the distance between the at least two registers and at least one input port corresponding to the first sub-function, a strategy is determined for the at least two registers to input data to at least one input port corresponding to the first sub-function.

9. The method according to claim 1, characterized in that, The second sub-function corresponds to at least two registers; the at least two registers store the data output by the second sub-function, and the data stored in the at least two registers corresponding to the second sub-function is the same; Based on the distance between the at least two registers and at least one input port corresponding to the third sub-function, a strategy is determined for the at least two registers to input data to at least one input port corresponding to the third sub-function.

10. The method according to claim 1, characterized in that, The third sub-function corresponds to at least two registers; the at least two registers store the data output by the third sub-function, and the data stored in the at least two registers corresponding to the third sub-function is the same; Based on the distance between the at least two registers and at least one input port corresponding to the fourth sub-function, a strategy is determined for the at least two registers to input data to at least one input port corresponding to the fourth sub-function.

11. The method according to claim 1, characterized in that, The fifth sub-function modifies at least one bit in the channel and transmits the modification results to the aggregation module based on the buffer. The summarization module summarizes the modification results of at least one bit buffered by the buffer and the data output by the fourth sub-function, and uses the summarization result as the input of the first sub-function in the next round of iteration calculation.

12. The method according to claim 11, characterized in that, If the current iteration is the last iteration, then at least two registers corresponding to the first sub-function are not configured, and the final result of the iteration calculation module is directly output. Alternatively, if the current iteration is not the last iteration, then at least two registers are configured for the first sub-function, and the processing result of the fifth sub-function and the output of the fourth sub-function are stored in the at least two registers.

13. The method according to claim 1, characterized in that, Based on performance requirement information and / or field-programmable gate array (FPGA) resource information, determine at least one FPGA partition for implementing the iterative computing module. If the iterative calculation module is implemented based on two field-programmable gate array (FPGA) partitions, then the two FPGA partitions are adjacent.

14. The method according to claim 13, characterized in that, The method further includes: In response to the iterative calculation module implemented based on two field-programmable gate array partitions, the data output by the fifth sub-function is buffered based on a global clock buffer, and all buffered data is summarized as the input of the first sub-function in the next round of iterative calculation.

15. The method according to claim 13, characterized in that, The method further includes: In response to the iterative calculation module being implemented based on a field-programmable gate array partition, the data output by the fifth sub-function is buffered based on a global clock buffer or a regional clock buffer, and all buffered data is summarized as the input of the first sub-function for the next round of iterative calculation.

16. The method according to claim 1, characterized in that, The iterative calculation module, based on the first function, performs iterative calculations on the first data to obtain the output result corresponding to the data to be processed, including: The first data is stored in at least two registers corresponding to the first sub-function, and the first data is transmitted to the first sub-function based on the strategy of inputting data to at least one input port corresponding to the first sub-function using the at least two registers. The first sub-function processes the first data and transmits the processing result to the second sub-function. After processing by the second sub-function, the result is transmitted to at least two registers corresponding to the second sub-function. At least two registers corresponding to the second sub-function will transfer the stored data to the third sub-function according to a strategy. The third sub-function processes the received data and transmits the processing result to at least two registers corresponding to the third sub-function. The at least two registers corresponding to the third sub-function then transmit the stored data to the fourth sub-function according to a strategy. The fourth sub-function will process the received data and transmit the processing result to the fifth sub-function; The fifth sub-function modifies at least one bit of the received data and transmits the modification results to the aggregation module based on the buffer. The summarization module summarizes the modification results of at least one bit buffered by the buffer and the data output by the fourth sub-function, and uses the summarization result as the input of the first sub-function in the next round of iteration calculation.

17. A data processing device, characterized in that, The data processing device includes a data processing unit and a buffer unit. Each module of the data processing unit is implemented based on at least one partition of a field-programmable gate array (FPGA). The data processing unit includes at least a data packetization module, a message filling module, and an iterative calculation module. The device includes: A buffering device is used to buffer the input valid signal based on the global clock buffer corresponding to the field programmable gate array to obtain a first signal, and transmit the first signal to each module of the data processing device so that each module of the data processing device starts up based on the first signal in a first time interval. The data grouping module and message filling module are used to process the data to be processed, obtain the first data, and transmit the first data to the iterative calculation module; The iterative calculation module is used to perform iterative calculations on the first data based on the various sub-functions included in the first function, so as to obtain the output result corresponding to the data to be processed; The first function includes a first sub-function, a second sub-function, a third sub-function, a fourth sub-function, and a fifth sub-function; the first sub-function, the second sub-function, and the third sub-function are each configured with at least two registers; the registers are used to store data input to the corresponding sub-function or data output by the corresponding sub-function, so that the data input to the corresponding sub-function is input to the corresponding sub-function via the shortest path.

18. An electronic device, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-16.

19. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-16.

20. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method of any one of claims 1-16.

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