Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises an interlayer dielectric layer electric leakage test structure located in a test area, wherein the interlayer dielectric layer electric leakage test structure comprises a semiconductor body with a first surface and a second surface which are oppositely arranged; a first insulating layer; a plurality of second insulating layers arranged at intervals; a plurality of first electrode layers; the interlayer dielectric layer is provided with a first through hole and a second through hole; the test electrode layer comprises a first test electrode and a second test electrode; the first test electrode is connected with the first electrode layer through the first through hole; the second test electrode is connected with the first insulating layer through the second through hole; and the third through hole is used for isolating the first test electrode from the second test electrode. The interlayer dielectric layer electric leakage test structure is arranged, voltage control is provided through the test electrode layer, the electric leakage condition is tested, the same effect as that of a monitoring chip area is achieved, and the reliability of the semiconductor device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and manufacturing method, a power module, a power conversion circuit and a vehicle. BACKGROUND

[0002] In a semiconductor device, an intermediate insulating layer (interlayer dielectric layer) is arranged between a conductor region and a metal to provide electrical insulation between the conductor region and the metal and to isolate the surrounding environment. The sidewall layer of the interlayer dielectric layer can effectively prevent short circuiting between the source region and the gate region. Therefore, monitoring the leakage of the interlayer dielectric layer plays an important role in the performance of the chip.

[0003] The existing semiconductor device cannot monitor the leakage of the interlayer dielectric layer, so it cannot monitor whether the isolation leakage effect of the interlayer dielectric layer meets the requirements. Directly testing the chip region cannot achieve monitoring of the leakage of the interlayer dielectric layer, which reduces the reliability of the semiconductor device. SUMMARY

[0004] The present application provides a semiconductor device and manufacturing method, a power module, a power conversion circuit and a vehicle to monitor the isolation leakage effect of the interlayer dielectric layer and improve the reliability of the semiconductor device.

[0005] According to an aspect of the present application, a semiconductor device is provided, which comprises:

[0006] An interlayer dielectric layer leakage test structure, the interlayer dielectric layer leakage test structure comprising a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the interlayer dielectric layer leakage test structure being located in a test region of the semiconductor device;

[0007] A first insulating layer located on the first surface;

[0008] A plurality of second insulating layers located on a side of the first insulating layer away from the first surface; the plurality of second insulating layers being arranged at intervals;

[0009] A plurality of first electrode layers located on a side of the second insulating layer away from the first insulating layer; the first electrode layers being arranged one-to-one corresponding to the second insulating layers;

[0010] An interlayer dielectric layer located on a side of the first electrode layer away from the second insulating layer; the interlayer dielectric layer being provided with a first through hole and a second through hole; the first through hole extending from a side of the interlayer dielectric layer away from the first surface to the first electrode layer; the second through hole extending from a side of the interlayer dielectric layer away from the first surface to the first insulating layer;

[0011] The test electrode layer is located on the side of the interlayer dielectric layer away from the first surface; the test electrode layer comprises a first test electrode and a second test electrode; the first test electrode is connected with the first electrode layer through a first through hole; the second test electrode is connected with the first insulating layer through a second through hole; the test electrode layer is provided with a third through hole for isolating the first test electrode and the second test electrode.

[0012] Optionally, the semiconductor device further comprises a semiconductor functional structure, the semiconductor functional structure is located on the side of the interlayer dielectric layer leakage test structure, and the semiconductor functional structure is located in a functional region of the semiconductor device; the semiconductor functional structure comprises: a semiconductor body, a second insulating layer, a gate electrode, an interlayer dielectric layer, a source electrode and a drain electrode.

[0013] The semiconductor body extends from the test region to the functional region, and the semiconductor body is provided as a first conduction type; the semiconductor body further comprises a well region and a first region; the first region is provided as the first conduction type and is located on the first surface; the well region is provided as a second conduction type and is located on the side of the first region away from the first surface; the first conduction type and the second conduction type are different;

[0014] The second insulating layer extends from the test region to the functional region, and the second insulating layer is located on the first surface;

[0015] The gate electrode is located on the side of the second insulating layer away from the first surface; the gate electrode and the first electrode layer are located in the same layer;

[0016] The interlayer dielectric layer extends from the test region to the functional region, and the interlayer dielectric layer is located on the side of the gate electrode away from the second insulating layer; the interlayer dielectric layer covers the gate electrode; the interlayer dielectric layer is provided with a fourth through hole;

[0017] The gate electrode is located on the side of the second insulating layer away from the first surface; the gate electrode and the first electrode layer are located in the same layer;

[0018] The source electrode is located on the first surface;

[0019] The drain electrode is located on the second surface;

[0020] The first test electrode and the gate electrode are located in the same layer;

[0021] The second test electrode and the source electrode are located in the same layer.

[0022] Optionally, the semiconductor body comprises a silicon carbide semiconductor body, or the semiconductor body comprises a gallium nitride semiconductor body.

[0023] Optionally, the first insulating layer comprises a first silicon oxide insulating layer; and / or, the second insulating layer comprises a second silicon oxide insulating layer.

[0024] Optionally, the shape of the projection of the semiconductor body on the first surface includes a polygon, and the number of sides of the polygon is greater than or equal to four.

[0025] Optionally, the shape of the projection of the semiconductor body on the first surface includes a circle.

[0026] According to another aspect of the present application, a method for manufacturing a semiconductor device is provided, the method comprising:

[0027] forming an interlayer dielectric layer leakage test structure; the interlayer dielectric layer leakage test structure includes a semiconductor body, the semiconductor body includes oppositely arranged first and second surfaces; the interlayer dielectric layer leakage test structure is located in a test area of the semiconductor device; a first insulating layer is located on the first surface; a plurality of second insulating layers are located on a side of the first insulating layer away from the first surface; the plurality of second insulating layers are spaced apart; a plurality of first electrode layers are located on a side of the second insulating layer away from the first insulating layer; the first electrode layers are arranged one-to-one corresponding to the second insulating layers; an interlayer dielectric layer is located on a side of the first electrode layer away from the second insulating layer; the interlayer dielectric layer is provided with a first via and a second via; the first via extends from a side of the interlayer dielectric layer away from the first surface to the first electrode layer; the second via extends from a side of the interlayer dielectric layer away from the first surface to the first insulating layer; a test electrode layer is located on a side of the interlayer dielectric layer away from the first surface; the test electrode layer includes a first test electrode and a second test electrode; the first test electrode is connected to the first electrode layer through the first via; the second test electrode is connected to the first insulating layer through the second via; the test electrode layer is provided with a third via, and the third via is used to isolate the first test electrode and the second test electrode.

[0028] Optionally, forming the interlayer dielectric layer leakage test structure comprises:

[0029] providing a semiconductor body, the semiconductor body includes oppositely arranged first and second surfaces;

[0030] forming a first insulating layer on the first surface;

[0031] forming a plurality of second insulating layers on a side of the first insulating layer away from the first surface; the plurality of second insulating layers are spaced apart;

[0032] forming a plurality of first electrode layers on a side of the second insulating layer away from the first insulating layer; the first electrode layers are arranged one-to-one corresponding to the second insulating layers;

[0033] forming an interlayer dielectric layer on a side of the first electrode layer away from the second insulating layer; the interlayer dielectric layer is provided with a first via and a second via; the first via extends from a side of the interlayer dielectric layer away from the first surface to the first electrode layer; the second via extends from a side of the interlayer dielectric layer away from the first surface to the first insulating layer;

[0034] forming a test electrode layer on a side of the interlayer dielectric layer away from the first surface; the test electrode layer includes a first test electrode and a second test electrode; the first test electrode is connected to the first electrode layer through a first via; the second test electrode is connected to the first insulating layer through a second via; the test electrode layer is provided with a third via for isolating the first test electrode and the second test electrode.

[0035] Optionally, an interlayer dielectric layer is formed on a side of the first electrode layer away from the second insulating layer, comprising:

[0036] forming a transition interlayer dielectric layer on a side of the first electrode layer away from the second insulating layer;

[0037] forming a first via in the transition interlayer dielectric layer; the first via extends from a side of the transition interlayer dielectric layer away from the first surface to the first electrode layer;

[0038] forming a second via in the transition interlayer dielectric layer; the second via extends from a side of the transition interlayer dielectric layer away from the first surface to the first insulating layer; the transition interlayer dielectric layer after forming the first via and the second via serves as the interlayer dielectric layer.

[0039] Optionally, the method for manufacturing the semiconductor device further comprises:

[0040] forming a semiconductor functional structure on a side of the interlayer dielectric layer leakage test structure; the semiconductor functional structure is located in a functional region of the semiconductor device; the semiconductor functional structure comprises: a semiconductor body, a second insulating layer, a gate, an interlayer dielectric layer, a source and a drain; the semiconductor body extends from the test region to the functional region; the semiconductor body is provided as a first conductivity type; the semiconductor body further comprises a first region provided as the first conductivity type and located on the first surface, and a well region provided as a second conductivity type and located on a side of the first region away from the first surface; the first conductivity type and the second conductivity type are different; the second insulating layer extends from the test region to the functional region; the second insulating layer is located on the first surface; the gate is located on a side of the second insulating layer away from the first surface; the gate and the first electrode layer are located in the same layer; the interlayer dielectric layer extends from the test region to the functional region; the interlayer dielectric layer is located on a side of the gate away from the second insulating layer; the interlayer dielectric layer covers the gate; the interlayer dielectric layer is provided with a fourth via; the gate electrode is located on a side of the interlayer dielectric layer away from the first surface; the gate electrode is connected to the gate through the fourth via; the source is located on the first surface; the drain is located on the second surface; the first test electrode and the gate electrode are located in the same layer; the second test electrode and the source are located in the same layer.

[0041] Optionally, the semiconductor body is provided, comprising:

[0042] providing a semiconductor body comprising a silicon carbide semiconductor body or a silicon nitride semiconductor body.

[0043] According to another aspect of the present application, there is provided a power module including a substrate for carrying the semiconductor device and at least one of the above-described semiconductor device.

[0044] According to another aspect of the present application, there is provided a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction.

[0045] The power conversion circuit includes a circuit board and at least one of the above-described semiconductor device, the semiconductor device being electrically connected to the circuit board.

[0046] According to another aspect of the present application, there is provided a vehicle including a load and the above-described power conversion circuit for converting AC power to DC power, AC power to AC power, DC power to DC power, or DC power to AC power and inputting the converted power to the load.

[0047] The technical scheme of the embodiment of the present application sets the interlayer dielectric layer leakage test structure, monitors the leakage of the interlayer dielectric layer, adopts a design of a sufficient number of chip area unit cells, provides voltage control through the test electrode layer, and tests the leakage between the first test electrode and the second test electrode. The first insulating layer is set to insulate the epitaxial layer and the interlayer dielectric layer, so that the epitaxial layer can avoid interfering with the test path during testing, and the accuracy of the test is improved. Under normal circumstances, if no leakage current is detected or the detected leakage current is small enough, it can be determined that the isolation effect of the interlayer dielectric layer is good; if a large leakage current is detected, it indicates that the isolation effect of the interlayer dielectric layer is poor, which will cause a short circuit of the circuit and cannot achieve the isolation effect. The interlayer dielectric layer leakage test structure monitors the leakage of the interlayer dielectric layer to achieve the same effect as the chip area, thereby improving the reliability of the semiconductor device.

[0048] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0050] Figure 1 is a structural schematic diagram of a semiconductor device provided by the embodiments of the present application.

[0051] Figure 2 is a structural diagram of another semiconductor device according to an embodiment of the application;

[0052] Figure 3 is a top view of an interlayer dielectric layer leakage test structure according to an embodiment of the application;

[0053] Figure 4 is a top view of another interlayer dielectric layer leakage test structure according to an embodiment of the application;

[0054] Figure 5 is a top view of yet another interlayer dielectric layer leakage test structure according to an embodiment of the application;

[0055] Figure 6 is a flow chart of a semiconductor device manufacturing method according to an embodiment of the application;

[0056] Figure 7 is a flow chart of a semiconductor device manufacturing method according to an embodiment of the application; Figure 6 is a flow chart included in S110 of the method;

[0057] Figures 8-12 is a cross-sectional view corresponding to each step of the method according to an embodiment of the application; Figure 7

[0058] is a cross-sectional view corresponding to each step of the method according to an embodiment of the application; Figure 13 Figure 7 is a flow chart included in S1105 of the method according to an embodiment of the application;

[0059] Figures 14-15 Figure 13 is a cross-sectional view corresponding to each step of the method according to an embodiment of the application;

[0060] Figure 16 is a flow chart of another semiconductor device manufacturing method according to an embodiment of the application. DETAILED DESCRIPTION

[0061] In order to enable persons skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative labor should fall within the scope of protection of the present application.

[0062] ​​It should be noted that the terms "first", "second", and the like in the description and in the claims of the present application and the above-described accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular sequential or chronological order. It should be understood that the data thus used can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or apparatus that includes a list of steps or units need not be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to such processes, methods, products, or apparatuses.

[0063] In order to monitor the insulation leakage effect of the interlayer dielectric layer and improve the reliability of the semiconductor device, the embodiments of the present application provide the following technical solutions.

[0064] Figure 1 is a structural schematic diagram of a semiconductor device provided by the embodiments of the present application, as shown in Figure 1 The semiconductor device includes: an interlayer dielectric layer leakage test structure 200, the interlayer dielectric layer leakage test structure 200 includes a semiconductor body 100, the semiconductor body 100 includes oppositely arranged first and second surfaces 101 and 102; the interlayer dielectric layer leakage test structure 200 is located in a test region of the semiconductor device; a first insulating layer 301 is located on the first surface 101; a plurality of second insulating layers 302 are located on a side of the first insulating layer 301 away from the first surface 101; the plurality of second insulating layers 302 are arranged at intervals; a plurality of first electrode layers 303 are located on a side of the second insulating layer 302 away from the first insulating layer 301; the first electrode layer 303 is arranged one-to-one corresponding to the second insulating layer 302; an interlayer dielectric layer 400 is located on a side of the first electrode layer 303 away from the second insulating layer 302; the interlayer dielectric layer 400 is provided with a first via hole 401 and a second via hole 402; the first via hole 401 extends from a side of the interlayer dielectric layer 400 away from the first surface 101 to the first electrode layer 303; the second via hole 402 extends from a side of the interlayer dielectric layer 400 away from the first surface 101 to the first insulating layer 301; a test electrode layer 500 is located on a side of the interlayer dielectric layer 400 away from the first surface 101; the test electrode layer 500 includes a first test electrode 501 and a second test electrode 502; the first test electrode 501 is connected to the first electrode layer 303 through the first via hole 401; the second test electrode 502 is connected to the first insulating layer 301 through the second via hole 402; the test electrode layer 500 is provided with a third via hole 503, and the third via hole 503 is used to isolate the first test electrode 501 and the second test electrode 502.

[0065] In the embodiments of the present application, the interlayer dielectric layer leakage test structure 200 is located in the test region of the semiconductor device, and is used to test the isolation leakage effect of the interlayer dielectric layer in the semiconductor device, thereby improving the reliability of the semiconductor device. The interlayer dielectric layer leakage test structure 200 comprises a semiconductor body 100. As shown in Figure 1 The semiconductor body 100 comprises a substrate 10 and an epitaxial layer 20. In some embodiments of the present application, the semiconductor body 100 can only comprise the epitaxial layer 20. In other embodiments of the present application, the semiconductor body 100 can comprise the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the basis of the substrate 10 by a one-time epitaxial process, and the epitaxial process comprises a chemical vapor phase epitaxy (CVE), a molecular beam epitaxy (MBD) and an atomic layer epitaxy (ALE) process.

[0066] The first insulating layer 301 is a field oxide layer. The material of the field oxide layer can comprise silicon dioxide. The first insulating layer 301 is used to isolate the epitaxial layer 20 and the interlayer dielectric layer 400, so as to avoid the interference of the epitaxial layer 20 on the test path during the test, thereby improving the accuracy of the test. Generally, the silicon dioxide formed by the furnace tube thermal oxidation growth, the wet oxidation method, the oxidation of silicon by hydrogen and oxygen at a temperature of about 1000 ℃, can be used as the field oxide layer.

[0067] The second insulating layer 302 can be a gate oxide layer. The second insulating layer 302 can be formed by a thermal oxidation process. The first electrode layer 303 can be a gate in a metal-oxide-semiconductor field-effect transistor (MOSFET). In the MOSFET, the interlayer dielectric layer 400 can be used to insulate and isolate the gate and the source.

[0068] The test electrode layer 500 comprises a first test electrode 501 and a second test electrode 502. The first test electrode 501 is connected with the first electrode layer 303 through the first via hole 401, and the second test electrode 502 is connected with the first insulating layer 301 through the second via hole 402. The first test electrode 501 and the second test electrode 502 are isolated by the third via hole 503. The voltage is provided through the first test electrode 501, and the leakage condition is tested, so as to achieve the same effect as monitoring the chip area. For example, the positive voltage is provided through the first test electrode 501, and the current between the first test electrode 501 and the second test electrode 502 is monitored. Under normal circumstances, if no leakage current is detected or the detected leakage current is small enough, it can be determined that the isolation effect of the interlayer dielectric layer 400 is good. If a large leakage current is detected, it indicates that the isolation effect of the interlayer dielectric layer 400 is poor, and the isolation effect cannot be achieved, which will cause the short circuit of the gate and the source, and further cause the failure of the MOSFET.

[0069] The technical scheme of the embodiment of the present application sets the interlayer dielectric layer leakage test structure 200 to monitor the leakage of the interlayer dielectric layer 400, adopts a design of a sufficient number of chip area unit cells, provides voltage control through the test electrode layer 500, and tests the leakage between the first test electrode 501 and the second test electrode 502. The first insulating layer 301 is set to isolate the epitaxial layer 20 and the interlayer dielectric layer 400, so that the epitaxial layer 20 can avoid interfering with the test path during testing, and the accuracy of the test is improved. Under normal circumstances, if no leakage current is detected or the detected leakage current is small enough, it can be determined that the isolation effect of the interlayer dielectric layer 400 is good; if a large leakage current is detected, it indicates that the isolation effect of the interlayer dielectric layer 400 is poor, which will cause a short circuit of the circuit and cannot achieve the isolation effect. The interlayer dielectric layer leakage test structure 200 monitors the leakage of the interlayer dielectric layer 400 to achieve the same effect as monitoring the chip area, and improves the reliability of the semiconductor device.

[0070] Figure 2 is another structure diagram of a semiconductor device provided according to the embodiment of the present application, like Figure 2As shown, the semiconductor device further comprises a semiconductor functional structure 300 located on one side of the interlayer dielectric layer leakage test structure 200, the semiconductor functional structure 300 is located in a functional region 40 of the semiconductor device, and the semiconductor functional structure 300 comprises: the semiconductor body 100, a second insulating layer 302, the gate 50, an interlayer dielectric layer 400, the source 60, and the drain 70; the semiconductor body 100 extends from the test region 30 to the functional region 40, and the semiconductor body 100 is set to a first conduction type; the semiconductor body 100 further comprises a well region 103 and a first region 104, the first region 104 is set to the first conduction type and is located on the first surface 101, and the well region 103 is set to a second conduction type and is located on a side of the first region 104 away from the first surface 101, the first conduction type and the second conduction type being different; the second insulating layer 302 extends from the test region 30 to the functional region 40, and the second insulating layer 302 is located on the first surface 101; the gate 50 is located on a side of the second insulating layer 302 away from the first surface 101; the gate 50 and the first electrode layer 303 are located in the same layer; the interlayer dielectric layer 400 extends from the test region 30 to the functional region 40, and the interlayer dielectric layer 400 is located on a side of the gate 50 away from the second insulating layer 302; the interlayer dielectric layer 400 covers the gate 50; the interlayer dielectric layer 400 is provided with a fourth through hole 403; the gate electrode 80 is located on a side of the interlayer dielectric layer 400 away from the first surface 101; the gate electrode 80 is connected with the gate 50 through the fourth through hole 403; the source 60 is located on the first surface 101; the drain 70 is located on the second surface 102; the first test electrode 501 and the gate electrode 80 are located in the same layer; and the second test electrode 502 and the source 60 are located in the same layer.

[0071] In the embodiments of the present application, the semiconductor functional structure 300 includes but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor functional structure 300 includes but is not limited to a planar MOSFET or a trench MOSFET. Figure 2 Only the planar MOSFET structure is shown. The semiconductor body 100 can comprise a third-generation wide-bandgap semiconductor material such as a silicon carbide semiconductor body, and the semiconductor functional structure 300 is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 can also comprise a third-generation wide-bandgap semiconductor material such as a gallium nitride semiconductor body, and the semiconductor functional structure 300 is a gallium nitride MOSFET semiconductor device. The silicon carbide MOSFET semiconductor device or the gallium nitride MOSFET semiconductor device has the advantages of high withstand voltage, low on-resistance, and high frequency, and can further improve the performance of the semiconductor device.

[0072] For N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type. For example, for N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions of the N+ doped region can be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, and the P-type doping ions of the P-well region can be aluminum (Al) ions or boron (B) ions. The first region 104 can be formed on the first surface 101 of the semiconductor body 100 by ion implantation, ion diffusion, or vapor deposition process. The metal deposited on the first surface 101 forms the source 60. The metal deposited on the second surface 102 forms the drain 70. The deposited metal includes but is not limited to silver or titanium.

[0073] The first test electrode 501 and the gate electrode 80 are located in the same layer; the gate electrode 80 is connected with the gate 50 through the fourth via hole 403; the second test electrode 502 and the source 60 are located in the same layer; the interlayer dielectric layer 400 extends from the test region 30 to the functional region 40; the leakage of the interlayer dielectric layer 400 is monitored in the interlayer dielectric layer leakage test structure 200, the voltage is controlled through the test electrode layer 500, and the leakage between the first test electrode 501 and the second test electrode 502 is tested, and a sufficient number of the same design as the semiconductor functional structure 300 is used in the interlayer dielectric layer leakage test structure 200 to achieve the same effect as the semiconductor functional structure 300 and monitor the reliability of the semiconductor device.

[0074] In an optional embodiment of the present application, the semiconductor body 100 further comprises a second region 105, which can be a P+ doped region and located on the first surface 101. The ion concentration of the second region 105 is greater than that of the well region 103, and can form a good ohmic contact with the source 60.

[0075] In an optional embodiment of the present application, referring to Figure 1 , the first insulating layer 301 comprises a first silicon oxide insulating layer; and / or, the second insulating layer 302 comprises a second silicon oxide insulating layer.

[0076] Specifically, the materials of the first insulating layer 301 and the second insulating layer 302 can both be silicon oxide, but the functions of the first insulating layer 301 and the second insulating layer 302 are different. The first insulating layer 301 is a first silicon oxide insulating layer, which is used to isolate the epitaxial layer 20 and the interlayer dielectric layer 400. The second insulating layer 302 is a second silicon oxide insulating layer, which is used to isolate the semiconductor body 100 and the first electrode layer 303.

[0077] Figure 3 is a top view of an interlayer dielectric layer leakage test structure according to an embodiment of the present application. Figure 4is a top view of another interlayer dielectric layer leakage test structure provided by an embodiment of the present application. As shown in Figure 3 and Figure 4 The shape of the projection of the first via 401 and the second via 402 on the semiconductor body 100 includes a polygon, and the number of sides of the polygon is greater than or equal to four.

[0078] Specifically, the shape of the projection of the first via 401 and the second via 402 on the semiconductor body 100 can be a polygon such as a quadrilateral, a pentagon, or a hexagon. The shape of the projection of the first via 401 and the second via 402 on the semiconductor body 100 can be set according to the shape of the unit cell, and the unit cell structure is reduced to the maximum, so that the isolation leakage of the interlayer dielectric layer in the interlayer dielectric layer leakage test structure 200 is tested in the same way as the test chip area. Figure 3 As shown in Figure 4 As shown in

[0079] Figure 5 is a top view of another interlayer dielectric layer leakage test structure provided by an embodiment of the present application. The shape of the projection of the first via 401 and the second via 402 on the semiconductor body 100 also includes a circle.

[0080] Specifically, Figure 3 , Figure 4 and Figure 5 include the first electrode layer 303 and the interlayer dielectric layer 400. It should be noted that the shape of the projection of the first via 401 and the second via 402 on the semiconductor body 100 can be designed according to the shape of the unit cell, and the specific shape is not limited.

[0081] Figure 6 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application. As shown in Figure 6 The method for manufacturing a semiconductor device includes:

[0082] S110, form an interlayer dielectric layer leakage test structure; the interlayer dielectric layer leakage test structure includes a semiconductor body, the semiconductor body includes oppositely arranged first and second surfaces; the interlayer dielectric layer leakage test structure is located in a test region of the semiconductor device; a first insulating layer is located on the first surface; a plurality of second insulating layers are located on a side of the first insulating layer away from the first surface; the plurality of second insulating layers are spaced apart; a plurality of first electrode layers are located on a side of the second insulating layer away from the first insulating layer; the first electrode layers are arranged one-to-one corresponding to the second insulating layers; an interlayer dielectric layer is located on a side of the first electrode layer away from the second insulating layer; the interlayer dielectric layer is provided with a first via and a second via; the first via extends from a side of the interlayer dielectric layer away from the first surface to the first electrode layer; the second via extends from a side of the interlayer dielectric layer away from the first surface to the first insulating layer; a test electrode layer is located on a side of the interlayer dielectric layer away from the first surface; the test electrode layer includes a first test electrode and a second test electrode; the first test electrode is connected to the first electrode layer through the first via; the second test electrode is connected to the first insulating layer through the second via; the test electrode layer is provided with a third via, and the third via is used to isolate the first test electrode and the second test electrode.

[0083] Specifically, referring to Figure 1 , an interlayer dielectric layer leakage test structure 200 is formed. The interlayer dielectric layer leakage test structure 200 includes a semiconductor body 100, the semiconductor body 100 includes oppositely arranged first and second surfaces 101 and 102; the interlayer dielectric layer leakage test structure 200 is located in a test region of the semiconductor device; a first insulating layer 301 is located on the first surface 101; a plurality of second insulating layers 302 are located on a side of the first insulating layer 301 away from the first surface 101; the plurality of second insulating layers 302 are spaced apart; a plurality of first electrode layers 303 are located on a side of the second insulating layer 302 away from the first insulating layer 301; the first electrode layers 303 are arranged one-to-one corresponding to the second insulating layers 302; an interlayer dielectric layer 400 is located on a side of the first electrode layer 303 away from the second insulating layer 302; the interlayer dielectric layer 400 is provided with a first via 401 and a second via 402; the first via 401 extends from a side of the interlayer dielectric layer 400 away from the first surface 101 to the first electrode layer 303; the second via 402 extends from a side of the interlayer dielectric layer 400 away from the first surface 101 to the first insulating layer 301; a test electrode layer 500 is located on a side of the interlayer dielectric layer 400 away from the first surface 101; the test electrode layer 500 includes a first test electrode 501 and a second test electrode 502; the first test electrode 501 is connected to the first electrode layer 303 through the first via 401; the second test electrode 502 is connected to the first insulating layer 301 through the second via 402; the test electrode layer 500 is provided with a third via 503, and the third via 503 is used to isolate the first test electrode 501 and the second test electrode 502.

[0084] The technical solution of this application embodiment forms an interlayer dielectric layer leakage test structure 200 to monitor leakage current in the interlayer dielectric layer 400. It employs a design with a sufficient number of cells identical to those in the chip region, provides voltage control through the test electrode layer 500, and tests the leakage current between the first test electrode 501 and the second test electrode 502. A first insulating layer 301 is provided to isolate the epitaxial layer 20 and the interlayer dielectric layer 400, preventing interference from the epitaxial layer 20 to the test path during testing and improving test accuracy. Under normal circumstances, if no leakage current is detected or the detected leakage current is sufficiently small, it can be determined that the isolation effect of the interlayer dielectric layer 400 is good; if a large leakage current is detected, it indicates that the isolation effect of the interlayer dielectric layer 400 is poor, which will cause a short circuit and fail to achieve the isolation effect. By monitoring the leakage current of the interlayer dielectric layer 400 through the interlayer dielectric layer leakage test structure 200, the same effect as monitoring the chip region is achieved, improving the reliability of the semiconductor device.

[0085] Figure 7 Provided according to the embodiments of this application Figure 6 The process diagram includes S110. (For example...) Figure 7 As shown, in an optional embodiment of this application, S110, forming an interlayer dielectric layer leakage test structure includes:

[0086] S1101. A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other.

[0087] For details, please refer to Figure 8 A semiconductor body 100 is provided, the semiconductor body 100 including a first surface 101 and a second surface 102 disposed opposite to each other. For example... Figure 8 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of this application, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of this application, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by a single epitaxial process, including chemical vapor deposition (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0088] S1102, A first insulating layer is formed on the first surface.

[0089] refer to Figure 9A first insulating layer 301 is formed on the first surface 101. The first insulating layer 301 is a field oxide layer. The material of the field oxide layer can include silicon dioxide. The field oxide layer can be formed by a furnace tube thermal oxidation growth, a wet oxidation method, and oxidation of silicon by hydrogen and oxygen at a temperature of about 1000 degrees Celsius.

[0090] S1103. A plurality of second insulating layers are formed on a side of the first insulating layer away from the first surface; the plurality of second insulating layers are arranged at intervals.

[0091] Reference Figure 10 A plurality of second insulating layers 302 are formed on a side of the first insulating layer 301 away from the first surface 101; the plurality of second insulating layers 302 are arranged at intervals. The second insulating layer 302 can be a gate oxide layer. The second insulating layer 302 can be formed by a thermal oxidation process.

[0092] S1104. A plurality of first electrode layers are formed on a side of the second insulating layer away from the first insulating layer; the first electrode layers are arranged one-to-one corresponding to the second insulating layers.

[0093] Reference Figure 11 A plurality of first electrode layers 303 are formed on a side of the second insulating layer 302 away from the first insulating layer 301; the first electrode layers 303 are arranged one-to-one corresponding to the second insulating layers 302. The first electrode layers 303 can be formed by depositing polysilicon on a side of the second insulating layer 302 away from the first insulating layer 301.

[0094] S1105. An interlayer dielectric layer is formed on a side of the first electrode layer away from the second insulating layer; the interlayer dielectric layer is provided with a first via and a second via; the first via extends from a side of the interlayer dielectric layer away from the first surface to the first electrode layer; the second via extends from a side of the interlayer dielectric layer away from the first surface to the first insulating layer.

[0095] Reference Figure 12 An interlayer dielectric layer 400 is formed on a side of the first electrode layer 303 away from the second insulating layer 302; the interlayer dielectric layer 400 is provided with a first via 401 and a second via 402; the first via 401 extends from a side of the interlayer dielectric layer 400 away from the first surface 101 to the first electrode layer 303; the second via 402 extends from a side of the interlayer dielectric layer 400 away from the first surface 101 to the first insulating layer 301. The first via 401 and the second via 402 can be formed by a photolithography and etching process.

[0096] S1106, forming a test electrode layer on a side of the interlayer dielectric layer away from the first surface; the test electrode layer includes a first test electrode and a second test electrode; the first test electrode is connected with the first electrode layer through a first via hole; the second test electrode is connected with the first insulating layer through a second via hole; the test electrode layer is provided with a third via hole for isolating the first test electrode and the second test electrode.

[0097] Reference Figure 1 A test electrode layer 500 is formed on a side of the interlayer dielectric layer 400 away from the first surface 101; the test electrode layer 500 includes a first test electrode 501 and a second test electrode 502; the first test electrode 501 is connected with the first electrode layer 303 through a first via hole 401; the second test electrode 502 is connected with the first insulating layer 301 through a second via hole 402; the test electrode layer 500 is provided with a third via hole 503 for isolating the first test electrode 501 and the second test electrode 502.

[0098] Figure 13 According to the embodiments of the present application Figure 7 The flowchart included in S1105. As shown in Figure 13 S1105, forming an interlayer dielectric layer on a side of the first electrode layer away from the second insulating layer, including:

[0099] S1107, forming a transition interlayer dielectric layer on a side of the first electrode layer away from the second insulating layer.

[0100] Reference Figure 14 Silicon oxide is deposited on a side of the first electrode layer 303 away from the second insulating layer 302 to form a transition interlayer dielectric layer 404.

[0101] S1108, forming a first via hole in the transition interlayer dielectric layer; the first via hole extends from a side of the transition interlayer dielectric layer away from the first surface to the first electrode layer.

[0102] Reference Figure 15 A first via hole 401 is formed in the transition interlayer dielectric layer 404; the first via hole 401 extends from a side of the transition interlayer dielectric layer 404 away from the first surface 101 to the first electrode layer 303.

[0103] S1109, forming a second via hole in the transition interlayer dielectric layer; the second via hole extends from a side of the transition interlayer dielectric layer away from the first surface to the first insulating layer; the transition interlayer dielectric layer after forming the first via hole and the second via hole serves as an interlayer dielectric layer.

[0104] Reference Figure 12The second via hole 402 is formed in the transition interlayer dielectric layer 404; the second via hole 402 extends from the side of the transition interlayer dielectric layer 404 away from the first surface 101 to the first insulating layer 301; the transition interlayer dielectric layer 404 after the formation of the first via hole 401 and the second via hole 402 serves as the interlayer dielectric layer 400.

[0105] Figure 16 is a flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present application. As shown in Figure 16 the method for manufacturing a semiconductor device includes:

[0106] S210, forming an interlayer dielectric layer leakage test structure; the interlayer dielectric layer leakage test structure includes a semiconductor body, the semiconductor body includes a first surface and a second surface arranged opposite to each other; the interlayer dielectric layer leakage test structure is located in a test area of the semiconductor device; a first insulating layer is located at the first surface; a plurality of second insulating layers are located at the side of the first insulating layer away from the first surface; the plurality of second insulating layers are arranged at intervals; a plurality of first electrode layers are located at the side of the second insulating layer away from the first insulating layer; the first electrode layers are arranged one-to-one corresponding to the second insulating layers; an interlayer dielectric layer is located at the side of the first electrode layer away from the second insulating layer; the interlayer dielectric layer is provided with a first via hole and a second via hole; the first via hole extends from the side of the interlayer dielectric layer away from the first surface to the first electrode layer; the second via hole extends from the side of the interlayer dielectric layer away from the first surface to the first insulating layer; a test electrode layer is located at the side of the interlayer dielectric layer away from the first surface; the test electrode layer includes a first test electrode and a second test electrode; the first test electrode is connected to the first electrode layer through the first via hole; the second test electrode is connected to the first insulating layer through the second via hole; the test electrode layer is provided with a third via hole, and the third via hole is used to isolate the first test electrode and the second test electrode.

[0107] S220, forming a semiconductor functional structure, the semiconductor functional structure is located on one side of the interlayer dielectric layer leakage test structure, the semiconductor functional structure is located in the functional area of the semiconductor device, and the semiconductor functional structure comprises a semiconductor body, a second insulating layer, a gate, an interlayer dielectric layer, a source and a drain; the semiconductor body extends from the test area to the functional area, and the semiconductor body is set as a first conduction type; the semiconductor body further comprises a well region and a first region, the first region is set as the first conduction type and is located on the first surface, the well region is set as a second conduction type and is located on the side of the first region away from the first surface, and the first conduction type and the second conduction type are different; the second insulating layer extends from the test area to the functional area, and the second insulating layer is located on the first surface; the gate is located on the side of the second insulating layer away from the first surface; the gate and the first electrode layer are located in the same layer; the interlayer dielectric layer extends from the test area to the functional area, and the interlayer dielectric layer is located on the side of the gate away from the second insulating layer; the interlayer dielectric layer covers the gate; the interlayer dielectric layer is provided with a fourth through hole; the gate electrode is located on the side of the interlayer dielectric layer away from the first surface; the gate electrode is connected with the gate through the fourth through hole; the source is located on the first surface; the drain is located on the second surface; the first test electrode and the gate electrode are located in the same layer; and the second test electrode and the source are located in the same layer.

[0108] Reference Figure 2, the semiconductor functional structure 300 is formed on one side of the interlayer dielectric layer leakage test structure 200, the semiconductor functional structure 300 is located in the functional region 40 of the semiconductor device, and the semiconductor functional structure 300 comprises: the semiconductor body 100, the second insulating layer 302, the gate 50, the interlayer dielectric layer 400, the source 60, and the drain 70; the semiconductor body 100 extends from the test region 30 to the functional region 40, and the semiconductor body 100 is configured as a first conduction type; the semiconductor body 100 further comprises a well region 103 and a first region 104, the first region 104 is configured as the first conduction type and is located on the first surface 101, and the well region 103 is configured as a second conduction type and is located on a side of the first region 104 away from the first surface 101, the first conduction type and the second conduction type being different; the second insulating layer 302 extends from the test region 30 to the functional region 40, and the second insulating layer 302 is located on the first surface 101; the gate 50 is located on a side of the second insulating layer 302 away from the first surface 101; the gate 50 and the first electrode layer 303 are located in the same layer; the interlayer dielectric layer 400 extends from the test region 30 to the functional region 40, and the interlayer dielectric layer 400 is located on a side of the gate 50 away from the second insulating layer 302; the interlayer dielectric layer 400 covers the gate 50; the interlayer dielectric layer 400 is provided with a fourth through hole 403; the gate electrode 80 is located on a side of the interlayer dielectric layer 400 away from the first surface 101; the gate electrode 80 is connected with the gate 50 through the fourth through hole 403; the source 60 is located on the first surface 101; the drain 70 is located on the second surface 102; the first test electrode 501 and the gate electrode 80 are located in the same layer; and the second test electrode 502 and the source 60 are located in the same layer.

[0109] In the embodiment of the present application, the semiconductor functional structure 300 comprises but is not limited to an N-type MOSFET or a P-type MOSFET. For the N-type MOSFET, the first conduction type is N-type, and the second conduction type is P-type. For the P-type MOSFET, the first conduction type is P-type, and the second conduction type is N-type. For example, for the N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions of the N+ doped region can be phosphorus (P) ions or nitrogen (N) ions; and the well region 103 is a P-well region, and the P-type doping ions of the P-well region can be aluminum (Al) ions or boron (B) ions. The first region 104 can be formed on the first surface 101 of the semiconductor body 100 through ion implantation, ion diffusion, or vapor deposition process. The source 60 can be formed by depositing metal on the first surface 101. The drain 70 can be formed by depositing metal on the second surface 102. The deposited metal comprises but is not limited to silver or titanium.

[0110] The first test electrode 501 and the gate electrode 80 are located in the same layer; the gate electrode 80 is connected with the gate electrode 50 through the fourth via hole 403; the second test electrode 502 and the source electrode 60 are located in the same layer; the interlayer dielectric layer 400 extends from the test area 30 to the functional area 40; the leakage of the interlayer dielectric layer 400 is monitored in the interlayer dielectric layer leakage test structure 200, the voltage is controlled through the test electrode layer 500, and the leakage between the first test electrode 501 and the second test electrode 502 is tested, and a sufficient number of semiconductor functional structures 300 are used in the interlayer dielectric layer leakage test structure 200 to achieve the same effect as the semiconductor functional structure 300 and monitor the same effect, thereby improving the reliability of the semiconductor device.

[0111] In an optional embodiment of the present application, the semiconductor body 100 further comprises a second region 105, which can be a P+ doped region and located at the first surface 101. The ion concentration of the second region 105 is greater than that of the well region 103, and can form a good ohmic contact with the source electrode 60.

[0112] In an optional embodiment of the present application, a semiconductor body is provided, comprising: providing a semiconductor body comprising a silicon carbide semiconductor body or a silicon nitride semiconductor body.

[0113] In the formula, the reference Figure 2 The semiconductor body 100 comprises a silicon carbide semiconductor body, and the semiconductor functional structure 300 is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 comprises a gallium nitride semiconductor body, and the semiconductor functional structure 300 is a gallium nitride MOSFET semiconductor device.

[0114] The silicon carbide MOSFET semiconductor device or the gallium nitride MOSFET semiconductor device has the advantages of high withstand voltage, low on-resistance and high frequency, and can further improve the performance of the semiconductor device.

[0115] The embodiment of the present application provides a power module, which comprises a substrate and at least one semiconductor device provided by any of the embodiments of the present application, and the substrate is used for carrying the semiconductor device. Therefore, the power module has the beneficial effects of the semiconductor device provided by any of the embodiments of the present application, which will not be described here.

[0116] The embodiment of the present application provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion and power factor correction; the power conversion circuit comprises a circuit board and at least one semiconductor device provided by any of the embodiments of the present application, and the semiconductor device is electrically connected with the circuit board.

[0117] Therefore, the power conversion circuit has the beneficial effects of the semiconductor device provided by any of the embodiments of the present application, which will not be described here. Therefore, the power conversion circuit has the beneficial effects of the semiconductor device provided by any of the embodiments of the present application, which will not be described here.

[0118] The embodiments of the present application also provide a vehicle, which comprises a load and the power conversion circuit described above, and the power conversion circuit is used to convert AC into DC, convert AC into AC, convert DC into DC or convert DC into AC, and then input to the load.

[0119] Therefore, the vehicle comprises the beneficial effects of the power conversion circuit package described in any of the embodiments of the present application, which will not be repeated here.

[0120] It should be understood that the steps shown above can be reordered, added or deleted using various forms of flow. For example, the steps described in the present application can be executed in parallel, sequentially or in different order, as long as the desired results of the technical solutions of the present application can be achieved, which is not limited herein.

[0121] The specific embodiments described above do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that, include: An interlayer dielectric layer leakage current test structure, the interlayer dielectric layer leakage current test structure includes a semiconductor body, the semiconductor body includes a first surface and a second surface disposed opposite to each other; The interlayer dielectric layer leakage current test structure is located in the test area of ​​the semiconductor device; A first insulating layer is located on the first surface; Multiple second insulating layers are located on the side of the first insulating layer away from the first surface; the multiple second insulating layers are spaced apart. Multiple first electrode layers are located on the side of the second insulating layer away from the first insulating layer; the first electrode layers and the second insulating layers are arranged in a one-to-one correspondence. An interlayer dielectric layer is located on the side of the first electrode layer away from the second insulating layer; the interlayer dielectric layer is provided with a first through-hole and a second through-hole; the first through-hole extends from the side of the interlayer dielectric layer away from the first surface to the first electrode layer; the second through-hole extends from the side of the interlayer dielectric layer away from the first surface to the first insulating layer; A test electrode layer is located on the side of the interlayer dielectric layer away from the first surface; the test electrode layer includes a first test electrode and a second test electrode; the first test electrode is connected to the first electrode layer through the first through-hole; the second test electrode is connected to the first insulating layer through the second through-hole; the test electrode layer is provided with a third through-hole, the third through-hole being used to isolate the first test electrode and the second test electrode.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a semiconductor functional structure located on one side of the interlayer dielectric layer leakage test structure. The semiconductor functional structure is located in the functional region of the semiconductor device and includes: the semiconductor body, the second insulating layer, the gate, the interlayer dielectric layer, the source, and the drain. The semiconductor body extends from the test area to the functional area, and the semiconductor body is configured with a first conductivity type; the semiconductor body also includes a well region and a first region, the first region is configured with a first conductivity type and is located on the first surface, the well region is configured with a second conductivity type and is located on the side of the first region away from the first surface, and the first conductivity type and the second conductivity type are different; The second insulating layer extends from the test area to the functional area, and the second insulating layer is located on the first surface; The gate is located on the side of the second insulating layer away from the first surface; the gate and the first electrode layer are located in the same layer; The interlayer dielectric layer extends from the test region to the functional region, and is located on the side of the gate away from the second insulating layer; the interlayer dielectric layer covers the gate; the interlayer dielectric layer is provided with a fourth via; The gate electrode is located on the side of the interlayer dielectric layer away from the first surface; the gate electrode is connected to the gate electrode through the fourth via. The source electrode is located on the first surface; The drain electrode is located on the second surface; The first test electrode and the gate electrode are located in the same layer; The second test electrode and the source electrode are located in the same layer.

3. The semiconductor device according to claim 2, characterized in that, The semiconductor body includes a silicon carbide semiconductor body, or the semiconductor body includes a gallium nitride semiconductor body.

4. The semiconductor device according to claim 1, characterized in that, The first insulating layer comprises a first silicon oxide insulating layer; and / or, the second insulating layer comprises a second silicon oxide insulating layer.

5. The semiconductor device according to claim 1, characterized in that, The shapes of the projections of the first via and the second via onto the semiconductor body include polygons, wherein the number of sides of the polygon is greater than or equal to four.

6. The semiconductor device according to claim 1, characterized in that, The shapes of the projections of the first and second vias onto the semiconductor body also include circles.

7. A method for manufacturing a semiconductor device, characterized in that, include: Form a leakage current test structure for the interlayer dielectric layer; The interlayer dielectric layer leakage test structure includes a semiconductor body, which includes a first surface and a second surface disposed opposite to each other. The interlayer dielectric layer leakage current test structure is located in the test area of ​​the semiconductor device; A first insulating layer is located on the first surface; a plurality of second insulating layers are located on the side of the first insulating layer away from the first surface; the plurality of second insulating layers are spaced apart; a plurality of first electrode layers are located on the side of the second insulating layers away from the first insulating layer; the first electrode layers and the second insulating layers are arranged in a one-to-one correspondence; an interlayer dielectric layer is located on the side of the first electrode layers away from the second insulating layer; the interlayer dielectric layer is provided with a first through-hole and a second through-hole; the first through-hole extends from the side of the interlayer dielectric layer away from the first surface to the first electrode layer; the second through-hole extends from the side of the interlayer dielectric layer away from the first surface to the first insulating layer; a test electrode layer is located on the side of the interlayer dielectric layer away from the first surface; the test electrode layer includes a first test electrode and a second test electrode; the first test electrode is connected to the first electrode layer through the first through-hole; the second test electrode is connected to the first insulating layer through the second through-hole; the test electrode layer is provided with a third through-hole, the third through-hole being used to isolate the first test electrode and the second test electrode.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The interlayer dielectric layer leakage current test structure includes: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other; A first insulating layer is formed on the first surface; A plurality of second insulating layers are formed on the side of the first insulating layer away from the first surface; the plurality of second insulating layers are spaced apart. A plurality of first electrode layers are formed on the side of the second insulating layer away from the first insulating layer; the first electrode layers are disposed in a one-to-one correspondence with the second insulating layer. An interlayer dielectric layer is formed on the side of the first electrode layer away from the second insulating layer; the interlayer dielectric layer is provided with a first through-hole and a second through-hole; the first through-hole extends from the side of the interlayer dielectric layer away from the first surface to the first electrode layer; the second through-hole extends from the side of the interlayer dielectric layer away from the first surface to the first insulating layer; A test electrode layer is formed on the side of the interlayer dielectric layer away from the first surface; the test electrode layer includes a first test electrode and a second test electrode; the first test electrode is connected to the first electrode layer through the first through-hole; the second test electrode is connected to the first insulating layer through the second through-hole; the test electrode layer is provided with a third through-hole, the third through-hole being used to isolate the first test electrode and the second test electrode.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, An interlayer dielectric layer is formed on the side of the first electrode layer away from the second insulating layer, including: A transition interlayer dielectric layer is formed on the side of the first electrode layer away from the second insulating layer; A first via is formed in the interlayer dielectric layer; the first via extends from the side of the interlayer dielectric layer away from the first surface to the first electrode layer; A second via is formed in the transition interlayer dielectric layer; the second via extends from the side of the transition interlayer dielectric layer away from the first surface to the first insulating layer; the transition interlayer dielectric layer after forming the first via and the second via serves as the interlayer dielectric layer.

10. The method for manufacturing a semiconductor device according to claim 7, characterized in that, Also includes: A semiconductor functional structure is formed, located on one side of the interlayer dielectric layer leakage test structure. The semiconductor functional structure is situated within the functional region of the semiconductor device. The semiconductor functional structure includes: a semiconductor body, a second insulating layer, a gate, the interlayer dielectric layer, a source, and a drain. The semiconductor body extends from the test region to the functional region and is configured with a first conductivity type. The semiconductor body further includes a well region and a first region. The first region is configured with the first conductivity type and is located on the first surface. The well region is configured with the second conductivity type and is located on the side of the first region away from the first surface. The first conductivity type and the second conductivity type are different. The second insulating layer extends from the test region... The test area extends to the functional area, and the second insulating layer is located on the first surface; the gate is located on the side of the second insulating layer away from the first surface; the gate and the first electrode layer are located on the same layer; the interlayer dielectric layer extends from the test area to the functional area, and the interlayer dielectric layer is located on the side of the gate away from the second insulating layer; the interlayer dielectric layer covers the gate; the interlayer dielectric layer is provided with a fourth via; the gate electrode is located on the side of the interlayer dielectric layer away from the first surface; the gate electrode is connected to the gate through the fourth via; the source is located on the first surface; the drain is located on the second surface; the first test electrode and the gate electrode are located on the same layer; the second test electrode and the source are located on the same layer.

11. The method for manufacturing a semiconductor device according to claim 8, characterized in that, Provide semiconductor bodies, including: Provide a semiconductor body including a silicon carbide semiconductor body or a silicon nitride semiconductor body.

12. A power module, characterized in that, The device includes a substrate and the semiconductor device according to any one of claims 1-6, wherein the substrate is used to support the semiconductor device.

13. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-6, wherein the semiconductor device is electrically connected to the circuit board.

14. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 13, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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