Ten-layer circuit board production process

Abstract

The invention discloses a ten-layer circuit board production process. The ten-layer circuit board production process comprises the following steps: (1) material distribution; (2) manufacturing an inner layer; (3) pressing; (4) first drilling; (5) a degumming process: step 1, degumming with supercritical CO2; secondly, plasma degumming and strengthening are carried out, O2 / CF4 mixed gas is adopted, and the radio frequency power is 1500 W; (6) primary PTHs / electroplating: ultrasonic microetching is carried out before chemical copper deposition, and the frequency is 40kHz; adding sodium 3, 3 '-dithiodipropane sulfonate and polyethyleneimine into the electroplating solution; (7) first tree plugging / grinding; (8) micro-etching copper reduction; (9) performing second drilling, namely a blind hole; (10) secondary degumming + PTHs / electroplating: blind hole degumming and a vacuum-assisted permeation process are added; (11) drying the film on the outer layer; (12) outer layer etching / AOI: an AOI system is integrated with an AI defect recognition algorithm, and the copper nodule detection sensitivity is 10 microns; (13) performing solder mask; (14) characters are obtained; (15) chemical gold plating; (16) shape fishing; (17), V-cut is carried out; (18) electrical testing; (19) carrying out AVI; and (20) packaging. The occurrence rate of copper nodules is lower than 0.3%, and the qualified rate of through hole resistance is larger than 99.5%.

Description

Technical Field

[0001] This invention relates to the field of circuit board processing, and more specifically to a ten-layer circuit board manufacturing process. Background Technology

[0002] Chinese patent application publication number CN 113923866 A, published on January 11, 2022, discloses a processing method for improving the blockage of vias in PTFE circuit boards. This method belongs to the field of PTFE circuit board manufacturing technology. The processing method includes: cutting a double-sided copper-clad laminate (CCL), with the middle layer being a PTFE board layer; selecting a first drill bit to drill through the CCL for the first time, obtaining vias; first using a plasma desmearing machine to remove adhesive from the CCL, then performing a first copper plating on the CCL to adhere a copper layer to the via wall; selecting a second drill bit with a diameter 0.05 mm smaller than the first drill bit to drill through the via a second time, removing and expelling the copper nodules generated during the first copper plating; and first using a plasma desmearing machine to remove adhesive from the CCL, then performing a second copper plating on the CCL. The first copper plating process fully elongates the burrs generated during the first drilling, and the second drilling cuts and removes these burrs, preventing blockage of the PTFE circuit board's vias. However, this existing technology has the following drawback in the production process: incomplete chemical desmearing leads to copper nodules inside the holes after electroplating. Therefore, improvement is urgently needed. Summary of the Invention

[0003] To address the above problems, this invention provides a ten-layer circuit board manufacturing process with a copper nodule incidence rate of less than 0.3% and a through-hole resistance pass rate of greater than 99.5%.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A manufacturing process for a ten-layer circuit board includes the following steps:

[0006] (1) Material preparation: The substrate pretreatment is vacuum baking with parameters of 150℃ / 2h;

[0007] (2) Inner layer fabrication: After pattern transfer, acidic etching solution CuCl2 / H2O2 is used instead of alkaline etching;

[0008] (3) Pressing: The interlayer is pre-filled with nano-silica modified resin into the blind holes;

[0009] (4) First drilling: Use a diamond-coated drill bit;

[0010] (5) Adhesive removal process:

[0011] Step 1: Supercritical CO2 degumming, with parameters of CO2 pressure 25MPa, temperature 60℃, and time 45min;

[0012] Step 2: Plasma debonding and strengthening, using O2 / CF4 mixed gas, RF power 1500W;

[0013] (6) One-time PTH / electroplating: Ultrasonic micro-etching is performed before chemical copper plating at a frequency of 40kHz; sodium polydisulfide dipropane sulfonate and polyethyleneimine are added to the electroplating solution.

[0014] (7) First resin plug / grinding: After the resin plugs the holes, laser depth grinding is used with an accuracy of ±5μm;

[0015] (8) Micro-etching to reduce copper: using a sodium persulfate-sulfuric acid system;

[0016] (9) Second borehole - blind hole: nitrogen protection and sealing immediately after drilling;

[0017] (10) Secondary descaling + PTH / electroplating: Blind hole descaling with vacuum-assisted penetration process;

[0018] (11) Outer dry film: The dry film pre-lamination adopts hot roller pressing technology with parameters of 80℃ / 0.5MPa;

[0019] (12) Outer layer etching / AOI: The AOI system integrates AI defect recognition algorithm, with copper nodule detection sensitivity of 10μm;

[0020] (13) Solder resist: Polytetrafluoroethylene microparticles are added to the ink;

[0021] (14), text;

[0022] (15) Gold plating: Plasma cleaning is added before gold plating;

[0023] (16) Scooping type;

[0024] (17) V-cut: The V-cut adopts a laser real-time monitoring system with a depth error ≤ ±0.02mm;

[0025] (18) Electrical measurement;

[0026] (19) AVI: AVI system integrated 3D confocal microscope;

[0027] (20) Packaging.

[0028] Preferably, the degumming process in step (5) is implemented in step (10) using a vacuum-assisted permeation process, with a vacuum pressure range of -85 kPa to -95 kPa.

[0029] Preferably, the O2 / CF4 mixed gas ratio in step (5) is 7±0.5:3±0.5.

[0030] Preferably, in step (6), the concentration of sodium polydisulfide dipropane sulfonate is 4–6 ppm and the concentration of polyethyleneimine is 45–55 ppm.

[0031] Preferably, the AI ​​defect identification algorithm in step (12) includes a convolutional neural network model, and the training dataset contains 100,000 copper nodule microscopic images.

[0032] Preferably, the silica particle size in the nano-silica modified resin of step (3) is 20–50 nm, and the amount added is 3–5 wt% of the total resin.

[0033] Preferably, the diamond-coated drill bit of step (4) has a coating thickness of 8–12 μm and a Vickers hardness ≥9000 HV.

[0034] Preferably, the 3D confocal microscope in step (19) has a longitudinal resolution of 0.1 μm and a scanning speed of ≥5 mm. 2 / s.

[0035] Preferably, the degumming process parameters in step (10) are the same as those in step (5), and the vacuum-assisted permeation process is only applied to blind holes.

[0036] Preferably, in the hot roller pressing technology of step (11), the temperature uniformity deviation of the roller surface is ≤ ±2℃.

[0037] The beneficial effects of this invention are as follows: by using supercritical desiccant to dissolve deep resin, plasma-enhanced removal of residues, vacuum penetration to ensure clean blind holes, sodium dithiopropane sulfonate to inhibit the reduction rate of copper ions, and polyethyleneimine to smooth the electroplating layer, a good copper nodule inhibition effect is achieved, with a copper nodule incidence rate ≤0.3% and a through-hole resistance qualification rate ≥99.5%.

[0038] Instruction manual illustrations

[0039] Figure 1 This is a flowchart of the present invention. Detailed Implementation

[0040] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments, but the implementation of the present invention is not limited thereto.

[0041] A manufacturing process for a ten-layer circuit board includes the following steps:

[0042] (1) Material preparation: The substrate pretreatment is vacuum baking with parameters of 150℃ / 2h;

[0043] (2) Inner layer fabrication: After pattern transfer, acidic etching solution CuCl2 / H2O2 is used instead of alkaline etching;

[0044] (3) Pressing: The interlayer is pre-filled with nano-silica modified resin into the blind hole; the silica particle size in the nano-silica modified resin is 20-50nm, and the amount added is 3-5wt% of the total amount of resin; the burr height of the hole wall after drilling is ≤5μm;

[0045] (4) First drilling: Use diamond-coated drill bits; the coating thickness of the diamond-coated drill bits is 8–12 μm, and the Vickers hardness is ≥9000HV; the life of the drill bit is extended to 3000 holes / time, and the burr rate at the hole opening is ≤0.1%;

[0046] (5) Adhesive removal process:

[0047] Step 1: Supercritical CO2 degumming, with parameters of CO2 pressure 25MPa, temperature 60℃, and time 45min;

[0048] Step 2: Plasma desmearing and strengthening, using O2 / CF4 mixed gas with a ratio of 7±0.5:3±0.5 and RF power of 1500W; the hole wall roughness is reduced to Ra≤1.2μm, and the uniformity of the electroplated copper layer is improved.

[0049] (6) One-time PTH / electroplating: Ultrasonic micro-etching is performed before chemical copper plating at a frequency of 40kHz; sodium polydisulfide dipropane sulfonate and polyethyleneimine are added to the electroplating solution; the concentration of sodium polydisulfide dipropane sulfonate is 4–6ppm and the concentration of polyethyleneimine is 45–55ppm; the copper deposition rate deviation is ≤5%, and the formation of hollow copper nodules is inhibited.

[0050] (7) First resin plug / grinding: After the resin plugs the holes, laser depth grinding is used with an accuracy of ±5μm;

[0051] (8) Micro-etching to reduce copper: using a sodium persulfate-sulfuric acid system;

[0052] (9) Second borehole - blind hole: nitrogen protection and sealing immediately after drilling;

[0053] (10) Secondary desmearing + PTH / electroplation: Vacuum-assisted penetration process is added to the desmearing of blind holes, with a vacuum pressure range of -85kPa to -95kPa; the resin residue removal rate of deep blind holes is increased to 99.8%, avoiding microporous copper nodules; the desmearing process parameters of step (10) are consistent with those of step (5), and the vacuum-assisted penetration process is only applied to blind holes, with a difference of ≤0.2% between the desmearing pass rate of blind holes and through holes in ten-layer boards;

[0054] (11) Outer dry film: The dry film pre-lamination adopts hot roller pressing technology with parameters of 80℃ / 0.5MPa; the temperature uniformity deviation of the roller surface in the hot roller pressing technology is ≤±2℃; the dry film bubble occurrence rate is reduced to below 0.3%;

[0055] (12) Outer layer etching / AOI: The AOI system integrates an AI defect recognition algorithm with a copper nodule detection sensitivity of 10μm; the AI ​​defect recognition algorithm includes a convolutional neural network model, and the training dataset contains 100,000 copper nodule microscopic images; the false detection rate is ≤0.1%, and the false negative rate is ≤0.05%.

[0056] (13) Solder resist: Polytetrafluoroethylene microparticles are added to the ink;

[0057] (14), text;

[0058] (15) Gold plating: Plasma cleaning is added before gold plating;

[0059] (16) Scooping type;

[0060] (17) V-cut: The V-cut adopts a laser real-time monitoring system with a depth error ≤ ±0.02mm;

[0061] (18) Electrical measurement;

[0062] (19) AVI: AVI system integrated 3D confocal microscope; the longitudinal resolution of the 3D confocal microscope is 0.1μm, and the scanning speed is ≥5mm. 2 / s; Copper nodule three-dimensional positioning accuracy ±2μm;

[0063] (20) Packaging.

[0064] In this embodiment, supercritical desmearing dissolves deep resin, plasma-enhanced removal removes residues, vacuum penetration ensures clean blind holes, sodium dithiopropane sulfonate inhibits the reduction rate of copper ions, and polyethyleneimine smooths the electroplating layer. These steps work together to achieve a good copper nodule suppression effect, with a copper nodule incidence rate ≤0.3% and a through-hole resistance pass rate ≥99.5%.

[0065] The above embodiments illustrate only one implementation of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A manufacturing process for a ten-layer circuit board, characterized in that, Includes the following steps: (1) Material preparation: The substrate pretreatment adopts vacuum baking with parameters of 150℃ / 2h; (2) Inner layer fabrication: After pattern transfer, acidic etching solution CuCl2 / H2O2 is used instead of alkaline etching; (3) Pressing: The interlayer is pre-filled with nano-silica modified resin into the blind holes; (4) First drilling: Use a diamond-coated drill bit; (5) Adhesive removal process: Step 1: Supercritical CO2 degumming, with parameters of CO2 pressure 25MPa, temperature 60℃, and time 45min; Step 2: Plasma debonding and strengthening, using O2 / CF4 mixed gas, RF power 1500W; (6) One-time PTH / electroplating: Ultrasonic micro-etching is performed before chemical copper plating at a frequency of 40kHz; sodium polydisulfide dipropane sulfonate and polyethyleneimine are added to the electroplating solution. (7) First resin plug / grinding: After the resin plug is used, laser depth grinding is performed with an accuracy of ±5μm; (8) Micro-etching to reduce copper: using a sodium persulfate-sulfuric acid system; (9) Second borehole - blind hole: nitrogen protection and sealing immediately after drilling; (10) Secondary descaling + PTH / electroplating: Blind hole descaling with vacuum-assisted penetration process; (11) Outer dry film: The dry film pre-lamination adopts hot roller pressing technology with parameters of 80℃ / 0.5MPa; (12) Outer layer etching / AOI: The AOI system integrates an AI defect recognition algorithm, with a copper nodule detection sensitivity of 10μm; (13) Solder resist: Polytetrafluoroethylene microparticles are added to the ink; (14), text; (15) Gold plating: Plasma cleaning is added before gold plating; (16) Scooping type; (17) V-cut: The V-cut adopts a laser real-time monitoring system with a depth error ≤ ±0.02mm; (18) Electrical measurement; (19) AVI: AVI system integrated 3D confocal microscope; (20) Packaging.

2. The manufacturing process for a ten-layer circuit board according to claim 1, characterized in that, The degumming process in step (5) is implemented in step (10) using a vacuum-assisted permeation process with a vacuum pressure range of -85 kPa to -95 kPa.

3. The manufacturing process for a ten-layer circuit board according to claim 1, characterized in that, In step (5), the ratio of O2 / CF4 mixed gas is 7±0.5:3±0.

5.

4. The manufacturing process for a ten-layer circuit board according to claim 1, characterized in that, In step (6), the concentration of sodium polydisulfide dipropane sulfonate is 4–6 ppm and the concentration of polyethyleneimine is 45–55 ppm.

5. The manufacturing process for a ten-layer circuit board according to claim 1, characterized in that, The AI ​​defect identification algorithm in step (12) includes a convolutional neural network model, and the training dataset contains 100,000 copper lumps microscopic images.

6. The manufacturing process for a ten-layer circuit board according to claim 1, characterized in that, The silica particles in the nano-silica modified resin of step (3) have a particle size of 20–50 nm and are added in an amount of 3–5 wt% of the total resin.

7. The manufacturing process for a ten-layer circuit board according to claim 1, characterized in that, The diamond-coated drill bit of step (4) has a coating thickness of 8–12 μm and a Vickers hardness ≥9000 HV.

8. The manufacturing process for a ten-layer circuit board according to claim 1, characterized in that, The 3D confocal microscope used in step (19) has a longitudinal resolution of 0.1 μm and a scanning speed of ≥5 mm. 2 / s.

9. The manufacturing process for a ten-layer circuit board according to claim 1, characterized in that, The degumming process parameters in step (10) are the same as those in step (5), and the vacuum-assisted permeation process is only applied to blind holes.

10. A ten-layer circuit board manufacturing process according to claim 1, characterized in that, In the hot roller pressing technology of step (11), the temperature uniformity deviation of the roller surface is ≤ ±2℃.

Images