Method for optimizing multi-phase quantization error inconsistency of SAR-ADC

Abstract

The invention provides a method for optimizing multi-phase quantization error inconsistency of SAR-ADC, and the method comprises the steps: S1, obtaining output data of a plurality of parallel SAR-ADC sub-channels, and enabling the output data to form high-speed data; s2, defining an initial phase, and assuming that N parallel sub-channels exist and N phases exist, so that 0 phase / 1 phase / ... / (N-1) phase is obtained; s3, N phases correspond to N accumulators, and each accumulator completes accumulation of corresponding phase data and performs mean value calculation; s4, each sampling point of the state machine controls N phases to complete accumulation of the N phases; and S5, according to sampling point time control, corresponding phase accumulation is completed, an average value is solved, and a state machine controls the corresponding phase average value to carry out cancellation. The method solves the problem of multiphase quantization error inconsistency, not only has theoretical value for improving SAR-ADC performance, but also has engineering significance for application scenes such as high-precision radar, millimeter wave communication and medical imaging.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of wideband wireless communication systems, in particular to a method for optimizing SAR-ADC multi-phase quantization error inconsistency. BACKGROUND

[0002] With the development of Internet of Things, 5G communication and high-speed data acquisition system, successive approximation register analog-to-digital converter (SAR-ADC) has become one of the core components of mixed signal system due to its low power consumption, high energy efficiency and medium resolution. In order to further improve the conversion rate or reduce the load of single channel, multi-phase implementation structure (such as time interleaving, segmented quantization or parallel sub-channel architecture) is widely used. However, the core challenge of multi-phase structure lies in the difference of non-ideal characteristics between each phase or sub-channel, especially the inconsistency of multi-phase quantization error, which seriously restricts the optimization of overall system performance. The essence of this problem lies in the manufacturing process deviation, dynamic environmental disturbance and circuit nonlinear coupling effect, which leads to significant differences in statistical distribution, amplitude-frequency characteristics and nonlinear behavior of quantization error between each phase, and further causes systematic defects such as harmonic distortion, signal-to-noise ratio reduction and dynamic range compression.

[0003] In traditional single-channel SAR-ADC, the calibration of quantization error mainly focuses on the compensation of static errors such as capacitor mismatch and comparator offset, and the calibration algorithm is usually based on statistical learning or closed-loop feedback mechanism. However, the introduction of multi-phase architecture makes the error characteristics expand from single dimension to multi-dimensional space. For example, in time-interleaved SAR-ADC, the sampling time deviation (timing mismatch) and capacitor weight error (amplitude mismatch) of each sub-channel will jointly act to form frequency domain image spur; while in segmented quantization structure, the nonlinear charge distribution between adjacent sub-channels may cause cascading error accumulation. More complex is that the signal coupling between multi-phases (such as power supply crosstalk, substrate noise) will lead to dynamic correlation of errors, making the traditional independent channel calibration method invalid. Studies have shown that in multi-phase SAR-ADC with resolution above 8 bits, only 0.1% of the inter-channel gain mismatch can cause the spurious-free dynamic range (SFDR) to decrease by more than 10 dB, highlighting the necessity of multi-phase error collaborative control.

[0004] Current research on multi-phase quantization error still has significant limitations. First, existing calibration techniques are mostly based on static or quasi-static assumptions, ignoring the dynamic error propagation mechanism under multi-phase interaction. For example, although blind calibration methods based on output code statistical distribution can suppress fixed mismatches, they are difficult to track time-varying errors caused by temperature and voltage fluctuations. Second, the coupling effect of multi-phase errors makes it difficult for single-parameter calibration to converge globally. Taking capacitance mismatch as an example, traditional gradient descent algorithms can effectively optimize weights in a single channel, but may fall into local optimum in a multi-phase structure due to channel interference. In addition, the nonlinear superposition of timing errors (such as clock jitter and aperture delay difference) and quantization errors in high-speed applications further increases the complexity of modeling and separation. Therefore, it is urgent to establish a unified analysis framework for multi-phase quantization error and develop adaptive collaborative calibration strategies.

[0005] Solving the inconsistency problem of multi-phase quantization error not only has theoretical value in improving the performance of SAR-ADC, but also has engineering significance for application scenarios such as high-precision radar, millimeter-wave communication, and medical imaging. This paper will start from the time-frequency domain coupling mechanism of multi-phase error, combine statistical learning and dynamic system theory, and propose an error decoupling method based on multi-dimensional feature extraction, with the aim of achieving efficient adaptive calibration of multi-phase SAR-ADC and providing technical support for the next generation of high-speed high-precision data conversion systems. SUMMARY

[0006] The purpose of the present application is to provide a method for optimizing the inconsistency of multi-phase quantization error of SAR-ADC to solve the problems raised in the background art.

[0007] To achieve the above purpose, the present application provides the following technical scheme: a method for optimizing the inconsistency of multi-phase quantization error of SAR-ADC, comprising:

[0008] S1: Obtain the output data of a plurality of parallel SAR-ADC sub-channels and group them into high-speed data;

[0009] S2: Define the initial phase, assuming there are N parallel sub-channels, there are N phases, so 0 phase / 1 phase / … / (N-1) phase;

[0010] S3: N phases correspond to N accumulators, each accumulator completes the accumulation of the corresponding phase data and takes the mean value;

[0011] S4: The state machine controls N phases to complete the accumulation of N phases at each sample point;

[0012] S5: According to the sample time control, the corresponding phase accumulation is taken to the mean value, and the state machine controls the corresponding phase mean value to do cancellation.

[0013] Preferably, the N phase data in step S2 are accurately completed for corresponding accumulation summation, and the independent phase is completed for cancellation in the form of mean value.

[0014] Preferably, the mean value of the multi-phase independent calculation is completed for corresponding cancellation of the phase at the corresponding moment.

[0015] Preferably, after the SAR-ADC completes the initialization configuration, the SAR-ADC optimization correction is directly performed, and the SAR-ADC device is directly started to ensure that it works in the optimal performance state.

[0016] Preferably, the high-speed data path is selected from a plurality of data paths for testing, a consistent clock data pattern is driven on one or more of the remaining data paths in the plurality of data paths, wherein the consistent clock data pattern is consistent with a low-speed base clock, the first high-speed data path is sampled through the consistent clock data pattern to generate a sampled first high-speed data path, and finally the data in the sampled first high-speed data path is compared with the data in the first high-speed data path at the speed of the low-speed base clock.

[0017] Preferably, in step S4, the plurality of states of the state machine are coded as state codes, each state corresponding to a state code having only one bit different from other bits, the number of bits of the state code is the same as the number of states of the state machine, the state code of the current state of the state machine and the input data obtain the state code of the next state of the state machine and the output data through combination logic, the state code of the next state of the state machine is parity checked to obtain a parity check bit; and whether the state code of the next state of the state machine is correct is determined according to the parity check bit.

[0018] Preferably, the parity check of the state code of the next state of the state machine obtains a parity check bit, including: if the number of bits of 1 in the state code of the next state of the state machine is odd, the parity check bit is 1; if the number of bits of 1 in the state code of the next state of the state machine is even, the parity check bit is 0.

[0019] Preferably, the correction method of the multi-phase quantization error comprises:

[0020] (1) a model is established, wherein an input signal is defined as x(n);

[0021] (2) the accumulation length M of the mean value estimation algorithm corresponding to the phase is calculated, each phase is calculated for M length, and the output of N*M high-speed samples is actually completed, wherein the mean value estimation algorithm is to calculate the mean value of the signal in a certain phase in a certain period of time:

[0022]

[0023] (3) output y p1 The (n+M+1) signal is the DC offset estimated at the (n+M+1) time point before the input signal is cancelled at the M time point.

[0024] Compared with the prior art, the present application has the following beneficial effects:

[0025] (1) The quantization noise of the ADC of the present application theoretically satisfies Gaussian distribution, the mean value is 0, and the variance is noise. The SAR-ADC structure implementation principle limits its theoretical performance, and the inconsistency of multi-phase quantization error will affect the performance, causing the re-generation of the received signal spectrum, and further affecting the key quantization index ENOB (effective bit width) of the ADC. Solving the inconsistency of multi-phase quantization error not only has theoretical value for improving the performance of SAR-ADC, but also has engineering significance for application scenarios such as high-precision radar, millimeter wave communication and medical imaging.

[0026] (2) In the present application, the state machine encodes the state by adopting a state code corresponding to each state, and only one bit is different from the other bits, and correspondingly adopts a parity check bit to check the state code, thereby solving the problem that the state machine cannot be determined whether it is in error in the state change process in the prior art, and realizing the rapid checking of the state code. In addition, the present application also provides two processing methods when the state code is in error, so that the next state of the state machine is idle or the next state of the state machine is still the current state, thereby reducing the resource waste caused by the state code error of the state machine, improving the stability of the state machine, and in the implementation of retrying the current state, when the state code is correct, it can be automatically restored, further improving the fault tolerance experience of the state machine. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0028] Figure 1 is the operation flowchart of the present application;

[0029] Figure 2 is the actual implementation structure diagram of the present application;

[0030] Figure 3 is the result diagram of the multi-phase quantization optimization without trigger enablement;

[0031] Figure 4 is the result diagram of the multi-phase quantization optimization with trigger enablement.

[0032] The objectives, functional characteristics and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application; the use of the terms "including", "comprising" and "having" and any variations thereof in the specification and claims and the description herein is intended to cover both the inclusive and exclusive cases.

[0035] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. It is expressly understood that any of the features, structures, or characteristics described in connection with an embodiment can be included in a similar or alternative embodiment.

[0036] Please refer to Figures 1-4 The test signal in the present application is a single tone with a deviation of 10M, the test downlink frequency point is 3.5G, the signal frequency point is 3.49GHz, the Transceiver chip is YXW9009, the chip is a TDD dedicated radio frequency Transver chip, the zero intermediate frequency receiving architecture, and the ORx receiving channel is a SAR-ADC structure, which is an 8-phase structure.

[0037] The implementation method of the present application comprises S1: initialization power-on, no external input signal, and the software operation logic register does not make SAR-ADC 8-phase quantization inconsistency optimization; S2: external input of a single tone signal with a frequency point of 3.49GHz, power-15dBm, gain ATT gear unchanged, software configuration enables multi-phase quantization error optimization estimation; S3: trigger multi-phase quantization cancellation; S4: analyze the spectrum difference between S1 and S3.

[0038] A method for optimizing SAR-ADC multi-phase quantization error inconsistency comprises the following steps:

[0039] S1: obtaining a plurality of parallel SAR-ADC sub-channel output data and grouping the data into high-speed data;

[0040] S2: define initial phase, assuming there are N parallel sub-channels, there are N phases, so 0 phase / 1 phase / … / (N-1) phase, N phase data to accurately complete the corresponding accumulation sum, in the form of mean independent phase to complete cancellation;

[0041] S3: N phases correspond to N accumulators, each accumulator completes the accumulation of the corresponding phase data and makes the mean;

[0042] S4: the state machine controls N phases to complete N phase accumulation every sample point; the state codes of multiple states of the state machine are coded as state codes, each state corresponds to a state code which has only one bit different from other bits, the number of bits of the state code is the same as the number of states of the state machine, the state code of the current state of the state machine and the input data obtain the state code of the next state of the state machine and the output data through combination logic, and the parity check of the state code of the next state of the state machine obtains a parity check bit; and whether the state code of the next state of the state machine is wrong is determined according to the parity check bit.

[0043] S5: according to the sample point control to complete the corresponding phase accumulation and averaging, the state machine controls the corresponding phase mean to do cancellation.

[0044] The mean of multi-phase independent calculation needs to complete the corresponding cancellation of the phase at the corresponding time. After the SAR-ADC completes the initialization configuration, the SAR-ADC optimization correction is directly performed, and the SAR-ADC device is directly started to ensure that it works in the optimal performance state. The high-speed data path is selected from a plurality of data paths to test the first high-speed data path, and a consistent clock data pattern is driven in one or more of the remaining data paths in the plurality of data paths, wherein the consistent clock data pattern is consistent with the low-speed base clock, and the first high-speed data path is sampled through the consistent clock data pattern to generate a sampled first high-speed data path, and finally the data in the sampled first high-speed data path is compared with the data in the first high-speed data path at the speed of the low-speed base clock.

[0045] The step division of the above various methods is only for clear description, and can be combined into one step or split into multiple steps in implementation, as long as the same logical relationship is included, all are within the protection scope of the patent; adding irrelevant modifications or introducing irrelevant designs in the algorithm or process, but not changing the core design of the algorithm and process are within the protection scope of the patent.

[0046] The parity check of the state code of the next state of the state machine obtains a parity check bit, including: if the number of bits of 1 in the state code of the next state of the state machine is odd, the parity check bit is 1; if the number of bits of 1 in the state code of the next state of the state machine is even, the parity check bit is 0. The state machine encodes the state by adopting the mode that only one bit of the state code corresponding to each state is different from other bits, and correspondingly adopts the parity check bit to check the state code, thereby solving the problem that whether the state machine is wrong in the state change process cannot be judged in the prior art, and realizing the rapid checking of the state code. In addition, the application also provides two processing modes when the state code is wrong, so that the next state of the state machine is the idle state or the next state of the state machine is still the current state, thereby, the resource waste caused by the state code error of the state machine can be reduced, the stability of the state machine is improved, in the implementation of retrying the current state, when the state code is correct, automatic recovery can be realized, and the fault tolerance experience of the state machine is further improved.

[0047] The application encodes the state by adopting the mode that only one bit of the state code corresponding to each state is different from other bits, and correspondingly adopts the parity check bit to check the state code, thereby solving the problem that whether the state machine is wrong in the state change process cannot be judged in the prior art, and realizing the rapid checking of the state code. In addition, the application also provides two processing modes when the state code is wrong, so that the next state of the state machine is the idle state or the next state of the state machine is still the current state, thereby, the resource waste caused by the state code error of the state machine can be reduced, the stability of the state machine is improved, in the implementation of retrying the current state, when the state code is correct, automatic recovery can be realized, and the fault tolerance experience of the state machine is further improved.

[0048] The correction method for the multi-phase quantization error comprises:

[0049] (1) a model is established, wherein an input signal is defined as x(n);

[0050] (2) the length M of the mean value estimation algorithm corresponding to the phase is accumulated, each phase is statistically completed in M length, and the output of N*M high-speed samples is actually completed, and the mean value estimation algorithm is to statistically complete the mean value of the signal in a phase in a period of time:

[0051]

[0052] (3) the output y p1 (n+M+1) signal is the direct current offset estimated at the time of n+M+1 before the cancellation of the input signal.

[0053] The quantization noise of ADC theoretically satisfies Gaussian distribution with mean value of 0 and variance of noise. The implementation principle of SAR-ADC structure limits its theoretical performance, and the inconsistent multi-phase quantization error will affect the performance, causing the re-generation of the received signal spectrum, and further affecting the key quantization index ENOB (effective bit width) of ADC. Solving the problem of inconsistent multi-phase quantization error not only has theoretical value for improving the performance of SAR-ADC, but also has engineering significance for application scenarios such as high-precision radar, millimeter wave communication and medical imaging.

[0054] The above-described and above-embodied examples are only used to illustrate the technical solutions of the present application, but not to limit the same; although the present application has been described in detail with reference to the foregoing examples, it should be understood by those skilled in the art that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for optimizing SAR-ADC polyphase quantization error inconsistency, characterized in that, The application relates to a multi-phase SAR-ADC quantization error correction method. S1: obtaining multiple parallel SAR-ADC sub-channel output data and combining the data into high-speed data; S2: defining initial phases, assuming that there are N phases corresponding to N parallel sub-channels, so that there are 0 phase / 1 phase / ... / (N-1) phase; S3: N phases correspond to N accumulators, each of which completes accumulation of data of the corresponding phase and calculates the mean value; S4: a state machine controls N phases to complete accumulation of N phases every sample point; S5: according to the sample point control, the corresponding phase accumulation is calculated, and the state machine controls the corresponding phase mean value to complete cancellation.

2. The method of claim 1, wherein: The N phase data in the step S2 accurately complete corresponding accumulation and summation, and the mean value of independent phases completes cancellation.

3. The method of claim 1, wherein: The mean value of the multi-phase independent calculation completes corresponding cancellation of the phase at the corresponding time.

4. The method of claim 1, wherein: After the SAR-ADC completes initialization configuration, SAR-ADC optimization correction is directly carried out, and the SAR-ADC device is directly started to ensure that the SAR-ADC device works in an optimal performance state.

5. The method of claim 1, wherein: The high-speed data path is selected from multiple data paths for testing, a consistent clock data pattern is driven on one or more of the remaining data paths in the multiple data paths, the consistent clock data pattern is consistent with a low-speed basic clock, the first high-speed data path is sampled through the consistent clock data pattern to generate a sampled first high-speed data path, and finally the data in the sampled first high-speed data path is compared with the data in the first high-speed data path at the speed of the low-speed basic clock.

6. The method of claim 1, wherein: The multiple states of the state machine in the step S4 are coded as state codes, each state code has only one bit different from other bits, the number of bits of the state code is the same as the number of states of the state machine, the state code of the current state of the state machine and input data obtain the state code of the next state of the state machine and output data through combination logic, the state code of the next state of the state machine is subjected to parity check to obtain a parity check bit, and whether the state code of the next state of the state machine is wrong is determined according to the parity check bit.

7. The method of claim 6, wherein: The parity check bit of the state code of the next state of the state machine includes: if the number of bits of 1 in the state code of the next state of the state machine is odd, the parity check bit is 1; and if the number of bits of 1 in the state code of the next state of the state machine is even, the parity check bit is 0.

8. The method of claim 1, wherein: The multi-phase quantization error correction method comprises the following steps: (1) establishing a model, wherein an input signal is defined as x(n); (2) the mean value estimation algorithm of the corresponding phase has an accumulation length M, each phase is statistically completed for M lengths, and N*M high-speed sample outputs are actually completed, and the mean value estimation algorithm is to statistically calculate the mean value of a signal in a phase in a period of time: (3) output y p1 (n + M + 1) signal is the DC offset estimated at time n + M + 1 before cancellation of the input signal at time n + M.

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