NOR type flash memory and operation method thereof

Abstract

A NOR-type flash memory suitable for protection of data requiring high reliability and a method of operating the same are provided. The NOR-type flash memory of the present invention comprises: a memory cell array comprising a plurality of memory cells; an ECC circuit that performs error detection and correction of data read from the boot save area of the memory cell array; a means for storing, in the startup management area, identification information for identifying the error form of the faulty memory cell that has been subjected to error detection and correction by the ECC circuit; and a recovery component that recovers the faulty memory cell based on the identified error form to eliminate the error of the faulty memory cell.

Description

Technical Field

[0001] This invention relates to a NOR flash memory and its operating method, and more particularly to a NOR flash memory equipped with ECC function. Background Technology

[0002] In NAND flash memory, repeated read / program / erase operations can cause threshold fluctuations due to degradation of the tunneling insulating film or Gm (transconductance), sometimes leading to bit errors. As a countermeasure against such bit errors, an error detection and correction function (hereinafter referred to as Error Checking and Correcting (ECC) function) is used (e.g., Japanese Patent No. 7253594).

[0003] NOR (Not OR, NOR) flash memory, because it connects memory cells in parallel, allows access to memory cells bit by bit. Therefore, it is less affected by disturbances and has a lower probability of bit errors compared to NAND flash memory. This makes it suitable for storing data with high reliability requirements, such as startup data or program code used to enable system operation.

[0004] In recent years, the amount of boot data or program code has increased. On the other hand, the miniaturization of NOR flash memory has also promoted the increase in memory capacity. Due to the miniaturization of storage cells, even NOR flash memory cannot ignore the occurrence of bit errors, and the integration of ECC functionality continues to be reviewed.

[0005] However, relying solely on ECC (Electronic Control Classification) to correct errors is insufficient to protect data requiring high reliability. For example, boot data is read from NOR flash memory during system startup or software activation. Since boot data is read more frequently than other data, the probability of errors occurring in the boot data is higher. If the number of errors exceeds the correction limit of the ECC function, the boot data errors cannot be corrected, which is fatal to a system that boots from that data. Summary of the Invention

[0006] The purpose of this invention is to solve this existing problem and provide a NOR flash memory suitable for protecting data requiring high reliability, and a method for operating the same.

[0007] The NOR flash memory of the present invention includes: a memory cell array including a plurality of memory cells; an ECC component for detecting and correcting errors in data read from the memory cell array; an error identification component for identifying the error patterns of faulty memory cells that have been detected and corrected by the ECC component; and a recovery component for recovering the faulty memory cells based on the identified error patterns to eliminate the errors in the faulty memory cells.

[0008] In one embodiment, when the threshold of the faulty memory cell representing the error mode decreases, the recovery component programs the faulty memory cell to raise the threshold. In one embodiment, the error identification component holds the address of the faulty memory cell, and the recovery component programs the faulty memory cell based on the address. In one embodiment, when the threshold of the faulty memory cell representing the error mode increases, the recovery component increases the read verification voltage of the faulty memory cell. In one embodiment, the error identification component stores the address of the faulty memory cell, and the recovery component increases the read verification voltage when reading the faulty memory cell based on the address. In one embodiment, the NOR flash memory further includes: a management component that manages the generation of faulty memory cells within sectors of the memory cell array; and a transmission component that, based on the management result of the management component, transmits data of the sector containing the faulty memory cell to a redundant area of ​​the memory cell array. In one embodiment, the memory cell array includes a boot data storage area that stores boot data, and the recovery component performs recovery of faulty memory cells storing boot data.

[0009] The operation method performed by the NOR flash memory of the present invention includes: a step of error detection and correction of data read from a memory cell array by means of an ECC component; a step of identifying the error pattern of a faulty memory cell that has been error detected and corrected by the ECC component; and a step of restoring the faulty memory cell based on the identified error pattern to eliminate the error of the faulty memory cell.

[0010] In one embodiment, when the threshold of the faulty memory cell decreases due to the error pattern, the recovery step programs the faulty memory cell to raise the threshold. In another embodiment, when the threshold of the faulty memory cell increases due to the error pattern, the recovery step increases the read verification voltage of the faulty memory cell.

[0011] According to the present invention, the faulty storage unit is restored to eliminate the error of the faulty storage unit that has undergone error detection and correction, thus giving the error detection and correction function of the ECC component a margin, thereby maintaining high data reliability. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating the schematic structure of a NOR flash memory according to an embodiment of the present invention;

[0013] Figure 2 This is a diagram illustrating an example of the structure of the startup storage area and the startup management area in an embodiment of the present invention;

[0014] Figure 3(A) shows an error that migrates along the direction of decreasing threshold of the storage cell, and Figure 3(B) is a diagram illustrating the recovery from the error.

[0015] Figure 4(A) shows an error migrating in the direction of increasing threshold of the storage cell, and Figure 4(B) is a diagram illustrating the recovery from the error.

[0016] Figure 5 This is the operation flow when the startup data of this embodiment is programmed;

[0017] Figure 6 This describes the operation flow when reading the startup data in this embodiment;

[0018] Figure 7 This is a diagram illustrating an example of the startup management region being updated during startup data reading;

[0019] Figure 8 This is the operation flow when replacing the startup data in another embodiment of the present invention.

[0020] Explanation of icon numbers

[0021] 100: NOR flash memory

[0022] 110: Memory cell array

[0023] 112: Start saving area

[0024] 114: Redundant Area

[0025] 120: Input / Output Circuit

[0026] 130: ECC circuit

[0027] 140: Address Register

[0028] 150: Controller

[0029] 160: Row selection circuit

[0030] 170: Sensing / Write Circuit

[0031] 180: Column Selection Circuit

[0032] 190: Internal voltage generation circuit

[0033] 200: RAM

[0034] 210: Start Management Area

[0035] Ax: Row address information

[0036] Ay: Column address information

[0037] ExCLK: Clock signal

[0038] S100, S110, S120, S200, S210, S220, S230, S240, S250, S260, S270, S300, S310, S320, S330: Steps

[0039] Vers: Erasure voltage

[0040] Vpgm: Programmed Voltage

[0041] Vread: Read voltage

[0042] VWL, VWL_R: Read verification voltage Detailed Implementation

[0043] The NOR flash memory of the present invention includes a memory management scheme that is suitable for protecting data requiring high reliability, such as startup data or program code read during system startup or software activation, and strives to eliminate errors in the stored data, thereby providing highly reliable data.

[0044] like Figure 1As shown, the NOR flash memory 100 of this embodiment is configured with the following components: a memory cell array 110, which forms a plurality of memory cells; an input / output circuit 120, which outputs read data to the outside or retrieves data input from the outside in sync with the clock signal ExCLK; an ECC circuit 130, which performs code generation for programmed data or error detection and correction of the read data; an address register 140, which receives address data via the input / output circuit 120; a controller 150, which controls the operation based on command data received via the input / output circuit 120 or control signals applied to external terminals; and a row selection circuit 160, which receives data from the address register 140. The system includes: a row address information Ax, a decoder for Ax, and a word line or sector selection based on the decoding result; a sensing / writing circuit 170, which reads data from the memory cell selected by the row selection circuit 160 or writes programmed data to the selected memory cell; a column selection circuit 180, which receives column address information Ay from the address register 140, decodes Ay, and performs bit line / source line selection based on the decoding result; and an internal voltage generation circuit 190, which generates various voltages (programming voltage Vpgm, read voltage Vread, erase voltage Vers, etc.) required for data reading, programming, and erasure.

[0045] The memory cell array 110 includes a plurality of memory cells configured in rows and columns, each of which is connected in parallel between a bit line and a source line. That is, it has a NOR structure. The memory cells can be two-dimensional structures formed on the surface of a substrate such as silicon, or three-dimensional structures formed perpendicularly from the substrate surface. Furthermore, the memory cells can be single-level cells (SLCs) storing binary data, or multilevel cells (MLCs) storing multi-level data.

[0046] Input / output circuit 120 receives commands, addresses, and data from the host system synchronously with clock signal ExCLK, and provides the received commands, addresses, and data to controller 150, address register 140, column select circuit 180, and sensing / writing circuit 170. Additionally, input / output circuit 120 receives data read from memory cell array 110 from sensing / writing circuit 170 and provides it to the host system.

[0047] ECC circuit 130 includes an encoder that encodes data to generate ECC codes, and a decoder that decodes data based on the ECC codes. During programmed operation, ECC circuit 130 generates ECC codes required for error detection and correction of the input data by performing operations on the bit rows of data input via input / output circuit 120. During read operation, error detection and correction of data read from memory cell array 110 are performed based on the ECC codes.

[0048] There is no particular limitation on the number of bits that can be used for error detection and correction by the ECC circuit 130. The ECC circuit 130 can use, for example, Hamming code, Reed-solomon codes, or Bose-Chaudhuri-Hocquenghem code (BCH code) for error detection and correction. In the case of BCH code, multi-bit (e.g., 2-bit, 4-bit, 8-bit) error detection and correction can be performed. Furthermore, the ECC circuit 130 can correct (bit-invert) erroneous bits in the read data held by the sensing / writing circuit 170. Alternatively, the ECC circuit 130 can also receive read data, perform error correction there, and output the error-corrected data to the sensing / writing circuit 170.

[0049] The controller 150 is composed of hardware and / or software resources, such as a microcontroller or state machine including read-only memory (ROM) / random access memory (RAM). The controller 150 receives commands from the host system and controls overall operations such as reading, programming, and erasing based on the commands.

[0050] During a read operation of a memory cell, a positive voltage is applied to the select word line via the row select circuit 160, and the current or voltage flowing between the select bit line and the select source line is read by the sensing / writing circuit 170. During a programmable (write) operation of a memory cell, a programming voltage is applied to the select word line via the row select circuit 160, and a voltage corresponding to the data to be programmed is applied to the select bit line via the sensing / writing circuit 170. Thermionic electrons flowing from the select bit line to the select source line accumulate in the charge accumulation layer. However, the write method can also be other than this, and charge can be captured in the charge accumulation layer through Fowler-Nordheim (FN) tunneling. Erasing a memory cell involves applying a voltage to the select word line, for example, injecting a thermoelectric hole into the charge accumulation layer, or applying an erase voltage to the substrate to allow the charge accumulated in the charge accumulation layer to be discharged through FN tunneling. Erasing of a memory cell can be performed on a sector-by-sector basis, or it can be performed on a cell-by-cell basis.

[0051] In this embodiment, the memory management scheme identifies the error type when a faulty memory cell (error bit) is detected by the ECC circuit 130; and restores the faulty memory cell according to the identified error type to eliminate the error. By restoring the faulty memory cell, error correction can be ensured within the range where error detection and correction can be performed by the ECC circuit 130, thereby improving data reliability.

[0052] In another embodiment, recovery of the faulty storage unit is performed during the replacement of the data in the faulty storage unit. That is, in parallel with the recovery of the faulty storage unit, the data stored in the faulty storage unit or the sector containing the faulty storage unit is transferred to a new redundant area, and the recovery of the faulty storage unit ends. The generation of a faulty storage unit is a precursor to a fault, and by avoiding the storage area where the faulty storage unit was generated, the generation of faulty storage units can be further suppressed.

[0053] The memory management scheme in this embodiment is implemented for data requiring high reliability. Here, boot data is used as an example of such data. Boot data (boot code) is data required for system operation and is protected to distinguish it from the data normally used by the user. Boot data is read from the memory cell array and provided to the external host system when the system is running or when the flash memory is powered on. If part of the boot data is lost or part is overwritten, it will cause obstacles to system operation. Therefore, high reliability is required for boot data.

[0054] Figure 2This diagram illustrates a schematic example of data stored in the memory cell array and RAM. The memory cell array 110 includes areas used by the user to store general data, as well as a startup save area 112 and a redundancy area 114 for storing startup data. On the other hand, the RAM 200 is volatile memory such as static random access memory (SRAM), and is provided, for example, in the controller 150. The RAM 200 includes a startup management area 210 for storing management information related to startup data. The startup save area 112 and the redundancy area 114 can be set in any address space of the memory cell array 110, and information related to the set address space is stored, for example, in the fuse ROM of the memory cell array 110. The fuse ROM stores various information related to the operation of the NOR flash memory 100. When the NOR flash memory 100 is started, the data stored in the fuse ROM is loaded into configuration registers, etc., and referenced by the controller 150.

[0055] Startup data is input via input / output circuit 120, and controller 150 writes the input startup data into the main area of ​​startup storage area 112. In addition, ECC circuit 130 performs calculations on the input startup data to generate ECC codes required for error detection and correction, and the generated ECC codes are written into the spare area of ​​startup storage area 112.

[0056] like Figure 2 As shown, the boot storage area 112 has multiple sectors #1 to #n (or multiple blocks). A memory cell connected to a word line is called a page, and a sector comprises multiple pages. A sector includes a main area accessible to the user and a spare area inaccessible to the user. Boot data is stored in the main area, and attribute information such as the ECC code of the boot data generated by the ECC circuit 130, which is written to the main area, is stored in the spare area. Furthermore, the ECC code of the boot data can be managed in units of sectors or pages.

[0057] On the other hand, the boot management area 210 of RAM 200 stores the following information: identification information indicating that a faulty memory cell (error bit) was detected by the ECC circuit 130 during a boot data read operation, or an ECC flag indicating that the faulty memory cell has been corrected, the address of the faulty memory cell, the error type of the faulty memory cell, and information related to the recovery of the faulty memory cell corresponding to the error type. Furthermore, although not illustrated here, the boot management area 210 may include a lookup table (LUT) that defines the address correspondence between the boot storage area 112 and the redundancy area 114.

[0058] The boot management area 210 is not specifically limited; for example, boot data in the boot storage area 112 can be managed in sectors. Figure 2 The image illustrates a management area, sector #1, used to store management information for sector #1 of the boot save region 112. Management area sector #1 includes a faulty memory cell, an ECC flag, the address of the faulty memory cell, identification of the faulty memory cell's error type, and recovery information corresponding to the error type.

[0059] For example, if a faulty memory cell FC1 is detected during the reading of startup data in sector #1, the faulty memory cell FC1 is logged in the management area_sector #1, an ECC flag indicating that the faulty memory cell FC1 is an error bit or has been error-corrected is set, and the address of the faulty memory cell FC1 is saved. Furthermore, the identification of the error pattern of the faulty memory cell FC1 is saved. In this example, data "0" indicating that the faulty memory cell FC1 has migrated from data "1" to data "0" is exemplified as identification information. In other words, it means that the faulty memory cell FC1 has been corrected from data "0" to data "1" by the ECC circuit 130.

[0060] Furthermore, if another faulty memory cell FC2 is detected during the reading of sector #1, the faulty memory cell FC2 is logged, its ECC flag is set, and its address is saved. As an identification of the error type of the faulty memory cell FC2, data "1" indicating that the faulty memory cell FC2 has migrated from data "0" to data "1" is shown here as identification information. In other words, it means that the faulty memory cell FC2 has been corrected from data "1" to data "0" through the ECC circuit 130.

[0061] Next, the relationship between error patterns and recovery will be explained. Figure 3(A) illustrates the error when data in a memory cell migrates from "0" to "1" (i.e., the threshold of the faulty memory cell decreases from □ to ■). The threshold of a memory cell programmed with data "0" must be greater than the read verification voltage VWL. However, in faulty memory cells where the threshold migrates to a direction less than the read verification voltage VWL, data "1" will still be read even though data "0" has been programmed. This is due to errors caused by charge loss accumulated in the memory cell, gradual threshold reduction, and deterioration of retention characteristics.

[0062] In this embodiment, as a recovery from this type of error based on retention characteristics, the address of the faulty memory cell is stored in the boot management region 210. Then, the faulty memory cell is overprogrammed so that at any given time, its threshold exceeds the read verification voltage VWL, and the faulty memory cell is refreshed. This scenario is shown in Figure 3(B) (the threshold of the faulty memory cell increases from □ to ■). For example, if the programming voltage at the time of the last programming is known, a programming voltage larger than the previous programming voltage can be applied to the faulty memory cell, causing the threshold of the memory cell to increase in the positive direction; if it is not known, overprogramming can be performed using the Incremental Step Pulse Program (ISPP) method, similar to the case of a normal memory cell. Finally, the overprogramming ends at the time point when the programming verification is successful. A flag indicating whether the overprogramming has ended is set in the recovery related to the faulty memory cell FC1 in the boot management region.

[0063] Unlike NAND flash memory, NOR flash memory uses parallel cell connections, making it easy to program only faulty cells and suppress programming interference to non-selectable cells, similar to NAND flash memory. By recovering faulty cells through over-programming, bit errors in the recovered faulty cells are not detected during the next boot data read. This provides a margin for the number of bits that can be used for error detection and correction using the ECC circuit 130, ensuring that the number of faulty bits in the boot data does not exceed the number of bits that can be detected and corrected using the ECC circuit 130, thereby improving the reliability of the boot data.

[0064] Figure 4(A) illustrates the error that occurs when data in a memory cell migrates from "1" to "0" (the threshold of the faulty memory cell increases from □ to ■). The threshold for data "1", i.e., the erased memory cell, must be less than the read verification voltage VWL. However, in faulty memory cells where the threshold migrates to a value greater than VWL, even though the data is erased to "1", data "0" will still be read. This is because the read frequency of startup data is higher than that of other data. When a memory cell with data "1" is read multiple times, Gm (transconductance) deteriorates due to the current flowing in the memory cell, causing the threshold to gradually rise and resulting in the error.

[0065] As a recovery measure against errors caused by an increased threshold, a new read verification voltage VWL_R is set to increase the read verification voltage VWL by ΔV when reading the faulty memory cell. ΔV can be set to a predetermined value (e.g., 0.2 V), which can be determined, for example, by empirical rules. Figure 4(B) illustrates the recovery process. The threshold of the recovered faulty memory cell is less than the new read verification voltage VWL_R, and during a read operation, the read data of the recovered faulty memory cell becomes "1". The newly set read verification voltage VWL_R is stored in the recovery of the faulty memory cell FC2 in the boot management region 210. Thus, during the next read, the recovered faulty memory cell will not be detected as an error bit, providing a margin for the number of bits that can be used for error correction using the ECC circuit 130, thereby improving the reliability of the boot data.

[0066] Furthermore, if the recovered faulty memory cell is detected as an error bit again by the ECC circuit 130, the read verification voltage VWL_R set in the startup management region 210 can be increased by ΔV.

[0067] Next, the operation of the NOR flash memory in this embodiment will be described. Figure 5 This describes the operation process of programming the boot data into the boot storage area. In the NOR flash memory 100, when the host system receives the command, address, and boot data for programming the boot data via the input / output circuit 120 (S100), the ECC circuit 130 processes the received boot data to generate an ECC code (S110).

[0068] The controller 150 controls the programming of the boot data based on the received command. Based on the address held in the address register 140, it programs the boot data and ECC code in the selected sector of the boot storage area 112 via the row selection circuit 160 and the column selection circuit 180 (S120). The boot data is written to the main area, and the ECC code is written to the spare area. Furthermore, if the location for storing the boot data is predetermined, it may not be necessary to receive the address from the host system. For example, if the address for storing the boot data is stored in the fuse ROM, the controller 150 can refer to the address stored in the fuse ROM to program the boot data into the boot storage area 112.

[0069] Next, the operation of reading startup data will be explained. When reading startup data, the controller 150 refers to the information stored in the startup management area 210 to control the reading of startup data and update the management information of startup data.

[0070] Figure 6This describes the process of reading startup data. When a command for reading startup data is received from the host system (S200), the controller 150 reads the management information corresponding to the selected sector of the startup storage area 112 from the startup management area 210, and detects that an ECC flag fault storage unit is set in the sector (S210). For example, during the read operation... Figure 2 When the startup data of sector #1 is shown, the controller 150 detects that ECC flag fault storage unit FC1 and fault storage unit FC2 are set.

[0071] When a faulty memory cell with an ECC flag is detected, the controller 150 performs read control corresponding to the error type (S220). Specifically, for a faulty memory cell corresponding to an error type of "1", read control is performed based on the address of the faulty memory cell stored in the boot management area 210, changing the read verification voltage when reading the faulty memory cell to the read verification voltage VWL_R set during recovery. On the other hand, for a faulty memory cell corresponding to an error type of "0", at an appropriate time point after error detection, the overprogramming of the faulty memory cell has been completed, and a recovery flag is set.

[0072] Next, the controller 150 applies a read verification voltage VWL to the word line when reading the selected memory cell, and applies a read verification voltage VWL_R to the word line when reading the faulty memory cell, and reads the startup data from the startup storage area (S230). During the reading of the startup data, the ECC circuit 130 detects whether a faulty memory cell (error bit) has been generated in the startup data based on the ECC code (S240). As described above, the recovered faulty memory cell is not detected as an error bit, but if a new error is generated in a memory cell other than the recovered faulty memory cell, the faulty memory cell is detected.

[0073] If an error is detected, the ECC circuit 130 corrects the error of the new faulty memory cell (S250), and the controller 150 updates the data related to the newly detected faulty memory cell to the boot management area (S260). For example, if a new faulty memory cell FC3 is detected during a read of sector #1, such as... Figure 7 As shown, fault storage unit FC3 is registered in sector #1 of the management area, the ECC flag is set and the address is saved, and the identification of the error mode is saved. In addition, the ECC flags of fault storage units FC1 and FC2 are rewritten to reset. Then, the read boot data is output to the host system via input / output circuit 120 (S270).

[0074] Thus, according to this embodiment, the error pattern of the faulty storage unit that has been detected and corrected by the ECC circuit 130 is identified, and the faulty storage unit is restored based on the error pattern, thereby ensuring the error detection and correction function of the ECC circuit 130 and maintaining the reliability of the startup data.

[0075] In the described embodiment, the boot management region 210 is located within the RAM 200 of the controller 150, but the data stored in the RAM 200 is lost when the NOR flash memory 100 is powered off. Therefore, ideally, during power-off sequencing of the NOR flash memory 100, the data in the boot management region 210 is backed up to non-volatile memory, such as the memory cell array 110. When the NOR flash memory 100 is restarted, the data in the boot management region is prevented from disappearing by loading the backed-up data into the boot management region 210.

[0076] Next, another embodiment will be described. In the above embodiment, the error correction function of the ECC circuit 130 is maximized by restoring the faulty storage unit, thus ensuring the reliability of the startup data. However, in this embodiment, the reliability of the startup data is further improved by limiting the recovery period.

[0077] The occurrence of a faulty memory cell is a precursor to a sector failure caused by multiple reads. Furthermore, performing recovery as shown in Figure 4(B) (increasing the read verification voltage) can easily lead to errors as shown in Figure 3(A) (the memory threshold shifts towards a value lower than the read verification voltage). Therefore, the recovery of persistent faulty memory cells increases the probability of faulty memory cell occurrences and reduces the reliability of boot data.

[0078] Therefore, in the described embodiment, a certain number of sectors of faulty storage units (referred to as faulty sectors for convenience) are determined to be unsuitable for protecting highly reliable data. The data stored in the faulty sectors is replaced in new sectors of the redundant area 114. After replacement, the data in the faulty sectors is erased, and the faulty sectors are reused as areas for storing general data. This replacement of faulty sectors is related to loss equalization to achieve equalization of the usage frequency of the storage unit array.

[0079] Figure 8 This describes the operation flow when replacing startup data. The controller 150, referring to the startup management area 210, determines whether a certain number of faulty memory units have been generated within the sector (S300). The startup management area 210 manages faulty memory units on a sector-by-sector basis, storing the history of the faulty memory units generated within the sector. The "certain number" can be arbitrarily determined; for example, it can be one faulty memory unit or multiple faulty memory units.

[0080] When the controller 150 determines that a certain number of faulty storage units have occurred within a sector, it transfers the data of the sector to a new sector in the redundancy area 114 (S310). When replacing data between sectors, the controller 150 registers the relationship between the address of the source sector and the address of the destination sector in a lookup table in the startup management area 210 and establishes an association between the two (S320). After the transfer is completed, the controller 150 erases the data of the faulty sector of the source sector (S330).

[0081] Thus, when a certain number of faulty memory cells occur within a sector, replacing the boot data with new sectors can protect the boot data, minimizing its errors and improving its reliability. Furthermore, replacing the boot data can equalize the usage frequency of sectors within the memory cell array.

[0082] Next, a variation will be described. In the above embodiment, the boot data is replaced when a certain number of faulty memory cells are generated within a sector. However, in this variation, the controller 150 refers to the ECC flags of the boot management region. When at least one ECC flag is detected in a sector, the controller transmits the boot data of that sector to a sector in the redundant region. After the data transmission is completed, the controller 150 erases the data from the sector that was the source of the transmission.

[0083] In the description of the embodiments, boot data (boot code) is illustrated as data requiring high reliability. However, this data is not limited to boot data and can also be other specific data that should be protected, which can be arbitrarily defined by the user. In addition, the embodiment illustrates an example of storing the ECC flag in the boot management area. This is just one example; the ECC flag can also be stored in the spare area within a sector.

[0084] Preferred embodiments of the present invention have been described in detail, but the present invention is not limited to specific embodiments and various modifications and alterations can be made within the scope of the spirit of the invention as described in the claims.

Claims

1. A NOR flash memory, characterized in that, The NOR flash memory includes: A storage cell array, comprising multiple storage cells; An error checking and correction component performs error detection and correction on the data read from the storage cell array; An error identification component identifies the error patterns of faulty storage units that have undergone error detection and correction by the error checking and correction component; and The recovery component recovers the faulty storage unit based on the identified error pattern to eliminate the error in the faulty storage unit.

2. The NOR flash memory according to claim 1, characterized in that, When the error pattern indicates a decrease in the threshold of the storage cell, the recovery component programs the faulty storage cell to raise the threshold.

3. The NOR flash memory according to claim 2, characterized in that, The error identification component stores the address of the fault storage unit. The recovery component programs the faulty storage unit based on the address.

4. The NOR flash memory according to claim 1, characterized in that, When the threshold of the faulty storage cell increases, the recovery component increases the read verification voltage of the faulty storage cell.

5. The NOR flash memory according to claim 4, characterized in that, The error identification component stores the address of the fault storage unit. The recovery component increases the read verification voltage when reading the faulty storage unit based on the address.

6. The NOR flash memory according to claim 1, characterized in that, The NOR flash memory also includes: The management component manages the generation of faulty memory cells within sectors of the memory cell array; and The transmission component, based on the management result of the management component, transmits the data of the sector containing the faulty storage unit to the redundant area of ​​the storage unit array.

7. The NOR flash memory according to claim 1, characterized in that, The storage unit array includes a boot data storage area for storing boot data. The recovery component restores the faulty storage unit that stores startup data.

8. An operation method, an operation method performed on a NOR flash memory, characterized in that, The operation method includes: The steps of error detection and correction are performed on the data read from the storage cell array by error checking and correction components; The step of identifying the error pattern of the faulty storage unit after error detection and correction by the error checking and correction component; and The step of recovering the faulty storage unit based on the identified error pattern to eliminate the error of the faulty storage unit.

9. The operating method according to claim 8, characterized in that, When the error pattern indicates a decrease in the threshold of a storage cell, the recovery step is programmed to raise the threshold of the faulty storage cell.

10. The operating method according to claim 8, characterized in that, When the threshold of the faulty storage cell increases, the recovery step increases the read verification voltage of the faulty storage cell.

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