Integrally-formed equal-depth double-groove SiC MOSFET structure and preparation method thereof

Abstract

The invention relates to the technical field of silicon carbide semiconductor devices, in particular to an integrally-formed equal-depth double-groove SiC MOSFET structure and a preparation method thereof. According to the structure, an N + buffer layer and an N-drift layer are sequentially formed on an N-type SiC substrate, and a main groove and an auxiliary groove which are consistent in depth are formed in the surface of the N-type SiC substrate; a gate oxide layer and a polycrystalline silicon gate are sequentially formed in the main groove, and the auxiliary groove is filled with a SiC epitaxial material which is doped with the drift layer in the same type, so that a charge compensation and electric field regulation and control unit is formed; the P-type body region surrounds the trench structure and forms an N + source region, and the drain electrode is formed through a back metallization process. Through the collaborative design of the equal-depth double grooves, the uniformization of electric field distribution is realized, the on-resistance and the switching loss are effectively reduced, the thermal stability and the reliability of the device are improved, the integrated process is adopted for integration, the process is simplified, the production efficiency and the yield are improved, and the semiconductor device is suitable for high-frequency and high-voltage application scenes and has a wide industrialization prospect.

Description

Technical Field

[0001] This invention relates to the field of silicon carbide semiconductor device technology, and in particular to an integrally formed, equal-depth dual-trench SiCMOSFET structure and its fabrication method. Background Technology

[0002] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, possesses advantages such as a wide bandgap, high breakdown electric field, high thermal conductivity, and excellent thermal stability, and has been widely used in the field of power semiconductor devices in recent years. Especially in high-power-density and high-frequency applications such as new energy vehicles, rail transit, and smart grids, SiC MOSFETs are gradually replacing traditional silicon-based power devices due to their superior conductivity and switching characteristics, becoming the mainstream trend in power semiconductor development.

[0003] However, with the continuous increase in device operating frequency and current density, traditional single-trench or multi-trench SiC MOSFETs have gradually exposed a series of technical bottlenecks. On the one hand, the single-trench structure is limited by the channel width and carrier migration path, resulting in a large on-resistance and affecting the overall conductivity of the device. On the other hand, although the traditional double-trench structure improves the carrier distribution to some extent, its inconsistent trench depth and uneven filling process can easily lead to local electric field concentration, high interface state density, and large parasitic capacitance. This not only limits the further reduction of on-resistance but may also exacerbate energy loss during switching, affecting the dynamic performance of the device. How to optimize the trench structure design and improve the channel control capability without increasing the device complexity, while taking into account both conduction and switching performance, has become a key technical challenge in the current development of SiC MOSFET devices.

[0004] Therefore, there is an urgent need to propose a novel integrally formed, equal-depth dual-trench SiC MOSFET structure. By optimizing the trench design, improving the epitaxial and filling processes, and enhancing the interface quality, the on-resistance can be significantly reduced and the switching losses can be effectively controlled to meet the stringent performance requirements of high-frequency and high-power applications. Summary of the Invention

[0005] In view of this, the purpose of this invention is to propose an integrally formed equal-depth dual-trench SiC MOSFET structure and its fabrication method. Through the co-design of equal-depth dual trenches and the integrated fabrication process, the on-resistance is reduced, the switching characteristics are optimized, the reliability is improved, the process is simplified, and the requirements of high-voltage and high-power scenarios are met.

[0006] To achieve the above objectives, the present invention provides an integrally formed, uniform-depth dual-trench SiC MOSFET structure, comprising, from bottom to top, a drain, a SiC substrate, and an N2D substrate. + Buffer layer, N -Drift layer; The N - The drift layer surface has a main trench and an auxiliary trench. A gate oxide layer and a polysilicon gate are sequentially disposed within the main trench. The auxiliary trench is filled with a material similar to N... - The drift layer isomorphically doped SiC epitaxial material constitutes the charge compensation and electric field modulation unit; The main trench and auxiliary trench are surrounded by a P-shaped body region, and an N-shaped body region is provided within the P-shaped body region. + Source region; The drain electrode is formed on the back side of the SiC substrate by a metallization process; The main trench and the auxiliary trench have the same depth, with an error of ≤5%.

[0007] Preferably, the SiC substrate is a high-purity N-type SiC substrate.

[0008] Preferably, the N + The buffer layer enhances the ohmic contact between the substrate and the drift layer.

[0009] Preferably, the N - The drift layer provides a high-pressure withstand foundation.

[0010] Preferably, the width of the main groove is 0.3-1 μm, and the width of the auxiliary groove is 0.2-0.8 μm.

[0011] Preferably, the double trench design with equal depth makes the electric field distribution more uniform and synergistically reduces the on-resistance.

[0012] Furthermore, the present invention also provides a method for fabricating a monolithically formed, uniform-depth dual-trench SiC MOSFET structure, comprising the following steps: S1 Epitaxial Growth: N-type SiC substrates are epitaxially grown sequentially via chemical vapor deposition. + Buffer layer and N - The drift layer ensures the crystal quality and doping uniformity of the epitaxial layer; S2 equal-depth dual-trench etching: Employing photolithography and inductively coupled plasma etching processes, in N... - Main trenches and auxiliary trenches of equal depth are defined and etched on the drift layer; S3 trench etching post-surface treatment: plasma treatment and thermal oxidation repair are performed on the surface after double trench etching; S4 main trench gate fabrication: thermal oxidation to grow a gate oxide layer in the main trench, and CVD deposition of polysilicon to form a polysilicon gate structure; S5 auxiliary trench filling: Selective epitaxial growth technology is used to fill the auxiliary trench with N... -The purpose of isomorphically doped SiC material in the drift layer is to achieve the integrated molding of charge compensation structure. In this process, it is necessary to control the growth temperature and gas flow rate to ensure the crystallization matching between the fill layer and the drift layer. S6 source / drain fabrication: Aluminum ions and N2 ions implanted into the P-type body region. + Phosphorus ions are implanted into the source region, followed by high-temperature annealing, and a drain electrode is formed by sputtering on the back side of the substrate. S7 dielectric and passivation layer growth: A field oxide layer is formed by thermal oxidation, and a silicon nitride passivation layer is formed by plasma-enhanced chemical vapor deposition, resulting in an integrally formed dual-trench SiC MOSFET structure with equal depth.

[0013] Preferably, the temperature of the chemical vapor deposition in step S1 is 1500-1750°C and the pressure is 100 mbar.

[0014] Preferably, the N mentioned in step S1 + Buffer layer thickness 0.5-2μm, doping concentration 1×10 19 -5×10 19 cm -3 .

[0015] Preferably, the N mentioned in step S1 - Drift layer thickness 5-20 μm, doping concentration 5×10 15 -2×10 16 cm -3 .

[0016] Preferably, the etching gas in step S2 is an SF6 / O2 mixed gas, with an SF6 flow rate of 50 sccm and an O2 flow rate of 10 sccm.

[0017] Preferably, the etching power in step S2 is 500W, the bias voltage is 100V, and the etching time is 60s.

[0018] Preferably, during the dual-groove etching process in step S2, an optical profilometer is used to monitor the depth to ensure equal depth accuracy.

[0019] Preferably, the plasma treatment in step S3 is to introduce argon gas for plasma bombardment, with a power of 200-300W and a time of 10-20s, in order to remove etching residues and damage layers from the trench sidewalls.

[0020] Preferably, the thermal oxidation repair process in step S3 involves introducing a mixed gas of O2 and N2 at 400-600°C. The purpose of this process is to form an extremely thin oxide layer, further reducing the defect density on the trench surface and improving the quality of the gate oxide layer.

[0021] Preferably, the thickness of the gate oxide layer in step S4 is 20-100 nm.

[0022] Preferably, the polycrystalline silicon deposition thickness in step S4 is 1 μm.

[0023] Preferably, in step S4, when depositing polysilicon by CVD, patterning is required, and photolithography and etching are used to remove the polysilicon outside the trench to form a gate structure and construct a gate-controlled channel.

[0024] Preferably, the operating parameters of the selective epitaxial growth technology in step S5 are: temperature 1600℃, pressure 50mbar, and growth time 40min.

[0025] Preferably, the energy of the implanted aluminum ions in step S6 is 50-200 keV, and the dose is 1×10⁻⁶. 14 -5×10 15 cm -2 .

[0026] Preferably, the energy of the phosphorus ion implantation in step S6 is 30-150 keV, and the dose is 5 × 10⁻⁶. 15 -2×10 16 cm -2 .

[0027] Preferably, the high-temperature annealing temperature in step S6 is 1300-1600℃ and the time is 30-120s, the purpose of which is to activate the implanted ions.

[0028] Preferably, the drain electrode in step S6 is formed by sputtering a titanium / nickel / gold metal layer to form an ohmic contact.

[0029] Preferably, the sputtered Ti layer has a thickness of 20 nm, the Ni layer has a thickness of 50 nm, and the Au layer has a thickness of 200 nm.

[0030] Preferably, the thickness of the field oxide layer in step S7 is 100-300 nm to cover the device surface.

[0031] Preferably, the thickness of the silicon nitride passivation layer in step S7 is 200-500 nm.

[0032] The beneficial effects of this invention are: The integrated molding process of this invention reduces the number of photolithography, etching and cleaning steps in traditional processes, thereby reducing equipment usage costs and raw material consumption. At the same time, the improved production yield further reduces the manufacturing cost per unit device, making the SiC MOSFET more price-competitive in the market.

[0033] The synergistic effect of the equal-depth double trenches in this invention provides a uniform electric field distribution and effectively reduces on-resistance through auxiliary trench charge compensation. The combination of gate control and charge regulation improves switching speed, reduces switching losses, and is suitable for high-frequency and high-voltage applications.

[0034] The equal-depth dual-groove design of this invention optimizes the heat conduction path inside the device. Combined with the high thermal conductivity of SiC material itself, it makes the temperature distribution of the device more uniform under high-temperature operating conditions, reducing the risk of performance degradation and failure caused by local overheating.

[0035] The integral molding process of this invention reduces interface defects, and the equal depth design optimizes the distribution of thermal stress. The dielectric and passivation layers effectively suppress surface states and ion migration, enhancing the device's resistance to thermal cycling and radiation, and improving its reliability.

[0036] The equal-depth trench etching and selective epitaxial filling processes of this invention have a high degree of integration, simplifying the process and reducing costs; precise process control ensures structural consistency, improves production yield, and facilitates large-scale manufacturing. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in this invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Figure 1 This is a schematic diagram of the integrally formed equal-depth dual-trench SiC MOSFET structure according to an embodiment of the present invention; the figures are labeled as follows: 1: SiC substrate, 2: SiC N-type epitaxial layer, 3: P-type body region, 4: high-concentration P-type doped region, 5: gate oxide layer, 6: gate polysilicon, 7: N + Source region, 8: pseudo gate. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0039] Example 1: A monolithically formed, uniform-depth dual-trench SiC MOSFET structure, the specific fabrication steps are as follows: (1) Epitaxial growth: A 4-inch N-type SiC substrate (crystal orientation) was selected. <0001> Doping concentration 1×10 18 cm -3 The mixture of SiH4, C3H8, and NH3 was placed in a CVD reaction chamber and introduced. The temperature was set at 1500℃ and the pressure at 100mbar to grow N. + Buffer layer (thickness 0.5 μm, doping concentration 1 × 10⁻⁶) 19 cm -3 The growth time was 15 minutes, then the gas flow rate was adjusted to grow N. - Drift layer (thickness 5 μm, doping concentration 5 × 10⁻⁶) 15 The growth time was 1 hour, and the crystal quality of the epitaxial layer was monitored by reflection high-energy electron diffraction to ensure that there were no obvious defects. (2) Equal depth double trench etching: spin-coated photoresist (thickness 1μm), exposed and developed through a photomask, defining the main trench (width 0.3μm) and auxiliary trench (width 0.2μm) pattern, placing the sample into an ICP etching machine, introducing SF6 (flow rate 50sccm) and O2 (flow rate 10sccm), setting the etching power to 500W, bias voltage to 100V, and etching time to 60s, measuring with an optical profilometer after etching, the depth of both trenches is 2μm, with a depth error of <3%, meeting the equal depth requirement; (3) Surface treatment: After the deep double trench etching is completed, Ar gas is introduced for plasma bombardment, the power is controlled at 200W and the time is 10s. Then, thermal oxidation process is used for repair. A mixture of O2 and N2 gas is introduced at 400℃ to form an extremely thin oxide layer. (4) Main trench gate fabrication: The surface-treated sample is placed in an oxidation furnace and O2 is introduced at 1150℃ to grow a 20nm thick gate oxide layer. Then, polysilicon (1μm thick) is deposited by CVD, photoresist is spin-coated and photolithography is performed to define the gate pattern. Reactive ion etching is used to remove the polysilicon outside the trench, leaving the polysilicon gate inside the main trench. The residual oxide is cleaned with BOE solution to complete the gate fabrication. (5) Auxiliary trench filling: The sample is transferred to the selective epitaxial growth equipment, and a mixture of SiH4, C3H8 and N2 gas is introduced. The temperature is set to 1600℃, the pressure to 50mbar, and the growth time to 40min. N-type SiC epitaxial material is filled in the auxiliary trench. The thickness of the filling layer is matched with the trench depth. The filling is dense and without voids, as observed by scanning electron microscopy. (6) Source and drain fabrication: Photolithography defines the P-type body region and the N-type body region. + Source region pattern, aluminum ion implantation in the P-type body region (energy 50 keV, dose 1 × 10⁻⁶). 14 cm -2 ), N + Phosphorus ions were injected into the source region (30 keV, dose 5 × 10⁻⁶). 15 cm -2 After implantation, the ions are rapidly thermally annealed at 1300℃ for 30s to activate them; the back side of the substrate is ground to a thickness of 100μm, a Ti (20nm) / Ni (50nm) / Au (200nm) metal layer is sputtered, and then annealed at 400℃ for 5min to form a drain ohmic contact. (7) Dielectric and passivation layer growth: The sample is placed in a thermal oxidation furnace and O2 is introduced at 1000℃ to grow a 100nm field oxide layer. Then, a 200nm thick silicon nitride passivation layer is deposited by plasma-enhanced chemical vapor deposition at a deposition temperature of 300℃ and a gas flow rate of SiH4:NH3 = 1:3 to ensure that the passivation layer is dense and free of pinholes, thus obtaining an integrally formed double trench SiC MOSFET structure with equal depth.

[0040] Example 2: A monolithically formed, uniform-depth dual-trench SiC MOSFET structure, the specific fabrication steps of which are as follows: (1) Epitaxial growth: A 4-inch N-type SiC substrate (crystal orientation) was selected. <0001> Doping concentration 1×10 18 cm -3 The mixture was placed in a CVD reaction chamber, and a mixture of SiH4, C3H8, and NH3 gas was introduced. The temperature was set at 1650℃ and the pressure at 100mbar to grow N. + Buffer layer (thickness 1 μm, doping concentration 3 × 10⁻⁶) 19 cm -3 The growth time was 30 minutes, then the gas flow rate was adjusted to grow N. - Drift layer (thickness 10 μm, doping concentration 1 × 10⁻⁶) 16 cm -3 The growth time was 2 hours, and the crystal quality of the epitaxial layer was monitored by reflection high-energy electron diffraction to ensure that there were no obvious defects. (2) Equal depth double trench etching: spin-coated photoresist (thickness 1μm), exposed and developed through a photomask, defining the main trench (width 0.5μm) and auxiliary trench (width 0.3μm) pattern, placing the sample into an ICP etching machine, introducing SF6 (flow rate 50sccm) and O2 (flow rate 10sccm), setting the etching power to 500W, bias voltage to 100V, and etching time to 60s, measuring with an optical profilometer after etching, the depth of both trenches is 2μm, with a depth error of <3%, meeting the equal depth requirement; (3) Surface treatment: After the deep double trench etching is completed, Ar gas is introduced for plasma bombardment, the power is controlled at 250W and the time is 150s. Then, thermal oxidation process is used for repair. A mixture of O2 and N2 gas is introduced at 500℃ to form an extremely thin oxide layer. (4) Main trench gate fabrication: The surface-treated sample is placed in an oxidation furnace and O2 is introduced at 1150℃ to grow a 50nm thick gate oxide layer. Then, polysilicon (1μm thick) is deposited by CVD, photoresist is spin-coated and photolithography is performed to define the gate pattern. Reactive ion etching is used to remove the polysilicon outside the trench, leaving the polysilicon gate inside the main trench. The residual oxide is cleaned with BOE solution to complete the gate fabrication. (5) Auxiliary trench filling: The sample is transferred to the selective epitaxial growth equipment, and a mixture of SiH4, C3H8 and N2 gas is introduced. The temperature is set to 1600℃, the pressure to 50mbar, and the growth time to 40min. N-type SiC epitaxial material is filled in the auxiliary trench. The thickness of the filling layer is matched with the trench depth. The filling is dense and without voids, as observed by scanning electron microscopy. (6) Source and drain fabrication: Photolithography defines the P-type body region and the N-type body region. +Source region pattern, aluminum ion implantation in the P-type body region (energy 100 keV, dose 3 × 10⁻⁶). 15 cm -2 ), N + Phosphorus ions were injected into the source region (80 keV, dose 1×10⁻⁶). 16 cm -2 After implantation, the substrate is rapidly thermally annealed at 1500℃ for 60s to activate the ions; the back side of the substrate is ground to a thickness of 100μm, a Ti (20nm) / Ni (50nm) / Au (200nm) metal layer is sputtered, and then annealed at 400℃ for 5min to form a drain ohmic contact. (7) Dielectric and passivation layer growth: The sample is placed in a thermal oxidation furnace and O2 is introduced at 1000℃ to grow a 200nm field oxide layer. Then, a 300nm thick silicon nitride passivation layer is deposited by plasma-enhanced chemical vapor deposition at a deposition temperature of 300℃ and a gas flow rate of SiH4:NH3 = 1:3 to ensure that the passivation layer is dense and free of pinholes, thus obtaining an integrally formed double trench SiC MOSFET structure with equal depth.

[0041] Example 3: A monolithically formed, uniform-depth dual-trench SiC MOSFET structure, the specific fabrication steps of which are as follows: (1) Epitaxial growth: A 4-inch N-type SiC substrate (crystal orientation) was selected. <0001> Doping concentration 1×10 18 cm -3 The mixture of SiH4, C3H8, and NH3 was placed in a CVD reaction chamber and introduced. The temperature was set at 1750℃ and the pressure at 100mbar to grow N. + Buffer layer (thickness 2μm, doping concentration 5×10⁻⁶) 19 cm -3 The growth time was 60 minutes, then the gas flow rate was adjusted to grow N. - Drift layer (thickness 20 μm, doping concentration 2 × 10⁻⁶) 16 cm -3 The growth time was 4 hours, and the crystal quality of the epitaxial layer was monitored by reflection high-energy electron diffraction to ensure that there were no obvious defects. (2) Equal depth double trench etching: spin-coated photoresist (thickness 1μm), exposed and developed through a photomask, defining the main trench (width 1μm) and auxiliary trench (width 0.8μm) pattern, placing the sample into an ICP etching machine, introducing SF6 (flow rate 50sccm) and O2 (flow rate 10sccm), setting the etching power to 500W, bias voltage to 100V, and etching time to 60s, measuring with an optical profilometer after etching, the depth of both trenches is 2μm, with a depth error of <3%, meeting the equal depth requirement; (3) Surface treatment: After the deep double trench etching is completed, Ar gas is introduced for plasma bombardment, the power is controlled at 300W and the time is 20s. Then, thermal oxidation process is used for repair. A mixture of O2 and N2 gas is introduced at 600℃ to form an extremely thin oxide layer. (4) Main trench gate fabrication: The surface-treated sample is placed in an oxidation furnace and O2 is introduced at 1150℃ to grow a 100nm thick gate oxide layer. Then, polysilicon (1μm thick) is deposited by CVD, photoresist is spin-coated and photolithography is performed to define the gate pattern. Reactive ion etching is used to remove the polysilicon outside the trench, leaving the polysilicon gate inside the main trench. The residual oxide is cleaned with BOE solution to complete the gate fabrication. (5) Auxiliary trench filling: The sample is transferred to the selective epitaxial growth equipment, and a mixture of SiH4, C3H8 and N2 gas is introduced. The temperature is set to 1600℃, the pressure to 50mbar, and the growth time to 40min. N-type SiC epitaxial material is filled in the auxiliary trench. The thickness of the filling layer is matched with the trench depth. The filling is dense and without voids, as observed by scanning electron microscopy. (6) Source and drain fabrication: Photolithography defines the P-type body region and the N-type body region. + Source region pattern, aluminum ion implantation in the P-type body region (energy 200 keV, dose 5 × 10⁻⁶). 15 cm -2 ), N + Phosphorus ions were injected into the source region at a dose of 150 keV (2 × 10⁻⁶). 16 cm -2 After implantation, the substrate is rapidly thermally annealed at 1600℃ for 120s to activate the ions; the back side of the substrate is ground to a thickness of 100μm, a Ti (20nm) / Ni (50nm) / Au (200nm) metal layer is sputtered, and then annealed at 400℃ for 5min to form a drain ohmic contact. (7) Dielectric and passivation layer growth: The sample is placed in a thermal oxidation furnace and O2 is introduced at 1000℃ to grow a 300nm field oxide layer. Then, a 500nm thick silicon nitride passivation layer is deposited by plasma-enhanced chemical vapor deposition at a deposition temperature of 300℃ and a gas flow rate of SiH4:NH3 = 1:3 to ensure that the passivation layer is dense and free of pinholes, thus obtaining an integrally formed double trench SiC MOSFET structure with equal depth.

[0042] Comparative Example 1: Traditional single-trench SiC MOSFET structure.

[0043] Comparative Example 2: Traditional dual-trench SiC MOSFET structure.

[0044] Performance testing On-resistance test: Under the conditions of VGS = 20V and VDS = 0V, measure the drain current ID and calculate the on-resistance; Switching loss test: The turn-on loss and turn-off loss of the device were tested using the double-pulse test method. The test conditions were: VDD = 600V, ID = 50A, RG = 10Ω, Tj = 150℃. The switching loss was calculated. The test results are shown in Table 1.

[0045] Table 1 Performance Test Results <![CDATA[On-resistance (mΩ·cm 2 )]]> Switching loss (μJ) Example 1 2.4 2.3 Example 2 2.0 2.1 Example 3 1.8 2.5 Comparative Example 1 3.5 3.8 Comparative Example 2 3.0 3.2 Data Analysis: Table 1 shows that the data from Examples 1 to 3 indicate that as the fabrication process parameters are gradually optimized, the on-resistance of the device decreases, while the switching loss remains at a low level. This demonstrates that the device achieves a synergistic improvement in electrical performance through structural design and process control. On the one hand, the introduction of the equal-depth dual-trench structure effectively expands the carrier conduction path and reduces the channel resistance. Simultaneously, the integrated filling and molding design of the main and auxiliary trenches helps improve the uniformity of current conduction and reduce non-ideal conduction losses caused by localized electric field concentration. On the other hand, as the epitaxial layer thickness and doping concentration gradually increase, the conductivity of the drift region is enhanced, which is beneficial for further reducing the on-resistance. Furthermore, the selective epitaxial filling process in the auxiliary trench is excellent, ensuring structural integrity and electrical continuity, and reducing energy losses caused by interface defects and non-ideal contacts. Overall, this integrated equal-depth dual-trench SiC MOSFET structure achieves a good balance between conductivity and switching efficiency, demonstrating its potential in high-frequency, high-power applications.

[0046] As can be seen from the test data in Table 1, Example 2 exhibits superior characteristics in both on-resistance and switching loss compared to Comparative Examples 1 and 2. The reduction in on-resistance may be due to the optimization of carrier distribution by the equal-depth dual-trench structure, which improves channel mobility and shortens the current path, thereby effectively reducing resistance loss in the on-state. At the same time, the integrated dual-trench design helps to enhance the gate's ability to control the channel region and improve the device's conduction efficiency.

[0047] Regarding switching losses, the reduction in Example 2 may be attributed to the improved uniformity of electric field distribution brought about by the equal-depth trench structure, as well as the suppression effect of the auxiliary trench filling process on parasitic capacitance, which reduces energy loss during switching. In addition, the integrated molding process of the main trench and the auxiliary trench may improve the synergy of various functional regions inside the device, reduce the interface state density, thereby improving the switching dynamic characteristics and further reducing energy dissipation during turn-on and turn-off.

[0048] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention is limited to these examples; within the framework of the invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity.

Claims

1. An integrally formed equal-depth double-trench SiC MOSFET structure, characterized by, comprises, in order from bottom to top, a drain electrode, a SiC substrate, an N + buffer layer, an N - drift layer; The N - The surface of the drift layer has main trenches and auxiliary trenches, the gate oxide layer and the polysilicon gate are sequentially arranged in the main trenches, and the auxiliary trenches are filled with N - The drift layer is a SiC epitaxial material with the same type of doping. The main trench and the auxiliary trench are surrounded by a P-type body region, and the P-type body region is provided with an N + source region; The drain is formed on the back surface of the SiC substrate by a metallization process; The main trench and the auxiliary trench have the same depth, with an error of less than 5%.

2. The equal-depth double-trench SiC MOSFET structure of claim 1, wherein, The SiC substrate is a high-purity N-type SiC substrate.

3. The equal-depth double-trench SiC MOSFET structure of claim 1, wherein, The main trench has a width of 0.3-1 μm, and the auxiliary trench has a width of 0.2-0.8 μm.

4. A method of fabricating the equal-depth double-trench SiC MOSFET structure according to any one of claims 1-3, characterized by, The method comprises the following steps: S1 epitaxial growth: N-type SiC substrate is sequentially epitaxially grown by chemical vapor deposition + buffer layer and N - drift layer; S2 isodense double-groove etching: using photolithography and inductively coupled plasma etching process, main groove and auxiliary groove with isodense are defined and etched on N - main groove and auxiliary groove with isodense are defined and etched on drift layer; S3: surface treatment after trench etching: plasma treatment and thermal oxidation repair are performed on the surface after double-trench etching; S4: main trench gate preparation: a gate oxide layer is grown in the main trench by thermal oxidation, and a polysilicon gate structure is formed by CVD deposition of polysilicon; S5 Auxiliary trench filling: Selective epitaxial growth technique is used to fill the auxiliary trench with N - SiC material of the same type of doping as the drift layer; S6 source-drain fabrication: implant aluminum ions in P-type body region, N + source region implant phosphorus ions, high temperature annealing, and sputtering to form a drain on the back of the substrate; S7: growth of dielectric and passivation layer: a field oxide layer is formed by thermal oxidation, and a silicon nitride passivation layer is formed by plasma-enhanced chemical vapor deposition, thereby obtaining an integrated equal-depth double-trench SiC MOSFET structure.

5. The preparation method according to claim 4, characterized in that, The N + Buffer layer thickness 0.5-2 μm, doping concentration 1 x 10 19 -5 x 10 19 cm -3 The N - Drift layer thickness 5-20 μm, doping concentration 5 x 10 15 -2 x 10 16 cm -3 .

6. The preparation method according to claim 4, characterized in that, The etching gas in step S2 is SF6 / O2 mixed gas.

7. The preparation method according to claim 4, characterized in that, In step S3, the plasma treatment is plasma bombardment by introducing argon gas, with a power of 200-300 W and a time of 10-20 s; the thermal oxidation repair process is to introduce a mixed gas of O2 and N2 at 400-600 ℃.

8. The preparation method according to claim 4, characterized in that, In step S4, the thickness of the gate oxide layer is 20-100 nm.

9. The preparation method according to claim 4, characterized in that, The energy of the implanted aluminum ions in step S6 is 50-200 keV, and the dose is 1 x 10 14 -5 x 10 15 cm -2 -2. The energy of the implanted phosphorus ions is 30-150 keV, and the dose is 5 x 10 15 -2 x 10 16 cm -2 .

10. The method of claim 4, wherein, In step S7, the thickness of the field oxide layer is 100-300 nm to cover the surface of the device; the thickness of the silicon nitride passivation layer is 200-500 nm.

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