Device structure for reducing zero temperature coefficient voltage of transfer characteristic curve of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and preparation method thereof
By adjusting the substrate structure and oxide layer design of the SiC MOSFET device and regulating the resistance ratio, the problem of excessively high zero temperature coefficient voltage was solved, and the reliability of the device under short-circuit conditions was improved.
Patent Information
- Application Number
- CN202511090267.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-05
- Publication Date
- 2025-12-16
AI Technical Summary
Existing SiC MOSFET devices have excessively high zero-temperature coefficient voltages at different temperatures, causing the current to increase over time under short-circuit conditions, resulting in thermal damage and affecting reliability.
By adjusting the substrate structure, including forming pwell regions on the N-drift region and implanting Al ions at different energies, and combining the design of silicon dioxide regions and oxide layers, the ratio of Rdrift, Rchannel, and Rneck can be adjusted to reduce the zero temperature coefficient voltage.
This effectively reduces the zero temperature coefficient voltage of SiC MOSFET devices, avoids positive feedback phenomena of temperature and current, and enhances the reliability of devices under short-circuit conditions.
Smart Images
Figure CN121152260A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of semiconductor devices, and particularly relates to a device structure for reducing zero-temperature-coefficient voltage of a SiC MOSFET transfer characteristic curve and a preparation method thereof. BACKGROUND
[0002] At present, the SiC MOSFET is a widely used and commercialized SiC power device, as a third-generation wide-bandgap power semiconductor device, has the advantages of fast switching speed, small on-resistance, high breakdown voltage, high thermal conductivity, and is widely used in the field of power electronics, and is expected to replace Si IGBT to become a new generation of high-power switching device. If the MOSFET withstands high voltage while passing through a large current, the device with a small area withstands a large power density, which is easy to cause local overheating and other reasons to cause device failure. In the case of constant drain voltage, the Id-Vg curve at different temperatures has a general focus point, as shown in Figure 1 The focus point of the two curves at 300k and 450k is the zero-temperature-coefficient point at this drain voltage, and the voltage corresponding to this point is called the zero-temperature-coefficient voltage. The zero-temperature-coefficient voltage will increase with the increase of the drain voltage. When the gate voltage is less than the zero-temperature-coefficient voltage, the device current becomes larger as the temperature rises; when the gate voltage is greater than the zero-temperature-coefficient voltage, the device current becomes smaller as the temperature rises. Because the gate resistance corresponding to different positions of the device is different, there is a situation that the farther the real gate voltage of the cell from the GatePad position is, the smaller it is. If the zero-temperature-coefficient voltage is too high, once the real gate voltage of the edge position is reduced, the positive feedback phenomenon of the higher temperature and the larger current at this position is easy to occur, and in the short circuit condition, the short circuit current will become larger and larger with the increase of time, which is easy to cause thermal damage, and is very unfavorable to the reliability of the device.
[0003] The existing schemes mostly focus on reducing the short circuit current peak value, for example, reducing the current when the drain voltage is too large through the JFET effect, ignoring the contribution of temperature change to the change of short circuit current with time, and also having the risk of increasing the on-resistance. SUMMARY
[0004] The technical problem to be solved by the application is to provide a device structure for reducing zero-temperature-coefficient voltage of a SiC MOSFET transfer characteristic curve and a preparation method thereof, which effectively reduces the zero-temperature-coefficient voltage through structural design, and has important significance for SiC MOSFET.
[0005] The application provides a device structure for reducing zero-temperature coefficient voltage of a SiC MOSFET transfer characteristic curve, which comprises a substrate, an N-drift region, a current spreading layer and a jfet region in sequence.
[0006] Further, the pwell region comprises a shallow layer region and a deep layer region, and the deep layer region is close to the substrate side; the width of the deep layer region is smaller than that of the shallow layer region, and the deep layer region is in a ladder type.
[0007] Further, the shallow layer region is formed by low-energy Al ion implantation, and the deep layer region is formed by high-energy Al ion implantation.
[0008] Further, the first metal forms a source electrode.
[0009] Further, the substrate is a silicon carbide substrate.
[0010] Further, the other side of the substrate is deposited with a second metal to form a drain electrode.
[0011] The application provides a preparation method of a device structure for reducing zero-temperature coefficient voltage of a SiC MOSFET transfer characteristic curve, which comprises the following steps:
[0012] S1, growing an N-drift region on a substrate;
[0013] S2, performing N ion implantation on the N-drift region to form a current spreading layer and a jfet region;
[0014] S3, performing ion implantation on the N-drift region to form a pwell region;
[0015] S4, performing N ion implantation on the pwell region to form an nplus region;
[0016] S5, performing Al ion implantation on the pwell region to form a pplus region;
[0017] S6, after annealing, etching a window on the jfet region and filling the window with silicon dioxide to form a silicon dioxide region;
[0018] S7, high-temperature oxidation on the jfet region to form a gate oxide layer, and depositing gate polysilicon on the gate oxide layer;
[0019] S8, depositing silicon dioxide as a field oxide layer;
[0020] S9, etching the field oxide layer and the gate oxide layer to form a source window;
[0021] S10, depositing a first metal to fill the via and form a source;
[0022] S11, depositing a second metal on the other surface of the substrate to form a drain.
[0023] As Figure 2 shown, according to the current path, the resistance can be roughly divided into three parts in series, Rdrift, Rchannel and Rneck. Since Rdrift, Rchannel and Rneck have different trends of change with temperature, the zero temperature coefficient voltage can be adjusted by adjusting the proportional relationship of the three. As the temperature rises, the threshold voltage decreases, and when the gate voltage is constant, the number of carriers increases exponentially, and the current rises rapidly. It can be seen that the channel region resistance decreases with the increase of temperature. As the temperature rises, the lattice vibration intensifies, and the scattering leads to the decrease of mobility, while the carrier concentration of the drift region hardly changes and the electric field intensity increases limitedly. Therefore, the resistance of the drift region increases with the increase of temperature. As for the neck region, since the number of carriers flowing from the channel increases, and the mobility changes less, Rneck decreases with the increase of temperature. Adjusting the proportional relationship of the three requires focusing on reducing the proportion of Rchannel and Rneck. Based on this, the present application provides a device structure for reducing the zero temperature coefficient point of the transfer characteristic curve of SiC MOSFET. This scheme is mainly applicable to circuits that have certain requirements for device short-circuit resistance and pass large current for a long time.
[0024] Beneficial effects
[0025] The present application effectively reduces the zero temperature coefficient voltage through structural design, which is of great significance for SiC MOSFET. In the case of excessive drain voltage or low gate voltage, the real gate voltage of each part of the device is still greater than the zero temperature coefficient voltage, which avoids the positive feedback phenomenon of temperature and current, so that the short-circuit current decreases with time in the short-circuit condition, and the reliability of the device is enhanced. It can be applied to circuits with high requirements for short-circuit resistance. BRIEF DESCRIPTION OF DRAWINGS
[0026] Figure 1 is a transfer characteristic curve diagram of SiC MOSFET at different temperatures.
[0027] Figure 2 is a resistance distribution diagram.
[0028] Figure 3 is a structural diagram of the device of the present application.
[0029] Figure 4 This is a comparison diagram of the zero temperature coefficient points of the device of the present invention and existing devices.
[0030] Figure 5 This is a comparison chart of the short-circuit capabilities of the device of the present invention and existing devices. Detailed Implementation
[0031] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.
[0032] Example 1
[0033] like Figure 3 As shown, this embodiment provides a device structure for reducing the zero temperature coefficient voltage of the transfer characteristic curve of a SiC MOSFET. The device structure sequentially includes a substrate 1, an N-drift region 2, a current spreading layer 3, and a jfet region 4. A pwell region 5 is formed on the N-drift region 2 by ion implantation. An nplus region 6 is formed on the pwell region 5 by N-ion implantation, and a pplus region 7 is formed on the pwell region 5 by Al-ion implantation. A silicon dioxide region 12 is filled above the jfet region 4. A gate oxide layer 13 is formed on the jfet region 4 by oxidation. A gate polysilicon 9 is deposited on the gate oxide layer 13. A field oxide layer 8 is deposited on the gate oxide layer 13. A source window is etched on the field oxide layer 8 and the gate oxide layer 13, and a first metal 10 is deposited. The pwell region 5 includes a shallow region and a deep region. The deep region is closer to the substrate 1. The width of the deep region is smaller than the width of the shallow region, and it is stepped. The shallow region is formed by low-energy Al ion implantation, and the deep region is formed by high-energy Al ion implantation. The first metal 10 forms the source. The substrate 1 is a silicon carbide substrate. A second metal 11 is deposited on the other side of the substrate 1 to form the drain.
[0034] This embodiment also provides a method for fabricating a device structure that reduces the zero temperature coefficient voltage of the SiC MOSFET transfer characteristic curve, including the following steps:
[0035] S1. An N-drift region 2 is grown on substrate 1;
[0036] S2. N-ion implantation is performed on the N-drift region 2 to form a current-spreading layer 3 and a JFET region 4;
[0037] S3, ion implantation on N-drift region 2 to form pwell region 5; including low-energy Al ion implantation to form pwell shallow region, and high-energy Al ion implantation to form pwell deep region;
[0038] S4, N ion implantation on pwell region 5 to form nplus region 6;
[0039] S5, Al ion implantation on pwell region 5 to form pplus region 7;
[0040] S6, after annealing, etching window on jfet region 4 and filling with silicon dioxide to form silicon dioxide region 12;
[0041] S7, high-temperature oxidation on jfet region 4 to form gate oxide layer 13, and depositing gate polysilicon 9;
[0042] S8, depositing silicon dioxide as field oxide layer 8;
[0043] S9, etching field oxide layer 8 and gate oxide layer 13 to form source window;
[0044] S10, depositing first metal 10 to fill the via and form source;
[0045] S11, depositing second metal 11 on the other surface of substrate 1 to form drain.
[0046] In the device structure, the channel length is only 0.45 μm, so as to reduce the channel resistance. By introducing current spreading layer, the neck resistance partial resistance is reduced. The filled silicon dioxide region avoids the main current path, and reduces the parallel component of the jfet region top current, so as to increase the vertical component, further reducing the neck resistance. The ladder type pwell region is adopted, and the pwell deep layer injection is moved away from the jfet region, so as to widen the width of the neck current channel. And the two measures reduce the length of the neck resistance, and correspondingly increase the length of the drift region resistance, which reduces the proportion of the neck resistance and increases the proportion of the drift region resistance, so as to well reduce the zero temperature coefficient voltage. Figure 4 As shown, the zero temperature coefficient point voltage of the redesigned device transfer characteristic is reduced from 13.1 V to 10.2 V, which is obviously reduced. Figure 5 The short circuit test image is given, it can be seen that after reducing the zero temperature coefficient point voltage, the current of the device when short circuit will rapidly decrease after reaching the peak value, and the circuit endurance time is greatly increased.
Claims
1. A device structure to reduce zero temperature coefficient voltage of SiC MOSFET transfer characteristic curve, characterized in that: The device structure comprises in sequence a substrate (1), an N-drift region (2), a current spreading layer (3), a jfet region (4); a pwell region (5) is formed on the N-drift region (2) by ion implantation; an nplus region (6) is formed on the pwell region (5) by N ion implantation, and a pplus region (7) is formed on the pwell region (5) by Al ion implantation; a silicon dioxide region (12) is filled on the jfet region (4); a gate oxide layer (13) is formed on the jfet region (4) by oxidation; the gate oxide layer (13) is deposited with a gate polysilicon (9); a field oxide layer (8) is deposited on the gate oxide layer (13); an active electrode window is etched in the field oxide layer (8) and the gate oxide layer (13), and a first metal (10) is deposited.
2. The device structure of claim 1, wherein: The pwell region (5) comprises a shallow region and a deep region, and the deep region is close to one side of the substrate (1); the width of the deep region is smaller than that of the shallow region, and the deep region is in a ladder type.
3. The device structure of claim 2, wherein: The shallow region is formed by low-energy Al ion implantation, and the deep region is formed by high-energy Al ion implantation.
4. The device structure of claim 1, wherein: The first metal (10) forms a source electrode.
5. The device structure of claim 1, wherein: The substrate (1) is a silicon carbide substrate.
6. The device structure of claim 1, wherein: A second metal (11) is deposited on the other surface of the substrate (1) to form a drain electrode.
7. A preparation method of a device structure for reducing the zero temperature coefficient voltage of a SiC MOSFET transfer characteristic curve, comprising the following steps: S1, growing an N-drift region (2) on a substrate (1); S2, forming a current spreading layer (3) and a jfet region (4) by N ion implantation on the N-drift region (2); S3, forming a pwell region (5) by ion implantation on the N-drift region (2); S4, forming an nplus region (6) by N ion implantation on the pwell region (5); S5, forming a pplus region (7) by Al ion implantation on the pwell region (5); S6, after annealing, etching a window in the jfet region (4) and filling silicon dioxide to form a silicon dioxide region (12); S7, forming a gate oxide layer (13) by high-temperature oxidation on the jfet region (4) and depositing a gate polysilicon (9); S8, depositing silicon dioxide as a field oxide layer (8); S9, etching the field oxide layer (8) and the gate oxide layer (13) to form a source electrode window; S10, depositing a first metal (10) to fill the via hole and form a source electrode; S11, depositing a second metal (11) on the other surface of the substrate (1) to form a drain electrode.