Embedded substrate and manufacturing method thereof

Abstract

The invention provides an embedded substrate and a manufacturing method thereof. The manufacturing method specifically comprises the following steps: forming a conduction copper column and a shielding copper column on a first circuit layer of the substrate; pressing a second dielectric layer on the first circuit layer, the conduction copper column and the shielding copper column; mounting a component on the second dielectric layer; pressing the component into the second dielectric layer to enable the shielding copper column and the first circuit layer to surround the component; pressing a fourth dielectric layer on the second dielectric layer and the component, and curing the second dielectric layer and the fourth dielectric layer; forming an outer circuit layer on the fourth dielectric layer; and the outer circuit layer is in conducting connection with the conducting copper column, the shielding copper column and the terminal of the component. The shielding copper columns can reduce the deviation of the component in the extrusion process of the component and improve the yield, five surfaces of the embedded component are all provided with metal copper, and a good electromagnetic shielding effect can be achieved. Moreover, the second dielectric layer and the fourth dielectric layer are made of high-thermal-conductivity materials, so that heat can be quickly guided into the shielding copper columns, and the heat dissipation effect is obviously improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor packaging, and in particular to an embedded substrate and a manufacturing method thereof. BACKGROUND

[0002] The embedded substrate is an advanced packaging substrate technology, which realizes three-dimensional integration and ultra-high-density interconnection by directly embedding passive or active components inside the substrate, and is applied to fields such as server graphics processors and new energy modules. However, the embedding method of the related art still has deficiencies, such as poor stability, insufficient heat dissipation performance, etc. SUMMARY

[0003] Therefore, the present disclosure aims to provide an embedded substrate and a manufacturing method thereof.

[0004] To achieve the above object, in a first aspect, the present disclosure provides a manufacturing method of an embedded substrate, comprising: (a) providing a substrate; wherein a first circuit layer is formed on a surface of the substrate; (b) forming a conductive copper pillar and a shielding copper pillar on the first circuit layer; (c) pressing a second dielectric layer on the first circuit layer, so that the conductive copper pillar and the shielding copper pillar are embedded in the second dielectric layer; (d) mounting a component on the second dielectric layer, wherein a direct projection of the component on the substrate is surrounded by the shielding copper pillar; (e) pressing the component into the second dielectric layer, so that the shielding copper pillar and the first circuit layer surround the component; (f) pressing a fourth dielectric layer on the second dielectric layer and the component, and curing the second dielectric layer and the fourth dielectric layer; (g) forming an outer circuit layer on the fourth dielectric layer; wherein the outer circuit layer is conductively connected to the conductive copper pillar, the shielding copper pillar and the terminal of the component.

[0005] In some embodiments, step (a) comprises: (a1) providing a core board; wherein the core board comprises a first dielectric layer; (a2) forming a first circuit layer on the first dielectric layer.

[0006] In some embodiments, the distance between the shielding copper pillar and the component is 10-300 μm; and / or the width of the shielding copper pillar is 50-200 μm; and / or the height of the shielding copper pillar is 30-700 μm.

[0007] In some embodiments, the shielding copper pillar encloses a shielding area that horizontally surrounds the component.

[0008] In some embodiments, the height of the shielding copper pillar is not less than the height of the component.

[0009] In some embodiments, the thickness of the second dielectric layer is not less than the height of the conductive copper pillar and the shielding copper pillar.

[0010] In some embodiments, step (e) adopts a vacuum hot pressing process.

[0011] In some embodiments, the second dielectric layer and the fourth dielectric layer are made of the same material.

[0012] In some embodiments, step (g) comprises: (g1) laser drilling blind holes to expose the conductive copper pillar, the shielding copper pillar and the terminal of the component; (g2) forming a first seed layer on the fourth dielectric layer; (g3) pasting a film on the first seed layer, exposing and developing; (g4) filling hole electroplating to form the outer layer circuit layer; (g5) removing the film and etching the first seed layer.

[0013] In some embodiments, the substrate further comprises a first dielectric layer and a second circuit layer; the first circuit layer and the second circuit layer are respectively located on both sides of the first dielectric layer. Step (c) further comprises: laminating a third dielectric layer on the surface of the second circuit layer.

[0014] In some embodiments, the material of the second dielectric layer is a resin material that has normal temperature viscosity and high thermal conductivity before curing.

[0015] In a second aspect, the embodiments of the present disclosure further provide a buried substrate, comprising a first dielectric layer, a first circuit layer, a conductive copper pillar, a shielding copper pillar, a component, a second dielectric layer, a fourth dielectric layer and an outer layer circuit layer; wherein, the first circuit layer is located on the first dielectric layer, the shielding copper pillar and the conductive copper pillar are located on the first circuit layer, the second dielectric layer covers the first circuit layer, the shielding copper pillar and the conductive copper pillar, the component is embedded in the second dielectric layer and surrounded by the shielding copper pillar and the first circuit layer, the fourth dielectric layer is located on the second dielectric layer, and the outer layer circuit layer is located on the fourth dielectric layer and connected to the shielding copper pillar, the conductive copper pillar and the terminal of the component.

[0016] In some embodiments, the material of the second dielectric layer is a resin material that has room temperature viscosity and high thermal conductivity before curing.

[0017] In some embodiments, the spacing between the shielding copper pillar and the component is 10~300 μm; and / or The width of the shielding copper pillar is 50~200 μm; and / or The height of the shielding copper pillar is 30~700 μm.

[0018] In some embodiments, the shielding copper pillars enclose a shielding area that surrounds the component in the horizontal direction.

[0019] In some embodiments, a second circuit layer and a third dielectric layer are further included; wherein the second circuit layer is located on the side of the first dielectric layer away from the first circuit layer; and the third dielectric layer is located above the second circuit layer.

[0020] As can be seen from the above description, the present disclosure provides an embedded substrate and its manufacturing method. The manufacturing method specifically includes (a) providing a substrate; wherein a first circuit layer is formed on the surface of the substrate; (b) forming conductive copper pillars and shielding copper pillars on the first circuit layer; (c) laminating a second dielectric layer on the first circuit layer, such that the conductive copper pillars and the shielding copper pillars are embedded in the second dielectric layer; (d) mounting components on the second dielectric layer, wherein the orthographic projection of the components on the substrate is surrounded by the shielding copper pillars; (e) pressing the components into the second dielectric layer, such that the shielding copper pillars and the first circuit layer surround the components; (f) laminating a fourth dielectric layer on the second dielectric layer and the components, and curing the second dielectric layer and the fourth dielectric layer; (g) forming an outer circuit layer on the fourth dielectric layer; wherein the outer circuit layer conductively connects the conductive copper pillars, the shielding copper pillars, and the terminals of the components. By fabricating shielding copper pillars, component misalignment can be reduced during component extrusion, thereby improving yield. After embedding, all five sides of the component are covered with metallic copper, providing excellent electromagnetic shielding. The second and fourth dielectric layers can be made of high thermal conductivity materials, which can quickly conduct the heat generated by the component into the shielding copper pillars, thus significantly improving heat dissipation. No wire bonding is required; blind vias can effectively shorten the conduction loop. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this disclosure or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This diagram illustrates a structural schematic of an embedded substrate provided by related technologies. Figure 2(a) shows a cross-sectional schematic diagram of a structure corresponding to step (a) in a method for manufacturing an embedded substrate provided in this embodiment of the present disclosure; Figure 2(b) shows a cross-sectional schematic diagram of another structure corresponding to step (a) in a method for manufacturing an embedded substrate provided in this embodiment of the present disclosure; Figure 2(c) shows a cross-sectional schematic diagram of a structure corresponding to step (b) in a method for manufacturing an embedded substrate provided in an embodiment of the present disclosure; Figure 2(d) shows a top view of a shielding copper pillar in an embedded substrate provided in an embodiment of the present disclosure; Figure 2(e) shows a cross-sectional schematic diagram of a structure corresponding to step (c) in a method for manufacturing an embedded substrate provided in an embodiment of the present disclosure; Figure 2(f) shows a cross-sectional schematic diagram of a structure corresponding to step (d) in a method for manufacturing an embedded substrate provided in this embodiment of the present disclosure; Figure 2(g) shows a top view of a portion of the structure corresponding to step (d) in a method for manufacturing an embedded substrate according to an embodiment of the present disclosure; Figure 2(h) shows a cross-sectional schematic diagram of a structure corresponding to step (e) in a method for manufacturing an embedded substrate according to an embodiment of the present disclosure; Figure 2(i) shows a cross-sectional schematic diagram of a structure corresponding to step (f) in a method for manufacturing an embedded substrate provided in this embodiment of the present disclosure; Figure 2(j) shows a cross-sectional schematic diagram of a structure corresponding to step (g) in a method for manufacturing an embedded substrate provided in this embodiment of the present disclosure; Figure 2(k) shows a cross-sectional schematic diagram of another structure corresponding to step (g) in a method for manufacturing an embedded substrate provided in an embodiment of the present disclosure; Figure 3 This diagram illustrates the structure of an embedded substrate provided in an embodiment of the present disclosure. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0024] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0025] In the accompanying drawings, the thickness and shape of some layers and regions may be exaggerated for better understanding and ease of description.

[0026] When one element or layer is placed "on" another element or layer, the other layer or element can be directly inserted on or between the other element.

[0027] Figure 1 A schematic diagram of an embedded substrate provided by related technologies is shown. For example... Figure 1 As shown, a conductive dam 130', a conductive pillar 111', and a first chip 170' are disposed on a substrate 100'. An arc-shaped conductor 140' is disposed on the conductive dam 130', and a second chip 110' is disposed on the conductive pillar 111'. A molding compound 150' is pressed onto the substrate 100', covering the first chip 170', the conductive dam 130', the arc-shaped conductor 140', the conductive pillar 111', and the second chip 110'. A conductive layer 160' is disposed on the molding compound 150', and the conductive layer 160' is electrically connected to the arc-shaped conductor 140'. The conductive dam 130' is electrically connected to the conductive ground layer 101' located in the substrate 100' via a solder pad 102'. This technical solution uses a conductive dam 130' and an arc-shaped conductor 140' to form a Faraday cage. The height of the arc-shaped conductor 140' is reduced, and the sum of the heights of the conductive dam 130' and the arc-shaped conductor 140' is the height of the Faraday cage. The relatively high height of the arc-shaped conductor 140' leads to poor stability, making it prone to skew, causing short circuits or open circuits, and affecting the electromagnetic shielding effect. In addition, the heat dissipation performance of the encapsulation 150' is insufficient.

[0028] In view of the above, this disclosure provides an embedded substrate and a method for manufacturing the same. The manufacturing method specifically includes: (a) providing a substrate; wherein a first circuit layer is formed on the surface of the substrate; (b) forming conductive copper pillars and shielding copper pillars on the first circuit layer; (c) laminating a second dielectric layer on the first circuit layer, such that the conductive copper pillars and the shielding copper pillars are embedded within the second dielectric layer; (d) mounting components on the second dielectric layer, wherein the orthographic projection of the components on the substrate is surrounded by the shielding copper pillars; (e) pressing the components into the second dielectric layer, such that the shielding copper pillars and the first circuit layer surround the components; (f) laminating a fourth dielectric layer on the second dielectric layer and the components, and curing the second dielectric layer and the fourth dielectric layer; (g) forming an outer circuit layer on the fourth dielectric layer; wherein the outer circuit layer conductively connects the conductive copper pillars, the shielding copper pillars, and the terminals of the components. By fabricating shielding copper pillars, component misalignment can be reduced during component extrusion, thereby improving yield. After embedding, all five sides of the component are covered with metallic copper, providing excellent electromagnetic shielding. The second and fourth dielectric layers can be made of high thermal conductivity materials, which can quickly conduct the heat generated by the component into the shielding copper pillars, thus significantly improving heat dissipation. No wire bonding is required; blind vias can effectively shorten the conduction loop.

[0029] In a first aspect, embodiments of this disclosure provide a method for fabricating an embedded substrate. Figures 2(a) to 2(k) show cross-sectional schematic diagrams or top views of intermediate structures or partial structures of each step in the fabrication method of an embedded substrate provided by embodiments of this disclosure. As shown in Figures 2(a) to 2(k), the fabrication method includes: First, a semi-finished substrate is provided—step (a), as shown in Figures 2(a) to 2(b). Here, the semi-finished substrate can be a multilayer substrate, which can be manufactured using core-based or coreless processes.

[0030] In some embodiments, the semi-finished substrate includes a first circuit layer 201, a first dielectric layer 102, and a second circuit layer 202; the first circuit layer 201 and the second circuit layer 202 are located on both sides of the first dielectric layer 102. The following example uses the core process to demonstrate the fabrication method of a semi-finished substrate, but it is not limited to this method in practice.

[0031] In some embodiments, step (a) includes: (a1) As shown in Figure 2(a), a core board 100 is provided. Here, the core board 100 includes a first dielectric layer 102 and a first copper foil 103 and a second copper foil 101 attached to the surface of the first dielectric layer 102.

[0032] Optionally, the material of the first dielectric layer 102 may be a glass fiber-containing resin material, such as one selected from the group consisting of liquid crystal polymers, BT (bismaleimide triazine) resin, prepreg, ABF (Ajinomoto Build-up) film, epoxy resin and polyimide resin, but this disclosure does not limit it.

[0033] (a2) As shown in Figure 2(b), a first circuit layer 201 and a second circuit layer 202 are formed on the first dielectric layer 102. For example, the first circuit layer 201 can be formed on the first copper foil 103; the second circuit layer 202 can be formed on the second copper foil 101.

[0034] Next, conductive copper pillars 301 and shielding copper pillars 302 are formed on the first circuit layer 201—step (b), as shown in Figure 2(c). It should be noted that conductive copper pillars 301 and shielding copper pillars 302 can be formed by methods such as pattern transfer and electroplating, which will not be described in detail in this disclosure.

[0035] Figure 2(d) shows a top view of the shielding copper pillar 302. As shown in Figure 2(d), the shielding copper pillar 302 encloses and forms a shielding area. The width of the shielding copper pillar 302 (corresponding to the distance between arrows J1 and J2) is 50~200 μm, for example, 50 μm, 80 μm, 100 μm, 135 μm, 150 μm, 180 μm, 200 μm.

[0036] In some embodiments, the height of the shielding copper pillar 302 is 30~700 μm, including 30 μm, 40 μm, 80 μm, 100 μm, 150 μm, 180 μm, 300 μm, 435 μm, 500 μm, 580 μm, 650 μm, and 700 μm.

[0037] In some embodiments, the enclosing shape of the shielding copper pillar 302 can be determined according to the shape of the mounted component 501, such as square, circular, etc.

[0038] In some embodiments, the enclosure state of the shielding copper pillar 302 can be fully enclosed (as shown in Figure 2(d)) or have partial openings. It should be understood that the enclosure state of the shielding copper pillar 302 can be adjusted according to actual needs, and this disclosure does not limit it.

[0039] In some embodiments, the heights of the conducting copper pillar 301 and the shielding copper pillar 302 may be the same or different, and this disclosure does not limit this.

[0040] Optionally, the height of the conductive copper pillar 301 is no greater than the height of the shielding copper pillar 302. This arrangement helps ensure that the subsequent component 501 is surrounded by the shielding copper pillar 302 on all four sides.

[0041] Then, a second dielectric layer 401 is laminated onto the first circuit layer 201, the conductive copper pillar 301 and the shielding copper pillar 302—step (c), as shown in Figure 2(e).

[0042] In some embodiments, step (c) further includes: laminating a third dielectric layer 402 onto the second circuit layer 202.

[0043] In some embodiments, the thickness of the second dielectric layer 401 is not less than the height of the conductive copper pillar 301 and the shielding copper pillar 302.

[0044] In some embodiments, the material of the second dielectric layer 401 is a resin material with viscosity and high thermal conductivity, such as a high thermal conductivity adhesive film (pressure-sensitive adhesive film, thermosetting adhesive film). Here, the high thermal conductivity resin material can be λ≥1 Wm. -1 K -1 (25 ℃) resin material.

[0045] It should be noted that the material of the third dielectric layer 402 can be the same as or different from the material of the second dielectric layer 401.

[0046] It should be understood that the second dielectric layer 401 and the third dielectric layer 402 in step (c) are in an uncured state.

[0047] Next, component 501 is mounted on the second dielectric layer 401, with the orthographic projection of component 501 onto the semi-finished substrate located within the orthographic projection of the shielding copper pillar 302 onto the semi-finished substrate—step (d), as shown in Figures 2(f) and 2(g). This arrangement reduces the offset of component 501 during the pressing of component 501 into the second dielectric layer 401.

[0048] Here, component 501 can be an active component (such as a transistor, IC chip, logic circuit element, or power amplifier) ​​or a passive component (capacitor, inductor, or resistor).

[0049] In some embodiments, the height of the shielding copper pillar 302 is flush with the height of the component 501.

[0050] In some embodiments, as shown in FIG2(g), the spacing L1 between the shielding copper pillar 302 and the component 501 is 10~300μm, such as 10 μm, 20 μm, 40 μm, 80 μm, 100 μm, 150 μm, 180 μm, 300 μm, etc., and this disclosure does not limit it.

[0051] Then, component 501 is pressed into the second dielectric layer 401, so that the shielding copper pillar 302 and the first circuit layer 201 surround component 501 on five sides—step (e), as shown in Figure 2 (h).

[0052] Here, component 501 is pressed into shielding copper pillar 302. Component 501 is surrounded by copper (corresponding to shielding copper pillar 302 and the first circuit layer 201) on all sides and at the bottom, forming an embedded structure that provides five-sided shielding for component 501, which can achieve a good electromagnetic shielding effect.

[0053] Furthermore, by using a resin material with viscosity and high thermal conductivity to form the second dielectric layer 401 and the subsequent fourth dielectric layer 601, it can serve as the adhesive layer and encapsulation layer for component 501, encapsulating all six sides of component 501. Compared with encapsulation plastic, it can play a good role in heat dissipation of component 501.

[0054] Optionally, step (e) employs a vacuum hot pressing process.

[0055] Next, a fourth dielectric layer 601 is pressed onto the surfaces of the second dielectric layer 401 and the component 501, and the second dielectric layer 401, the third dielectric layer 402 and the fourth dielectric layer 601 are cured—step (f), as shown in Figure 2(i).

[0056] Optionally, the second dielectric layer 401 and the fourth dielectric layer 601 are made of the same material. Using the same material for both can reduce the stress at the interface between them, which helps to improve the stability of the embedded substrate.

[0057] Finally, an outer circuit layer 701 is formed on the fourth dielectric layer 601; the outer circuit layer 701 is connected to the terminals of the conductive copper pillar 301, the shielding copper pillar 302 and the component 501—step (g), as shown in Figures 2(j) and 2(k).

[0058] In some embodiments, step (g) includes: (g1), as shown in Figure 2(j), a blind hole is made by laser to expose the terminals of the conductive copper pillar 301, the shielding copper pillar 302 and the component 501; Here, the terminals of the outer circuit layer 701, the conductive copper pillar 301, the shielding copper pillar 302 and the component 501 are connected by blind holes, eliminating the need for wire bonding and helping to shorten the conduction loop; (g2) A first seed layer is formed in the fourth dielectric layer 601; (g3) Apply a film to the first seed layer, expose it, and develop it; (g4) Through-hole electroplating forms the outer circuit layer 701; (g5) Remove the film and etch the first seed layer.

[0059] It should be noted that, depending on actual needs, additional layers or surface treatments can be applied to the outer circuit layer 701, which are detailed in this disclosure.

[0060] Based on the same inventive concept, the second aspect of this disclosure also provides an embedded substrate.

[0061] Figure 3 This diagram illustrates the structure of an embedded substrate provided in an embodiment of the present disclosure. Figure 3 As shown, the embedded substrate includes a first dielectric layer 102, a first circuit layer 201, shielding copper pillars 302, conductive copper pillars 301, components 501, a second dielectric layer 401, a fourth dielectric layer 601, and an outer circuit layer 701; wherein, The first circuit layer 201 is located on the first dielectric layer 102. The conductive copper pillar 301 and the shielding copper pillar 302 are located on the first circuit layer 201. The second dielectric layer 401 covers the first circuit layer 201, the conductive copper pillar 301 and the shielding copper pillar 302. The component 501 is embedded in the second dielectric layer 401 and is surrounded by the shielding copper pillar 302 and the first circuit layer 201. The fourth dielectric layer 601 is located on the second dielectric layer 401. The outer circuit layer 701 is located on the fourth dielectric layer 601 and is conductively connected to the terminals of the conductive copper pillar 301, the shielding copper pillar 302 and the component 501.

[0062] In some embodiments, the material of the second dielectric layer 401 is a resin material with viscosity and high thermal conductivity.

[0063] In some embodiments, the spacing between the shielding copper pillar 302 and the component 501 is 10~300 μm; and / or The width of the shielding copper pillar 302 is 50~200 μm; and / or The height of the shielding copper pillar 302 is 30~700 μm.

[0064] In some embodiments, the shielding copper pillar 302 may be fully enclosed or have partial openings.

[0065] In some embodiments, the system further includes a second circuit layer 202 and a third dielectric layer 402; wherein the second circuit layer 202 is located on the side of the first dielectric layer 102 away from the first circuit layer 201; and the third dielectric layer 402 is located above the second circuit layer 202.

[0066] It should be noted that the above-described embodiments of the embedded substrate and the aforementioned manufacturing method are based on the same inventive concept and have similar technical effects, and will not be described again.

[0067] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0068] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for manufacturing an embedded substrate, characterized in that, include: (a) Provide a substrate; A first circuit layer is formed on the surface of the substrate; (b) Forming conductive copper pillars and shielding copper pillars on the first line layer; (c) A second dielectric layer is laminated onto the first circuit layer, such that the conductive copper pillar and the shielding copper pillar are embedded in the second dielectric layer; (d) Components are mounted on the second dielectric layer, wherein the orthographic projection of the components on the substrate is surrounded by the shielding copper pillars; (e) Press the component into the second dielectric layer, such that the shielding copper pillar and the first circuit layer surround the component; (f) A fourth dielectric layer is laminated onto the second dielectric layer and the component, and the second dielectric layer and the fourth dielectric layer are cured. (g) An outer circuit layer is formed on the fourth dielectric layer; wherein the outer circuit layer is conductively connected to the conductive copper pillar, the shielding copper pillar and the terminal of the component.

2. The manufacturing method according to claim 1, characterized in that, Step (a) includes: (a1) A core board is provided; wherein the core board includes a first dielectric layer; (a2) The first circuit layer is formed on the first dielectric layer.

3. The manufacturing method according to claim 1, characterized in that, The distance between the shielding copper pillar and the component is 10~300 μm; and / or The width of the shielding copper pillar is 50~200 μm; and / or The height of the shielding copper pillar is 30~700 μm.

4. The manufacturing method according to claim 1, characterized in that, The shielding copper pillars form a shielding area that surrounds the component in the horizontal direction.

5. The manufacturing method according to claim 1, characterized in that, The height of the shielding copper pillar is not less than the height of the component.

6. The manufacturing method according to claim 1, characterized in that, The thickness of the second dielectric layer is not less than the height of the conductive copper pillar and the shielding copper pillar.

7. The manufacturing method according to claim 1, characterized in that, Step (e) employs a vacuum hot pressing process.

8. The manufacturing method according to claim 1, characterized in that, The second dielectric layer and the fourth dielectric layer are made of the same material.

9. The manufacturing method according to claim 1, characterized in that, Step (g) includes: (g1) A blind hole is created using laser to expose the conductive copper pillar, the shielding copper pillar, and the terminals of the component; (g2) A first seed layer is formed in the fourth medium layer; (g3) Apply a film to the first seed layer, expose it, and develop it; (g4) Through-hole electroplating is performed to form the outer circuit layer; (g5) Remove the film and etch the first seed layer.

10. The manufacturing method according to claim 1, characterized in that, The substrate further includes a first dielectric layer and a second circuit layer; the first circuit layer and the second circuit layer are respectively located on both sides of the first dielectric layer; Step (c) further includes: laminating a third dielectric layer onto the surface of the second circuit layer.

11. The manufacturing method according to claim 1, characterized in that, The material of the second dielectric layer is a resin material that has room temperature viscosity and high thermal conductivity before curing.

12. An embedded substrate, characterized in that, It includes a first dielectric layer, a first circuit layer, conductive copper pillars, shielding copper pillars, components, a second dielectric layer, a fourth dielectric layer, and an outer circuit layer; wherein, The first circuit layer is located on the first dielectric layer, the shielding copper pillar and the conducting copper pillar are located on the first circuit layer, the second dielectric layer covers the first circuit layer, the shielding copper pillar and the conducting copper pillar, the component is embedded in the second dielectric layer and surrounded by the shielding copper pillar and the first circuit layer, the fourth dielectric layer is located on the second dielectric layer, and the outer circuit layer is located on the fourth dielectric layer and is conductively connected to the shielding copper pillar, the conducting copper pillar and the terminal of the component.

13. The embedded substrate according to claim 12, characterized in that, The material of the second dielectric layer is a resin material that has room temperature viscosity and high thermal conductivity before curing.

14. The embedded substrate according to claim 12, characterized in that, The distance between the shielding copper pillar and the component is 10~300 μm; and / or The width of the shielding copper pillar is 50~200 μm; and / or The height of the shielding copper pillar is 30~700 μm.

15. The embedded substrate according to claim 12, characterized in that, The shielding copper pillars form a shielding area that surrounds the component in the horizontal direction.

16. The embedded substrate according to claim 12, characterized in that, It also includes a second circuit layer and a third dielectric layer; wherein the second circuit layer is located on the side of the first dielectric layer away from the first circuit layer; and the third dielectric layer is located above the second circuit layer.

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