System and method for detecting and positioning code memory change of power secondary equipment

Abstract

The invention discloses an electric power secondary equipment code memory change detection positioning system and method. The system comprises upper computer detection software, a device management plug-in and a monitored core processing plug-in, wherein the device management plug-in and the monitored core processing plug-in communicate with the upper computer detection software; the method comprises the following steps: configuring a CPU memory code segment; the upper computer obtains CPU code space distribution of the device; forming a code memory space configuration file; the upper computer software sequentially obtains the normal code memory space of each plug-in; the device performs code memory change detection and alarm; and the upper computer software reads the memory space value of the abnormal operation code of the alarm CPU, and the upper computer locates the memory change position. According to the method, the dependence on the resources of the processor is effectively reduced, a method for accurately positioning the fault is provided, and the situation that the operation needs to be quitted for maintenance due to function failure caused by a single fault in the equipment engineering operation process is reduced.

Description

Technical Field

[0001] This invention relates to the field of detection technology for power secondary system devices, and in particular to a system and method for detecting and locating changes in the code memory of power secondary equipment. Background Technology

[0002] Secondary power system devices are a crucial component of the protection and control functions in power systems. As the system's "brain," they receive and process data from various sensors, issue control commands based on preset control algorithms and logic, and monitor, control, and protect different objects in various power scenarios, ensuring the system's efficient, stable, and safe operation. Secondary power system devices often employ a platform design based on multi-CPU plug-in modules for functional combination. Due to the complex field environment of secondary power system devices, and under long-term uninterrupted power operation, factors such as cosmic rays, packaging materials, and software defects may alter the CPU memory, leading to device malfunctions or potential operational risks.

[0003] With the increasing number of new energy power generation devices and the growing complexity of power grid structures, the stable operation of new power systems has become particularly important. Power secondary system devices, through advanced control algorithms and efficient power electronics, can ensure stable operation of the system under various operating conditions and achieve precise regulation of the output power of new energy power generation systems, thereby maximizing grid stability and energy utilization efficiency.

[0004] Due to the computational resource requirements of complex algorithms and rapid control responses, system hardware typically employs extended computing CPU boards to flexibly expand computing resources. Protection and control operational algorithms can be deployed across multiple computing CPU boards, with each board performing parallel computations. Some CPU chips use methods such as ECC and parity checking to monitor and correct memory, while others lack these capabilities. Power secondary system software generally monitors critical data such as setpoints, but rarely monitors code memory. Furthermore, the real-time nature of power secondary system devices and the limitations of board resources prevent real-time software from employing complex algorithms and large memory footprints for code memory monitoring. Consequently, changes in code memory are difficult to detect, leading to malfunctions, loss of function, or even malfunctions. Even after detection, troubleshooting becomes extremely difficult, increasing processing time.

[0005] To address the aforementioned issues, existing solutions include two approaches: one is to add real-time software memory verification functionality. This involves using external programmable logic devices (PLDs) or coprocessors to divide the processor's memory space into different levels of regions. Based on the importance of each region, the PLDs or coprocessors can then verify the memory within the processor. The other approach is to reconstruct the protection application into two independent logic processing programs. These programs have identical content but different exit methods. If the execution results of the two programs are consistent, the exit operation is executed; otherwise, the system is restarted.

[0006] Chinese patent CN112053737 discloses a method and system for real-time soft error detection and recovery in online parallel processing. The method describes a hierarchical verification and recovery method for the RAM space of the processor, which is protected by a programmable logic device. However, this method mainly relies on peripheral programmable logic devices to realize memory monitoring, which requires the processor's memory to be re-divided. The application needs to reallocate the programs in the processor according to the partition definition, which requires a large amount of work to upgrade existing devices. At the same time, if the critical programs and data volume are large, the bus bandwidth requirements between the programmable logic device and the processor are relatively high. Otherwise, it is impossible to complete the data verification within the specified task cycle. Chinese patent CN116701029A discloses a method for real-time blocking and system recovery of soft errors in relay protection devices. The method, addressing the storage and memory of relay protection devices, proposes a soft error detection method that decomposes and reconstructs the fault handling program of the relay protection device, forming two independent logic processing programs. However, it primarily prevents device malfunctions caused by single memory faults through redundant logic processing. This solution requires reconstructing the application processing program, and important protection output logic needs to be deployed in duplicate, greatly increasing the complexity of upper-level module development. Simultaneously, the memory space occupied by the application increases exponentially, increasing the probability of soft errors and the risk of device failure to operate.

[0007] Both of these methods can only detect whether there is an error in the memory space; they cannot accurately pinpoint the memory address where the soft error occurred, nor can they accurately determine whether the error was caused by a program overflow or a single-bit flip due to a soft error. Furthermore, they require additional hardware or complex software overhead, making upgrades to existing operational equipment difficult and costly. Summary of the Invention

[0008] Purpose of the invention: The purpose of this invention is to provide a system and method for detecting and locating changes in the code memory of secondary power equipment.

[0009] Technical solution: The power secondary equipment code memory change detection and positioning system of the present invention includes host computer detection software, device management plug-in and monitored core processing plug-in that communicate with the host computer detection software. The device management plug-in is responsible for the management of configuration files and memory allocation files, and realizes data interaction between the host computer software and the monitored plug-in.

[0010] Furthermore, the host computer software communicates with the device's management plug-in via the standard IEC103 protocol. After establishing a link with the device, it uploads the device's configuration file and memory allocation file, as well as the code memory of each monitored plug-in, which serves as a comparison benchmark for locating the error address when the device malfunctions.

[0011] The method for detecting and locating code memory changes in secondary power equipment according to the present invention includes the following steps:

[0012] (1) CPU memory code segment configuration;

[0013] (2) The host computer obtains the CPU code space allocation of the device;

[0014] (3) Formation of code memory space configuration files;

[0015] (4) The host computer software sequentially obtains the normal code memory space of each plug-in;

[0016] (5) The device performs code memory change detection and alarm;

[0017] (6) The host computer software reads the abnormal memory space value of the alarm CPU running code;

[0018] (7) The host computer locates the memory and changes its position.

[0019] Further, step (1) includes defining the code space for the CPU's code segment in the memory configuration file LDF and predefining the actual length variable of the code space; after compilation, generating the running program and the memory allocation file map; after running, the software program obtains the actual length of the code space used through this variable.

[0020] Furthermore, step (2) includes the host computer reading the device configuration file to confirm the address of each CPU plug-in of the device; and identifying the starting address of the code segment and its actual allocated space according to the memory allocation file map corresponding to each CPU software.

[0021] Furthermore, step (3) includes the CPU software generating a code memory space configuration file corresponding to each plug-in of the device based on the starting address of each code segment and the actual space length.

[0022] Furthermore, step (4) includes the host computer reading the normal code memory data of each CPU by interacting with the device platform program based on the memory space configuration file of each plug-in code obtained in step (3); and generating a text file of each CPU memory according to a certain format.

[0023] Furthermore, step (5) includes summing the code space value based on the fixed starting address of the code and the actual code length obtained at the initial stage of each CPU software operation of the device, accumulating the code space value when the application task is idle, verifying it with the initial value after the calculation is completed, and issuing an alarm when there is a discrepancy.

[0024] Furthermore, step (6) includes identifying the alarm information sent by the host computer and determining the alarm board address. Based on the CPU code memory configuration space obtained in step (3), the alarm plug-in's code memory data is read by interacting with the device platform program.

[0025] Further, step (7) includes comparing the newly added alarm plugin memory file with the CPU normal code memory file sent during device initialization, and determining again whether the device code memory has changed. If it has changed, the specific location of the change is recorded.

[0026] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages:

[0027] (1) Existing technologies require the deployment of complex monitoring logic in the device or the use of auxiliary devices in the device, and the workload of program development is relatively large. This invention makes full use of the processing power of the host computer, and through the full analysis of the processor, the unified processing of the underlying general platform and the cooperation of the host computer software, without changing the application logic and adding auxiliary devices, it realizes the function of monitoring the code memory of the power secondary system device, which can reduce the risk of device functional failure or malfunction, and at the same time reduce the difficulty and workload of device upgrade;

[0028] (2) Existing technologies usually rely on the computing power and resources of the processor, and relatively complex detection functions will increase the load on the processor; the present invention deploys only simple logic on the device side, making full use of the computing power of the host computer, and reducing the requirements for the processor resources and performance of the device side.

[0029] (3) When analyzing on-site problems, most existing technologies require the use of analysis tools (simulators) to locate the error location. This invention uses host computer software to save the device's memory file in binary format in real time. Combined with the corresponding pre-compiled configuration file, the error address can be given directly, which greatly reduces the complexity of on-site problem analysis and effectively shortens the problem analysis and location time.

[0030] (4) Based on effectively monitoring the memory changes of the power secondary system device, the present invention effectively reduces the dependence on the processor's own resources, provides a method for accurately locating faults, and reduces the situation where equipment fails due to a single fault and needs to be taken out of operation for maintenance. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the system structure of the present invention;

[0032] Figure 2 This is a flowchart of the real-time memory anomaly detection process of the device of the present invention;

[0033] Figure 3 This is a flowchart of the host computer anomaly location process of the present invention. Detailed Implementation

[0034] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0035] like Figure 1 As shown, the power secondary equipment code memory change detection and positioning system of the present invention includes host computer detection software, device management plug-in that communicates with the host computer software, and core processing plug-in that is being monitored.

[0036] The host computer software communicates with the device's management plug-in via the standard IEC103 protocol. After establishing a link with the device, it uploads the device's configuration file and memory allocation file, and uploads the code memory of each monitored plug-in based on the above information, which serves as a comparison benchmark for locating the error address when the device malfunctions.

[0037] The device management plugin is responsible for managing configuration files and memory allocation files, enabling data interaction between the host computer software and the monitored plugin.

[0038] like Figure 3 As shown, the method for detecting and locating changes in the code memory of secondary power equipment according to the present invention includes the following steps:

[0039] (1) CPU memory code segment configuration: Define the code space for the CPU code segment in the memory configuration file (LDF) and predefine the actual length variable of the code space; after compilation, the executable program and memory allocation file (map) can be generated. After running, the software program can obtain the actual length of the code space used through this variable, preventing invalid space errors caused by full space verification from affecting the operation of the device;

[0040] (2) The host computer obtains the CPU code space allocation of the device: The host computer reads the device configuration file to confirm the address of each CPU plug-in of the device; and identifies the starting address of the code segment and its actual allocated space according to the memory allocation file (map) corresponding to each CPU software.

[0041] (3) The CPU software generates a code memory space configuration file corresponding to each plug-in of the device based on the starting address of each code segment and the actual space length.

[0042] (4) The host computer software sequentially obtains the normal code memory space of each plug-in: The host computer reads the normal code memory data of each CPU by interacting with the device platform program according to the configuration file of the memory space of each plug-in obtained in step S03; and generates a text file of each CPU memory according to a certain format.

[0043] (5) Figure 2 As shown, the device performs code memory change detection and alarm: At the beginning of operation, each CPU software of the device sums the code space value according to the fixed starting address of the code and the actual code length obtained. When the application task is idle, the device platform program accumulates the code space value. After the calculation is completed, it is verified with the initial value. If there is a discrepancy, an alarm is triggered.

[0044] (6) The host computer software reads the alarm CPU running code abnormal memory space value: The host computer identifies the alarm information sent by the device, determines the alarm board address, and reads the code memory data of the alarm plug-in by interacting with the device platform program according to the CPU code memory configuration space obtained in step S03.

[0045] (7) The host computer locates the memory change location: The host computer compares the newly added alarm plugin memory file with the normal CPU code memory file sent by the device during initialization, and determines again whether the device code memory has changed. If it has changed, the specific location of the change is recorded.

[0046] Example:

[0047] This embodiment mainly describes a power electronic control device based on using an ADI DSP chip as the CPU.

[0048] Example 1 provides a power electronic control device code memory change detection and positioning system, including a host industrial control computer with monitoring software and a power electronic control system device. The monitoring software is connected to the device's management plug-in via a network cable, and data interaction uses the IEC103 protocol. The device management plug-in and the monitored plug-in are connected via a CAN bus, and the local code memory is uploaded according to a private protocol.

[0049] The host industrial control computer is equipped with monitoring software that communicates with the device via the IEC103 protocol. It can monitor multiple devices simultaneously based on different IP addresses, and create a memory backup file locally to achieve accurate location of real-time memory and backup memory. Based on whether the error is a single bit or multiple bits, it can effectively filter out soft errors and program anomalies.

[0050] The device's management plugin acts as an intermediary, responsible for storing pre-compiled memory space files and device configuration files, and providing these files to the host computer. The host computer can then determine the address of the monitored plugin and the memory location of the code to be monitored based on these files. Simultaneously, it manages all monitored plugins via the CAN bus, forwards commands from the host computer, and transmits data from the monitored plugins.

[0051] The monitored plug-in of the device deploys a local code space verification module. The local verification result is sent to the monitoring software of the host industrial control computer through the management plug-in. According to the issued command, the local code space is sent up.

[0052] Example 2 provides a method for detecting and locating changes in the code memory of a power electronic control system device.

[0053] 1. In S1, by defining a memory length variable in the LDF, the compiler generates this variable as a global variable and assigns it a value. During device runtime, the CPU software can read this variable. The maximum space allocation for the LDF code is defined as follows:

[0054]

[0055] The actual length variable of the code space is defined as follows:

[0056]

[0057] 2. The board configuration content in the device configuration file in step (2) is as follows:

[0058] [CARD NUM=3]

[0059] ADDR = 1 TYPE = board 1

[0060] ADDR = 2TYPE = board2

[0061] ADDR = 3TYPE = board3

[0062] The memory allocation file contains the following information about memory, including the starting address and actual length of the memory allocation.

[0063] <MEMORY id=′00EABA28′name=′seg_int_code′start_address=′0x124300′end_address=′0x13bfff′type=′SW′qualifier=′RAM′width=′0x10′words_used=′0x17d00′words_unused=′0x0′>

[0064] 3. The code space file format in step (3) is as follows, which includes the board address, board name, number of memory blocks, and the start address and actual end address of each memory block;

[0065]

[0066] 4. After the host computer establishes a connection with the device in step (4), it sequentially accesses the memory of each plug-in of the device according to the configuration information in S02 and S03, and generates a text file of the memory. The format is as follows, which includes the board address, the number of memory blocks and the actual memory value of each memory block.

[0067] Board No.: 2

[0068] Memory Count: 4

[0069] Memeory1: 0x00092000 0x0009Afff

[0070] 0x00092000: 0x00000000 0x00000000 0x00000000 0x00000000…

[0071] 5. The implementation process of step (5) is as follows: Figure 2 As shown;

[0072] 6. The overall logic is as follows: Figure 3 As shown, due to the fixed nature of code memory, the code memory space value can be implemented on any device of the same type when the reading device is running normally.

Claims

1. A system for detecting and locating code memory changes in secondary power equipment, characterized in that, It includes host computer detection software, device management plugins that communicate with the host computer detection software, and core processing plugins that are being monitored. The device management plugin is responsible for managing configuration files and memory allocation files, and enables data interaction between the host computer software and the monitored plugins.

2. The power secondary equipment code memory change detection and positioning system according to claim 1, characterized in that, The host computer software communicates with the device's management plugin via the standard IEC103 protocol. After establishing a link with the device, it uploads the device's configuration file and memory allocation file, as well as the code memory of each monitored plugin, which serves as a comparison benchmark for locating the error address when the device malfunctions.

3. A method for detecting and locating changes in the code memory of secondary power equipment, characterized in that, Includes the following steps: (1) CPU memory code segment configuration; (2) The host computer obtains the CPU code space allocation of the device; (3) Formation of code memory space configuration files; (4) The host computer software sequentially obtains the normal code memory space of each plug-in; (5) The device performs code memory change detection and alarm; (6) The host computer software reads the abnormal memory space value of the alarm CPU running code; (7) The host computer locates the memory and changes its position.

4. The method for detecting and locating changes in the code memory of secondary power equipment according to claim 3, characterized in that, Step (1) includes defining the code space for the CPU's code segment in the memory configuration file LDF and predefining the actual length variable of the code space; after compilation, generating the running program and the memory allocation file map; after running, the software program obtains the actual length of the code space used through this variable.

5. The method for detecting and locating changes in the code memory of secondary power equipment according to claim 3, characterized in that, Step (2) includes the host computer reading the device configuration file to confirm the address of each CPU plug-in of the device; and identifying the starting address of the code segment and its actual allocated space according to the memory allocation file map corresponding to each CPU software.

6. The method for detecting and locating changes in the code memory of secondary power equipment according to claim 3, characterized in that, Step (3) includes the CPU software generating a code memory space configuration file corresponding to each plug-in of the device based on the starting address of each code segment and the actual space length.

7. The method for detecting and locating changes in the code memory of secondary power equipment according to claim 3, characterized in that, Step (4) includes the host computer reading the normal code memory data of each CPU by interacting with the device platform program based on the memory space configuration file of each plug-in code obtained in step (3); and generating a text file of each CPU memory according to a certain format.

8. The method for detecting and locating changes in the code memory of secondary power equipment according to claim 3, characterized in that, Step (5) includes summing the code space value based on the fixed starting address of the code and the actual code length at the beginning of the operation of each CPU software in the device. The device platform program accumulates the code space value when the application task is idle. After the calculation is completed, it is verified with the initial value. If there is a discrepancy, an alarm is triggered.

9. The method for detecting and locating changes in the code memory of secondary power equipment according to claim 3, characterized in that, Step (6) includes identifying the alarm information sent by the host computer and determining the alarm board address. Based on the CPU code memory configuration space obtained in step (3), the alarm plug-in's code memory data is read by interacting with the device platform program.

10. The method for detecting and locating changes in the code memory of secondary power equipment according to claim 3, characterized in that, Step (7) includes comparing the newly added alarm plugin memory file with the CPU normal code memory file sent during device initialization, and determining again whether the device code memory has changed. If it has changed, the specific location of the change is recorded.

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