Over-constraint excitation positioning method, system and equipment based on relaxation constraint

Abstract

The invention relates to the technical field of integrated circuit design verification, and discloses a relaxation constraint-based over-constraint excitation positioning method, system and device, and the method achieves the automatic recognition of the over-constraint in a test platform through a systematic relaxation constraint method, and solves the problems of high concealment and low recognition efficiency of the over-constraint in the prior art. The excessive constraint can be quickly identified, the coverage rate loss and the simulation resource waste caused by the constraint problem are reduced, the chip verification period is shortened, and the project cost is reduced; hidden excessive constraints which are difficult to find by traditional coverage rate analysis can be identified; and the method is suitable for various test platforms based on SystemVerilog, and particularly has outstanding performance in integration-level complex design.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design verification, for example, to a method, system, device and storage medium for locating over-constrained excitation based on relaxed constraints. BACKGROUND

[0002] Modern verification environment highly depends on SystemVerilog constraint solver to generate excitation to verify the functional correctness of the design. With the increasing complexity of integrated circuit design, the scale of constraint set in verification platform expands dramatically. In unit and system level verification platform, the number of constraints can reach thousands. However, during the project advancement, the constraint set will be over-constrained due to various factors.

[0003] For example, after the requirement changes, the original constraints are not updated synchronously, resulting in the disconnection between the constraints and the actual functional requirements; the temporary constraints in the legacy code for avoiding known problems are not removed in time, forming redundant constraints; the verification engineers have deviations in understanding the design specifications, or mistakes occur in the coding process, resulting in over-tightening of the constraint range.

[0004] Over-constraints will not cause test failures like under-constraints, but will reduce the feasible space of excitation, reduce test coverage, and even increase simulation time and resource consumption. The traditional coverage analysis method relies on manual marking of legal and illegal intervals. If the verification personnel and the design personnel have common misunderstandings about the specifications, they may misjudge the un-covered interval caused by over-constraints as "illegal", thereby missing the problem. In addition, the coverage miss may be caused by non-constraint factors such as test platform code defects, which is difficult to directly attribute to over-constraints.

[0005] In summary, the existing technical solutions have the problems of strong over-constraint concealment and low identification efficiency.

[0006] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present application. SUMMARY

[0007] To have a basic understanding of some aspects of the disclosed embodiments, a brief overview is given below. The overview is not a comprehensive review of the application, nor is it intended to determine key / important elements or delineate the scope of the embodiments. It is intended to serve as an introduction to the detailed description below.

[0008] The method, system and device for locating over-constrained excitation based on relaxed constraints provided by the embodiments of the present disclosure can solve the problems of strong over-constraint concealment and low identification efficiency in the existing solutions.

[0009] The embodiments of the present disclosure provide a method for locating over-constrained excitation based on relaxed constraints, which can include:

[0010] Traverse the file including constraints in the test platform, split each compound constraint into independent constraint blocks by parsing the logical structure of the constraints, that is, each constraint block corresponds to a single constraint condition, and ensure that each constraint block can be relaxed independently;

[0011] Insert custom code in the pre_randomize and post_randomize functions of the verification platform. In the pre_randomize phase, save the original state of the random variable, disable the target constraint block, and perform secondary randomization to generate a candidate solution. In the post_randomize phase, restore the original state of the random variable to ensure that the original logic of the test platform is not disturbed;

[0012] For each independent constraint block, generate a random solution P by secondary randomization, and determine whether P belongs to the feasible region F defined by the original constraint set;

[0013] Based on the region attribution of the random solution P and the test result, determine whether the constraint is excessive.

[0014] In some embodiments, the above method further comprises:

[0015] Ensure that the code of the original pre_randomize and post_randomize functions is executed in a predetermined order, and only the constraint relaxation and secondary randomization steps are inserted in the middle.

[0016] In some embodiments, the above random solution P is a set of stimulus parameters specifically including data length and type;

[0017] The feasible region F is the set of all solutions that satisfy the original constraints.

[0018] In some embodiments, the above determination of whether the constraint is excessive based on the region attribution of the random solution P and the test result comprises:

[0019] If P∈F, then regardless of whether the test passes or fails, it is not marked as an excessive constraint;

[0020] If and the test passes, mark the corresponding constraint as an excessive constraint, in which case P belongs to the excessive constraint region R that is supported by the design but excluded by the constraint;

[0021] If and the test fails, it is not marked as an excessive constraint, in which case P belongs to the infeasible region X that is not supported by the design.

[0022] In some embodiments, the above excessive constraint region R is the solution space that the design itself can correctly handle but is incorrectly excluded by the original constraint, and the infeasible region X is the solution space that the design cannot handle, both of which have no intersection with the feasible region F.

[0023] In some embodiments, the above method further includes:

[0024] Generate structured reports based on information that is over-constrained.

[0025] This disclosure provides an over-constraint excitation localization system based on relaxed constraints, the system comprising:

[0026] The constraint processing module is used to traverse the files containing constraints in the test platform. By parsing the logical structure of the constraints, it breaks down each composite constraint into an independent constraint block. That is, each constraint block corresponds to a single constraint condition, ensuring that each constraint block can be relaxed individually.

[0027] A custom code module is used to insert custom code into the pre_randomize and post_randomize functions of the verification platform. In the pre_randomize stage, the original state of the random variables is saved, the target constraint block is disabled, and a second randomization is performed to generate candidate solutions. In the post_randomize stage, the original state of the random variables is restored to ensure that the original logic of the test platform is not disturbed.

[0028] The simulation execution module is used to generate a random solution P for each independent constraint block through secondary randomization, and to determine whether P belongs to the feasible region F defined by the original constraint set.

[0029] The result judgment module is used to determine whether the constraints are excessive based on the region assignment of the random solution P and the test results.

[0030] This disclosure provides an electronic device that includes at least one processor;

[0031] and memory that is communicatively connected to at least one processor;

[0032] The memory stores instructions that can be executed by at least one processor, which enables the at least one processor to perform the above-described over-constraint excitation localization method based on relaxed constraints.

[0033] This disclosure provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the above-described over-constraint excitation localization method based on relaxation constraints.

[0034] The over-constraint excitation localization method, system, device, and storage medium based on relaxed constraints provided in this disclosure can achieve the following technical effects:

[0035] This disclosure utilizes a systematic constraint relaxation method to automatically identify excessive constraints in test platforms, addressing the problems of strong concealment and low identification efficiency of excessive constraints in existing technologies. It can quickly identify excessive constraints, reducing coverage loss and simulation resource waste caused by constraint issues, shortening chip verification cycles, and lowering project costs. Furthermore, it can identify implicit excessive constraints that are difficult to detect using traditional coverage analysis. Moreover, it is applicable to various SystemVerilog-based test platforms, and performs particularly well in complex integrated designs.

[0036] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0037] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0038] Figure 1 This is a flowchart illustrating an over-constraint excitation localization method based on relaxed constraints provided in an embodiment of this disclosure;

[0039] Figure 2 This is a flowchart illustrating another over-constraint excitation localization method based on relaxed constraints provided in this embodiment of the present disclosure;

[0040] Figure 3 This is a schematic block diagram of an over-constraint excitation positioning system based on relaxed constraints provided in an embodiment of this disclosure;

[0041] Figure 4 This is a schematic diagram of the structure of an over-constraint excitation positioning device based on relaxation constraints provided in an embodiment of this disclosure. Detailed Implementation

[0042] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0043] The terms "first," "second," etc., used in the embodiments of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0044] Unless otherwise stated, the term "multiple" means two or more.

[0045] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0046] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0047] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0048] To address the aforementioned issues, this disclosure provides a method, system, device, and storage medium for locating over-constraint excitations based on relaxed constraints.

[0049] The following description, in conjunction with the accompanying drawings, illustrates the over-constraint excitation localization method, system, device, and storage medium based on relaxed constraints provided in the embodiments of this disclosure.

[0050] Figure 1 This is a flowchart illustrating an over-constraint excitation localization method based on relaxed constraints provided in an embodiment of this disclosure.

[0051] Combination Figure 1 As shown, the over-constraint excitation localization method based on relaxed constraints may include:

[0052] S101, traverse the files containing constraints in the test platform, and by parsing the logical structure of the constraints, split each composite constraint into an independent constraint block, that is, each constraint block corresponds to a single constraint condition, ensuring that each constraint block can be relaxed individually.

[0053] S102. Insert custom code into the pre_randomize and post_randomize functions of the verification platform. In the pre_randomize stage, save the original state of the random variables, disable the target constraint block, and perform secondary randomization to generate candidate solutions. In the post_randomize stage, restore the original state of the random variables to ensure that the original logic of the test platform is not disturbed.

[0054] S103, For each independent constraint block, generate a random solution P through secondary randomization, and determine whether P belongs to the feasible region F defined by the original constraint set;

[0055] S104, based on the region assignment of the random solution P and the test results, determines whether the constraints are excessive.

[0056] In some embodiments, Figure 1 The methods also include:

[0057] The code of the original pre_randomize and post_randomize functions is guaranteed to be executed in a preset order, with constraint relaxation and secondary randomization steps inserted only in between.

[0058] In some embodiments, the above-mentioned random solution P is a set of excitation parameters specifically including data length and type;

[0059] The feasible region F is the set of all solutions that satisfy the original constraints.

[0060] In some embodiments, the determination of whether the constraints are excessive based on the region attribution and test results of the random solution P includes:

[0061] If P∈F, then regardless of whether the test passes or fails, it is not marked as an over-constraint;

[0062] like If the test passes, the corresponding constraint is marked as an over-constraint. At this time, P belongs to the over-constraint region R that is supported by the design but excluded by the constraint.

[0063] like If the test fails, it is not marked as an over-constraint; in this case, P belongs to the infeasible region X that is not supported by the design.

[0064] In some embodiments, the over-constrained region R is a solution space that the design itself can handle correctly but is incorrectly excluded by the original constraints, and the infeasible region X is a solution space that the design cannot handle. Both of them have no intersection with the feasible region F.

[0065] In some embodiments, Figure 1 The methods may also include:

[0066] Generate structured reports based on information that is over-constrained.

[0067] In a specific embodiment, the constraint processing stage involves traversing the files containing constraints in the test platform. By parsing the logical structure of the constraints, each composite constraint is broken down into independent constraint blocks, meaning each constraint block corresponds to a single constraint condition, ensuring that each constraint block can be relaxed independently.

[0068] Custom code stage. Insert custom code into the `pre_randomize` and `post_randomize` functions of the validation platform to achieve the following functionality:

[0069] In the pre_randomize phase: save the original state of the random variables, disable the target constraint block, and perform secondary randomization to generate candidate solutions;

[0070] In the post_randomize phase: restore the original state of the random variables to ensure that the original logic of the test platform is not disturbed.

[0071] The above process ensures that the code of the original pre_randomize and post_randomize functions is executed in a preset order, with only constraint relaxation and secondary randomization steps inserted in between.

[0072] Simulation execution phase. During simulation testing, for each independent constraint block, a random solution P (i.e., a set of specific excitation parameters, such as data length, type, etc.) is generated through quadratic randomization. It is then determined whether P belongs to the feasible region F defined by the original constraint set (F is the set of all solutions satisfying the original constraints). The determination method is: if P satisfies all original constraints, then P∈F; otherwise...

[0073] Result Judgment Stage. Based on the region assignment of the random solution P and the test results, determine whether the constraint is excessive. If P∈F: regardless of whether the test passes, it is not marked as excessive constraint (because P does not exceed the original constraint range, it cannot reflect whether the constraint is too strict); if And the test passed: the corresponding constraint is marked as an over-constraint (at this time, P belongs to the over-constraint region R that is supported by the design but excluded by the constraint); if And if the test fails: it is not marked as over-constrained (at this time, P belongs to the infeasible region X that the design does not support). Among them, the over-constrained region R is the solution space that the design itself can handle but is incorrectly excluded by the original constraints, and the infeasible region X is the solution space that the design cannot handle. Both have no intersection with the feasible region F.

[0074] Results extraction phase. All information marked as over-constrained (including the corresponding constraint block, specific parameters of the random solution P, detailed logs of successful tests, etc.) is collected, a structured report is generated, and verification engineers review and examine it.

[0075] Figure 2 This is a flowchart illustrating another over-constraint excitation localization method based on relaxed constraints provided in this disclosure, combined with... Figure 2 ,right Figure 1 The over-constraint excitation localization method based on relaxation constraints will be further described.

[0076] The specific workflow of this over-constraint excitation localization method based on relaxed constraints can be as follows:

[0077] 1. Constraint handling: Splitting constraint blocks

[0078] The purpose of constraint processing is to break down composite constraints in the test platform into independent constraint blocks, so that each constraint can be relaxed individually later. This process is automatically completed by the constraint processing module using a Python script.

[0079] File traversal and parsing. The Python script first traverses all SystemVerilog files with the .sv extension in the test platform. By recognizing the `constraint` keyword and code structure symbols such as { and}, it accurately locates the start and end lines of each constraint, recording the class to which the constraint belongs, the associated random variables, and the logical relationships between the constraint conditions. For example, for constraints containing multiple conditions, the script will identify their internal logical structure, providing a basis for subsequent decomposition.

[0080] Constraint splitting rules. Following the principle of "single condition, single constraint block," the script splits each composite constraint into multiple independent constraint blocks, each corresponding to a specific condition in the original constraint. During splitting, constraints containing special keywords such as `solve / before`, `dist`, and `soft` are ignored. After splitting, the original constraints are commented out, and the correspondence between constraint blocks and original constraints is recorded in a mapping file for easy future reference.

[0081] For example, if the original constraint contains multiple conditions, the script will break it down into multiple independent constraint blocks, each corresponding to one condition, while annotating the original constraint to ensure the traceability of the test platform.

[0082] 2. Code Insertion: Implementing Quadratic Randomization

[0083] The purpose of code insertion is to relax the target constraints and perform secondary randomization without affecting the original logic of the test platform, so as to generate random solutions that may be located in the over-constrained region. This involves modifying the pre_randomize and post_randomize functions.

[0084] Modify the `pre_randomize` function. Insert custom code into the `pre_randomize` function, and the execution flow is as follows:

[0085] Save the rand_mode state of all random variables and temporarily set it to rand_mode(0) (disable randomization).

[0086] Execute the existing code in the function;

[0087] Set the constraint_mode of the target constraint to 0 (relax the constraint), and call this.randomize() to perform secondary randomization;

[0088] Based on the results of the second randomization, mark whether the random solution P belongs to the feasible region F: if the randomization fails, then... If successful, then P∈F;

[0089] The constraint_mode of the target constraint is restored to 1 (constraint enabled).

[0090] The `post_randomize` function has been modified by inserting custom code. The execution flow is as follows:

[0091] Restore the original state of rand_mode for all random variables;

[0092] The original code in the execution function is executed.

[0093] Through the above modifications, the secondary randomization process is transparent to the verification platform and does not affect the execution order of the original test logic.

[0094] 3. Test Execution and Result Judgment

[0095] The purpose of test execution and result evaluation is to generate random solutions by executing tests and to identify over-constraints by combining the test results. This process is completed collaboratively by the test execution module and the result evaluation module.

[0096] Test execution. The test execution module executes tests according to the following rules:

[0097] In each test, a split constraint block is randomly selected as the target constraint.

[0098] After generating a random solution P, record the specific value of P and the actual test result (pass / fail); repeat the test up to a preset number of times (e.g., 300 times) to ensure sufficient sample coverage.

[0099] Result Judgment. The result judgment module makes a judgment based on the region affiliation of P and the test results:

[0100] If P∈F: Regardless of whether the test passes or not, the constraint is not marked as an over-constraint (it is still within the feasible region after relaxation and has no reference value);

[0101] like And the test passed: the constraint was marked as an over-constraint (P belongs to the over-constraint region R supported by the design);

[0102] like And the test failed: constraint not marked (P belongs to an infeasible region X that is not supported by the design).

[0103] 4. Results Extraction and Review

[0104] The result extraction and processing script extracts the following information from the test log: the ID of the constraint block marked as over-constrained; the specific value of the corresponding random solution P; and a structured report formed from the detailed logs of the test pass, containing the relationship between "constraint block - random solution - test result".

[0105] Verification personnel review the report in accordance with design specifications. A typical example is as follows:

[0106] Implicit over-constraint: A constraint restricts the field F3 ∈ {x, y, z}, but this field is only valid for ID1 packets and has no meaning for ID2 packets. Relaxing the constraint reveals that ID2 packets... The test passed, but it was marked as over-constrained. The adjusted constraint only applies to ID1.

[0107] Explicit over-constraint: A constraint is excluded due to a coding error, resulting in complex cross-scenario exclusion. After the constraint is relaxed, the verifier corrects the constraint logic, and the coverage is improved.

[0108] This invention includes at least the following beneficial effects:

[0109] Improve verification quality and efficiency: Quickly identify excessive constraints, reduce coverage loss and simulation resource waste caused by constraint problems, shorten chip verification cycle, and reduce project costs;

[0110] Wide coverage: It can identify implicit over-constraints that are difficult to detect with traditional coverage analysis;

[0111] High versatility: Applicable to various SystemVerilog-based test platforms, especially excelling in complex integrated designs.

[0112] The over-constraint stimulus localization method based on relaxed constraints disclosed herein is applicable to the automated identification of over-constraint stimuli in verification platforms built on SystemVerilog. It can be widely used in functional verification scenarios of complex integrated circuits such as digital chips and hardware accelerators, and can play a role in both unit-level and system-level verification platforms.

[0113] and Figure 1 Corresponding to the flowchart of the over-constraint excitation localization method based on relaxed constraints, this disclosure also provides an over-constraint excitation localization system based on relaxed constraints, such as... Figure 3 As shown, an over-constraint excitation localization system based on relaxed constraints may include:

[0114] The constraint processing module 301 is used to traverse the files containing constraints in the test platform, and by parsing the logical structure of the constraints, it splits each composite constraint into an independent constraint block, that is, each constraint block corresponds to a single constraint condition, ensuring that each constraint block can be relaxed individually.

[0115] Custom code module 302 is used to insert custom code into the pre_randomize and post_randomize functions of the verification platform. In the pre_randomize stage, the original state of the random variables is saved, the target constraint block is disabled, and secondary randomization is performed to generate candidate solutions. In the post_randomize stage, the original state of the random variables is restored to ensure that the original logic of the test platform is not disturbed.

[0116] The simulation execution module 303 is used to generate a random solution P for each independent constraint block through secondary randomization, and to determine whether P belongs to the feasible region F defined by the original constraint set.

[0117] The result judgment module 304 is used to determine whether the constraints are excessive based on the region assignment of the random solution P and the test results.

[0118] In some embodiments, Figure 3 The over-constraint excitation localization system based on relaxed constraints can also be used to ensure that the code of the original pre_randomize and post_randomize functions is executed in a preset order, with only constraint relaxation and secondary randomization steps inserted in the middle.

[0119] In some embodiments, the above-mentioned random solution P is a set of excitation parameters specifically including data length and type;

[0120] The feasible region F is the set of all solutions that satisfy the original constraints.

[0121] In some embodiments, the determination of whether the constraints are excessive based on the region attribution and test results of the random solution P includes:

[0122] If P∈F, then regardless of whether the test passes or fails, it is not marked as an over-constraint;

[0123] like If the test passes, the corresponding constraint is marked as an over-constraint. At this time, P belongs to the over-constraint region R that is supported by the design but excluded by the constraint.

[0124] like If the test fails, it is not marked as an over-constraint; in this case, P belongs to the infeasible region X that is not supported by the design.

[0125] In some embodiments, the over-constrained region R is a solution space that the design itself can handle correctly but is incorrectly excluded by the original constraints, and the infeasible region X is a solution space that the design cannot handle. Both of them have no intersection with the feasible region F.

[0126] In some embodiments, Figure 3 The over-constraint excitation localization system based on relaxed constraints can also be used to generate structured reports based on over-constraint information.

[0127] Combination Figure 4 As shown in the illustration, this disclosure also provides an over-constraint excitation localization device 400 based on relaxed constraints, including a processor 404 and a memory 401. Optionally, the system may further include a communication interface 402 and a bus 403. The processor 404, communication interface 402, and memory 401 can communicate with each other via the bus 403. The communication interface 402 can be used for information transmission. The processor 404 can call logical instructions in the memory 401 to execute the over-constraint excitation localization method based on relaxed constraints described in the above embodiment.

[0128] Furthermore, the logic instructions in the aforementioned memory 401 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0129] The memory 401, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 404 executes functional applications and data processing by running the program instructions / modules stored in the memory 401, that is, it implements the over-constraint excitation localization method based on relaxation constraints in the above embodiments.

[0130] The memory 401 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 401 may include high-speed random access memory and may also include non-volatile memory.

[0131] This disclosure provides a computer-readable storage medium storing computer-executable instructions, which are configured as an over-constraint excitation localization method based on relaxed constraints.

[0132] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0133] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0134] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. As used in the description of the embodiments, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used herein means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the terms “comprise” and its variations “comprises” and / or “comprising” refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Unless otherwise specified, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes the element. In this document, each embodiment may focus on describing the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, then the relevant parts can be referred to the description of the method section.

[0135] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0136] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0137] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0138] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0139] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0140] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0141] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0142] The systems and technologies described herein can be implemented in computing systems that include back-end components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected via digital data communication (e.g., a communication network) of any form or medium. Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0143] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0144] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this disclosure can be achieved, and this is not limited herein.

[0145] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for locating over-constrained excitations based on relaxed constraints, characterized in that, The method includes; The test platform traverses the files containing constraints, and by parsing the logical structure of the constraints, each composite constraint is broken down into an independent constraint block. That is, each constraint block corresponds to a single constraint condition, ensuring that each constraint block can be relaxed individually. Custom code is inserted into the pre_randomize and post_randomize functions of the verification platform. In the pre_randomize stage, the original state of the random variables is saved, the target constraint block is disabled, and a second randomization is performed to generate candidate solutions. In the post_randomize stage, the original state of the random variables is restored to ensure that the original logic of the test platform is not disturbed. For each independent constraint block, a random solution P is generated through quadratic randomization, and it is determined whether P belongs to the feasible region F defined by the original constraint set. Based on the region attribution of the random solution P and the test results, determine whether the constraints are excessive.

2. The positioning method according to claim 1, characterized in that, The method further includes: The code of the original pre_randomize and post_randomize functions is guaranteed to be executed in a preset order, with constraint relaxation and secondary randomization steps inserted only in between.

3. The positioning method according to claim 1, characterized in that, The random solution P is a set of specific excitation parameters including data length and type; The feasible region F is the set of all solutions that satisfy the original constraints.

4. The positioning method according to claim 1, characterized in that, The determination of whether constraints are excessive based on the region assignment and test results of the random solution P includes: If P∈F, then regardless of whether the test passes or fails, it is not marked as an over-constraint; like If the test passes, the corresponding constraint is marked as an over-constraint. At this time, P belongs to the over-constraint region R that is supported by the design but excluded by the constraint. like If the test fails, it is not marked as an over-constraint; in this case, P belongs to the infeasible region X that is not supported by the design.

5. The positioning method according to claim 4, characterized in that, The over-constrained region R is the solution space that the design itself can handle but is incorrectly excluded by the original constraints, and the infeasible region X is the solution space that the design cannot handle. Both of them have no intersection with the feasible region F.

6. The positioning method according to claim 1, characterized in that, The method further includes: Generate structured reports based on information that is over-constrained.

7. An over-constraint excitation positioning system based on relaxed constraints, characterized in that, The system includes; The constraint processing module is used to traverse the files containing constraints in the test platform. By parsing the logical structure of the constraints, it breaks down each composite constraint into an independent constraint block. That is, each constraint block corresponds to a single constraint condition, ensuring that each constraint block can be relaxed individually. A custom code module is used to insert custom code into the pre_randomize and post_randomize functions of the verification platform. In the pre_randomize stage, the original state of the random variables is saved, the target constraint block is disabled, and a second randomization is performed to generate candidate solutions. In the post_randomize stage, the original state of the random variables is restored to ensure that the original logic of the test platform is not disturbed. The simulation execution module is used to generate a random solution P for each independent constraint block through secondary randomization, and to determine whether P belongs to the feasible region F defined by the original constraint set. The result judgment module is used to determine whether the constraints are excessive based on the region assignment of the random solution P and the test results.

8. The positioning system according to claim 7, characterized in that, The random solution P is a set of specific excitation parameters including data length and type; The feasible region F is the set of all solutions that satisfy the original constraints.

9. An electronic device, characterized in that, include: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-6.

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