Matrix decomposition-based two-channel biorthogonal filter bank FPGA (Field Programmable Gate Array) implementation method

Abstract

The invention discloses a two-channel biorthogonal filter bank FPGA (Field Programmable Gate Array) implementation method based on matrix decomposition. The method comprises the following steps: for a two-channel biorthogonal filter bank, firstly determining an initial coefficient of a filter, then decomposing the initial coefficient into a coefficient retention sequence and a coefficient matrix, and further decomposing the coefficient matrix into a common matrix, a low-pass branch matrix and a high-pass branch matrix through common-base N-dimensional intercepted LU decomposition; the FPGA implementation scheme is designed by combining the structural characteristics of the two-channel biorthogonal filter bank and adopting the time division multiplexing technology, the number of multipliers is effectively reduced through efficient multiplexing of a multi-phase structure and the multipliers, and the hardware resource overhead in FPGA implementation is remarkably reduced. On the premise that orthogonality and reconstruction precision of the filter bank are guaranteed, operation efficiency and data throughput capacity of the system are improved, and a feasible and efficient solution is provided for FPGA implementation of a high-performance and real-time signal processing system.

Description

Technical Field

[0001] This invention belongs to the field of digital signal processing technology and relates to an FPGA implementation method for a two-channel biorthogonal filter bank based on matrix decomposition. Background Technology

[0002] A two-channel biorthogonal filter bank (2c-Biorthogonal Filter Bank) is a flexible digital filter bank with excellent reconstruction performance, widely used in image processing, speech signal processing, medical signal analysis, and multi-resolution analysis. Compared to the earlier two-channel quadrature mirror filter bank (2c-QMFB), the biorthogonal filter bank relaxes the orthogonality constraints, introducing paired analysis and synthesis filter banks, thus providing greater design freedom while maintaining perfect reconstruction capabilities. The core advantage of the biorthogonal structure compared to quadrature filters lies in allowing the low-pass and high-pass filters in the analysis and synthesis filters to have different structures, and the filters are linear in phase. These characteristics make it particularly suitable for applications sensitive to boundary conditions, such as image and video processing.

[0003] To ensure good frequency domain characteristics and reconstruction accuracy, the FIR filters in a two-channel bisorthogonal filter bank typically require a high order. This introduces significant resource consumption in hardware implementation. Therefore, optimizing the structural design to reduce hardware resource overhead without sacrificing the filter bank's frequency response and reconstruction performance has become an important research direction in this field. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention proposes an FPGA implementation method for a two-channel biorthogonal filter bank based on matrix decomposition. By performing common-base matrix decomposition on the coefficients of the analysis and synthesis filters, the two-channel biorthogonal filter bank achieves efficient multiplexing of the polyphase structure and multipliers through time-division multiplexing. This optimization strategy significantly reduces the number of multipliers required, thereby lowering the resource overhead of the hardware implementation.

[0005] The specific steps for implementing a two-channel biorthogonal filter bank based on matrix factorization on an FPGA are as follows:

[0006] Step 1: Determine the length l of the low-pass and high-pass filters in the two-channel biorthogonal filter bank and set the reconstruction error PRE, passband cutoff frequency ω0, and stopband cutoff frequency ω1 to obtain the initial coefficients h0 = [h0(0), h0(1), ..., h0(l-1)] of the low-pass filter and h1 = [h1(0), h1(1), ..., h1(l-1)] of the high-pass filter.

[0007] Step 2: Obtain the new sequence H0 of the low-pass filter and the new sequence H1 of the high-pass filter using the initial coefficients h0 and h1.

[0008]

[0009]

[0010] The new sequence H0 is decomposed into a coefficient-preserving sequence HM0 with M0 coefficients and a coefficient matrix E0 of size a×b0:

[0011] HM0=[H0(0),H0(1),…,h0(M0-1)]

[0012]

[0013] Similarly, the new sequence H1 is decomposed into a coefficient-preserving sequence HM1 with M1 coefficients and a coefficient matrix E1 of size a×b1:

[0014] HM1=[H1(0),H1(1),…,h1(M1-1)

[0015]

[0016] Performing a common-basis N-dimensional LU decomposition on the coefficient matrices E0 and E1 yields the common matrix U and the low-pass branch matrix X0 and high-pass branch matrix X1:

[0017]

[0018] The coefficient matrices E0 and E1 are approximately restored by decomposing the matrices U, X0, and X1:

[0019] E0≈U·X0

[0020] E1≈U·X1

[0021] In the coefficients of the first half of the filter, the zero term in the multiphase of the low-pass filter is formed by multiplying the odd-numbered terms of HM0, the odd-numbered terms of U in E0, and X0; the 1 term in the multiphase is formed by multiplying the even-numbered terms of HM0, the even-numbered terms of U in E0, and X0. In the multiphase of the high-pass filter, the zero term in the multiphase is formed by multiplying the odd-numbered terms of HM1, the odd-numbered terms of U in E1, and X1; the 1 term in the multiphase is formed by multiplying the even-numbered terms of HM1, the even-numbered terms of U in E1, and X1.

[0022] In the coefficients of the latter half of the filter, the zero term in the multiphase low-pass filter is formed by multiplying the even-numbered HM0 term, the even-numbered U term in E0, and X0; the 1 term in the multiphase low-pass filter is formed by multiplying the odd-numbered HM0 term, the odd-numbered U term in E0, and X0. In the multiphase high-pass filter, the zero term in the multiphase high-pass filter is formed by multiplying the even-numbered Hm1 term, the even-numbered U term in E1, and X1; the 1 term in the multiphase high-pass filter is formed by multiplying the odd-numbered HM1 term, the odd-numbered U term in E1, and X1.

[0023] Therefore, the values ​​of the filter coefficients are symmetrical. Furthermore, according to the properties of a two-channel bisorthogonal filter, for the low-pass filter g0 and the high-pass filter g1 in the composite filter, in the frequency domain, they satisfy G0(z) = H1(-z) and G1(z) = -H0(-z). Therefore, the low-pass filter coefficient g0 in the composite filter is the inverted even-numbered terms of the h1 coefficient, and the high-pass filter coefficient g1 is the inverted odd-numbered terms of the g0 coefficient.

[0024] Step 3: Design an FPGA implementation method for the analysis filter, including N common base U modules, 2N branch X modules, and 2 coefficient-preserving HM modules. The branch X modules include a low-pass X0 module and a high-pass X1 module. The coefficient-preserving HM modules include a low-pass H0M module and a high-pass H1M module. The input signal of the analysis filter is signal_in, and the output signal is signal_out.

[0025] The common basis U module for analysis is a module shared by the low-pass and high-pass filters in the analysis filter. The system clock period is T, the input signal is signal_in, and the output signals are signal_k, signal_l0, and signal_l1. It includes a multipliers, a delay timers with a delay of T0 = 2T, and 2a-2 adders. The multiplier coefficients are column vectors in the U matrix. The multipliers perform parallel operations. The output value of each multiplier is delayed by a delay timer T0, added to the output of the next multiplier, and then input to the next delay timer T0.

[0026] A two-state signal counter is introduced to control the data. The filter coefficients in the multiplier are defined as being calculated in ascending order when their numbers are in ascending order, and in descending order when they are in descending order. When the signal counter is at time 1, the common basis U module is analyzed to perform ascending order calculation of the coefficients of the even-numbered column vectors in the U matrix, and in descending order calculation of the coefficients of the odd-numbered column vectors.

[0027] At time 0 of the signal counter, the common basis U module performs forward calculation of the coefficients of the odd-numbered terms and reverse calculation of the coefficients of the even-numbered terms in the column vectors of the U matrix. The output signal signal_k is the output of the final adder in the forward calculation at each signal counter time, the output signal signal_l0 is the output of the final adder in the reverse calculation at each signal counter time after a delay of (l / 2+M0)T, and the output signal signal_l1 is the output of the final adder in the reverse calculation at each signal counter time after a delay of (l / 2+M1)T.

[0028] The input signals of the analysis low-pass X0 module are signal_k and signal_l0, and the output signal is signal_x0. It includes b0 multipliers, 2(b0-1) delay units with a delay T1 = aT, and 2b0-1 adders. The coefficients of the multipliers are the row vectors of the X0 matrix. The b0-1 delay units form a forward delay chain with signal_l0 as the input. The other b0-1 delay units form a reverse delay chain with signal_k as the input. signal_l0 is added to the output of the last delay unit in the reverse delay chain and then input to the multiplier. After being delayed by the first delay unit in the forward delay chain, it is added to the output of the second-to-last delay unit in the reverse delay chain and then input to the multiplier. This process continues until the output of the last delay unit in the forward delay chain is added to signal_k and then input to the multiplier. The outputs of all multipliers are added sequentially to obtain the output signal signal_x0 of the analysis low-pass X0 module.

[0029] The structure of the analysis high-pass X1 module is the same as that of the analysis low-pass X0 module. The input signals are signal_k and signal_l1, and the output signal is signal_x1. It includes b1 multipliers, 2(b1-1) delay units with a delay of T1, and 2b1-1 adders. The coefficients of the multipliers are the row vectors of the X1 matrix.

[0030] The input signal of the analysis low-pass HM0 module is signal_in, and the output signal is signal_hm0. It includes M0 multipliers, 2(M0 / 2-1) delay timers T0 with a delay of T0, and 2M0-2 adders. The multiplier coefficients are an HM0 array, and the multipliers perform parallel calculations. The input signal signal_in, after a × b0 delays, enters the first multiplier. The output value of each multiplier, after a delay of T0, is added to the output of the next multiplier and then input to the next delay timer T0. When the signal counter is 1, the analysis low-pass HM0 module performs forward calculation of the coefficients of even-numbered terms and reverse calculation of the coefficients of odd-numbered terms in the HM0 array.

[0031] When the signal counter is at 0, the low-pass HM0 module performs forward calculations of the coefficients of odd-numbered terms in the HM0 array and reverse calculations of the coefficients of even-numbered terms. The output signal signal_hm0 is composed of two parts: the output of the final adder in the forward calculation at each signal counter time, and the output of the final adder in the reverse calculation at each signal counter time, after a MOSFET delay.

[0032] The structure of the high-pass HM1 module is the same as that of the low-pass HM0 module. The multiplier coefficients are HM1 arrays, the input signal is signal_in, and the output signal is signal_hm1. It includes M1 multipliers, 2(M1 / 2-1) delay units with a delay T1 = aT, and 2M1-2 adders. The input signal signal_in enters the first multiplier after a×b1 delays. The output signal signal_hm1 is the sum of two parts: one is the sum of the last-stage adders in the forward sequence calculation at each signal counter time, and the other is the sum of the outputs of the last-stage adders in the reverse sequence calculation at each signal counter time after a delay of M1T.

[0033] For the combined output signal `signal_out` of the analysis filter, the value of `signal_out` at time 1 is `signal_h0`, and the value of `signal_out` at time 0 is `signal_h1`. `signal_h0` is the sum of the values ​​of N `signal_x0` and `signal_hm0` at time 0 and 1 of the signal counter, and `signal_h1` is the sum of the values ​​of N `signal_x1` and `signal_hm1` at time 0 and 1 of the signal counter, delayed by a time interval `T`.

[0034] Step 4: Design the FPGA implementation method of the synthesis filter, including N synthesis common base U modules, 2N synthesis branch X modules and one synthesis coefficient retention HM module. The input signal is the output signal signal_out of the analysis filter, and the output signal is signal.

[0035] The input signal of the integrated common base U module is signal_out, and the output signal is signal_k. g0 ,signal_k g1 ,signal_l g0 and signal_l g1 It includes a multipliers, a delay units with a delay of T0 = 2T, and 2a-2 adders. The multiplier coefficients are column vectors of the U matrix. The structure is the same as the common basis U module of the analysis, and the coefficients of the odd-numbered terms are inverted.

[0036] At the moment when the signal counter is 1, the output signal signal_k of the synthesized common base U module is...g0 The output signal is signal_k, which is the output of the final adder in the positive order calculation of even-numbered coefficients. g1 The output signal_l is the result of the final adder in the positive order calculation of odd-numbered coefficients after a delay of T. g0 The output signal_l is the result of the final adder in the reverse calculation of odd-numbered coefficients after a delay of (l / 2+M1)T. g1 The output of the final adder in the reverse calculation of even-numbered coefficients is the result after being delayed by T and then by (l / 2+M0)T and inverted.

[0037] When the signal counter is 0, the output signal signal_k of the synthesized common base U module is... g0 The output signal_k is the result of the final adder in the positive order calculation of odd-numbered coefficients after a delay of T. g1 The output signal is signal_l, which is the output of the final adder in the positive order calculation of even-numbered coefficients. g0 The output of the final adder in the reverse calculation of even-numbered coefficients is delayed by T and (l / 2+M1)T, and the output signal is signal_l. g1 This is the result of the output of the final adder in the reverse calculation of odd-numbered coefficients being delayed by (l / 2+M0)T and then inverted.

[0038] The synthesis branch X module includes a synthesis low-pass X0 module and a synthesis high-pass X1 module. The synthesis low-pass X0 module is the same as the analysis high-pass X1 module, including b1 multipliers, 2(b1-1) delay units with a delay of T1, and 2b1-1 adders. The input signal is signal_k. g0 ,signal_l g0 The output signal is signal_x g0 The Qualcomm X1 module is identical to the Low-Pass X0 module, consisting of b0 multipliers, 2(b0-1) delay units with a delay of T1, and 2b0-1 adders. The input signal is signal_k. g1 ,signal_l g1 The output signal is signal_x g1 .

[0039] The input signal of the integrated coefficient retention HM module is signal_out, and the output signals are signal_gm0 and signal_gm1. It includes max(M0, M1) multipliers, max(M0, M1)·2-2 delay units with a delay of T0, and max(M0, M1)·2-2 adders, where max represents the maximum value. During multiplier multiplexing, the group with fewer coefficients is aligned with the tail of the group with more coefficients according to its sequence number. The remaining coefficients are then aligned to the left. Unmapped multiplier positions are filled with zero coefficients, ensuring that the output is always zero.

[0040] When the signal counter is at 1, the HM module retains the comprehensive coefficients and performs forward and reverse calculations of the even-numbered coefficients in the HM1 array, as well as forward and reverse calculations of the odd-numbered coefficients. The output signal `signal_gm0` is the result of adding the inverted output of the final adder in the reverse calculation of odd-numbered coefficients, after a delay of T2 = ab1 + 2M1 - max(M0, M1), to the output of the final adder in the forward calculation of even-numbered coefficients. The output signal `signal_gm1` is the result of adding the inverted output of the final adder in the forward calculation of odd-numbered coefficients, after delays T and T3 = ab0 + 2M0 - max(M0, M1), and then inverting the result.

[0041] When the signal counter is at 0, the HM module retains the comprehensive coefficients and performs forward and reverse calculations of the even-numbered coefficients in the HM0 array, as well as the forward and reverse calculations of the odd-numbered coefficients. The output signal `signal_gm0` is the sum of the inverted output of the final adder in the forward calculation of odd-numbered coefficients and the inverted output of the final adder in the reverse calculation of even-numbered coefficients (after a delay of T+T2). The output signal `signal_gm1` is the sum of the inverted output of the final adder in the forward calculation of even-numbered coefficients and the inverted output of the final adder in the reverse calculation of odd-numbered coefficients (after a delay of T3).

[0042] The combined output signal signal of the synthesis filter is signal_ g0 After a delay T and signal_ g1 The sum of. Where signal_ g0 The output signal_x of N integrated low-pass X0 modules g0 The sum of the integrated coefficients and the output signals signal_gm0 of the HM module, signal_h1 is the sum of the output signals signal_x of the N integrated Qualcomm X1 modules. g1 The sum of the comprehensive coefficients and the output signal signal_gm1 of the HM module is retained.

[0043] The present invention has the following beneficial effects:

[0044] By introducing a common-basis matrix decomposition method and combining it with the structural characteristics of a two-channel biorthogonal filter bank, time-division multiplexing technology is used to achieve efficient multiplexing of the polyphase structure and multipliers, effectively reducing the number of multipliers used and thus significantly reducing hardware resource consumption during FPGA implementation. While ensuring the orthogonality and reconstruction accuracy of the filter bank, this invention improves the system's computational efficiency and data throughput, making it suitable for various high-performance real-time signal processing applications. Attached Figure Description

[0045] Figure 1 To analyze the overall structure diagram of the filter;

[0046] Figure 2 This is a diagram showing the overall structure of the synthesis filter;

[0047] Figure 3 The structure diagram of the common U-module of the analysis filter;

[0048] Figure 4 The structure diagram of the branch X module for analysis and synthesis of the filter;

[0049] Figure 5 The structure diagram of the HM module is preserved to analyze the coefficients of the filter;

[0050] Figure 6 This is a structural diagram of the common Y module of the synthesized filter;

[0051] Figure 7 The structure diagram of the HM module is preserved to analyze the coefficients of the filter;

[0052] Figure 8 Reconstruction error under different implementation methods and filter lengths in the examples Detailed Implementation

[0053] The present invention will be further explained below with reference to the accompanying drawings;

[0054] The specific steps for implementing a two-channel biorthogonal filter bank based on matrix factorization on an FPGA are as follows:

[0055] Step 1: Set the length of the low-pass and high-pass filters in the two-channel biorthogonal filter bank to l = 120, the passband cutoff frequency ω0 = 0.47π, and the stopband cutoff frequency ω1 = 0.53π. The corresponding low-pass filter coefficients h0 and high-pass filter coefficients h1 are shown in Table 1 and Table 2, respectively.

[0056] Table 1

[0057]

[0058] Table 2

[0059]

[0060]

[0061] Step 2: Using the initial coefficients h0 and h1, obtain the new sequence H0 for the low-pass filter and the new sequence H1 for the high-pass filter. Decompose the new sequence H0 into a coefficient-preserving sequence HM0 with M0 coefficients and a coefficient matrix E0 of size a×b0. Decompose the new sequence H1 into a coefficient-preserving sequence HM1 with M1 coefficients and a coefficient matrix E1 of size a×b1. HM0 and HM1 are shown in Table 3.

[0062] Table 3

[0063]

[0064] Further, a common-basis 2D truncated LU decomposition is performed on the coefficient matrices E0 and E1 to obtain the common matrix U and the low-pass branch matrix X0 and high-pass branch matrix X1, as shown in Tables 4, 5, and 6:

[0065] Table 4

[0066]

[0067] Table 5

[0068]

[0069] Table 6

[0070]

[0071] Step 3: Design and analyze the FPGA implementation method of the filter, such as... Figure 1 As shown, the analysis includes N common basis U modules, 2N branch X modules, and 2 coefficient retention HM modules. The branch X modules include a low-pass X0 module and a high-pass X1 module. The coefficient retention HM modules include a low-pass H0M module and a high-pass H1M module. The input signal of the analysis filter is signal_in, and the output signal is signal_out.

[0072] The analysis common basis U module, such as Figure 3As shown, the system clock period is T, the input signal is signal_in, and the output signals are signal_k, signal_l0, and signal_l1. It includes *a* multipliers, *a* delay units with a delay of T0 = 2T, and 2a-2 adders. The coefficients of the *a* multipliers correspond to the values ​​of each column of the common basis U. The output value of each multiplier is delayed by T0, added to the output of the next multiplier, and then input to the next delay unit T0. At the moment the signal counter is 0, the common basis U module performs forward calculation of the coefficients of the odd-numbered terms and reverse calculation of the coefficients of the even-numbered terms in the column vectors of matrix U. The output signal signal_k is the output of the final stage adder in the forward sequence calculation at each signal counter time. The output signal signal_l0 is the output of the final stage adder in the reverse sequence calculation at each signal counter time after a delay of (l / 2+M0)T. The output signal signal_l1 is the output of the final stage adder in the reverse sequence calculation at each signal counter time after a delay of (l / 2+M1)T.

[0073] The branch X module includes a low-pass X0 analysis module and a high-pass X1 analysis module, which have the same structure, such as... Figure 4 As shown. The input signals of the analysis low-pass X0 module are signal_k and signal_l0, and the output signal is signal_x0. It includes b0 multipliers, 2(b0-1) delay units with a delay T1 = aT, and 2b0-1 adders. The coefficients of the multipliers are the values ​​of each row of matrix X0. The b0-1 delay units form a forward delay chain with signal_l0 as the input. The other b0-1 delay units form a reverse delay chain with signal_k as the input. signal_l0 is added to the output of the last delay unit in the reverse delay chain and then input to the multiplier. After being delayed by the first delay unit in the forward delay chain, it is added to the output of the second-to-last delay unit in the reverse delay chain and then input to the multiplier. This process continues until the output of the last delay unit in the forward delay chain is added to signal_k and then input to the multiplier. The outputs of all multipliers are added sequentially to obtain the output signal signal_x0 of the analysis low-pass X0 module.

[0074] The input signals of the Qualcomm X1 module are signal_k and signal-l1, and the output signal is signal_x1. It includes b1 multipliers, 2(b1-1) delay units with a delay of T1 = aT, and 2b1-1 adders. The coefficients of the multipliers are the row vectors of the X1 matrix.

[0075] The analysis coefficient retention HM module includes an analysis low-pass H0M module and an analysis high-pass H1M module, both of which have the same structure, such as... Figure 5 As shown.

[0076] The input signal of the analysis low-pass HM0 module is signal_in, and the output signal is signal_hm0. It includes M0 multipliers, 2(M0 / 2-1) delay timers T0 with a delay of T0, and 2M0-2 adders. The multiplier coefficients are an HM0 array, and the multipliers perform parallel calculations. The input signal signal_in, after a × b0 delays, enters the first multiplier. The output value of each multiplier, after a delay of T0, is added to the output of the next multiplier and then input to the next delay timer T0. When the signal counter is 1, the analysis low-pass HM0 module performs forward calculation of the coefficients of even-numbered terms and reverse calculation of the coefficients of odd-numbered terms in the HM0 array.

[0077] When the signal counter is at 0, the low-pass HM0 module performs forward calculations of the coefficients of odd-numbered terms in the HM0 array and reverse calculations of the coefficients of even-numbered terms. The output signal signal_hm0 is composed of two parts: the output of the final adder in the forward calculation at each signal counter time, and the output of the final adder in the reverse calculation at each signal counter time, after a MOSFET delay.

[0078] The structure of the high-pass HM1 module is the same as that of the low-pass HM0 module. The multiplier coefficients are HM1 arrays, the input signal is signal_in, and the output signal is signal_hm1. It includes M1 multipliers, 2(M1 / 2-1) delay units with a delay T1 = aT, and 2M1-2 adders. The input signal signal_in enters the first multiplier after a×b1 delays. The output signal signal_hm1 is the sum of two parts: one is the sum of the last-stage adders in the forward sequence calculation at each signal counter time, and the other is the sum of the outputs of the last-stage adders in the reverse sequence calculation at each signal counter time after a delay of M1T.

[0079] For the combined output signal `signal_out` of the analysis filter, `signal_h0` is the sum of the values ​​of N `signal_x0` and `signal_hm0` at time 0 and time 1 of the signal counter, and `signal_h1` is the sum of the values ​​of N `signal_x1` and `signal_hm1` at time 0 and time 1 of the signal counter, delayed by `T`. At time 1, the value of `signal_out` is `signal_h0`, and at time 0, the value of `signal_out` is `signal_h1`.

[0080] Step 4: Design the FPGA implementation method of the synthesis filter, such as... Figure 2 As shown, it includes N synthesis common base U modules, 2N synthesis branch X modules, and one synthesis coefficient retention HM module. The input signal is the output signal signal_out of the analysis filter, and the output signal is signal.

[0081] The integrated public base U module, such as Figure 6 As shown, the input signal is signal_out, and the output signal is signal_k. g0 ,signal_k g1 ,signal_l g0 and signal_l g1 It includes a multipliers, a delay units with a delay of T0 = 2T, and 2a-2 adders. The multiplier coefficients are column vectors of the U matrix. The structure is the same as the common basis U module of the analysis, and the coefficients of the odd-numbered terms are inverted.

[0082] At the moment when the signal counter is 1, the output signal signal_k of the synthesized common base U module is... g0 The output signal is signal_k, which is the output of the final adder in the positive order calculation of even-numbered coefficients. g1 The output signal_l is the result of the final adder in the positive order calculation of odd-numbered coefficients after a delay of T. g0 The output signal_l is the result of the final adder in the reverse calculation of odd-numbered coefficients after a delay of (l / 2+M1)T. g1 The output of the final adder in the reverse calculation of even-numbered coefficients is the result after being delayed by T and then by (l / 2+M0)T and inverted.

[0083] When the signal counter is 0, the output signal signal_k of the synthesized common base U module is... g0 The output signal_k is the result of the final adder in the positive order calculation of odd-numbered coefficients after a delay of T. g1 The output signal is signal_l, which is the output of the final adder in the positive order calculation of even-numbered coefficients. g0 The output of the final adder in the reverse calculation of even-numbered coefficients is delayed by T and (l / 2+M1)T, and the output signal is signal_l. g1 This is the result of the output of the final adder in the reverse calculation of odd-numbered coefficients being delayed by (l / 2+M0)T and then inverted.

[0084] The synthesis branch X module includes a synthesis low-pass X0 module and a synthesis high-pass X1 module. The synthesis low-pass X0 module is the same as the analysis high-pass X1 module, including b1 multipliers, 2(b1-1) delay units with a delay of T1, and 2b1-1 adders. The input signal is signal_k. g0 ,signal_l g0 The output signal is signal_x g0The Qualcomm X1 module is identical to the Low-Pass X0 module, consisting of b0 multipliers, 2(b0-1) delay units with a delay of T1, and 2b0-1 adders. The input signal is signal_k. g1 ,signal_l g1 The output signal is signal_x g1 .

[0085] like Figure 7 As shown, the input signal of the integrated coefficient retention HM module is signal_out, and the output signals are signal_gm0 and signal_gm1. It includes max(M0,M1) multipliers, max(M0,M1)·2-2 delay units with a delay of T0, and max(M0,M1)·2-2 adders, where max represents taking the maximum value. During multiplier multiplexing, the group with fewer coefficients is aligned with the tail of the group with more coefficients according to its sequence number. The remaining coefficients are then aligned to the left. For multiplier positions that cannot be mapped, zero coefficients are used to fill in the gaps, ensuring that the output is always zero.

[0086] When the signal counter is at 1, the HM module retains the comprehensive coefficients and performs forward and reverse calculations of the even-numbered coefficients in the HM1 array, as well as forward and reverse calculations of the odd-numbered coefficients. The output signal `signal_gm0` is the result of adding the inverted output of the final adder in the reverse calculation of odd-numbered coefficients, after a delay of T2 = ab1 + 2M1 - max(M0, M1), to the output of the final adder in the forward calculation of even-numbered coefficients. The output signal `signal_gm1` is the result of adding the inverted output of the final adder in the forward calculation of odd-numbered coefficients, after delays T and T3 = ab0 + 2M0 - max(M0, M1), and then inverting the result.

[0087] When the signal counter is at 0, the HM module retains the comprehensive coefficients and performs forward and reverse calculations of the even-numbered coefficients in the HM0 array, as well as the forward and reverse calculations of the odd-numbered coefficients. The output signal `signal_gm0` is the sum of the inverted output of the final adder in the forward calculation of odd-numbered coefficients and the inverted output of the final adder in the reverse calculation of even-numbered coefficients (after a delay of T+T2). The output signal `signal_gm1` is the sum of the inverted output of the final adder in the forward calculation of even-numbered coefficients and the inverted output of the final adder in the reverse calculation of odd-numbered coefficients (after a delay of T3).

[0088] The combined output signal signal of the synthesis filter is signal_ g0 After a delay T and signal_ g1 The sum of. Where signal_g0 The output signal_x of N integrated low-pass X0 modules g0 The sum of the integrated coefficients and the output signals signal_gm0 of the HM module, signal_h1 is the sum of the output signals signal_x of the N integrated Qualcomm X1 modules. g1 The sum of the comprehensive coefficients and the output signal signal_gm1 of the HM module is retained.

[0089] To illustrate the advantages of this method, a comparison is made with the two-channel biorthogonal filter bank defined in step 1 directly implemented on the FPGA and the two-channel biorthogonal filter bank with length l = 110 directly implemented on the FPGA. The number of multipliers used and the resources consumed by the three methods are shown in Tables 7 and 8:

[0090] Table 7

[0091]

[0092] Table 8

[0093]

[0094] It can be seen that this method uses fewer multipliers and consumes fewer logic resources. Regarding storage resources, since storage resources are relatively abundant, no restrictions are placed on their use in the analysis and discussion of this paper. For the same length, this method saves approximately 17% of logic resources (28510-23513) / 28510, and its operating frequency is approximately 2.8 times that of the direct implementation (76.4 / 26.59).

[0095] Figure 7 The reconstruction errors of filter banks implemented using three different methods under impulse response are shown. It can be seen that the filter implemented using the proposed method can maintain a certain level of reconstruction error performance. In summary, this method, by introducing common-basis matrix decomposition and combining the structural characteristics of a two-channel bisorthogonal filter bank, employs time-division multiplexing technology to achieve efficient multiplexing of the polyphase structure and multipliers, effectively reducing the number of multipliers and significantly lowering the hardware logic resource overhead in FPGA implementation. While ensuring the orthogonality and reconstruction accuracy of the filter bank, it improves the system's computational efficiency and data throughput, providing a feasible and efficient solution for the FPGA implementation of high-performance, real-time signal processing systems.

Claims

1. An FPGA implementation method for a two-channel biorthogonal filter bank based on matrix decomposition, characterized in that: Specifically, the following steps are included: Step 1: Determine the initial coefficients h0 = [h0(0), h0(1), ..., h0(l-1)] and h1 = [h1(0), h1(1), ..., h1(l-1)] of the low-pass filter and the high-pass filter in the two-channel biorthogonal filter bank, where l represents the filter length; Step 2: Transform the initial coefficients h0 and h1 into a new sequence. The new sequence H0 is decomposed into a coefficient-preserving sequence HM0 with M0 coefficients and a coefficient matrix E0 of size a×b0. The new sequence H1 is decomposed into a coefficient-preserving sequence HM1 with M1 coefficients and a coefficient matrix E1 of size α×b1. The coefficient matrices E0 and E1 are decomposed into N-dimensional common-base truncated LU decomposition to obtain the common matrix U and the low-pass branch matrix X0 and the high-pass branch matrix X1. Step 3: Design the FPGA implementation method for the analysis filter, including N common base U modules, N low-pass X0 modules, N high-pass X1 modules, 1 low-pass HM0 module, and 1 high-pass EM1 module. The combined output signal of the analysis filter is signal_out; when the signal counter is at time 1, the value of signal_out is signal_h0, and when the signal counter is at time 0, the value of signal_out is signal_h1; where signal_h0 is the sum of the output signals signal_x0 of N analysis low-pass X0 modules and the output signal signal_hm0 of analysis low-pass HM0 module at times 0 and 1; signal_h1 is the sum of the output signals signal_x1 of N analysis high-pass X1 modules and the output signal signal_hm1 of analysis high-pass HM1 module at times 0 and 1, delayed by T. Step 4: Design the FPGA implementation method of the synthesis filter, including N synthesis common base U modules, N synthesis low-pass X0 modules, N synthesis high-pass X1 modules and 1 synthesis coefficient retention HM module. The input signal is the output signal signal_out of the analysis filter, and the output signal is signal. The combined output signal `signal` of the synthesized filter is the sum of `signal_g0` after a delay of `T` and `signal_g1`; where `signal_g0` is the output signal `signal_x` of N synthesized low-pass X0 modules. g0 The sum of the integrated coefficients and the output signals signal_gm0 of the HM module, signal_h1 is the sum of the output signals signal_x of the N integrated Qualcomm X1 modules. g1 The sum of the comprehensive coefficients and the output signal signal_gm1 of the HM module is retained.

2. The FPGA implementation method for a two-channel biorthogonal filter bank based on matrix factorization as described in claim 1, characterized in that: The coefficient retention sequence HM0 and the coefficient matrix E0 are: HM0=[H0(0),H0(1),…,h0(M0-1)] The coefficient retention sequence HM1 and the coefficient matrix E1 are: HM1=[H1(0),H1(1),…,h1(M1-1)] The common matrix U, the low-pass branch matrix X0, and the high-pass branch matrix X1 are:

3. The FPGA implementation method for a two-channel biorthogonal filter bank based on matrix decomposition as described in claim 1, characterized in that: The common basis U module for analysis is a module shared by the low-pass and high-pass filters in the analysis filter. The system clock period is T, the input signal is signal_in, and the output signals are signal_k, signal_l0, and signal_l1. It includes a multipliers, a delay timers with a delay of T0 = 2T, and 2a-2 adders. The multiplier coefficients are column vectors in the U matrix. The multipliers perform parallel operations. The output value of each multiplier is delayed by a delay timer T0, added to the output of the next multiplier, and then input to the next delay timer T0. The filter coefficients in the multiplier are defined as being calculated in ascending order when arranged by their serial numbers, and in descending order when arranged in reverse order. When the signal counter is 1, the common basis U module performs ascending order calculation of the coefficients of the even-numbered terms and in reverse order calculation of the coefficients of the odd-numbered terms in the column vectors of the U matrix. When the signal counter is 0, the common basis U module performs ascending order calculation of the coefficients of the odd-numbered terms and in reverse order calculation of the coefficients of the column vectors of the U matrix. The output signal signal_k is the output of the final adder in the ascending order calculation at each signal counter time. The output signal signal_l0 is the output of the final adder in the inverse order calculation at each signal counter time after a delay of (l / 2+M0)T. The output signal signal_l1 is the output of the final adder in the inverse order calculation at each signal counter time after a delay of (l / 2+M1)T.

4. The FPGA implementation method for a two-channel biorthogonal filter bank based on matrix factorization as described in claim 3, characterized in that: The input signal of the integrated common base U module is signal_out, and the output signal is signal_k. g0 ,signal_k g1 ,signal_l g0 and signal_l g1 It includes a multipliers, a delay units with a delay of T0 = 2T, and 2a-2 adders. The multiplier coefficients are column vectors of the U matrix. The structure is the same as the common basis U module for analysis, and the coefficients of the odd-numbered terms are inverted. At the moment when the signal counter is 1, the output signal signal_k of the synthesized common base U module is... g0 The output signal is signal_k, which is the output of the final adder in the positive order calculation of even-numbered coefficients. g1 The output signal_l is the result of the final adder in the positive order calculation of odd-numbered coefficients after a delay of T. g0 The output signal_l is the result of the final adder in the reverse calculation of odd-numbered coefficients after a delay of (l / 2+M1)T. g1 The output of the final adder in the reverse calculation of even-numbered coefficients is the result of delaying T and delaying (l / 2+M0)T and then inverting it; When the signal counter is 0, the output signal signal_k of the synthesized common base U module is... g0 The output signal_k is the result of the final adder in the positive order calculation of odd-numbered coefficients after a delay of T. g1 The output signal is signal_l, which is the output of the final adder in the positive order calculation of even-numbered coefficients. g0 The output of the final adder in the reverse calculation of even-numbered coefficients is delayed by T and (l / 2+M1)T, and the output signal is signal_l. g1 This is the result of the output of the final adder in the reverse calculation of odd-numbered coefficients being delayed by (l / 2+M0)T and then inverted.

5. The FPGA implementation method for a two-channel biorthogonal filter bank based on matrix factorization as described in claim 1, characterized in that: The input signals of the analysis low-pass X0 module are signal_k and signal_l0, and the output signal is signal_x0. It includes b0 multipliers, 2(b0-1) delay units with a delay of T1 = aT, and 2b0-1 adders. The coefficients of the multipliers are the row vectors of the X0 matrix. The b0-1 delay units form a forward delay chain with signal_l0 as the input. The other b0-1 delay units form a reverse delay chain with signal_k as the input. signal_l0 is added to the output of the last delay unit in the reverse delay chain and then input to the multiplier. After being delayed by the first delay unit in the forward delay chain, it is added to the output of the second-to-last delay unit in the reverse delay chain and then input to the multiplier. This process continues until the output of the last delay unit in the forward delay chain is added to signal_k and then input to the multiplier. The outputs of all multipliers are added sequentially to obtain the output signal signal_x0 of the analysis low-pass X0 module. The structure of the analysis high-pass X1 module is the same as that of the analysis low-pass X0 module. The input signals are signal_k and signal_l1, and the output signal is signal_x1, including b1. 个 The system consists of a multiplier, two (b1-1) delay units with a delay of T1, and two b1-1 adders. The coefficients of the multiplier are the row vectors of the X1 matrix.

6. The FPGA implementation method for a two-channel biorthogonal filter bank based on matrix factorization as described in claim 5, characterized in that: The synthesis branch X module includes a synthesis low-pass X0 module and a synthesis high-pass X1 module. The synthesis low-pass X0 module is the same as the analysis high-pass X1 module, including b1 multipliers, 2(b1-1) delay units with a delay of T1, and 2b1-1 adders. The input signal is signal_k. g0 ,signal_l g0 The output signal is signal_x g0 The Qualcomm X1 module is identical to the low-pass X0 module, consisting of b0 multipliers, 2(b0-1) delay units with a delay of T1, and 2b0-1 adders. The input signal is signal_k. g1 ,signal_l g1 The output signal is signal_x g1 .

7. The FPGA implementation method for a two-channel biorthogonal filter bank based on matrix factorization as described in claim 1, characterized in that: The input signal of the analysis low-pass HM0 module is signal_in, and the output signal is signal_hm0. It includes M0 multipliers, 2(M0 / 2-1) delay timers T0 with a delay of T0, and 2M0-2 adders. The multiplier coefficients are the HM0 array. The input signal signal_in is delayed by a×b0 times and then enters the first multiplier. The output value of each multiplier is delayed by a delay of T0 and then added to the output of the next multiplier before being input to the next delay timer T0. When the signal counter is 1, the analysis low-pass HM0 module performs forward calculation of the coefficients of even-numbered terms and reverse calculation of the coefficients of odd-numbered terms in the HM0 array. When the signal counter is 0, the low-pass HM0 module is analyzed to perform forward calculation of the coefficients of odd-numbered terms in the HM0 array and reverse calculation of the coefficients of even-numbered terms. The output signal signal_hm0 is composed of two parts: one is the output of the last stage adder in the forward calculation at each signal counter time, and the other is the output of the last stage adder in the reverse calculation at each signal counter time after MT delay. The structure of the high-pass HM1 module is the same as that of the low-pass HM0 module. The multiplier coefficients are HM1 arrays, the input signal is signal_in, and the output signal is signal_hm1. It includes M1 multipliers, 2(M1 / 2-1) delay units with a delay T1 = aT, and 2M1-2 adders. The input signal signal_in enters the first multiplier after a×b1 delays. The output signal signal_hm1 is the sum of two parts: one is the sum of the last-stage adders in the forward sequence calculation at each signal counter time, and the other is the sum of the outputs of the last-stage adders in the reverse sequence calculation at each signal counter time after a delay of M1T.

8. The FPGA implementation method for a two-channel biorthogonal filter bank based on matrix factorization as described in claim 1, characterized in that: The input signal of the integrated coefficient retention HM module is signal_out, and the output signals are signal_gm0 and signal_gm1. It includes max(M0, M1) multipliers, max(M0, M1)·2-2 delays with a delay of T0, and max(M0, M1)·2-2 adders, where max represents taking the maximum value. During the multiplier multiplexing process, the group with fewer coefficients is aligned with the tail of the group with more coefficients according to the sequence number, and the remaining coefficients are aligned to the left in sequence. For multiplier positions that cannot be mapped, zero coefficients are used to fill them so that their output is always zero. When the signal counter is 1, the HM module retains the comprehensive coefficients and performs forward and reverse calculations of the even-numbered coefficients in the HM1 array, as well as forward and reverse calculations of the odd-numbered coefficients. The output signal_gm0 is the result of adding the output of the final adder in the reverse calculation of the odd-numbered coefficients after a delay of T2 = ab1 + 2M1 - max(M0, M1) and the output of the final adder in the forward calculation of the even-numbered coefficients. The output signal_gm1 is the result of adding the output of the final adder in the forward calculation of the odd-numbered coefficients after a delay of T and a delay of T3 = ab0 + 2M0 - max(M0, M1) and then inverting it. When the signal counter is 0, the HM module retains the comprehensive coefficients and performs forward and reverse calculations of the coefficients of even-numbered terms in the HM0 array, as well as forward and reverse calculations of the coefficients of odd-numbered terms. The output signal signal_gm0 is the sum of the inverted output of the final adder in the forward calculation of odd-numbered terms and the inverted output of the final adder in the reverse calculation of even-numbered terms after a delay of T+T2. The output signal signal_gm1 is the sum of the inverted output of the final adder in the forward calculation of even-numbered terms and the inverted output of the final adder in the reverse calculation of odd-numbered terms after a delay of T3.

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