Wafer structure and chip structure
By placing the alignment pattern within the dicing channel and outside the sealing ring pattern in the wafer structure, the problem of exposed metal layers is solved, enabling denser chip cell arrangement and higher chip throughput.
Patent Information
- Application Number
- CN202410819897.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-24
- Publication Date
- 2025-12-26
AI Technical Summary
Traditional pattern alignment technology can easily lead to the exposure of the metal layer of the alignment mark during wafer cutting, affecting the appearance, and the width of the wafer cutting track cannot be reduced, which limits chip production capacity.
In the wafer structure, the alignment pattern is set inside the dicing channel and outside the closed area enclosed by the sealing ring pattern to avoid cutting the alignment pattern during the dicing process. By setting the positional relationship between the sealing ring pattern and the alignment pattern, it is ensured that the appearance of the chip is not affected during dicing and the width of the dicing channel is reduced.
This effectively avoids the problem of exposed metal layers, increases the density of chip units, and improves the chip production capacity of each wafer.
Smart Images
Figure CN121215656A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present invention relates to a wafer structure and a chip structure. BACKGROUND
[0002] Generally, an integrated circuit includes multiple layers with different patterns, each of which is formed by a photolithography process. And, features on a successively patterned layer are spatially related to other features. Therefore, during fabrication, each patterned layer must be aligned with the previous patterned layer. To achieve this, a plurality of alignment marks (also referred to as alignment targets) are usually provided on the substrate or a dielectric layer formed thereon to determine the position of the previously exposed pattern using the position of the alignment marks.
[0003] Conventional pattern alignment techniques generally form alignment (or identification) marks on the scribe lane of each die, however, to improve throughput, the scribe lane on the wafer is gradually reduced to increase the number of dies per wafer, but this approach can easily cause the alignment marks on the scribe lane to be cut during wafer cutting, thus causing the metal layer of the alignment marks to be exposed, affecting the appearance. SUMMARY
[0004] The present invention provides a wafer structure whose alignment pattern setting position does not affect the appearance of the product after the cutting process, and can effectively reduce the scribe lane width of the wafer, thereby increasing the chip throughput of each wafer.
[0005] A wafer structure of the present invention includes a substrate, a scribe lane, a chip circuit pattern, and a peripheral metal pattern. The scribe lane defines a chip unit on the substrate. The chip circuit pattern is disposed in a central region of the chip unit. The peripheral metal pattern is disposed in a peripheral region of the chip unit, which surrounds the central region. The peripheral metal pattern includes a seal ring pattern surrounding the central region and an alignment pattern disposed between the scribe lane and the seal ring pattern.
[0006] In an embodiment of the present invention, the seal ring pattern includes a chamfer to leave a corner region in the chip unit, and the alignment pattern is disposed in the corner region left by the chamfer.
[0007] In an embodiment of the present invention, the alignment pattern is spaced apart from the seal ring pattern by a first distance.
[0008] In an embodiment of the present invention, an outer edge of the alignment pattern is spaced apart from an inner edge of the scribe lane by a second distance.
[0009] In an embodiment of the present invention, the peripheral metal pattern further includes a plurality of dummy metal pads, which are uniformly distributed between the seal ring pattern and the alignment pattern.
[0010] In an embodiment of the present application, the alignment pattern is co-linear with the outer edge of the corresponding sealing ring pattern.
[0011] In an embodiment of the present application, the alignment pattern does not overlap with the scribe lane as viewed from a top view direction.
[0012] In an embodiment of the present application, the alignment pattern is disposed on the same plane as the sealing ring pattern.
[0013] In an embodiment of the present application, the chip circuit pattern is electrically insulated from the perimeter metal pattern.
[0014] In an embodiment of the present application, the alignment pattern is in the shape of L, H, cross, Z or hourglass.
[0015] In an embodiment of the present application, the sealing ring pattern comprises a plurality of sealing ring pattern layers stacked on the substrate.
[0016] In an embodiment of the present application, the alignment pattern comprises a plurality of alignment pattern layers stacked on the substrate and disposed on the same layer as the corresponding plurality of sealing ring pattern layers, respectively.
[0017] In an embodiment of the present application, the sealing ring pattern comprises an inner sealing ring pattern surrounding the central region and an outer sealing ring pattern surrounding the inner sealing ring pattern.
[0018] In an embodiment of the present application, the alignment pattern is disposed between the scribe lane and the outer sealing ring pattern.
[0019] A chip structure of the present application comprises a substrate, a chip circuit pattern and a perimeter metal pattern. The substrate comprises a central region and a perimeter region surrounding the central region. The chip circuit pattern is disposed in the central region. The perimeter metal pattern is disposed in the perimeter region and comprises a sealing ring pattern surrounding the chip circuit pattern and an alignment pattern disposed outside an enclosed region enclosed by the sealing ring pattern.
[0020] In an embodiment of the present application, the alignment pattern is disposed between the outer edge of the chip structure and the sealing ring pattern.
[0021] In an embodiment of the present application, the sealing ring pattern has a chamfer at a corner of the substrate corresponding to the chamfer, and the alignment pattern is disposed at the corner vacated by the chamfer.
[0022] A wafer structure of one embodiment of the present application includes a substrate, a scribe line, a chip, a sealing ring, and an alignment mark. The scribe line defines a chip unit on the substrate. The chip is disposed in the chip unit. The sealing ring surrounds the chip and is located between the scribe line and the chip. The alignment mark is disposed between the scribe line and the sealing ring.
[0023] Based on the above, the wafer structure of the present application arranges the alignment pattern within the range framed by the scribe line and in the area outside the closed area framed by the sealing ring pattern, so that the alignment pattern on the scribe line is not cut during the chip cutting process, and the metal layer is not exposed, which affects the appearance of the chip. Moreover, since there is no need to worry about cutting the alignment pattern during the chip cutting process, the width of the scribe line can be further reduced, the chip units on the wafer can be arranged more densely, and the number of cuttable dies on the wafer is increased, thereby increasing the chip production capacity of each wafer. BRIEF DESCRIPTION OF DRAWINGS
[0024] The accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.
[0025] Figure 1 is a top view schematic diagram of a wafer structure of one embodiment of the present application;
[0026] Figure 2 is a partial enlarged schematic diagram of a wafer structure of one embodiment of the present application;
[0027] Figure 3A is a top view schematic diagram of a chip structure of one embodiment of the present application;
[0028] Figure 3B is a top view schematic diagram of a chip structure of one embodiment of the present application;
[0029] Figure 4 is a partial enlarged schematic diagram of a chip unit of a wafer structure of one embodiment of the present application;
[0030] Figure 5 is a top view schematic diagram of an alignment pattern of a wafer structure of one embodiment of the present application;
[0031] Figure 6 is a top view schematic diagram of an alignment pattern of wafer structures of different embodiments of the present application;
[0032] Figure 7A is a partial cross-sectional schematic diagram of a wafer structure of one embodiment of the present application;
[0033] Figure 7BFigure 1 is a partial cross-sectional schematic view of a wafer structure according to an embodiment of the present application.
[0034] BRIEF DESCRIPTION OF DRAWINGS
[0035] 100: wafer structure
[0036] 110: substrate
[0037] 112: element
[0038] 120: chip unit, chip structure
[0039] 121: chip
[0040] 122: chip wiring pattern
[0041] 124: peripheral metal pattern
[0042] 1241: sealing ring pattern, sealing ring
[0043] 1241a: outer sealing ring pattern, sealing ring pattern
[0044] 1241b: inner sealing ring pattern, sealing ring pattern
[0045] 1242, 1242a, 1242b, 1242c, 1242d: alignment pattern, alignment mark
[0046] 1243: dummy metal pad
[0047] 1244: pad layer
[0048] 125a, 125b, 127: wiring layer
[0049] 126a, 126b, 128: inter-wire via
[0050] 130: scribe lane
[0051] 140: passivation layer
[0052] A1: chamfer
[0053] C1: central region
[0054] d1: first distance
[0055] d2: second distance
[0056] P1: peripheral region
[0057] R1: corner region DETAILED DESCRIPTION
[0058] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.
[0059] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of the embodiments with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention. Furthermore, in the following embodiments, the same or similar elements will be referred to by the same or similar reference numerals.
[0060] Figure 1 This is a top view schematic diagram of a wafer structure according to an embodiment of the present invention. Figure 2 This is a partially enlarged schematic diagram of a wafer structure according to an embodiment of the present invention. Figure 3A This is a top view schematic diagram of a chip structure according to an embodiment of the present invention. Please refer to... Figures 1 to 3A In some embodiments, the wafer structure 100 includes a substrate 110. The substrate 110 may be formed of silicon, germanium (Ge), or other suitable semiconductor materials. In some embodiments, the substrate 110 may be made of a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, the substrate 110 is made of a compound semiconductor such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), or indium gallium phosphide. In some other embodiments, the substrate 110 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In some examples, the substrate 110 may include a doped epitaxial layer. In some examples, the silicon substrate may include a multilayer composite semiconductor structure. Alternatively, the wafer structure 100 may include a non-semiconductor material, such as a glass substrate, quartz, or suitable materials such as calcium fluoride. In some embodiments, the thickness of the substrate 110 may be greater than about 500 micrometers (μm).
[0061] In some embodiments, the wafer structure 100 may include a substrate 110, dicing channels 130, chip wiring patterns 122, and peripheral metal patterns 124. The substrate 110 has a front surface and a back surface opposite to the front surface, and the dicing channels 130 define a plurality of chip cells 120 on the substrate 110. Specifically, as Figure 1 and Figure 2The plurality of chip cells 120 shown are defined on the front surface of the substrate 110 via dicing channels 130. Generally, the wafer structure 100 serves as a manufacturing carrier during chip production. After the semiconductor process is completed, a plurality of chip cells 120 are formed on the wafer structure 100. Subsequently, these chip cells 120 are separated by a chip dicing or monomerization process to form a plurality of separate chip structures 120 (the diced chip structures 120 can be as follows...). Figure 3A (As shown). The individualization process may include methods such as mechanical cutting or laser cutting to cut the area between the individual chip cells 120 along the dicing 130. That is, the dicing 130 is the area between adjacent chip cells 120. In some embodiments, there are no functional devices within the dicing 130. In some embodiments, the dicing 130 does not contain metal; for example, the dicing 130 does not include any metal layer or metal structure. In some embodiments, the dicing 130 may include a plurality of test pads (not shown) for testing purposes.
[0062] Figure 3A This is a top view schematic diagram of a chip cell with a wafer structure according to an embodiment of the present invention. Figure 4 This is a partially enlarged schematic diagram of a chip cell with a wafer structure according to an embodiment of the present invention. Please also refer to... Figure 3A and Figure 4 In some embodiments, the chip cell 120 may include a central region C1 and a peripheral region P1 surrounding the central region C1. A chip circuit pattern 122 is disposed in the central region C1, while a peripheral metal pattern 124 is disposed in the peripheral region P1 to surround the chip circuit pattern 122, and the chip circuit pattern 122 and the peripheral metal pattern 124 are electrically insulated from each other. It should be noted that the above-mentioned orientation terms, such as the central region C1 and the peripheral region P1, are relative terms, and the central region C1 is not necessarily located at the center of the chip cell 120. The elements of the present invention can be positioned in many different orientations. Therefore, the orientation terms are for illustrative purposes and are not intended to be limiting.
[0063] In some embodiments, the center region CI can also be referred to as the active area of the chip, which can be composed of a plurality of elements, such as active and passive elements located on the substrate 110. The center region CI includes a large portion of the high-density active circuitry of the chip cell 120, i.e., the chip layout pattern 122. In particular, the chip layout pattern 122 can include multiple layers, such as active layers to define the active area of the integrated circuit, polysilicon layers to define the gate area of the integrated circuit, contact layers to define contacts to the active and polysilicon areas, implant layers, metal layers, and / or other suitable layers. The multiple layers of the chip layout pattern 122 can form various elements, including, for example, passive elements such as resistors, capacitors, inductors, etc., active elements such as metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor transistors (CMOSs), high voltage transistors, and / or high frequency transistors, other suitable elements, and / or combinations thereof. Initially, these elements formed on the substrate 110 can be isolated from one another, and then interconnected together through metal interconnect structures of the multiple layers to form functional circuitry. Typical interconnect structures include lateral interconnects (e.g., metal lines or wires) and vertical interconnects (e.g., vias and contacts).
[0064] Figure 3B is a top view schematic of a chip structure in accordance with an embodiment of the present application. Please refer to Figure 2 and Figure 3BIn this embodiment, from a structural perspective, the dicing channel 130 defines a plurality of chip cells 120 on the wafer structure. Each chip cell 120 includes a chip 121, a sealing ring (i.e., a sealing ring pattern) 1241, and an alignment mark (i.e., an alignment pattern) 1242. Specifically, the plurality of chip cells 120 are defined on the front surface of the substrate 110 via the dicing channel 130. Generally, the wafer structure 100 serves as a manufacturing carrier during chip production. After the semiconductor process is completed, a plurality of chip cells 120 are formed on the wafer structure 100. That is, the dicing channel 130 is the region between adjacent chip cells 120. Chips 121 are formed within the chip cells 120 defined by the dicing channel 130, and each chip 121 includes the aforementioned chip circuit pattern 122. In some embodiments, the chip 121 may include a plurality of elements, such as active and passive elements located on the substrate 110. Specifically, chip 121 may include a multilayer chip circuit pattern 122, such as an active layer defining the active region of the integrated circuit, a polysilicon layer defining the gate region of the integrated circuit, a contact layer, an implantation layer, a metal layer, and / or other suitable layers defining the contact between the active region and the polysilicon region. The multilayer chip circuit pattern 122 can form various components, including passive components such as resistors, capacitors, and inductors; active components such as MOSFETs, CMOS transistors, high-voltage transistors, and / or high-frequency transistors; other suitable components; and / or combinations of the above components. Initially, these components formed on substrate 110 can be isolated from each other, and then interconnected through a multilayer metal interconnect structure to form a functional circuit. Typical interconnect structures include lateral interconnects (e.g., metal lines or wires) and vertical interconnects (e.g., vias and contacts). A sealing ring 1241 surrounds the chip 121 and is located between the dicing channel 130 and the chip 121, while an alignment pattern 1242 is disposed between the dicing channel 130 and the sealing ring 1241.
[0065] In some embodiments, such as Figure 4 As shown, the peripheral metal pattern 124 of the chip unit 120 includes a sealing ring pattern 1241 surrounding the central region C1 and an alignment pattern 1242 disposed between the dicing channel 130 and the sealing ring pattern 1241. Specifically, the alignment pattern 1242 is disposed within the area enclosed by the dicing channel 130 and outside the closed area enclosed by the sealing ring pattern 1241. Therefore, from the... Figure 4 Viewed from the top view shown, the alignment pattern 1242 does not overlap with the dicing track 130. It should be noted that since the dicing track 130 is removed during the chip dicing process, the diced chip structure 120 (e.g., ...) is considered. Figure 3AAs shown, the alignment pattern 1242 is located outside the closed area enclosed by the sealing ring pattern 1241. In other words, the alignment pattern 1242 is located between the outer edge of the chip structure 120 and the sealing ring pattern 1241.
[0066] In this embodiment, the top layer of the chip circuit pattern 122 may include multiple pads, which may include multiple active metal pads and multiple dummy metal pads. The dummy metal pads have no electrical function. The active metal pads are electrically connected to active components on the substrate via pad vias and interconnect structures. The dummy metal pads are electrically insulated from the components in the chip structure 120. That is, the dummy metal pads may be electrically floating. In some embodiments, the active metal pads and dummy metal pads have the same top view shape, size, and / or contain the same material. Furthermore, the active metal pads and dummy metal pads are formed simultaneously. In alternative embodiments, the active metal pads and dummy metal pads have different top view shapes and / or different top view sizes.
[0067] like Figure 3A As shown, the sealing ring pattern 1241 surrounds the edge of the chip circuit pattern 122. The sealing ring pattern 1241 forms a barrier against moisture, corrosive gases, and chemicals entering the chip circuit pattern 122, and protects it from damage such as cracking and stress caused by cutting tools. The sealing ring pattern 1241 can typically be formed of a conductive material similar to pads (active metal pads and dummy metal pads), such as aluminum (Al), aluminum-copper (Al-Cu) alloy, or aluminum-copper-silicon (Al-Cu-Si) alloy. In some embodiments, the width of the sealing ring pattern 1241 in a top view is approximately 10 μm, but the invention is not limited thereto.
[0068] In some embodiments, the sealing ring pattern 1241 includes a chamfer A1 to create a corner area R1 in the chip unit 120, and the alignment pattern 1242 is disposed within the corner area R1 created by the chamfer A1. For example, viewed from a top view, the chip unit 120 may be a rectangle with four corners, and the sealing ring pattern 1241 may have chamfers A1 corresponding to these four corners, making it appear as... Figure 3A The octagon shown is designed to leave four corners of the chip unit 120 empty, and the alignment pattern 1242 can be correspondingly set at the four corners left empty by the chamfer A1. Of course, the present invention does not limit the shape of the chip unit and the sealing ring pattern, as long as the number and position of the chamfers of the sealing ring pattern correspond to the number and position of the corners of the chip unit.
[0069] In such a configuration, the alignment pattern 1242 is disposed within the range enclosed by the scribe lane 130 and outside the enclosed area enclosed by the seal ring pattern 1241, so that the alignment pattern on the scribe lane will not be damaged during the wafer dicing process, and the metal layer will not be exposed, which will affect the appearance of the chip. Furthermore, since the alignment pattern will not be damaged during the wafer dicing process, the width of the scribe lane can be reduced, so that the chip units on the wafer can be arranged more densely, and the number of dies per wafer can be increased, and the chip production capacity of each wafer can be increased. In an embodiment, the scribe lane 130 can be reduced to between 60 microns and 80 microns, but the present application is not limited thereto.
[0070] In an embodiment, the alignment pattern 1242 is electrically insulated from the seal ring pattern 1241 and spaced apart from each other by a first distance d1. For example, the first distance d1 is greater than about 1 micron. In an embodiment, the outer edge of the alignment pattern 1242 is spaced apart from the inner edge of the scribe lane 130 by a second distance d2, so as to further avoid damage to the alignment pattern 1242 during the wafer dicing process. In this embodiment, the second distance d2 is greater than about 1 micron. In this embodiment, the seal ring pattern 1241 includes an inner seal ring pattern 1241b surrounding the central region C1 and an outer seal ring pattern 1241a surrounding the inner seal ring pattern 1241b, and the outer seal ring pattern 1241a and the inner seal ring pattern 1241b are electrically insulated from each other. In this embodiment, the alignment pattern 1242 is disposed between the scribe lane 130 and the outer seal ring pattern 1241a.
[0071] In some embodiments, the peripheral metal pattern 124 can further include a plurality of dummy metal pads 1243 uniformly distributed between the seal ring pattern 1241 and the alignment pattern 1242. The dummy metal pads 1243 can be electrically insulated from the seal ring pattern 1241, the alignment pattern 1242, and the chip circuit pattern 122. That is, the dummy metal pads 1243 can be electrically floating. The dummy metal pads 1243 can be uniformly distributed in the wiring blank of the chip unit 120 to provide a more uniform pattern density, so that the chip unit 120 can have a smoother surface after undergoing a planarization process (such as a CMP process).
[0072] Figure 5 is a top view of an alignment pattern of a wafer structure according to an embodiment of the present application. Please refer to Figure 4 and Figure 5In the present embodiment, the outer edges of the alignment pattern 1242 are substantially co-linear with the outer edges of the corresponding seal ring pattern 1241. Specifically, in the present embodiment, the alignment pattern 1242 is L-shaped as viewed from the top view direction, having two substantially perpendicular outer edges (outer sides) that can be co-linear with the outer edges of the corresponding seal ring pattern 1241 and together flat on both sides of the corners of the chip unit 120. Here, the term "substantially perpendicular" means that the included angle between the two substantially perpendicular outer edges of the L-shaped alignment pattern 1242 is between 85 and 95 degrees. In the present embodiment, the lengths L1, L2 of the two substantially perpendicular outer sides of the alignment pattern 1242 can be greater than or equal to 10 microns, and the widths of the two outer sides can be greater than or equal to 2 microns. Of course, the present embodiment is merely used for illustration, and the present application is not limited thereto.
[0073] Figure 6 is a top view schematic diagram of an alignment pattern of a wafer structure according to different embodiments of the present application. Please refer to Figure 6 In addition to the L-shape as shown in Figure 4 , the shape of the alignment pattern 1242 as viewed from the top view direction can also be other suitable shapes. For example, the alignment pattern 1242a can be a mouth-shaped pattern, the alignment pattern 1242b can be a cross-shaped pattern, the alignment pattern 1242c can be a Z-shaped pattern, or the alignment pattern 1242d can be an hourglass-shaped pattern, etc. Each chip structure can have multiple alignment patterns, and the shapes thereof can adopt one of the above alignment patterns 1242, 1242a, 1242b, 1242c, 1242d or a combination of the above shapes. Of course, the present application only lists a few possible shapes of the alignment pattern, and the present application is not limited thereto. In an embodiment, the overall length and width of the alignment pattern can be greater than or equal to 10 microns, and the width of the pattern can be greater than or equal to 2 microns, so as to facilitate recognition by the image sensor.
[0074] Figure 7A is a partial cross-sectional schematic diagram of a wafer structure according to an embodiment of the present application. Please refer to Figure 7AIn this embodiment, the alignment mark pattern 1242 is disposed on the same plane as the seal ring pattern 1241 and can be formed using the same photoresist pattern and via the same photolithography process. Specifically, the seal ring pattern 1241 includes a plurality of seal ring pattern layers disposed on the substrate 110 in a stack, and the alignment mark pattern 1242 includes a plurality of alignment mark pattern layers disposed on the substrate 220 in a stack, and each of the alignment mark pattern layers can be disposed on the same layer as a corresponding seal ring pattern layer, and each of the alignment mark pattern layers and the seal ring pattern layers can be formed using the same photoresist pattern and via the same photolithography process. In this embodiment, the seal ring pattern 1241 can include an outer seal ring pattern 1241a and an inner seal ring pattern 1241b separated from each other by a dielectric material.
[0075] In one embodiment, the seal ring pattern 1241 can further include a pad layer 1244, which can be the uppermost layer of the plurality of seal ring pattern layers. In this embodiment, the pad layer 1244 is disposed on the uppermost layer of the outer seal ring pattern 1241a, but the present application is not limited thereto. In one embodiment, a passivation layer 140 is conformally disposed on the seal ring pattern 1241, the pad layer 1244, and the alignment mark pattern 1242, as shown, to protect the underlying pad layer 1244 and other electrical elements, to help prevent or reduce moisture damage, mechanical damage, and radiation damage, and to absorb or release heat and / or mechanical stress during wafer dicing and packaging processes. Figure 7A
[0076] In some embodiments, the outer seal ring pattern 1241a of the seal ring pattern 1241 is formed by a plurality of wiring layers 125a and inter-wire vias 126a stacked on each other. Similarly, the inner seal ring pattern 1241b of the seal ring pattern 1241 is formed by a plurality of wiring layers 125b and inter-wire vias 126b stacked on each other. In one embodiment, the seal ring pattern 1241 can be connected to the elements 112 of the substrate 110, and in other embodiments, the seal ring pattern 1241 can be electrically insulated from the elements of the substrate 110. The alignment mark pattern 1242 is disposed outside the outer seal ring pattern 1241a and is formed by a plurality of wiring layers 127 and inter-wire vias 128 stacked on each other. In this embodiment, the wiring layers 127 of each layer of the alignment mark pattern 1242 are disposed on the same plane as the wiring layers 125a, 125b of each layer of the seal ring pattern 1241a, 1241b and can be formed simultaneously using a photolithography process.
[0077] Figure 7B is a partial cross-sectional schematic view of a wafer structure according to an embodiment of the present application. It must be noted that the wafer structure 100 of the present embodiment is similar to the wafer structure of the foregoing embodiments, and thus the present embodiment reuses the element labels and parts of the foregoing embodiments, wherein the same labels are used to represent the same or similar elements, and the description of the same technical content is omitted. For the omitted parts, reference can be made to the foregoing embodiments, which will not be repeated here. Please refer to Figure 7B In some embodiments, the alignment pattern 1242 is formed by stacking a plurality of wiring layers 127 and inter-wire vias 128 on top of each other. The wiring layers 127 of the multi-layered alignment pattern 1242 can be disposed on the same plane as the wiring layers 125a, 125b of the multi-layered sealing ring pattern 1241a, 1241b, respectively, and can be formed simultaneously using a photolithography process. In the present embodiment, unlike the sealing ring pattern 1241a, 1241b, the alignment pattern 1242 can not be stacked on top of the substrate 110, that is, the alignment pattern 1242 can not be connected to the substrate 110, but can be formed on any dielectric layer above the substrate 110 and stacked on top of each other starting from this dielectric layer, and in the present embodiment, the alignment pattern 1242 is not connected to the element 112 of the substrate 110 via a via, that is, the alignment pattern 1242 does not include a via connected to the element 112 of the substrate 110. Of course, the present embodiment is only used for illustration, and the present application does not limit the stacking manner of the alignment pattern 1242.
[0078] In summary, the wafer structure of the present application arranges the alignment pattern within the range framed by the scribe lane and in the area outside the closed region framed by the sealing ring pattern, so as to avoid the problem of the metal layer being exposed due to the alignment pattern on the scribe lane being cut during the chip cutting process, affecting the appearance of the chip. Moreover, since there is no need to worry about the alignment pattern being cut during the chip cutting process, the width of the scribe lane can be further reduced, the chip units on the wafer can be arranged more densely, and thus the number of cut dies of the wafer can be increased, and the chip production capacity of each wafer can be increased.
[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some or all of the technical features; and these modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A wafer structure, characterized in that, include: Substrate; Cutting channels define chip cells on the substrate; The chip circuit pattern is located in the central region of the chip unit; as well as A peripheral metal pattern is disposed in the peripheral area of the chip unit, surrounding the central area, wherein the peripheral metal pattern includes a sealing ring pattern surrounding the central area and an alignment pattern disposed between the cutting channel and the sealing ring pattern.
2. The wafer structure according to claim 1, characterized in that, The sealing ring pattern includes a chamfer to create a corner area in the chip cell, and the alignment pattern is disposed within the corner area created by the chamfer.
3. The wafer structure according to claim 1, characterized in that, The peripheral metal pattern also includes multiple dummy metal pads, which are evenly distributed between the sealing ring pattern and the alignment pattern.
4. The wafer structure according to claim 1, characterized in that, The outer edge of the alignment pattern is collinear with the outer edge of the corresponding sealing ring pattern.
5. The wafer structure according to claim 1, characterized in that, Viewed from the top, the alignment pattern does not overlap with the cutting path.
6. The wafer structure according to claim 1, characterized in that, The chip circuit pattern is electrically insulated from the surrounding metal pattern.
7. The wafer structure according to claim 1, characterized in that, The alignment pattern is L-shaped, square-shaped, cross-shaped, Z-shaped, or hourglass-shaped.
8. The wafer structure according to claim 1, characterized in that, The sealing ring pattern comprises multiple sealing ring pattern layers stacked on top of each other on the substrate.
9. The wafer structure according to claim 1, characterized in that, The alignment pattern comprises multiple alignment pattern layers stacked on the substrate, and each layer is disposed in the same layer as the corresponding multiple sealing ring pattern layers.
10. The wafer structure according to claim 1, characterized in that, The sealing ring pattern includes an inner sealing ring pattern surrounding the central region and an outer sealing ring pattern surrounding the inner sealing ring pattern.
11. The wafer structure according to claim 10, characterized in that, The alignment pattern is positioned between the cutting channel and the outer sealing ring pattern.
12. A chip structure, characterized in that, include: The substrate includes a central region and a peripheral region surrounding the central region; The chip circuit pattern is set in the central area; as well as The peripheral metal pattern is disposed in the peripheral area and includes a sealing ring pattern surrounding the chip circuit pattern and an alignment pattern disposed outside the closed area enclosed by the sealing ring pattern.
13. The chip structure according to claim 12, characterized in that, The alignment pattern is disposed between the outer edge of the chip structure and the sealing ring pattern.
14. The chip structure according to claim 12, characterized in that, The sealing ring pattern has a chamfer at the corner corresponding to the substrate, and the alignment pattern is disposed at the corner where the chamfer is vacated.
15. A wafer structure, characterized in that, include: Substrate; Cutting channels define chip cells on the substrate; A chip is disposed in the chip unit; as well as A sealing ring surrounds the chip and is located between the dicing channel and the chip; as well as Alignment marks are placed between the cutting channel and the sealing ring.