Clock reset system level verification method and device based on general verification methodology

Abstract

The invention relates to the technical field of chip testing, and discloses a clock reset system-level verification method and device based on general verification methodology, and the method comprises the steps: firstly analyzing a clock topological relation defined in a system control unit architecture document, and generating a clock reset information table; on the basis of the information table, an executable verification environment component and a virtual interface component are automatically generated through a script, the verification environment component comprises an excitation forwarding and processing component and can generate clock and reset signals matched with framework definition, and the virtual interface component can generate actual clock and reset waveforms; and finally, constructing a verification platform based on the components, calling the excitation sequence in the parameterized test sequence library, and carrying out system-level clock reset verification on the digital chip. And meanwhile, the parameterized test sequence library supports flexible adjustment of a verification scene and ensures that a test case fits a clock frequency defined by an architecture document, and a reset mechanism can improve the efficiency, accuracy and reliability of digital chip clock reset system-level verification.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, in particular to a clock reset system-level verification method and device based on a general verification methodology. BACKGROUND

[0002] The digital IC front-end development process includes key links such as specification formulation and architecture design, register transfer level design and coding, functional simulation and verification, logic synthesis and formal verification, static timing analysis, and testability design. In the architecture design stage, a top-down hierarchical method is adopted, the functional definition and interface specification of the system-level chip are first completed, then the functional subsystem modules are disassembled, and finally the module-level reusable unit design is decomposed, while the system control unit architecture document is generated, the global clock topology relationship of the chip is clarified, and the key timing parameters such as the phase constraint of the main frequency / frequency division clock and the reset domain dependency are covered. In the register transfer level design and functional verification stage, a bottom-up reverse path is adopted, the register transfer level coding and functional verification of the unit module are first completed, then the module interconnection logic is ensured to be correct through subsystem level integration verification, and finally the system-level verification is carried out at the system-level chip level.

[0003] Clock and reset signals are the core of digital IC verification to ensure the correctness and reliability of circuit functions. As the "heart" of synchronous sequential circuits, the stability, frequency, duty cycle and phase relationship of the clock signal determine the timing behavior of the register and logic unit. If there are problems such as jitter and glitch, it may cause timing violations and functional failures, so verification needs to focus on clock switching logic, multi-clock domain synchronization mechanism and extreme scenario fault tolerance capability. The reset signal is related to system initialization, and asynchronous reset has the risk of metastability during reset release, and synchronous reset needs to be strictly aligned with the clock edge, so verification needs to cover reset glitch removal, reset and clock timing relationship and other aspects.

[0004] The traditional module-level or subsystem-level verification platform based on the general verification methodology relies on manual coding of fixed code modules for clock and reset signal generation. Engineers need to manually instantiate clock generators and reset controllers, configure relevant parameters and dynamically adjust reset properties. Although this method can achieve basic functions, as the chip scale evolves to subsystem or system-level chip level, the limitations become apparent: first, the code is redundant and the phase relationship is difficult to control. Subsystem-level design contains dozens of clock domains and multiple reset domains. The traditional platform needs to be independently configured for each clock and reset signal, making it difficult to efficiently manage multi-clock phase relationships and reset signal propagation path dependencies. Second, the risk of high-level reuse is high. In system-level chip verification, the global clock and reset are generated and managed by a dedicated system control unit, while the local clock / reset signal is manually driven in the module and subsystem level verification environment. When the module-level verification use case is reused at a higher level, it is easy to cause timing violations due to the difficulty of accurately reproducing the clock topology structure of the system control unit by the manual clock. Summary of the Invention

[0005] In view of this, to address the potential risks posed by the manual configuration redundancy and difficulty in accurately reproducing the clock topology of the system control unit module in traditional clock reset generation schemes, this application provides a clock reset system-level verification method and apparatus based on a general verification methodology. This method can automatically instantiate clock and reset signal sources that strictly match the clock logic defined in the architecture system control unit. Verification is performed based on the clock reset generated by this scheme, ensuring that test cases can run within the clock frequency, power mechanism, and reset mechanism defined in the high-level documentation.

[0006] This application provides a clock reset system-level verification method based on a general verification methodology, including:

[0007] Parse the clock topology defined in the system control unit architecture document and generate a clock reset information table;

[0008] Based on the clock reset information table, an executable verification environment component and a virtual interface component are automatically generated by a script. The verification environment component has an internally instantiated stimulus forwarding component and stimulus processing component, which are used to generate clock and reset signals that match the system control unit architecture definition. The virtual interface component is used to generate actual clock and reset waveforms.

[0009] A verification platform is built based on verification environment components and virtual interface components. By calling the stimulus sequences in the parameterized test sequence library, the system-level clock reset verification of the digital chip is performed to match the system control unit architecture definition.

[0010] This application also provides a clock reset system-level verification device based on a general verification methodology, including:

[0011] The clock reset information advance module is used to parse the clock topology relationship defined in the system control unit architecture document and generate a clock reset information table.

[0012] The verification platform component acquisition module is used to automatically generate executable verification environment components and virtual interface components through scripts based on the clock reset information table. The verification environment component has an internally instantiated stimulus forwarding component and stimulus processing component, which are used to generate clock and reset signals that match the system control unit architecture definition. The virtual interface component is used to generate actual clock and reset waveforms.

[0013] The clock reset verification module is used to build a verification platform based on the verification environment components and virtual interface components. By calling the stimulus sequences in the parameterized test sequence library, it performs system-level clock reset verification on the digital chip to match the system control unit architecture definition.

[0014] This application also provides an electronic device, including:

[0015] Memory, used to store computer programs;

[0016] A processor for implementing a clock-reset system-level verification method of any of the above-described general verification methodologies when executing the computer program.

[0017] This embodiment also provides a computer-readable storage medium storing computer instructions, which are used to cause a computer to execute any of the above-described clock reset system-level verification methods based on a general verification methodology.

[0018] This application provides a clock reset system-level verification method and apparatus based on a general verification methodology. It generates a clock reset information table by parsing the system control unit architecture document, and then automatically generates the verification environment and virtual interface components using scripts, combined with a parameterized test sequence library for verification. Compared to the traditional method of manually writing fixed code modules, this significantly reduces the workload of manual configuration and avoids code redundancy. The automatically generated components can accurately reproduce the clock topology relationships defined in the system control unit architecture, solving the problem of difficulty in matching global clock logic with manual coding, and eliminating the timing compatibility risk of reusing module-level verification test cases to higher levels. Simultaneously, the parameterized test sequence library supports flexible adjustment of verification scenarios, ensuring that test cases conform to the clock frequency, reset mechanism, etc., defined in the architecture document, improving the efficiency, accuracy, and reliability of digital chip clock reset system-level verification. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating a clock reset system-level verification method based on a general verification methodology according to an embodiment of this application.

[0021] Figure 2 This is a flowchart illustrating the workflow of uvm_driver according to an embodiment of this application;

[0022] Figure 3 This is a flowchart illustrating the interface according to an embodiment of this application;

[0023] Figure 4 This is a flowchart of the reset control function according to an embodiment of this application;

[0024] Figure 5 This is a flowchart of the clock divider function according to an embodiment of this application;

[0025] Figure 6 This is a flowchart of the clock generation function according to an embodiment of this application;

[0026] Figure 7 This is a structural block diagram of a clock reset system-level verification device based on a general verification methodology according to an embodiment of this application;

[0027] Figure 8 A schematic diagram of the hardware structure of the electronic device according to an embodiment of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] This embodiment provides a clock reset system-level verification method based on a general verification methodology. Figure 1 This is a flowchart of a clock reset system-level verification method based on a general verification methodology according to an embodiment of this application. The specific steps are as follows:

[0030] Step S1: Parse the clock topology relationship defined in the system control unit architecture document and generate a clock reset information table.

[0031] Specifically, this application embodiment extracts the chip global clock topology relationship defined in the System Control Unit (SCU) architecture document. The clock topology relationship includes the phase constraint relationship between the main frequency clock and the frequency divider clock (referring to the specific correspondence between the frequency divider clock obtained by dividing the main frequency clock and the main frequency clock in terms of phase) and the reset domain dependency relationship (referring to the associated constraint relationship between the reset signals of different functional modules or clock domains within the digital chip in terms of generation, release timing and validity). The clock reset information table defines a set of dynamically configurable attributes for each clock signal, including clock frequency, duty cycle, jitter amplitude and whether frequency reduction is supported. As shown in Table 1 below, clk_01 and clk_02 are both derived from clk_0 by frequency division, and their phase correlation characteristics are defined by a synchronization identifier. For clk_1, its period is 100MHz, its duty cycle is 60%, and its jitter amplitude is 1%. Therefore, its positive half-cycle fluctuates between 5.94 and 6.06 ns, and its negative half-cycle fluctuates between 3.96 and 4.04 ns. For clocks that support frequency reduction, users can flexibly adjust the clock frequency in dynamic simulation according to the test sequence library provided in this application. For the reset signal, its reset release timing and synchronous / asynchronous mode (whether the reset and reset release are synchronized with the clock) need to be extracted. During the verification process, targeted tests can be carried out for the unique attributes of different clock signals. For example, for clocks that support frequency reduction, their frequency reduction function and related timing can be accurately verified; for clocks with specific jitter amplitude requirements, jitter scenarios can be accurately simulated to further improve the comprehensiveness and accuracy of the verification and ensure that the verification results are more in line with the actual chip working requirements.

[0032] Table 1

[0033]

[0034] Step S2: Based on the clock reset information table, an executable verification environment component and a virtual interface component are automatically generated by a script. The verification environment component has an instantiated stimulus forwarding component and a stimulus processing component, which are used to generate clock and reset signals that match the system control unit architecture definition. The virtual interface component is used to generate actual clock and reset waveforms.

[0035] Specifically, a Python script (or Perl script) can be used to automate the process of "clock reset information table parsing → component code template calling → executable UVM verification component generation". The automatically generated verification environment component and virtual interface component fully reuse the topology parameters in the system control unit architecture document, eliminating the need for manual coding and configuration. The generated components come with initialization logic and mode control logic bound to the information table parameters, which can be directly compiled and integrated into the verification platform. This ensures that the verification component is strictly consistent with the clock reset logic defined in the architecture, laying the foundation for subsequent dynamic verification by calling the test sequence library.

[0036] In this embodiment, each set of stimulus forwarding components (uvm_sequencer), stimulus processing components (uvm_driver), and virtual interface components (interface) corresponds to a set of clock reset signals. The uvm_sequencer is used to pass the stimulus to the uvm_driver component; the uvm_driver is used to initialize and parse the stimulus and pass the result to the interface. Users can instantiate and mount any standardized test stimulus sequence, adjusting the clock frequency, duty cycle, jitter amplitude, and reset timing.

[0037] The uvm_driver core functional modules include a system initialization function (initial), a reset control function (reset_control), a clock generation function (clock_gen), and a clock divider function (clock_div). The reset control function controls the timing of the reset signal release and sets its synchronous / asynchronous mode. The clock generation function generates a reference clock based on the duration of the clock high level and the duration of the clock low level. The clock divider function performs integer division operations based on the input clock and the division coefficient to generate a divided clock signal. The system initialization function calls the clock generation function and the reset control function during the initial verification phase to generate an initial clock and reset signal that conform to the system control unit architecture definition.

[0038] The stimulus processing component in this application integrates multiple types of functional functions, each with a clear division of labor and collaborative operation. The system initialization function ensures the generation of clock and reset signals conforming to the architecture definition during the initial verification phase, avoiding errors and delays from manual initialization. The reset control function directly and precisely controls the reset signal, ensuring the effectiveness and timeliness of the reset operation and solving the problems of chaotic and untimely response in traditional reset control logic. The clock generation function and clock division function efficiently generate the reference clock and the divided clock, respectively, meeting different clock requirements. This integrated design makes the stimulus processing component functionally complete and logically clear. Compared to traditional distributed functional modules, it reduces interaction losses between components, improves the efficiency and accuracy of clock and reset signal generation, and lays a stable foundation for subsequent verification work.

[0039] Step S3: Construct a verification platform based on the verification environment component and the virtual interface component. By calling the stimulus sequence in the parameterized test sequence library, perform system-level clock reset verification on the digital chip to match the system control unit architecture definition.

[0040] Specifically, the workflow of the verification environment component includes a system initialization phase and a standardized test stimulus processing phase. In the system initialization phase, the parameters from the clock reset information table are passed to the clock generation function and reset control function through the system initialization function to generate an initial clock and reset signal matching the architecture definition. In the standardized test stimulus processing phase, the stimulus processing component parses the standardized test stimulus sequence called by the user, activates the corresponding function to modify the parameters in the virtual interface component, and achieves dynamic reconstruction of the clock and reset signals. Its workflow is as follows: Figure 2 As shown, after the system initialization phase is completed, uvm_driver and interface jointly generate the clock and reset signals extracted in Table 1. Then, uvm_driver enters a transaction listening state, receiving the verification stimuli forwarded by uvm_sequencer through a transaction-level transmission channel. Based on the stimuli header fields (gen_mode and type, where gen_mode is the mode selection signal used to select the clock generation working mode and is the core identifier distinguishing between "clock generation mode" and "clock division mode," and type is the type identifier used to identify the type of test stimulus sequence and is the basis for triggering "dynamic adjustment of clock / reset parameters" or "reset control"), a multiplexing mechanism is used to activate the corresponding clock reset processing function. Each function parses the stimuli, obtains the following parameters, and passes them to the interface, realizing the control of the clock reset signal by the stimuli. When facing diverse test scenarios, the clock and reset signals can be quickly switched and adjusted to meet different verification needs in a timely manner, reducing verification delays caused by process inefficiencies and improving the overall verification progress and quality.

[0041] The interface employs a dual-mode reconfigurable architecture (clock generation mode GEN_MODE and clock division mode DIV_MODE) to dynamically generate and control the clock signal. Specifically, the clock generation mode generates a reference clock signal based on the duration of the input high-level and low-level signals; the clock division mode divides the input reference clock signal and a division coefficient to generate a divided clock signal. In the clock generation mode, the virtual interface component constructs periodic level switching logic based on the high-level and low-level durations to generate the reference clock signal. Its working mechanism is as follows: Figure 3 As shown:

[0042] In GEN_MODE, periodic level switching logic is constructed using clk_delay (clock high-level duration) and clk_width (clock low-level duration) to generate the reference clock signal clk_o. In DIV_MODE, the rising edge of the input clock clk_in triggers the counter and edge alignment logic to perform integer frequency division and output a synchronous frequency-divided clock. After module initialization, the clock path is activated by the enable signal clk_enable (default set), and the functional state is switched in real time according to the mode selection signal gen_mode. The dynamic adjustment mechanism uses a clock domain synchronization detection unit to latch and sample clk_enable and gen_mode at each rising edge of clk_o, triggering the internal state machine to perform mode switching or parameter reload operations. This design achieves dynamic reconstruction of key parameters such as runtime clock frequency and frequency division coefficient, thereby completing the dynamic adjustment of the clk_o clock.

[0043] The virtual interface component adopts a dual-mode reconfigurable architecture. The clock generation mode and frequency division mode respectively meet the requirements for base clock generation and frequency division clock generation, eliminating the need for additional interface modules with different functions and reducing hardware resource consumption and development costs. Simultaneously, dynamic adjustment is achieved through a clock domain synchronization detection unit, ensuring the timeliness and accuracy of mode switching and parameter reloading, avoiding timing errors that occur during traditional interface mode switching. During verification, the mode can be flexibly switched according to test requirements, accurately generating the necessary clock signals, improving the adaptability and flexibility of the virtual interface component, and further ensuring the comprehensiveness and reliability of the verification.

[0044] Specifically, the interface, as the core interface module for interaction between the user and the verification platform, uses the clock and reset signals generated by the verification scheme in the user's verification platform in the following ways:

[0045] assign user.clk_o = inf.clk_o; / / Connect the clock of the interface component to the signal required by the user.

[0046] assign user.reset = inf.reset; / / Connect the interface component's reset to the user's required signal. assign inf.clk_in = user.clk_in; / / The user connects the clock that needs to be divided to the interface component's clk_in.

[0047] After the simulation begins, the interface operates in two phases: initialization and standardized test stimulus processing. During initialization, the uvm_driver executes the system initialization function (initial), passing the information extracted from Table 1 to the clock generation and reset control functions to generate clock and reset signals that match the architecture definition. After initialization, the uvm_driver awaits user calls for four types of standardized test stimulus sequences. Users can dynamically adjust the attributes of each clock and reset signal by calling the standardized test stimulus sequences according to test scenario requirements and simulation results.

[0048] The parameterized test sequence library in this application embodiment contains multiple standardized test stimulus sequences used to dynamically adjust clock and reset attributes in real time during simulation. Specifically, the test stimulus sequences include:

[0049] 1. clocks_clk_set_sequence (dynamic clock configuration stimulus) is used to set the clock, including frequency, duty cycle, and jitter amplitude. By setting the above parameters, the desired clock is generated. If clock jitter is enabled, the clock period will fluctuate randomly within the user-set range.

[0050] 2. clocks_clk_div_sequence (frequency division clock generation stimulus) is used to divide the input clock frequency by an arbitrary integer. Its adjustable parameter is the division coefficient.

[0051] 3. clocks_clk_stop_sequence (clock stop control stimulus) is used to pause the clock signal, and the clock can be restarted by calling other test stimuli;

[0052] 4. clocks_reset_sequence (reset control stimulus) is used to set the reset duration and synchronous / asynchronous release mode.

[0053] After the user invokes the stimulus sequence through test cases, uvm_driver parses the gen_mode and type fields in the stimulus transaction, and then activates the corresponding function (reset_controll, clock_gen, and clock_div) in uvm_driver. Within these functions, key parameters in the interface are modified accordingly, enabling dynamic reconstruction of critical signals such as the frequency of a specific clock and the reset / release timing during runtime.

[0054] The workflow of the reset control function reset_contorl is as follows: Figure 4As shown, first, it is determined whether it is a synchronous reset. For a synchronous reset, the reset signal must be set to 0 after the rising edge of the clock. For an asynchronous reset, it is set to 0 directly. Then, the set reset time is continuously activated, and then it is determined whether it is a synchronous release. For a synchronous release, the reset signal must be set to 1 after the rising edge of the clock. For an asynchronous release, it is set to 1 directly. Finally, the reset is completed.

[0055] The workflow of the clock divider function, clock_div, is as follows: Figure 5 As shown, first determine if the type is set (type=set). If not, execute reset control (reset_contorl). If yes, then determine if the enable is 1 (enable=1). If not, enter the clock enable branch in the interface to pause the clock. If yes, assign the division coefficient (inf.div) to the set division value (div). Finally, complete the division in the division mode (DIV_MODE) branch of the interface.

[0056] The workflow of the clock generation function clock_gen is as follows: Figure 6 As shown, jitter is the clock jitter amplitude; half_min and half_max are the maximum and minimum values ​​of half a clock cycle, affected by jitter; $urandom_range() is a UVM system function that returns an integer value within a range of parentheses (e.g., if a = $urandom_range(1,4), then the value of a could be 1, 2, 3, or 4). First, it checks if the type is set (type = set). If not, it executes reset control. If so, it checks if the enable is 1. If not, it enters the interface clock enable branch to pause the clock. If so, it calculates the minimum and maximum values ​​of the half cycle and jitter range. Then, based on the duty cycle and jitter range, it randomly generates the clock high-level duration (clk_delay) and low-level duration (clk_width), assigns them to the relevant interface parameters, enters the interface generation mode branch to generate the clock, and finally waits for the sum of clk_delay and clk_width, repeating this process.

[0057] In one embodiment, this application also includes the clock gating enable signal in the parsing scope of the system control unit architecture document. By extracting the correlation between the clock gating enable signal and the voltage domain and power state in the system control unit document, a dynamic gating verification scenario bound to the voltage domain or power state is automatically generated.

[0058] By adding a gating logic and power state simulation module to the existing verification components, dynamic gating verification scenarios are automatically generated. An example of the process is as follows:

[0059] Component generation: The script automatically adds gating control logic to the virtual interface component (interface) and adds power state simulation function to the excitation processing component (uvm_driver) to realize the linkage of "power state change → gating enable signal trigger → clock state switching";

[0060] Scenario execution: When the verification platform is initialized, the clock is in the "gated off" state by default (clock is output normally); when the test stimulus sequence is called to simulate the power state switch (such as the peripheral power supply switching from "ACTIVE" to "OFF"), the virtual interface component will automatically trigger the enable signal to switch the peripheral clock B to the high impedance state.

[0061] Scene verification: The excitation processing component monitors the clock status in real time. If the peripheral clock B does not become high impedance when the power is switched to "OFF", an error will be automatically reported, and the gate logic verification will be completed.

[0062] By including the clock gating enable signal in the analysis scope, the verification gap of clock gating logic in low-power scenarios in traditional verification is filled, covering the linkage scenario of "voltage domain-power state-clock gating", ensuring that the verification is closer to the actual working logic of the chip; the dynamic gating verification scenario strictly follows the "voltage domain-power state-gating" relationship defined in the SCU document, ensuring that the clock gating operation and power state switching timing are consistent, avoiding the risk of chip function failure due to gating logic disorder.

[0063] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0064] This embodiment also provides a clock reset system-level verification device based on a general verification methodology. This system is used to implement the above embodiments and preferred embodiments, and details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the systems described in the following embodiments are preferably implemented in software, hardware implementations, or a combination of software and hardware, are also possible and contemplated.

[0065] This application also provides a clock reset system-level verification device based on a general verification methodology, such as... Figure 7 As shown, it includes:

[0066] The clock reset information advance module 71 is used to parse the clock topology relationship defined in the system control unit architecture document and generate a clock reset information table.

[0067] The verification platform component acquisition module 72 is used to automatically generate an executable verification environment component and a virtual interface component through a script based on the clock reset information table. The verification environment component has an internally instantiated stimulus forwarding component and stimulus processing component, which are used to generate clock and reset signals that match the system control unit architecture definition. The virtual interface component is used to generate actual clock and reset waveforms.

[0068] The clock reset verification module 73 is used to build a verification platform based on the verification environment component and the virtual interface component. By calling the stimulus sequence in the parameterized test sequence library, it performs system-level clock reset verification on the digital chip to match the system control unit architecture definition.

[0069] The description of the features in the embodiments of the clock reset system-level verification device based on the general verification methodology described above can be found in the description of the embodiments of the clock reset system-level verification method based on the general verification methodology, and will not be repeated here.

[0070] Embodiments of this application also provide an electronic device, such as... Figure 8 As shown, it includes a memory 20 and a processor 10. The memory 20 stores a computer program, and the processor 10 is configured to run the computer program to perform the steps in any of the above embodiments of the clock reset system-level verification method based on a general verification methodology.

[0071] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the clock reset system-level verification method based on a general verification methodology when it is run.

[0072] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0073] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0074] The above provides a detailed description of a clock reset system-level verification method based on a general verification methodology. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of these embodiments are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this application.

Claims

1. A clock reset system-level verification method based on a general verification methodology, characterized in that, include: Parse the clock topology defined in the system control unit architecture document and generate a clock reset information table; Based on the clock reset information table, an executable verification environment component and a virtual interface component are automatically generated by a script. The verification environment component has an internally instantiated stimulus forwarding component and stimulus processing component, which are used to generate clock and reset signals that match the system control unit architecture definition. The virtual interface component is used to generate actual clock and reset waveforms. A verification platform is built based on verification environment components and virtual interface components. By calling the stimulus sequences in the parameterized test sequence library, the system-level clock reset verification of the digital chip is performed to match the system control unit architecture definition.

2. The method of claim 1, wherein, The clock topology relationship includes the phase constraint relationship between the master clock and the divider clock, and the reset domain dependency relationship; the clock reset information table defines a set of dynamically configurable attributes for each clock signal, including clock frequency, duty cycle, jitter amplitude, and whether frequency reduction is supported.

3. The method of claim 1, wherein, The excitation processing component integrates system initialization functions, reset control functions, clock generation functions, and clock division functions; among which... The reset control function is used to control the timing of the release of the reset signal and to set its synchronous / asynchronous mode; The clock generation function is used to generate a reference clock based on the duration of the clock high level and the duration of the clock low level. The clock division function is used to perform integer division operations based on the input clock and the division coefficient to generate a divided clock signal. The system initialization function is used to call the clock generation function and the reset control function during the initial verification phase to generate an initial clock and reset signal that conform to the system control unit architecture definition.

4. The method of claim 3, wherein, The workflow of the verification environment component includes a system initialization phase and a standardized test stimulus processing phase; wherein: During the system initialization phase, the parameters in the clock reset information table are passed to the clock generation function and the reset control function through the system initialization function to generate an initial clock and reset signal that match the architecture definition. During the standardized test stimulus processing phase, the stimulus processing component parses the standardized test stimulus sequence called by the user, activates the corresponding function to modify the parameters in the virtual interface component, and realizes dynamic reconstruction of the clock and reset signals.

5. The method of claim 1, wherein, The virtual interface component adopts a dual-mode reconfigurable architecture, including: Clock generation mode, used to generate a reference clock signal based on the duration of the high level and the duration of the low level input; The clock division mode is used to divide the input reference clock signal and the division coefficient to generate a divided clock signal; in the clock generation mode, the virtual interface component constructs periodic level switching logic through the high level duration and the low level duration to generate the reference clock signal; In the frequency division mode, the virtual interface component triggers the counter and the edge alignment logic based on the rising edge of the input clock, completes the integer frequency division operation and outputs the synchronous frequency division clock; and the virtual interface component realizes dynamic adjustment through the clock domain synchronization detection unit, latches and samples the clock enable signal and the mode selection signal on each rising edge of the reference clock signal, triggers the internal state machine to perform mode switching or parameter reloading operation.

6. The method of claim 1, wherein, The parameterized test sequence library contains a plurality of standardized test stimulus sequences for dynamically adjusting the clock and reset attributes in real time during simulation; The test stimulus sequence includes: The dynamic clock configuration stimulus is used for setting the clock, including frequency, duty cycle, jitter amplitude; The frequency division clock generation stimulus is used for performing arbitrary integer frequency division on the input clock frequency, and the adjustable parameter is the frequency division coefficient; The clock pause control stimulus is used for pausing the clock signal, and the clock can be restarted by calling other test stimuli; The reset control stimulus is used for setting the reset duration and synchronous / asynchronous release mode.

7. The method according to any of claims 1 to 6, characterized in that, Further comprising: The clock gating enable signal is included in the parsing range of the system control unit architecture document, and the association relationship between the clock gating enable signal and the voltage domain and the power state in the system control unit document is extracted to automatically generate the dynamic gating verification scene bound with the voltage domain or the power state.

8. A clock reset system-level verification apparatus based on a general verification methodology, characterized by, Comprising: A clock reset information pre-generation module for parsing the clock topology relationship defined in the system control unit architecture document to generate a clock reset information table; A verification platform component acquisition module for automatically generating executable verification environment components and virtual interface components through scripts based on the clock reset information table, the verification environment components internally instantiating stimulus forwarding components and stimulus processing components for generating clock and reset signals matching the system control unit architecture definition, and the virtual interface components for generating actual clock and reset waveforms; A clock reset verification module for constructing a verification platform based on the verification environment components and the virtual interface components, and performing system control unit architecture definition matching system-level clock reset verification on a digital chip by calling the stimulus sequences in the parameterized test sequence library.

9. An electronic device, comprising: Comprising: A memory and a processor, which are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the clock reset system-level verification method based on the general verification methodology according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for causing a computer to execute the clock reset system-level verification method based on the general verification methodology according to any one of claims 1 to 7.

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