A clock tree timing optimization method and a computer readable storage medium

Abstract

A clock tree timing optimization method and a computer readable storage medium, relate to the technical field of clock tree synthesis and timing optimization. The method comprises: obtaining a to-be-processed timing path, starting from the to-be-processed timing path, performing timing optimization on the to-be-processed timing path, the timing optimization comprising: determining a register with the smallest timing margin as a to-be-processed register; determining a target fan-in end timing margin according to a plurality of fan-in end timing margins of the to-be-processed register; and / or determining a target fan-out end timing margin according to a plurality of fan-out end timing margins of the to-be-processed register; calculating a clock offset according to the target fan-in end timing margin and / or the target fan-out end timing margin; adjusting each fan-in end timing margin of the to-be-processed register and / or each fan-out end timing margin of the to-be-processed register according to the clock offset; updating the to-be-processed timing path until a set ending condition is reached.

Description

Technical Field

[0001] This invention relates to the field of clock tree synthesis and timing optimization technology, specifically to a timing optimization method for clock trees and a computer-readable storage medium. Background Technology

[0002] Digital integrated circuits integrate multiple electronic components onto a single chip, interconnecting them to achieve specific digital logic functions. In digital integrated circuits, the timing synchronization of clock signals and data information is the benchmark for data transmission. With the development of digital information, integrated circuits are becoming increasingly larger, making the optimization of timing in complex circuits by electronic design automation (EDA) tools increasingly challenging.

[0003] Timing margin (slack) is a crucial metric for evaluating the effectiveness of timing in digital integrated circuits. Typically, digital logic circuits contain thousands of timing paths, each with a timing margin. A negative timing margin indicates that the timing path fails to meet setup time or hold time requirements, resulting in a timing violation. During clock tree timing optimization, the worst-case negative slack (wns) and the total negative slack (tns) are usually considered as evaluation criteria for timing optimization.

[0004] As mentioned above, effective timing is a fundamental prerequisite for a chip to achieve its intended function correctly and reliably. Timing convergence is also a key research focus and challenge in the clock tree synthesis stage. Existing timing optimization schemes mostly achieve timing optimization by reducing clock skew between clock paths, which is an indirect optimization method. It is difficult to adjust for specific paths, which can easily lead to unstable timing analysis results. Summary of the Invention

[0005] The main technical problem solved by this invention is to provide a timing optimization method that directly feeds timing problems back to the clock tree of clock delay.

[0006] According to the first aspect, one embodiment provides a timing optimization method for a clock tree, comprising:

[0007] Obtain the timing margin of all timing paths on the clock tree, and determine the timing path with the smallest timing margin among all timing paths as the timing path to be processed. The timing path to be processed includes a start register and a stop register.

[0008] Starting from the timing path to be processed, timing optimization is performed on the timing path to be processed, and the timing optimization includes:

[0009] The timing margin of the starting register in the timing path to be processed is compared with the timing margin of the ending register in the timing path to be processed, so as to determine the register with the smallest timing margin as the register to be processed.

[0010] Obtain multiple fan-in timing margins of the register to be processed, and determine the target fan-in timing margin based on the multiple fan-in timing margins of the register to be processed.

[0011] And / or,

[0012] Obtain multiple fan-out timing margins of the register to be processed, and determine the target fan-out timing margin based on the multiple fan-out timing margins of the register to be processed.

[0013] Calculate the clock offset based on the target fan-in timing margin and / or the target fan-out timing margin;

[0014] Adjust the timing margins of each fan-in terminal and / or each fan-out terminal of the register to be processed according to the clock offset to complete the timing optimization of the timing path to be processed.

[0015] Reacquire the timing margins of all timing paths on the clock tree, and update the timing path with the smallest timing margin among all timing paths as the timing path to be processed, so as to perform the timing optimization, until the set termination condition is reached.

[0016] In one embodiment, determining the target fan-in timing margin based on the multiple fan-in timing margins of the register to be processed includes:

[0017] The timing margins of multiple fan-in terminals of the register to be processed are compared;

[0018] The smallest fan-in timing margin among the plurality of fan-in timing margins is determined as the target fan-in timing margin.

[0019] Determining the target fan-out timing margin based on the multiple fan-out timing margins of the register to be processed includes:

[0020] The timing margins of multiple fan-out terminals of the register to be processed are compared;

[0021] The smallest fan-out timing margin among the plurality of fan-out timing margins is determined as the target fan-out timing margin.

[0022] In one embodiment, determining the target fan-in timing margin based on the multiple fan-in timing margins of the register to be processed includes:

[0023] The timing margins of multiple fan-in terminals of the register are compared; the multiple fan-in timing margins are arranged in ascending order of timing margin, and the target fan-in timing margin is determined based on the first n fan-in timing margins in ascending order, where n is a natural number.

[0024] Determining the target fan-out timing margin based on the multiple fan-out timing margins of the register to be processed includes:

[0025] The timing margins of multiple fan-out terminals of the register are compared;

[0026] The multiple fan-out timing margins are arranged in ascending order of timing margin. The target fan-out timing margin is determined based on the first m fan-out timing margins in ascending order, where m is a natural number.

[0027] In one embodiment, when the register to be processed is a first register that simultaneously contains fan-in timing margin and fan-out timing margin, the target fan-in timing margin and the target fan-out timing margin of the first register are obtained.

[0028] Calculate the clock offset of the first register based on the target fan-in timing margin and the target fan-out timing margin of the first register.

[0029] Adjust the timing margins of each fan-in terminal and each fan-out terminal of the first register according to the clock offset of the first register.

[0030] In one embodiment, calculating the clock offset of the first register based on the target fan-in timing margin and the target fan-out timing margin of the first register includes:

[0031] When the timing margin of the target fan-in terminal of the first register is greater than 0 and the timing margin of the target fan-out terminal of the first register is less than 0, calculate the timing margin difference between the timing margin of the target fan-out terminal of the first register and the timing margin of the target fan-in terminal of the first register.

[0032] The first preset ratio of the timing margin difference is the clock offset of the first register;

[0033] When the timing margin of the target fan-in terminal of the first register is less than 0 and the timing margin of the target fan-out terminal of the first register is greater than 0, calculate the timing margin difference between the timing margin of the target fan-out terminal of the first register and the timing margin of the target fan-in terminal of the first register.

[0034] The second preset ratio of the timing margin difference is the clock offset of the first register;

[0035] When the timing margin of the target fan-in terminal of the first register is less than 0 and the timing margin of the target fan-out terminal of the first register is less than 0, calculate the timing margin difference between the timing margin of the target fan-out terminal of the first register and the timing margin of the target fan-in terminal of the first register.

[0036] The third preset ratio of the timing margin difference is the clock offset of the first register.

[0037] In one embodiment, adjusting the timing margins of each fan-in terminal and each fan-out terminal of the first register according to the clock offset of the first register includes:

[0038] When the timing margin of the target fan-in terminal of the first register is greater than 0 and the timing margin of the target fan-out terminal of the first register is less than 0, the timing margins of each fan-in terminal and each fan-out terminal of the first register are adjusted according to the clock offset of the first register, so that the timing margins of each fan-in terminal of the first register decrease and the timing margins of each fan-out terminal of the first register increase.

[0039] When the timing margin of the target fan-in terminal of the first register is less than 0 and the timing margin of the target fan-out terminal of the first register is greater than 0, the timing margins of each fan-in terminal and each fan-out terminal of the first register are adjusted according to the clock offset of the first register, so that the timing margin of each fan-out terminal of the first register decreases and the timing margin of each fan-in terminal of the first register increases.

[0040] When the timing margin of the target fan-in terminal of the first register is less than 0 and the timing margin of the target fan-out terminal of the first register is less than 0, the timing margins of each fan-in terminal and each fan-out terminal of the first register are adjusted according to the clock offset of the first register, so that the timing margins of each terminal corresponding to the smaller timing margin of the target fan-in terminal timing margin and the target fan-out terminal timing margin in the first register are increased, and the timing margins of the other terminal are decreased.

[0041] In one embodiment, when the register to be processed is a second register that only contains fan-out timing margin, the target fan-out timing margin of the second register is obtained;

[0042] When the timing margin of the target fan-out terminal of the second register is less than 0, the clock offset of the second register is determined according to the timing margin of the target fan-out terminal of the second register.

[0043] Adjust the timing margin of each fan-out terminal of the second register according to the clock offset of the second register, so as to increase the timing margin of each fan-out terminal of the second register.

[0044] In one embodiment, when the register to be processed is a third register that only contains fan-in timing margin, the target fan-in timing margin of the third register is obtained;

[0045] When the timing margin of the target fan-in terminal of the third register is less than 0, the clock offset of the third register is determined according to the timing margin of the target fan-in terminal of the third register.

[0046] Adjust the timing margin of each fan-in terminal of the third register according to the clock offset of the third register, so as to increase the timing margin of each fan-in terminal of the third register.

[0047] In one embodiment, the set termination condition includes the timing margin of the updated timing path to be processed reaching a set value, or the number of times the timing path to be processed is time-optimized reaches a set number.

[0048] According to a second aspect, one embodiment provides a computer-readable storage medium storing a computer program that can be executed by a processor to implement the methods described in any of the above embodiments.

[0049] According to the timing optimization method for clock trees and the computer-readable storage medium of the above embodiments, in this method, the timing path with the smallest timing margin among all timing paths in the clock tree is determined as the timing path to be processed, and the register with the smallest timing margin in the timing path to be processed is determined as the register to be processed. For multiple fan-in terminals of the register to be processed, their respective timing margins are obtained, and a target fan-in timing margin is determined accordingly; and / or, for multiple fan-out terminals of the register to be processed, their respective timing margins are obtained, and a target fan-out timing margin is determined accordingly. A corresponding clock offset is calculated based on the target fan-in timing margin and / or the target fan-out timing margin, and the timing margins of the fan-in and / or fan-out terminals of the register to be processed are adjusted according to the clock offset, thereby completing the optimization of the timing path to be processed. The timing path with the smallest timing margin in the clock tree is updated as the timing path to be processed in the next iteration, and timing optimization is performed. This process is repeated until the set termination condition is met, at which point timing optimization of the clock tree stops. This application enables direct timing adjustment of registers. By calculating clock offsets in real time, timing violations can be quickly offset, accelerating the chip timing convergence process. Furthermore, this application can simultaneously consider the timing relationship between the input and output paths of registers. By selectively adjusting the fan-in or fan-out margins, timing balance can be achieved, avoiding a situation where fixing one aspect leads to a corresponding problem. Attached Figure Description

[0050] Figure 1This is a flowchart of a timing optimization method for a clock tree in one embodiment;

[0051] Figure 2 This is a flowchart of step S100 in a timing optimization method for a clock tree in one embodiment;

[0052] Figure 3 This is a schematic diagram of the connection of the first register in one embodiment;

[0053] Figure 4 This is a flowchart of a timing optimization method for a first register in one embodiment;

[0054] Figure 5 This is a schematic diagram of the connection of the second register in one embodiment;

[0055] Figure 6 This is a flowchart of a timing optimization method for a second register in one embodiment;

[0056] Figure 7 This is a schematic diagram of the connection of the third register in one embodiment;

[0057] Figure 8 This is a flowchart of a timing optimization method for a third register in one embodiment. Detailed Implementation

[0058] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0059] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0060] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0061] The following definitions apply to the terms used in this application:

[0062] Time margin: In digital circuits, a signal triggered by a flip-flop or register propagates through logic gates to reach the next register input. This process requires stabilization before the arrival of a clock edge. If the time margin is greater than 0, the signal has sufficient time to reach its destination register, and the timing requirements are met. If the time margin is equal to 0, the signal just barely makes it, indicating a timing boundary condition. If the time margin is less than 0, the signal is either too slow or too fast, resulting in a timing violation.

[0063] Setup time: The minimum time it takes for the input signal to stabilize before the rising edge of the clock arrives. If the signal arrives too late (failing to meet the setup time), the register may sample incorrect data.

[0064] Hold time: The minimum time the input signal needs to remain stable after the rising edge of the clock. If the signal changes too quickly (failing to meet the hold time), it may interfere with the register's sampling process.

[0065] Worst-case time margin: The smallest time margin among all paths, reflecting the most severe timing violation. If the worst-case time margin is less than 0, it indicates that at least one path has a violation.

[0066] Total negative time margin: The sum of the time margins of all paths with a time margin less than 0, reflecting the total number of timing violations in the entire circuit. The closer it is to 0, the better the overall timing.

[0067] Clock skew: The difference in arrival time of the same clock signal between different flip-flops or registers.

[0068] In one embodiment, in digital integrated circuit design, clock tree timing optimization is a complex process with multiple objectives and constraints. Its core objective is to minimize clock skew between clock paths through reasonable structural design, circuit adjustment and physical layout, thereby ensuring that each register is synchronously triggered within the same clock cycle, and achieving the goal of optimizing global timing performance.

[0069] Traditional clock tree synthesis (CTS) typically involves steps such as clock tree topology generation, buffer insertion, and trace length adjustment. This process not only needs to achieve low skew and low latency while meeting timing constraints, but also needs to comprehensively consider factors such as routing resources, power consumption, and chip area. Therefore, it is a typical multi-objective optimization problem. To reduce clock skew, current research mainly focuses on both algorithmic and structural aspects.

[0070] In terms of algorithms, the Deferred Merge Embedding (DME) algorithm is a classic algorithm used in clock tree synthesis to achieve zero or bounded deviation. Starting from the leaf nodes (i.e., the register ends), the algorithm recursively merges candidate merge regions upwards, and during the backtracking process from the root node, selects the point with the shortest Euclidean distance in the candidate regions as the actual merge point, thereby generating a zero-deviation clock tree with the fewest threads.

[0071] In terms of structure, with the continuous increase in chip size and integration, traditional single-source clock trees are struggling to cope with the timing uncertainties brought about by complex interconnect networks and long-distance transmission. For timing optimization of global interconnects and complex clock structures, one existing method proposes a timing optimization approach based on useful bias. This approach introduces controlled clock delay differences into the design to compensate for delay variations in long interconnects, thereby optimizing the time difference between different clock sources arriving at the synchronization point and improving global timing margin.

[0072] Another approach has proposed a top-level clock distribution scheme that combines a clock network and a resonant network. This scheme utilizes a clock grid for global distribution and combines it with a resonant network for clock calibration at the region level to achieve precise phase alignment. At the 5nm advanced process node, this method significantly reduces global clock skew and introduces an adaptive shutdown mechanism to reduce clock-driven power consumption of idle modules, thereby achieving a significant improvement in system energy efficiency.

[0073] In addition, another approach addresses the clock synchronization problem in three-dimensional integrated circuits by proposing a clock network design method based on thermally compensated through-silicon vias (TSVs). This method utilizes TSVs with thermal compensation properties to construct a clock spine structure that traverses the chip stack layers, thereby effectively mitigating the severe clock skew problem caused by uneven temperature gradient distribution.

[0074] With the rapid development of artificial intelligence technology, intelligent algorithms such as machine learning and reinforcement learning have been gradually introduced into the fields of clock tree synthesis and time series optimization, becoming an important research direction for improving optimization efficiency and result quality. Compared with traditional optimization methods based on heuristic rules or deterministic algorithms, intelligent algorithms can achieve adaptive optimization and global convergence under more complex design constraints.

[0075] This paper proposes a clock bias allocation optimization method based on reinforcement learning and supervised learning models to achieve intelligent allocation of useful biases under complex constraints. The method introduces a reinforcement learning agent that interacts with the design environment (including physical design tools and a time series analysis engine). The agent dynamically adjusts its bias allocation strategy based on environmental feedback. By continuously learning the optimal strategy under different design states through a reward function mechanism, the method avoids the local optima problem that traditional algorithms are prone to, even with increasing design complexity, thus automating and intelligentizing the bias allocation process.

[0076] Another approach utilizes deep reinforcement learning to transform the clock tree optimization task into a policy learning problem for the agent. During training, the agent learns the optimal position and size of the buffer insertion based on the reward function, simultaneously satisfying setup and hold time constraints while minimizing overall clock power consumption and deviation. This scheme enables the agent to achieve multi-objective global optimization in complex layout environments by jointly modeling timing features, geometric wiring constraints, and electrical characteristics.

[0077] Another approach proposes a clock tree generation method incorporating graph neural networks (GNNs). This method utilizes GNNs to perform graph structure encoding on the topology and timing constraints (such as critical paths and interconnect delays) of the circuit netlist, generating a learnable high-dimensional feature representation. Based on this high-dimensional feature representation, the model can directly predict the connection topology and routing of the clock tree, ensuring that the generated clock network meets setup / hold time constraints during the physical implementation phase, thereby significantly reducing the number of iterations required for subsequent timing convergence.

[0078] With the widespread application of advanced process nodes (7nm and below), process-related effects have become increasingly significant in their impact on clock tree timing performance, making them an important research direction in the field of timing optimization. These effects include factors such as device aging, stress variations, and uneven temperature distribution, which can cause transistor threshold voltage drift, carrier mobility changes, and interconnect delay fluctuations, thereby leading to a decrease in circuit timing margins or even timing violations.

[0079] One existing approach proposes a clock tree synthesis method that combines NBTI / PBTI aging models with a useful bias strategy. This method introduces an aging prediction model during the clock tree construction phase, performing feedforward corrections to the clock delay distribution based on the performance degradation trend of devices after long-term use. By reserving adjustable biases in the early design phase, it proactively offsets setup time violations caused by aging.

[0080] Another approach addresses the local delay variations caused by shallow trench isolation stress. This method establishes a quantitative model of the relationship between shallow trench isolation stress and device electrical performance, accurately identifying timing offset regions caused by stress unevenness. Combined with hold time analysis, structural optimization and clock phase fine-tuning are performed on the affected paths to achieve targeted repair of hold time violations.

[0081] Another approach proposes a timing compensation mechanism based on an on-chip temperature sensor and dynamic voltage and frequency adjustment. This method monitors temperature changes in different areas of the chip in real time and uses a feedback control strategy to dynamically adjust the supply voltage and clock frequency to compensate for delay drift caused by temperature gradients.

[0082] Timing optimization, whether using traditional methods, artificial intelligence, or process nodes, all have their limitations. Specifically, traditional timing optimization focuses on reducing clock skew between global clock paths, achieving timing optimization by eliminating clock skew. While various algorithms and architectures have emerged, this type of method provides indirect timing optimization. Although artificial intelligence methods have shown great potential in timing optimization, their application still has significant drawbacks, primarily data dependence and quality challenges. AI models require large amounts of high-quality training data; small-sample training can easily lead to underfitting and amplified data noise. Timing optimization at advanced process nodes is susceptible to the uncertainties of the process model; model errors can significantly increase overall error. Overly conservative timing margins waste performance and power consumption, while overly optimistic approaches can cause chip failure.

[0083] To address the various timing optimization issues mentioned above, this application proposes a timing optimization method for clock trees. This method directly feeds back timing problems in the clock tree to the clock delay, thus serving as a reference for changes in clock delay length. Changes in clock delay directly affect timing margin, thereby achieving timing optimization for the entire clock tree. The details are described below.

[0084] Please refer to Figure 1 In one embodiment, the timing optimization method for clock trees provided in this application includes the following steps.

[0085] Step S100: Determine the timing path with the smallest timing margin on the clock tree as the timing path to be processed.

[0086] In one embodiment, a clock tree is used to provide synchronous clock signals to various registers in a chip or logic circuit. Its structure typically includes multiple branch nodes for distributing clock signals to different timing paths. The clock tree includes several timing paths, which refer to a complete link in a clock-driven digital circuit where a signal is triggered from a register or input terminal, transmitted through a combinational logic network, and finally captured at another register or output terminal. Therefore, timing paths include four types: register-to-register paths, input-to-register paths, register-to-output paths, and input-to-output paths. This application primarily addresses the register-to-register path scenario.

[0087] In one embodiment, during timing optimization, the timing margin of all timing paths on the clock tree is obtained, and the timing margins of all timing paths are compared to determine the timing path with the smallest timing margin as the timing path to be processed. Since this application addresses the case of register-to-register paths, the start and end points of the timing path to be processed must be registers.

[0088] It should be noted that the timing margin of a timing path on a clock tree refers to the timing margin throughout the entire path, from the output of data at the beginning of the path to the reception of data at the end of the path. This timing margin takes into account data delay, clock arrival time, clock skew, and register setup and hold times, and is not simply the data propagation delay.

[0089] Please refer to Figure 2 In one embodiment, starting with the timing path to be processed, timing optimization is performed on the timing path to be processed, specifically including the following steps.

[0090] Step S110: Determine the register to be processed.

[0091] In one embodiment, the start register in the timing path to be processed is used to characterize its time margin when providing data to subsequent combinational logic circuits. The end register in the timing path to be processed is used to characterize its time margin when receiving data from the preceding stage. By comparing the timing margins of the start and end registers in the timing path to be processed, the register with the smallest timing margin is determined as the register to be processed. Since the path segment corresponding to this register is most prone to timing violations and has the most limited timing margin, it is chosen as the register to be processed.

[0092] Step S120: Obtain the timing margin of the register to be processed and determine the target timing margin of the register to be processed.

[0093] In one embodiment, when the register to be processed only has a fan-out path and no fan-in path, there is no need to consider the timing margin changes of the fan-in path. Such a register is usually located at the beginning of the timing path, and its clock signal path only serves as the start path in the fan-out timing path to provide a synchronous trigger signal to the subsequent logic unit or register.

[0094] In one embodiment, since the register has only multiple fan-out paths, the timing paths of the multiple fan-out ends of the register can be calculated separately to reflect the differences in timing transmission between different fan-out paths.

[0095] In one embodiment, after obtaining multiple fan-out timing margins, the timing margins of each fan-out terminal are compared. Based on the comparison results, the fan-out timing margin corresponding to the fan-out timing path with the smallest timing margin can be used as the target fan-out timing margin.

[0096] In one embodiment, to avoid overly concentrated optimization directions due to selecting only a single minimum timing margin, multiple fan-out timing paths with smaller margins can be considered simultaneously. Specifically, multiple fan-out timing margins are arranged in ascending order of timing margin, and the top m fan-out timing margins from smallest to largest are selected for calculation. The target fan-out timing margin is then determined based on the average value, weighted value, or comprehensive evaluation result of these m fan-out timing margins, where m is a natural number.

[0097] In one embodiment, when the register to be processed only has a fan-in path and no fan-out path, there is no need to consider the timing margin changes of the fan-out path. Such a register is usually located at the end of the timing path, and its clock signal path is only used as the capture path of the fan-in timing path to receive and latch signals from the preceding register or logic unit.

[0098] In one embodiment, since the register has only multiple fan-in paths, after obtaining multiple fan-in timing margins, the timing margins of each fan-in path are compared to evaluate the degree to which their timing constraints are met. Based on the comparison results, the fan-in timing margin corresponding to the fan-in timing path with the smallest timing margin is selected as the target fan-in timing margin. This target fan-in timing margin represents the most timing-critical path among all fan-in paths of the register, and is the constraint path that most critically affects the register's setup or hold time. By calculating the clock offset value based on this target fan-in timing margin, priority compensation for critical timing paths can be achieved, thereby effectively avoiding the occurrence of timing violations.

[0099] In one embodiment, to balance the timing of multiple fan-in paths, multiple smaller fan-in timing margins can be considered simultaneously. Specifically, the multiple fan-in timing margins are arranged in ascending order of timing margin, and the top n fan-in timing margins are selected for calculation. The target fan-in timing margin is determined based on the average value, weighted value, or comprehensive evaluation result of these n fan-in timing margins, where n is a natural number.

[0100] In one embodiment, the register has both a fan-in path and a fan-out path. This type of register is both the terminator of the fan-in timing path and the start of the fan-out timing path. Its clock signal path serves as both the capture path for the fan-in path and the initiation path for the fan-out path, undertaking a complex role in timing propagation. In this case, the fan-in timing margin and fan-out timing margin of the register are calculated separately. The fan-in timing margin can be calculated by analyzing multiple fan-in paths and selecting the path with the smallest timing margin as the target fan-in timing margin, or by selecting the average, weighted value, or comprehensive evaluation result of the first n fan-in timing margins as the target fan-in timing margin. Similarly, the fan-out timing margin can be calculated by analyzing multiple fan-out paths and selecting the path with the smallest timing margin as the target fan-out timing margin, or by selecting the average, weighted value, or comprehensive evaluation result of the first m fan-in timing margins as the target fan-in timing margin.

[0101] Step S130: Calculate the clock offset based on the target timing margin of the register to be processed.

[0102] In one embodiment, during clock tree synthesis, clock skew refers to a local offset value applied to the register clock. Its core purpose is to guide the clock tree towards optimization for specific design goals. Clock skew can fine-tune local timing, resolving violations related to setup and hold times of specific registers, and meeting the specific timing requirements of critical paths. The core idea of ​​using clock skew to correct setup and hold time violations is as follows: When a setup time violation exists in the path containing the register to be processed, it means that the clock of the register to be processed arrives later than the data. In this case, a negative clock skew can be applied to the clock of the register to be processed, prompting the clock tree synthesis tool to accelerate it, making its clock signal arrive earlier, thereby correcting the setup time violation. When a hold time violation exists in the path containing the register to be processed, it means that the clock of the register to be processed arrives earlier than the data. In this case, a positive clock skew can be applied to the clock of the register to be processed, prompting the clock tree synthesis tool to delay it, making its clock signal arrive later, thereby correcting the hold time violation. However, the timing paths in actual circuits are widely and complexly distributed. Under the premise of the above basic strategy, specific analysis is required based on different situations. Therefore, when performing step S130 to calculate the clock offset based on the target timing margin of each register, it is necessary to process different registers separately.

[0103] Please refer to Figure 3 In one embodiment, Figure 3 From left to right, the registers are register 1, register 2, and register 3. Register 1 and register 2 form one timing path, register 2 and register 3 form another timing path, while register 1 and register 3 do not form a timing path. Therefore, in... Figure 3 In this scenario, within the timing path formed by registers 1 and 2, register 1, as the starting point of the timing path, only has fan-out timing margin. Register 2 is both the ending point of the timing path formed by registers 1 and 2 and the starting point of the timing path formed by registers 2 and 3; therefore, register 2 has both fan-in and fan-out timing margins. Register 3, however, is only the ending point of the timing path formed by registers 2 and 3; therefore, register 3 only has fan-in timing margin. When the register to be processed is register 2, it contains both fan-in and fan-out timing margins; this type of register is defined as the first register.

[0104] Please refer to Figure 4 In one embodiment, calculating the clock offset for the first register includes the following steps.

[0105] Step S1311: Obtain the target fan-in timing margin and the target fan-out timing margin of the first register.

[0106] Step S1312: Calculate the clock offset of the first register based on the target fan-in timing margin and the target fan-out timing margin of the first register.

[0107] In one embodiment, for each first register, the target fan-in timing margin and target fan-out timing margin corresponding to that register are first obtained. The target fan-in timing margin reflects the timing state of the first register when capturing the output data of the preceding register, and the target fan-out timing margin reflects the timing state when the first register outputs data to the subsequent register. The clock offset of the register is calculated based on the target fan-in timing margin and the target fan-out timing margin. This clock offset indicates the degree of advance or delay adjustment of the register's clock signal within a local range, thereby improving the timing margin distribution of the register under different paths.

[0108] Specifically, when the timing margin of the target fan-in terminal of the first register is greater than 0 and the timing margin of the target fan-out terminal is less than 0, it indicates that there is a timing violation in the fan-out path, while the fan-in path still has a certain timing margin. In this case, the timing margin difference is determined by subtracting the timing margin of the target fan-in terminal of the first register from the timing margin of the target fan-out terminal. A first preset proportion of this timing margin difference is used as the clock offset of the register. A negative clock offset indicates that the clock arrival time of the register should be adjusted by the circuit, i.e., a negative offset should be made to cause the start clock of the fan-out path to arrive earlier. This allows the fan-in path to relinquish some timing margin to the fan-out path, thus reducing the timing margin of each fan-in terminal and increasing the timing margin of each fan-out terminal in the first register, thereby correcting the timing violation in the subsequent stage.

[0109] When the timing margin at the target fan-in end of the first register is less than 0 and the timing margin at the target fan-out end is greater than 0, it indicates that there is a timing violation in the fan-in path, while the fan-out path still has a certain timing margin. In this case, the timing margin difference is determined by subtracting the timing margin at the target fan-out end of the first register from the timing margin at the target fan-in end. A second preset proportion of this timing margin difference is used as the clock offset for that register. A positive clock offset indicates that the clock arrival time of the delay register should be adjusted by the circuit, i.e., a positive offset should be made so that the fan-out path relinquishes some timing margin to the fan-in path. This means that the timing margins at each fan-out end of the first register decrease, and the timing margins at each fan-in end increase, thereby correcting the timing violation in the preceding stage.

[0110] It should be noted that the negative offset is used to advance the clock arrival time of the register to speed up the startup path clock, thereby improving the timing of the subsequent fan-out path; the positive offset is used to delay the clock arrival time of the register to relax the capture path clock, thereby improving the timing of the preceding fan-in path.

[0111] In one embodiment, when the timing margin of the target fan-in terminal of the first register is less than 0, and the timing margin of the target fan-out terminal of the first register is also less than 0, it indicates that there are timing violations in both the fan-in and fan-out paths of the register. For this complex scenario where timing problems exist at both ends, the timing margin difference is first determined by subtracting the timing margin of the target fan-out terminal of the first register from the timing margin of the target fan-in terminal. A third preset ratio of the timing margin difference is determined as the clock offset of the first register. Based on this clock offset, the timing margins at each end corresponding to the smaller timing margin between the target fan-in and target fan-out terminal timing margins are adjusted, so that a portion of the timing margin is appropriately transferred to the other end in the timing space; that is, the timing margin at the smaller end is increased, and the timing margin at the larger end is decreased.

[0112] For example, if the timing margin of the target fan-in terminal of the first register is less than 0, and the timing margin of the target fan-out terminal of the first register is also less than 0, the timing margin of the target fan-in terminal is even smaller. In this case, the timing margin of each fan-in terminal of the first register is increased, and the timing margin of each fan-out terminal is decreased.

[0113] It should be noted that when both ends have negative timing margins, it means that neither path can meet timing constraints. In this case, simply adjusting the clock delay on either side will exacerbate violations on the other side. Therefore, when calculating the clock offset, the relative magnitudes of the timing margins at the fan-in and fan-out ends are considered. By appropriately allocating the positive and negative directions and magnitudes of the offset, the end with the worse timing margin appropriately relinquishes some timing space to the other end, achieving dynamic amortization of violation risk between the two paths.

[0114] This adjustment mechanism can balance the timing of the two paths to the maximum extent when timing violations exist at both the fan-in and fan-out ends, making the overall timing distribution more balanced and stable. It avoids the problem that repairing one end will cause deterioration at the other end, thereby improving the timing robustness and optimization efficiency of the circuit under complex boundary conditions.

[0115] It is also important to emphasize that the clock offset for the register is calculated based on the target fan-in timing margin and / or the target fan-out timing margin. Applying the clock offset to the clock input of the register will have a synchronous effect on all fan-in timing paths or all fan-out timing paths corresponding to that register, rather than adjusting only a single path.

[0116] In one embodiment, the first preset ratio, the second preset ratio, and the third preset ratio can be the same, or they can be set to different values ​​according to different timing optimization scenarios. Specifically, when the circuit structure is relatively balanced or the timing variation is small, the same ratio coefficient can be used to simplify the calculation process; while when there are many timing paths and the timing difference between the fan-in and fan-out ends is significant, different ratios can be set according to the timing characteristics of each path to achieve more refined clock offset control.

[0117] This application takes setting the first preset ratio, the second preset ratio, and the third preset ratio to the same value as an example, and calculates the clock offset using the following formula:

[0118]

[0119] Where offset represents the clock offset, dSlack represents the target fan-in timing margin, qSlack represents the target fan-out timing margin, and 0.5 represents the first preset ratio, the second preset ratio, and the third preset ratio.

[0120] Please refer to Figure 5 In one embodiment, the following is used: Figure 3 Register 1 and Register 2 are shown separately in the diagram. When the register to be processed is Register 1, it only contains the fan-out timing margin. In this case, the register to be processed is defined as the second register.

[0121] Please refer to Figure 6 In one embodiment, calculating the clock offset for the second register includes the following steps.

[0122] Step S1321: Obtain the timing margin of the target fan-out terminal of the second register.

[0123] Step S1322: Determine the clock offset of the second register based on the timing margin of the target fan-out terminal of the second register.

[0124] In one embodiment, when the timing margin of the target fan-out terminal of the register is detected to be greater than 0, it indicates that there is no timing violation in the fan-out path corresponding to the register. In this case, no offset needs to be applied to the clock signal, and the system can maintain its current timing state. When the timing margin of the target fan-out terminal of the register is detected to be less than 0, it indicates that a timing violation has occurred in the fan-out path of the register, and the normal setup time requirement cannot be met. In this case, the clock offset of the second register is determined based on the timing margin of the target fan-out terminal of the second register, specifically using the following formula:

[0125]

[0126] Where offset represents the clock offset, dSlack represents the timing margin at the target fan-in end, and qSlack represents the timing margin at the target fan-out end.

[0127] The clock offset calculated using this formula is negative. By applying a negative offset to the clock path, the clock signal in the circuit arrives at the second register earlier, thereby shortening the start time in the timing path. In other words, it increases the timing margin of each fan-out terminal of the second register, thus prompting the timing violation to be corrected.

[0128] It should be noted that when the timing margin of the target fan-out terminal of the second register is less than 0, the second register needs to receive the clock earlier. This can be achieved by adjusting the wiring length of the clock tree or changing the insertion method of the registers in the clock tree.

[0129] Please refer to Figure 7 In one embodiment, the following is used: Figure 3 Registers 2 and 3 are shown separately in the diagram. When the register to be processed is register 3, it only contains the fan-in timing margin. In this case, the register to be processed is defined as the third register.

[0130] Please refer to Figure 8 In one embodiment, calculating the clock offset for the third register includes the following steps.

[0131] Step S1331: Obtain the timing margin of the target fan-in terminal of the third register.

[0132] Step S1332: Determine the clock offset of the third register based on the timing margin of the target fan-in terminal of the third register.

[0133] In one embodiment, when the target fan-in timing margin of the third register is greater than 0, it indicates that there is no timing violation in the fan-in timing path, and the register has sufficient timing margin when capturing the signal. Therefore, there is no need to adjust the clock delay of the register through clock offset, and the system can maintain the current timing state. When the target fan-in timing margin of the third register is less than 0, it indicates that a timing violation has occurred in the fan-in timing path, and the signal cannot be stably captured within the specified setup time. In this case, the clock offset of the third register is determined based on the target fan-in timing margin of the third register, specifically using the following formula:

[0134]

[0135] Where offset represents the clock offset, dSlack represents the timing margin at the target fan-in end, and qSlack represents the timing margin at the target fan-out end.

[0136] The clock offset calculated using this formula is positive. By applying a positive offset to the clock path, the clock signal of the third register is delayed, thereby extending the hold time in the timing path. In other words, the timing margin of each fan-in terminal of the third register is increased, reducing the problem of insufficient setup time caused by the clock arriving too early.

[0137] It should be noted that when the timing margin of the target fan-in terminal of the third register is less than 0, the third register needs to receive the clock later. This can also be achieved by adjusting the wiring length of the clock tree or changing the insertion method of the registers in the clock tree.

[0138] Step S140: Adjust the register to be processed according to the clock offset of the register to be processed.

[0139] In one embodiment, after the clock offset of the register to be processed is determined in step S130, it has been clearly explained how to adjust the register to be processed according to the clock offset of the register to be processed, so it will not be repeated here.

[0140] It should be noted that when the register is a terminal register not located in any timing path, the register's clock delay is neither considered as the start path nor the capture path. In other words, the register's clock signal will not affect the timing setup or hold processes of other registers or logic units; therefore, the register does not participate in the timing path constraint calculation. In this case, even if the register itself has a certain clock delay variation, it will not cause any timing violations or affect the timing characteristics of the circuit. Since the clock delay of this type of register is not involved in the start and capture behavior of the timing path, it is not necessary to calculate its clock offset or adjust its clock delay during timing optimization.

[0141] Step S200: Update the timing path to be processed and perform timing optimization.

[0142] In one embodiment, after completing a timing optimization of the timing path to be processed, the timing margins of all timing paths in the clock tree are retrieved again, and the timing margins of each timing path are rearranged. The timing path with the smallest timing margin among all timing paths is updated as the timing path to be processed, and steps S110-S140 are executed again to optimize the timing path to be processed. This process is repeated until the timing margin of the timing path to be processed after optimization reaches a set value, or the number of times the timing path to be processed in the clock tree has been optimized reaches a set number. In either of these cases, timing optimization of the clock tree is stopped.

[0143] In summary, this application calculates the clock offset based on the timing margin of the clock tree registers, thereby affecting the clock delay time of the registers and optimizing the timing margin of the register timing path, ultimately achieving the goal of optimizing the clock tree timing. The clock offset is a local offset value applied to the terminal node of a single clock tree, used to affect the clock delay time and resolve setup and hold time violations of specific registers. During clock tree synthesis, the adjustment of the register timing offset depends on its position in the timing path and the timing margin of that path. After the clock offset is set, the circuit immediately makes adjustments, modifying the size and position of logic gates, changing the number of buffers in the circuit, etc., to adjust the register clock delay. The change in register clock delay further optimizes the timing margin of the fan-in and fan-out paths, ultimately achieving the goal of optimizing the overall clock tree timing.

[0144] During clock tree synthesis, various complex timing paths exist in the circuit. This application starts with the first, second, and third registers, decoupling the fan-in and fan-out timing paths of each register, selecting the target timing path, classifying the timing margins of the fan-in and fan-out terminals, and calculating a reasonable clock offset. This simplifies complex problems and can accurately and quickly handle timing violations in the circuit.

[0145] The clock tree timing optimization method proposed in this application dynamically adjusts the timing offset of the terminal registers during clock tree synthesis, guiding the clock tree synthesis tool to achieve the desired delay or skew characteristics. Dynamically inserting offsets with specific timing relationships into the terminal devices can solve specific timing problems, balance the relationships between different clock domains, overcome the limitations of the default optimization behavior of clock tree synthesis tools, and improve the overall circuit efficiency and performance.

[0146] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0147] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A timing optimization method for clock trees, characterized in that, include: Obtain the timing margin of all timing paths on the clock tree, and determine the timing path with the smallest timing margin among all timing paths as the timing path to be processed. The timing path to be processed includes a start register and a stop register. Starting from the timing path to be processed, timing optimization is performed on the timing path to be processed, and the timing optimization includes: The timing margin of the starting register in the timing path to be processed is compared with the timing margin of the ending register in the timing path to be processed, so as to determine the register with the smallest timing margin as the register to be processed. Obtain multiple fan-in timing margins of the register to be processed, and determine the target fan-in timing margin based on the multiple fan-in timing margins of the register to be processed. Obtain multiple fan-out timing margins of the register to be processed, and determine the target fan-out timing margin based on the multiple fan-out timing margins of the register to be processed. Calculate the clock offset based on the target fan-in timing margin and / or the target fan-out timing margin; Adjust the timing margins of each fan-in terminal and / or each fan-out terminal of the register to be processed according to the clock offset to complete the timing optimization of the timing path to be processed. Reacquire the timing margins of all timing paths on the clock tree, and update the timing path with the smallest timing margin among all timing paths as the timing path to be processed, so as to perform the timing optimization, until the set termination condition is reached.

2. The timing optimization method for clock trees as described in claim 1, characterized in that, Determining the target fan-in timing margin based on the multiple fan-in timing margins of the register to be processed includes: The timing margins of multiple fan-in terminals of the register to be processed are compared; The smallest fan-in timing margin among the plurality of fan-in timing margins is determined as the target fan-in timing margin. Determining the target fan-out timing margin based on the multiple fan-out timing margins of the register to be processed includes: The timing margins of multiple fan-out terminals of the register to be processed are compared; The smallest fan-out timing margin among the plurality of fan-out timing margins is determined as the target fan-out timing margin.

3. The timing optimization method for clock trees as described in claim 1, characterized in that, Determining the target fan-in timing margin based on the multiple fan-in timing margins of the register to be processed includes: The timing margins of multiple fan-in terminals of the register to be processed are compared; The multiple fan-in timing margins are arranged in ascending order of timing margin. The target fan-in timing margin is determined based on the first n fan-in timing margins in ascending order, where n is a natural number. Determining the target fan-out timing margin based on the multiple fan-out timing margins of the register to be processed includes: The timing margins of multiple fan-out terminals of the register to be processed are compared; The multiple fan-out timing margins are arranged in ascending order of timing margin. The target fan-out timing margin is determined based on the first m fan-out timing margins in ascending order, where m is a natural number.

4. The timing optimization method for clock trees as described in claim 1, characterized in that, When the register to be processed is a first register that simultaneously contains fan-in timing margin and fan-out timing margin, the target fan-in timing margin and the target fan-out timing margin of the first register are obtained. Calculate the clock offset of the first register based on the target fan-in timing margin and the target fan-out timing margin of the first register. Adjust the timing margins of each fan-in terminal and each fan-out terminal of the first register according to the clock offset of the first register.

5. The timing optimization method for clock trees as described in claim 4, characterized in that, The step of calculating the clock offset of the first register based on the target fan-in timing margin and the target fan-out timing margin of the first register includes: When the timing margin of the target fan-in terminal of the first register is greater than 0 and the timing margin of the target fan-out terminal of the first register is less than 0, calculate the timing margin difference between the timing margin of the target fan-out terminal of the first register and the timing margin of the target fan-in terminal of the first register. The first preset ratio of the timing margin difference is the clock offset of the first register; When the timing margin of the target fan-in terminal of the first register is less than 0 and the timing margin of the target fan-out terminal of the first register is greater than 0, calculate the timing margin difference between the timing margin of the target fan-out terminal of the first register and the timing margin of the target fan-in terminal of the first register. The second preset ratio of the timing margin difference is the clock offset of the first register; When the timing margin of the target fan-in terminal of the first register is less than 0 and the timing margin of the target fan-out terminal of the first register is less than 0, calculate the timing margin difference between the timing margin of the target fan-out terminal of the first register and the timing margin of the target fan-in terminal of the first register. The third preset ratio of the timing margin difference is the clock offset of the first register.

6. The timing optimization method for clock trees as described in claim 5, characterized in that, The step of adjusting the timing margins of each fan-in terminal and each fan-out terminal of the first register according to the clock offset of the first register includes: When the timing margin of the target fan-in terminal of the first register is greater than 0 and the timing margin of the target fan-out terminal of the first register is less than 0, the timing margins of each fan-in terminal and each fan-out terminal of the first register are adjusted according to the clock offset of the first register, so that the timing margins of each fan-in terminal of the first register decrease and the timing margins of each fan-out terminal of the first register increase. When the timing margin of the target fan-in terminal of the first register is less than 0 and the timing margin of the target fan-out terminal of the first register is greater than 0, the timing margins of each fan-in terminal and each fan-out terminal of the first register are adjusted according to the clock offset of the first register, so that the timing margin of each fan-out terminal of the first register decreases and the timing margin of each fan-in terminal of the first register increases. When the timing margin of the target fan-in terminal of the first register is less than 0 and the timing margin of the target fan-out terminal of the first register is less than 0, the timing margins of each fan-in terminal and each fan-out terminal of the first register are adjusted according to the clock offset of the first register, so that the timing margins of each terminal corresponding to the smaller timing margin of the target fan-in terminal timing margin and the target fan-out terminal timing margin in the first register are increased, and the timing margins of the other terminal are decreased.

7. The timing optimization method for clock trees as described in claim 1, characterized in that, When the register to be processed is a second register that only contains fan-out timing margin, obtain the target fan-out timing margin of the second register; When the timing margin of the target fan-out terminal of the second register is less than 0, the clock offset of the second register is determined according to the timing margin of the target fan-out terminal of the second register. Adjust the timing margin of each fan-out terminal of the second register according to the clock offset of the second register, so as to increase the timing margin of each fan-out terminal of the second register.

8. The timing optimization method for clock trees as described in claim 1, characterized in that, When the register to be processed is a third register that only contains fan-in timing margin, obtain the target fan-in timing margin of the third register; When the timing margin of the target fan-in terminal of the third register is less than 0, the clock offset of the third register is determined according to the timing margin of the target fan-in terminal of the third register. Adjust the timing margin of each fan-in terminal of the third register according to the clock offset of the third register, so as to increase the timing margin of each fan-in terminal of the third register.

9. The timing optimization method for clock trees as described in claim 1, characterized in that, The set termination conditions include the timing margin of the updated timing path to be processed reaching a set value, or the number of times the timing path to be processed is timed to be optimized reaching a set number.

10. A computer-readable storage medium, characterized in that, The medium stores a computer program that can be executed by a processor to implement the method as described in any one of claims 1-9.

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