Laminated solar cell with stress buffer composite layer and preparation method thereof

Abstract

The invention belongs to the technical field of solar cells, and particularly relates to a laminated solar cell with a stress buffer composite layer and a preparation method of the laminated solar cell. The laminated solar cell comprises a crystalline silicon cell unit, a perovskite cell unit and a composite layer, the composite layer is located between the crystalline silicon cell unit and the perovskite cell unit; particularly, the composite layer comprises FTO particles and nanocrystalline silicon, the FTO particles are distributed on the surface of the crystalline silicon cell unit, and the nanocrystalline silicon is filled among the FTO particles and electrically connected with the FTO particles and the crystalline silicon cell unit. According to the composite layer, the FTO particles and the nanocrystalline silicon form a three-dimensional nested structure, interface stress concentration caused by the difference of thermal expansion coefficients between the nanocrystalline silicon and the perovskite material is relieved, the failure risks of layering, cracking and the like are reduced, and the mechanical reliability and the photoelectric property of a device are improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of solar cells, and particularly relates to a laminated solar cell with a stress buffer composite layer and a preparation method thereof. BACKGROUND

[0002] With the development of photovoltaic technology, laminated solar cells have become an important development direction for improving the photoelectric conversion efficiency of photovoltaic devices due to their ability to break through the limitations of single light absorption layer band gap and achieve multi-spectrum efficient utilization. Among them, the heterojunction structure represented by perovskite / silicon laminated solar cells has become a hot spot in current research and industry due to its high efficiency and low cost potential.

[0003] Perovskite / silicon laminated solar cells usually adopt a two-terminal or three-terminal structure, in which the silicon cell unit serves as the bottom cell and the perovskite cell unit serves as the top cell. In order to realize electrical coupling and optical coordination between the two sub-cells, a composite interlayer must be introduced between them. The composite layer not only bears the functions of charge selective transmission, energy band matching and interface passivation, but also needs to consider light transmittance, thermal stability and preparation compatibility, and is one of the key structures for realizing high-performance laminated devices.

[0004] However, due to the significant differences in physical properties (such as thermal expansion coefficient, electrical conductivity, preparation temperature, etc.) between perovskite materials and silicon, thermal stress or structural stress mismatch often occurs at the interface of the composite layer during the construction of the laminated structure, which leads to problems such as interface cracking, enhanced carrier recombination or decreased device stability.

[0005] In the prior art, some schemes attempt to use oxide transparent conductive films (such as ITO, SnO2, IZO, etc.) as composite layer materials, which have certain advantages in electrical performance, but due to their high brittleness and poor flexibility, they are prone to stress concentration during subsequent high-temperature annealing or laminated pressing, affecting the overall performance. Therefore, there is an urgent need for a composite interlayer structure and its construction method that has good interface electrical compatibility and can buffer stress gradient, suitable for perovskite / silicon laminated structure, to realize efficient and stable laminated solar cell devices. SUMMARY

[0006] To solve the above problems, the application provides a laminated solar cell with a stress buffer composite layer, which comprises a crystalline silicon cell unit, a perovskite cell unit and a composite layer; the composite layer is located between the crystalline silicon cell unit and the perovskite cell unit; in particular, the composite layer comprises FTO (fluorine-doped tin oxide) particles and nanocrystalline silicon, the FTO particles are distributed on the surface of the crystalline silicon cell unit, and the nanocrystalline silicon is filled between the FTO particles and electrically connected with the FTO particles and the crystalline silicon cell unit.

[0007] The application forms a three-dimensional nested structure with stress buffering capability by setting a composite layer composed of FTO particles and nanocrystalline silicon between the crystalline silicon cell unit and the perovskite cell unit, and relieves the interface stress concentration problem caused by the difference in the coefficient of thermal expansion between different materials. The FTO particles are attached to the surface of the crystalline silicon cell in a discrete form and exhibit a certain flexibility and deformability in the nanometer scale; and the nanocrystalline silicon is filled between the FTO particles, which not only realizes electrical bridging between the particles, but also provides a certain strain buffer zone for thermal stress release. Compared with the traditional continuous film layer structure, the composite layer of the application has better interface matching and structural flexibility, thereby improving the stability and long-term reliability of the laminated solar cell structure during thermal cycling or packaging.

[0008] Further, the crystalline silicon cell unit is any one of PERC, TOPCon or HJT structure. The three types of crystalline silicon cell units all belong to high-efficiency single-crystalline silicon cell types, and respectively adopt back surface passivation (PERC), tunnel oxide passivation contact (TOPCon) and heterojunction structure (HJT) to improve the carrier passivation efficiency and conversion performance. When the perovskite cell unit is laminated to construct a heterojunction device, although there are differences in structural details and process temperature among the three, due to the essential differences in the coefficient of thermal expansion, film stress response and interface mechanical properties of the crystalline silicon and perovskite materials, stress mismatch problems may be caused during the lamination process, which are manifested as interface peeling, cracking, performance degradation and other unstable phenomena. Therefore, regardless of which type of crystalline silicon cell unit is used, a composite intermediate layer structure with stress buffering capability needs to be introduced to realize stable coupling of the device structure and function.

[0009] Further, the perovskite battery cell includes a perovskite light-absorbing layer, a hole transport layer, and an electron transport layer, the electron transport layer covering the composite layer, ensuring that photo-generated electrons can be efficiently injected from the perovskite light-absorbing layer to the bottom crystalline silicon battery cell through the electron transport layer, and realizing barrier-free transfer of electric charges through the composite layer. Since the composite layer is connected to the front surface emission layer of the crystalline silicon battery, and the electrons in the perovskite battery flow from the light-absorbing layer to the bottom electrode, it is necessary to first form a good ohmic contact relationship between the electron transport layer and the composite layer to establish an electron channel. If the hole transport layer or the perovskite layer is directly in contact with the composite layer, the loss of carrier selectivity and the enhancement of interface recombination will seriously affect the efficiency and stability of the device. Therefore, the structure of the electron transport layer covering the composite layer is a necessary design to achieve efficient charge separation, minimize band mismatch, and minimize interface recombination.

[0010] Further, the FTO particles are spherical or spherical-like, and the diameter of the FTO particles is 50-100 nanometers, which is conducive to forming a regular and uniformly distributed conductive microstructure array on the surface of the crystalline silicon battery. On the one hand, the spherical or spherical-like morphology can reduce the mechanical stress concentration between the particles, enhance the structural flexibility and strain release capability of the composite layer; on the other hand, the size range of 50-100 nanometers balances the optical transparency and electrical conductivity, which can provide sufficient charge transport paths without significantly blocking the transmitted light, ensuring the light incidence efficiency of the perovskite absorption layer. At the same time, the gap between particles of this size level facilitates the filling of nanocrystalline silicon, forming a dense and continuous composite interface, further optimizing the interface electrical performance and mechanical stability, and improving the overall efficiency and durability of the stacked battery.

[0011] Further, the nanocrystalline silicon is intrinsic or n-type doped, and the size of the nanocrystalline silicon is less than 20 nanometers, which helps to form a dense and continuous conductive channel between the FTO particles, enhancing the charge transport efficiency of the composite layer. The smaller size of the nanocrystalline silicon has a higher specific surface area and better interface adhesion, which can fully fill the micro-gaps between the FTO particles, forming a low interface resistance electrical bridging structure. At the same time, small-size grains have higher structural flexibility and fracture toughness under thermal stress, which helps to alleviate the stress concentration caused by the difference in thermal expansion between the perovskite and the crystalline silicon. In addition, n-type doping can improve the electron mobility of the nanocrystalline silicon, further optimizing the injection process of electrons from the perovskite battery to the crystalline silicon battery, thereby improving the electrical performance and interface stability of the overall stacked device.

[0012] Further, the overall thickness of the composite layer is less than 200 nanometers, which helps to balance the optical transmittance, charge transport efficiency and mechanical stability of the device. On the one hand, the thinner composite layer can significantly reduce the shielding of incident light on the perovskite battery, maximize the light intensity of the bottom crystalline silicon battery, and avoid light loss. On the other hand, the thin layer structure is conducive to the rapid transport of charge carriers in the composite layer, reduces the series resistance, and improves the fill factor and power conversion efficiency of the device. In addition, the residual stress introduced by the thinner composite layer during material thermal expansion and mechanical strain is smaller, which can reduce the risk of delamination, cracking and other failures, thereby enhancing the structural stability and long-term reliability of the stacked solar cell.

[0013] On the other hand, the present application provides a preparation method of a stacked solar cell with a stress buffering composite layer, comprising the following steps: Step 1: Forming FTO particles on the surface of the crystalline silicon cell unit; Step 2: Depositing nanocrystalline silicon in the gap between the FTO particles; Step 3: Building a perovskite cell unit on the composite layer.

[0014] The step-by-step construction strategy of the present application avoids stress concentration and interface warping caused by direct deposition of a continuous film layer, which is conducive to local release and adjustment of inter-particle stress. In addition, the method is suitable for low-temperature process preparation, has strong material compatibility and process universality, and improves the preparation yield, interface stability and device performance of the stacked structure.

[0015] Further, in step 1, a spray pyrolysis process is used to deposit FTO particles on the surface of the crystalline silicon cell unit and form island-like distribution after heat treatment, which has significant advantages in structure regulation and process compatibility. Spray pyrolysis can accurately control the particle size, distribution density and morphology, so as to construct a discrete and uniform FTO particle array without forming a continuous film layer, and form a three-dimensional microstructure with local conductivity and stress buffering capacity. The island-like distributed FTO particles enhance the bonding force with the crystalline silicon surface after heat treatment, while retaining the inter-particle gap, which is beneficial for subsequent filling and interface transition of nanocrystalline silicon, improves the structural stability of the composite layer, optimizes the charge transport path, helps to reduce the interface stress, reduces the generation of defects, and improves the overall performance and reliability of the stacked battery.

[0016] Furthermore, in step 2, nanocrystalline silicon is deposited between FTO particles using the PECVD method, which offers excellent film formation controllability and interface compatibility. The PECVD process enables in-situ deposition of high-quality nanocrystalline silicon at relatively low temperatures, avoiding thermal damage to the crystalline silicon battery substrate and the FTO particle structure. Simultaneously, the size, doping type, and deposition rate of the nanocrystalline silicon can be precisely controlled by adjusting gas flow rate, power, and time, ensuring it fully fills the gaps between FTO particles to form dense and continuous conductive channels. This method also improves the interfacial bonding between nanocrystalline silicon and FTO particles, as well as between nanocrystalline silicon battery cells, reducing interfacial resistance and carrier recombination, and enhancing the electrical performance and mechanical stability of the composite layer, thereby improving the overall efficiency and fabrication process consistency of the tandem battery.

[0017] Furthermore, following step 2, plasma surface treatment is performed to improve the physicochemical properties of the composite layer surface, providing excellent interfacial conditions for the subsequent deposition of perovskite solar cell units. Plasma treatment can remove organic residues and weakly bound groups from the nanocrystalline silicon surface, improving surface cleanliness and bandgap consistency. Simultaneously, it can introduce active groups or modulate surface energy, enhancing the wettability of the perovskite precursor to the composite layer and improving film uniformity. In addition, plasma treatment can adjust surface roughness at the nanoscale, promoting mechanical bonding and charge injection efficiency between upper and lower layers, thereby further reducing interfacial defect density and resistance, and improving the photoelectric performance and long-term stability of the tandem solar cell.

[0018] The beneficial effects of this invention are: (1) The composite layer of the present invention is composed of FTO particles and nanocrystalline silicon in a three-dimensional nested structure, which alleviates the interface stress concentration caused by the difference in thermal expansion coefficient between crystalline silicon and perovskite material, reduces the risk of failure such as delamination and cracking, and improves the mechanical reliability of the device.

[0019] (2) In this invention, nanocrystalline silicon is filled between FTO particles to form a continuous conductive channel, thereby achieving efficient charge bridging between the upper and lower cells, reducing interface resistance, improving carrier transport efficiency, and enhancing the overall photoelectric performance of the tandem cell.

[0020] (3) The overall thickness of the composite layer of the present invention is less than 200nm, and the FTO particle size is controlled at 50–100nm, which is conducive to maximizing the light transmission through the perovskite layer to the bottom crystalline silicon cell, avoiding light loss due to shading, and increasing the short-circuit current density.

[0021] (4) The composite layer of the present invention is applicable to various types of crystalline silicon cell structures such as PERC, TOPCon, and HJT, and has good material and process compatibility, making it easy to promote to different stacked cell process systems.

[0022] (5) The present invention adopts mature and controllable preparation processes such as spray pyrolysis, PECVD, and plasma treatment, which facilitates precise control of the structural parameters of each layer, and is conducive to improving the preparation yield and batch consistency, thus meeting the needs of large-scale industrialization.

[0023] Based on the above beneficial effects, this invention has good application prospects in the field of tandem solar cell technology. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a stacked solar cell with a stress-buffered composite layer.

[0025] In the figure: 1. Crystalline silicon solar cell; 2. Perovskite solar cell; 3. Composite layer; 31. FTO particles; 32. Nanocrystalline silicon. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.

[0027] Example 1 This embodiment provides a stacked solar cell with a stress-buffered composite layer, such as Figure 1 As shown, it includes a crystalline silicon solar cell unit 1, a composite layer 3, and a perovskite solar cell unit 2 stacked sequentially.

[0028] The crystalline silicon solar cell 1 adopts a PERC (Passivated Emitter and Rear Cell) structure. The PERC cell includes a phosphorus-doped front emitter, a passivation layer on the back, and an aluminum back electrode. The cell thickness is approximately 180 micrometers, and the surface has a textured structure to enhance light capture efficiency. The top region of the PERC cell is either exposed or partially texturized and polished to provide a compatible interface for the formation of composite layer 3.

[0029] Composite layer 3 is disposed between the top surface of crystalline silicon cell 1 and the bottom of perovskite cell 2, serving to electrically connect the two sub-cells and buffer interfacial stress caused by differences in thermal expansion coefficients. Composite layer 3 has a two-component structure, including FTO particles 31 and nanocrystalline silicon 32. FTO particles 31 are spherical or near-spherical microstructured particles with a size of 50-100 nm, dispersed on the surface of crystalline silicon cell 1 in an island-like arrangement, forming interparticle gaps. FTO has good transparency, conductivity, and thermal stability, enabling electron extraction and providing a supporting framework for the intercalation structure. Nanocrystalline silicon 32 fills the gap regions between FTO particles 31, forming continuous electron channels with FTO particles 31 and the crystalline silicon substrate. Nanocrystalline silicon 32 is intrinsically or n-type doped, with a particle size of less than 20 nm, exhibiting excellent interfacial affinity and conductivity. By precisely controlling the thickness (overall composite layer 3 less than 200 nm), excellent electrical connectivity is maintained while mitigating the interfacial stress concentration effect in the vertical direction.

[0030] The perovskite solar cell unit 2 is disposed above the composite layer 3, forming a top-cell structure. It primarily absorbs short-wavelength spectra, improving the overall spectral utilization efficiency of the stack. The perovskite solar cell unit 2 sequentially comprises an electron transport layer, a perovskite light-absorbing layer, and a hole transport layer, with the electron transport layer directly deposited on top of the composite layer 3. Preferably, a FA (Fabry-Perovskite) structure is adopted. 0.9 MA 0.1 PbI3 (ABX3 type) perovskite material has good crystal quality and photogenerated charge transport characteristics. The electron transport layer (preferably SnO2) is in direct contact with the composite layer to ensure rapid electron injection; the hole transport layer (preferably PTAA) is located on the top layer and is connected to the top transparent electrode to form a closed circuit loop.

[0031] In this embodiment, the synergistic structure of FTO particles 31 and nanocrystalline silicon 32 in composite layer 3 achieves charge bridging while guiding and mitigating stress concentration caused by thermal cycling and humid environments, thereby improving the interface stability and device reliability of the stacked structure. Furthermore, this structure ensures electron selective extraction, recombination rate control, and vertical conductivity continuity without significantly increasing process complexity, providing a feasible solution for the industrial realization of high-efficiency and stable stacked solar cells.

[0032] Preferably, this invention proposes a "coarse-fine nested structure" composite layer 3 construction scheme. Before depositing nanocrystalline silicon 32, large-particle silicon filler (such as microcrystalline silicon or spherical silicon nanoclusters with a particle size of 50–80 nm) is deposited between FTO particles 31 using low-temperature CVD or spraying methods to initially fill the large gaps between FTO particles 31, constructing a coarse-particle support network. Subsequently, small-sized nanocrystalline silicon 32 with a particle size of less than 20 nm is deposited using PECVD to fill the fine gaps between the coarse particles and between them and the FTO, achieving a dual-scale interlayer structure of "coarse skeleton + fine filler" within the composite layer 3. This multi-level filling strategy improves the density and structural uniformity of the composite layer 3. The rigid framework formed by large particles provides mechanical support, while the small-particle silicon enhances interfacial contact and electrical connectivity. Together, they reduce the risk of interfacial voids and microcracks, alleviate stress concentration, and optimize the electron injection path, improving charge transport efficiency and overall device stability.

[0033] Example 2 Compared to Example 1, the crystalline silicon solar cell 1 in Example 2 is replaced with a TOPCon structure instead of a PERC structure. The main differences lie in the front surface material and the overall band structure. TOPCon cells are typically covered with SiN... X Alternatively, a SiO2 passivation film may be used. To ensure good adhesion of FTO particles 31 and achieve electron channel connectivity, the passivation layer needs to be removed or partially opened before depositing the FTO particles using plasma etching or dilute hydrofluoric acid treatment. This allows the FTO particles 31 to directly contact the n-type silicon emitter layer, thereby achieving a stable electrical connection. On the other hand, since TOPCon has a higher open-circuit voltage, the nanocrystalline silicon 32 in the composite layer 3 needs to have its doping concentration and deposition temperature optimized to form a matching bandgap with the FTO particles 31 and the n-type silicon, reducing the interface barrier. Simultaneously, to avoid deformation or performance degradation of the TOPCon backside structure during heating, the deposition temperature of the composite layer 3 should be controlled below 200°C, using a low-temperature PECVD process to ensure structural integrity. In summary, Example 2 requires specialized design for the TOPCon battery surface passivation structure, charge extraction path, and thermal stability, so that the composite layer 3 maintains stress buffering capacity while achieving efficient electron transport.

[0034] Example 3 In specific embodiment 3, the crystalline silicon solar cell adopts an HJT (heterojunction) structure, whose front surface typically includes an ITO transparent conductive film and an intrinsic / doped amorphous silicon passivation layer. To avoid disrupting the passivation structure and high open-circuit voltage advantage of the HJT, this embodiment directly constructs a composite layer 3 on the ITO film surface of the HJT cell. First, spherical or near-spherical FTO particles 31 with a diameter of 50-100 nm are deposited on the ITO surface using a spray pyrolysis method, forming an island-like distribution and constructing an interface structure with a thermal expansion buffer space. Subsequently, PECVD is used to fill the gaps between the FTO particles 31 with n-type or intrinsic nanocrystalline silicon 32 with a particle size of less than 20 nm, forming a continuous conductive network to achieve electronic coupling between the upper and lower solar cells. The entire composite layer 3 has a thickness of less than 200 nm, balancing charge extraction efficiency and mechanical flexibility, alleviating the thermal expansion mismatch problem between the HJT cell and the perovskite cell, and improving the structural stability and long-term operational reliability of the stacked device.

[0035] Example 4 This embodiment provides a method for fabricating a tandem solar cell with a stress-buffered composite layer. The crystalline silicon cell unit 1 is of the PERC type, and the perovskite cell unit 2 adopts FA. 0.9 MA 0.1 PbI3 is the light-absorbing layer, and composite layer 3 is composed of FTO particles 31 and nanocrystalline silicon 32. The specific preparation steps are as follows: Step 1: Form FTO particles 31 on the surface of crystalline silicon cell 1.

[0036] Specifically, a pre-cleaned PERC crystalline silicon solar cell 1 was selected as the underlying structure, with an n-type surface. + A doped silicon emitter layer is used, but no traditional antireflective coating is applied to its surface. FTO particles 31 are deposited via a spray pyrolysis method: a precursor solution containing SnCl4·5H2O and NH4F is atomized and sprayed onto the surface of a PERC cell heated to approximately 450°C, forming spherical FTO particles 31 with a diameter of 50-100 nm. By adjusting the spray flow rate, carrier gas rate, and substrate temperature, their island-like distribution is controlled, ensuring that the FTO particles 31 maintain electrical contact while leaving gaps for subsequent filling.

[0037] Step 2: Deposit nanocrystalline silicon 32 in the gaps between FTO particles 31.

[0038] Specifically, a layer of nanocrystalline silicon 32 is deposited between the deposited FTO particles 31 using plasma-enhanced chemical vapor deposition. The reactive gas is a mixture of SiH4 and H2, the deposition temperature is controlled below 200℃ to ensure compatibility with the PERC structure, the RF power is set to 20W, and the deposition time is controlled within 30 minutes. The nanocrystalline silicon 32 particles have a diameter of less than 20nm and a thickness of 50-100nm, filling the gaps between the FTO particles 31 to form continuous electrical connections while also providing a certain degree of mechanical buffering capacity to reduce interfacial stress concentration.

[0039] Preferably, when depositing the composite layer 3 of FTO particles 31 and nanocrystalline silicon 32 on the surface of the crystalline silicon cell 1, a combination of mask patterned spray pyrolysis and spatially selective PECVD deposition is used. This allows the composite layer 3 to maintain a relatively thin thickness (e.g., less than 100 nm) in the central region of the cell, minimizing light shading and improving the light transmittance efficiency of the perovskite layer. In contrast, the composite layer is appropriately thickened (e.g., 150–200 nm) in the edge regions to enhance the interfacial bonding strength and stress buffering capacity in these areas. This differentiated thickness design in different regions mitigates edge stress concentration caused by differences in thermal expansion coefficients or encapsulation warping while maintaining excellent photoelectric conversion performance, thereby improving the overall structural stability and long-term reliability of the device.

[0040] Step 3: Construct perovskite solar cell 2 on composite layer 3.

[0041] Specifically, after completing composite layer 3, a SnO2 electron transport layer (prepared by solution method and annealed at 150°C) is deposited on it sequentially, followed by the deposition of a perovskite light-absorbing layer (FA). 0.9 MA 0.1 PbI3 (using a two-step or anti-solvent method) is annealed at 100°C. A hole transport layer (such as PTAA) and a top metal electrode (such as Au) are then applied to it, thus completing the construction of perovskite solar cell 2.

[0042] In this embodiment, FTO particles 31 deposited via spray pyrolysis form a good mechanical support and electrical contact platform, while nanocrystalline silicon 32 further connects the upper and lower functional layers. This simultaneously alleviates the stress problem caused by the mismatch in thermal expansion coefficients between PERC crystalline silicon and perovskite cells, improving device interface stability and conversion efficiency. The entire fabrication process features reasonable temperature control, meeting the thermal stability requirements of PERC cells and suitable for practical industrialization.

[0043] Example 5 Building upon Example 4, a further plasma surface treatment step is introduced to optimize the interface performance between the composite layer 3 and the perovskite solar cell 2. This example uses a PERC-type crystalline silicon solar cell as the base cell. The composite layer 3 still consists of FTO particles 31 formed by spray pyrolysis and nanocrystalline silicon 32 deposited by PECVD. Specific improvements are as follows: After completing step 2 (i.e., depositing nanocrystalline silicon 32 in the gaps between FTO particles 31 using the PECVD method), a plasma surface treatment process is added. An radio frequency (RF) plasma system is used with hydrogen as the working gas, and the treatment conditions are: RF power 30W, treatment time 90 seconds, and working pressure 80Pa. This treatment is used to remove surface adsorbates, repair surface defects of the nanocrystalline silicon 32, passivate dangling bonds on the silicon surface, and improve its bandgap matching and adhesion with the upper SnO2 electron transport layer.

[0044] The plasma-treated composite layer 3 exhibits a more uniform surface and increased surface energy, which improves the deposition quality of the subsequent electron transport layer and perovskite light-absorbing layer, reduces pinholes and interlayer voids, and lowers interfacial resistance and non-radiative recombination. Simultaneously, this treatment further releases stress concentration areas remaining from the nanocrystalline silicon 32 deposition process, thereby enhancing the overall mechanical stability of the device.

[0045] Subsequently, perovskite solar cell unit 2 is constructed following step 3 in Example 4, ultimately forming a high-performance tandem solar cell with good interfacial bonding, high charge transport efficiency, and excellent stress buffering capacity. This plasma treatment step has advantages such as simple process, strong compatibility, and significant gain, making it suitable for large-area tandem solar cell production and application.

[0046] Example 6 Based on Example 4, this example further introduces a hot plate pressing process to enhance the structural density, interfacial bonding strength, and overall stability of the composite layer 3. The bottom crystalline silicon cell 1 still has a PERC structure, on which a stress-buffered composite layer 3 is constructed. The composite layer 3 includes FTO particles 31 deposited by spray pyrolysis and nanocrystalline silicon 32 deposited by PECVD.

[0047] Specifically, after completing step 2, i.e., depositing nanocrystalline silicon 32 between FTO particles 31 to form a composite layer 3, the battery structure is placed in a hot plate press for pressing. A flat-plate hot press is used, with the hot pressing temperature set at 130°C, the pressure at 0.5 MPa, and the pressing time at 90 seconds. During the hot pressing process, the composite layer 3 faces upwards, and a high-temperature silicone pad is used to achieve a flexible transition pressing, avoiding mechanical damage to the FTO particles 31 or the nanocrystalline silicon 32 structure.

[0048] Hot pressing promotes dense packing of nanocrystalline silicon 32 particles, significantly reducing the internal voids of composite layer 3 and improving interlayer mechanical stability. Secondly, under thermo-coupling, the contact between nanocrystalline silicon 32 and FTO particles 31, as well as the surface of crystalline silicon cell 1, becomes tighter, facilitating the formation of low-resistance ohmic contacts and improving electron transport efficiency. Thirdly, hot pressing helps release localized residual stress generated during the PECVD deposition process, alleviating interface mismatch issues caused by thermal expansion mismatch between the composite layer and the upper and lower cells.

[0049] Furthermore, the hot-pressing process optimizes the surface smoothness of composite layer 3, providing a more uniform substrate for the subsequent deposition of the SnO2 electron transport layer and improving the film quality and crystallization uniformity of the perovskite light-absorbing layer. After hot-pressing and natural cooling, step 3 continues, sequentially constructing the SnO2 electron transport layer, perovskite light-absorbing layer, hole transport layer, and metal electrode on composite layer 3, ultimately forming a high-efficiency and stable tandem solar cell structure. This embodiment, by introducing a hot-plate pressing process after the composite layer 3 is constructed, achieves multiple optimizations in structural, electrical, and thermal properties, providing a practical intermediate processing technology for the manufacture of large-area, highly consistent tandem solar cells.

[0050] Preferably, an ultrasonic-assisted hot pressing process is further introduced to improve the density, charge transport continuity, and overall interface stability of the composite layer 3. This technical solution combines the synergistic effect of hot pressing and ultrasonic vibration, using physical perturbation to promote a closer arrangement of nanocrystalline silicon 32 between FTO particles 31, effectively eliminating voids and local residual stress. Specifically, after completing step 2, i.e., depositing nanocrystalline silicon 32 between FTO particles 31 using the PECVD method, the constructed battery structure is placed in a hot pressing device with ultrasonic vibration function. The hot pressing platform is an integrated composite structure with an integrated ultrasonic transducer, whose ultrasonic frequency is set to 40kHz and power to 100W. The hot pressing plate temperature is set to 130℃, the applied pressure is 0.5MPa, and the pressing time is 90 seconds; throughout the hot pressing process, ultrasonic vibration is applied in a pulse manner, starting for 10 seconds and then repeating at 5-second intervals until the hot pressing is completed. During the ultrasonic-assisted hot pressing process, ultrasonic waves apply high-frequency perturbations to the interior of the composite layer 3 in the vertical direction. This causes the nanocrystalline silicon 32 to further slide, rearrange, and fill the tiny gaps between the FTO particles 31 under the action of thermal energy, forming a denser and more continuous conductive channel. Simultaneously, the mechanical vibration of the ultrasonic waves helps to break up the agglomeration regions formed during the deposition of the nanocrystalline silicon 32, releasing localized stress concentration areas and improving the interfacial contact tightness between the composite layer 3, the crystalline silicon cell unit 1, and the upper perovskite structure. After ultrasonic-assisted hot pressing is completed, the cell structure is allowed to cool naturally to room temperature. Step 3 is then performed, where a SnO2 electron transport layer, a perovskite light-absorbing layer, a hole transport layer, and a metal electrode are sequentially deposited on the composite layer 3 to construct the perovskite cell unit 2, thus completing the fabrication of the tandem cell.

[0051] In summary, this invention provides a tandem solar cell with a stress-buffered composite layer and its fabrication method, aiming to solve the stress concentration and interface delamination problems caused by the mismatch of thermal expansion coefficients of materials during the structural stacking of crystalline silicon and perovskite sub-cells. By introducing a composite layer 3 composed of FTO particles 31 and nanocrystalline silicon 32 onto the surface of the crystalline silicon cell 1, an intermediate layer with mechanical buffering, charge bridging, and interface harmonization functions is formed, improving the mechanical stability and electrical coupling performance of the tandem structure. The FTO particles 31 provide a stable conductive framework, while the nanocrystalline silicon 32 achieves filling, bonding, and stress relief. The overall thickness of the composite layer 3 is controlled at the nanometer level, maintaining good light transmittance while ensuring device stability. Furthermore, this invention proposes controllable spray pyrolysis, PECVD deposition, plasma treatment, and hot plate pressing processes to achieve fine control of the composite layer structure and optimization of interface quality. It is applicable to the tandem integration of different types of crystalline silicon cells such as PERC, TOPCon, and HJT, and has broad applicability and industrialization potential.

[0052] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A tandem solar cell with a stress-buffered composite layer, comprising a crystalline silicon cell unit, a perovskite cell unit, and a composite layer, wherein the composite layer is located between the crystalline silicon cell unit and the perovskite cell unit, characterized in that: The composite layer includes FTO particles and nanocrystalline silicon. The FTO particles are distributed on the surface of the crystalline silicon cell, and the nanocrystalline silicon fills the spaces between the FTO particles and is electrically connected to the FTO particles and the crystalline silicon cell.

2. The tandem solar cell with a stress-buffered composite layer as described in claim 1, characterized in that: The crystalline silicon solar cell unit is any one of PERC, TOPCon, or HJT structures.

3. The tandem solar cell with a stress-buffered composite layer as described in claim 1, characterized in that: The perovskite solar cell unit includes a perovskite light-absorbing layer, a hole transport layer, and an electron transport layer, with the electron transport layer covering the composite layer.

4. The tandem solar cell with a stress-buffered composite layer as described in claim 1, characterized in that: The FTO particles are spherical or near-spherical, and the diameter of the FTO particles is 50-100 nanometers.

5. The tandem solar cell with a stress-buffered composite layer as described in claim 4, characterized in that: The nanocrystalline silicon is intrinsically or n-type doped, and the size of the nanocrystalline silicon is less than 20 nanometers.

6. The tandem solar cell with a stress-buffered composite layer as described in claim 5, characterized in that: The overall thickness of the composite layer is less than 200 nanometers.

7. A method for fabricating a tandem solar cell with a stress-buffered composite layer, characterized in that, Includes the following steps: Step 1: Form FTO particles on the surface of crystalline silicon solar cell cells; Step 2: Deposit nanocrystalline silicon between FTO particles; Step 3: Construct perovskite solar cell units on the composite layer.

8. The method for preparing a tandem solar cell with a stress-buffered composite layer as described in claim 7, characterized in that: In step 1, a spray pyrolysis process is used to deposit FTO particles on the surface of crystalline silicon solar cell cells and then heat-treat them to form an island-like distribution.

9. The method for preparing a tandem solar cell with a stress-buffered composite layer as described in claim 8, characterized in that: In step 2, nanocrystalline silicon is deposited in the interparticle spaces of FTO particles using the PECVD method.

10. The method for preparing a tandem solar cell with a stress-buffered composite layer as described in claim 9, characterized in that: After step 2, plasma surface treatment is performed.

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