Asymmetric organic light-emitting transistor with horizontal-vertical transmission channel and method and application thereof

Abstract

The invention discloses an asymmetric organic light-emitting transistor with a horizontal-vertical transmission channel and a method and application thereof, and belongs to the technical field of organic light-emitting transistors. The invention discloses an asymmetric organic light-emitting transistor with a horizontal-vertical transmission channel. The asymmetric organic light-emitting transistor comprises a substrate, a gate electrode, a double-gate electrode layer and an organic channel semiconductor layer which are sequentially arranged from bottom to top, the device further comprises a source electrode layer and a drain electrode. A plurality of layers of organic light-emitting units are also arranged between the source electrode layer and the organic channel semiconductor layer; the multiple layers of organic light-emitting units are of a vertical stacking structure; the source electrode layer is arranged on one side of the organic channel semiconductor layer and is in transverse contact with the organic channel semiconductor layer; the drain electrode is arranged at the top of the multi-layer organic light-emitting unit; and the electrode layer, the drain electrode and the gate electrode are arranged in a spatial non-coplanar manner. The transistor provided by the invention realizes a light-emitting device unit which is high in structural integration level, clear in charge injection path and adaptive to patterned array construction.

Description

Technical Field

[0001] This invention belongs to the field of organic light-emitting transistor technology, specifically relating to an asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels, as well as its method and application. Background Technology

[0002] Organic light-emitting transistors (OLETs) are three-terminal optoelectronic devices that integrate transistor and light-emitting functions. They possess both field-effect modulation and electroluminescence characteristics, making them suitable for integrated display systems. Based on the functional layer layout, OLET devices are mainly divided into single-layer and multi-layer structures. Single-layer structures balance carrier mobility and luminous efficiency through material molecular design, but are often limited by insufficient exciton quenching and charge recombination efficiency, limiting the potential for performance improvement. To overcome these problems, multi-layer OLET structures employ a functional layer separation design, spatially decoupling hole injection, electron injection, carrier transport, and exciton recombination processes, providing greater flexibility in material selection and structural control.

[0003] Based on the channel structure layout, existing multilayer OLETs are further divided into vertical and lateral types. Vertical devices typically employ a vertical charge transport path with upper and lower electrode injection and upper and lower electric field control, offering advantages such as short channels, enhanced optical cavity, and area emission. However, they are difficult to turn off effectively, have complex structures, and limited gate control capabilities. Lateral devices, on the other hand, use a non-coplanar arrangement of the source, drain, and gate, enabling stronger field-effect control and pixel pattern definition capabilities. However, they suffer from problems such as channel and light-emitting region reuse, unstable exciton recombination positions, and charge transport imbalance, limiting the device's optoelectronic performance and integration efficiency. In recent years, to further improve the electrical control precision, luminescence uniformity, and structural compatibility of OLET devices, some research has attempted to combine the short-channel advantages of vertical structures with the electric field control advantages of lateral structures, constructing light-emitting transistor devices with both vertical emission output and lateral driving capabilities through composite structure design. However, in existing devices, the light-emitting region and channel region often overlap, lacking clear spatial separation, making it difficult to simultaneously meet the requirements of high aperture ratio, low power consumption, and array integration. Summary of the Invention

[0004] The purpose of this invention is to provide an asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels, as well as a method and application, to solve the technical problem that the light-emitting area and the channel area often overlap in existing devices and lack clear spatial separation.

[0005] To achieve the above objectives, the present invention employs the following technical solution:

[0006] This invention discloses an asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels, comprising a substrate, a gate electrode, a double-gate dielectric layer, and an organic channel semiconductor layer arranged sequentially from bottom to top; it also includes a source electrode layer and a drain electrode; a multilayer organic light-emitting unit is disposed between the source electrode layer and the organic channel semiconductor layer; the multilayer organic light-emitting unit has a vertically stacked structure;

[0007] The source electrode layer is disposed on one side of the organic channel semiconductor layer and forms a lateral contact with the organic channel semiconductor layer; the drain electrode is disposed on the top of the multilayer organic light-emitting unit; the electrode layer, drain electrode and gate electrode are arranged in a spatially non-coplanar manner.

[0008] Furthermore, the multilayer organic light-emitting unit includes a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer stacked vertically from bottom to top.

[0009] Furthermore, the material of the dual-gate dielectric layer is a composition of high-dielectric-constant inorganic material and low-dielectric-constant inorganic material; the material of the dual-gate dielectric layer is a composition of high-dielectric-constant inorganic material and low-dielectric-constant polymer material; the high-dielectric-constant material is greater than 3.9; the low-dielectric-constant material is less than 3.9.

[0010] Furthermore, the organic channel semiconductor layer is an organic semiconductor thin film deposited by spin coating or thermal evaporation; the mobility of the organic semiconductor thin film is greater than 1 cm⁻¹. 2 V -1 s -1 .

[0011] Furthermore, the hole injection layer is made of inorganic oxides or organic electron acceptor materials; the hole transport layer is made of small organic molecules with aromatic amine, carbazole, or polycyclic aromatic hydrocarbon structures.

[0012] Furthermore, the light-emitting layer is an organic bipolar host material doped with an organic phosphorescent guest structure; the electron transport layer is an electron-withdrawing organic small molecule compound.

[0013] The electron injection layer is an alkaline earth metal compound or an organic complex;

[0014] The drain electrode is an aluminum film; the aluminum film has a reflectivity of 95%.

[0015] Furthermore, the substrate is made of inorganic glass or an organic polymer film.

[0016] This invention also discloses a method for fabricating the above-mentioned asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels, comprising the following steps:

[0017] A dual-gate dielectric layer and an organic channel semiconductor layer are sequentially fabricated on the surface of the gate electrode on the substrate;

[0018] The process involves fabricating a source electrode layer on one side of the organic channel semiconductor layer and fabricating a multilayer organic light-emitting unit on the other side; finally, a drain electrode is fabricated on top of the multilayer organic light-emitting unit.

[0019] Furthermore, the methods for preparing the dual-gate dielectric layer include spin coating, atomic deposition, or vacuum evaporation.

[0020] The methods for preparing organic channel semiconductor layers are spin coating or vacuum evaporation.

[0021] The method for preparing multilayer organic light-emitting units is vacuum evaporation.

[0022] The drain electrode is prepared by vapor deposition.

[0023] The present invention also discloses the application of the above-mentioned asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels in the construction of pixel units in a static light-emitting array.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] This invention discloses an asymmetric organic light-emitting transistor (OLED) with both horizontal and vertical transport channels. The transistor comprises multiple layers of organic light-emitting units disposed between the source electrode layer and the organic channel semiconductor layer. These multiple organic light-emitting units are vertically stacked, and a lateral contact is formed between the source electrode layer and the organic channel semiconductor layer. The staggered spatial arrangement of the source, drain, and gate electrodes allows for more effective control of the electric field for charge carrier transport. Combining lateral source-drain injection with a vertical electroluminescence output mechanism, this invention achieves a light-emitting device unit with high structural integration, a clear charge injection path, and adaptability to patterned array construction. Furthermore, the non-coplanar electrode layout effectively distinguishes the carrier transport path from the light-emitting region, making it suitable for pixel design requirements requiring large-area controllable light emission.

[0026] Furthermore, at the structural level, a double-layer gate dielectric layer with a high dielectric constant is introduced, combined with a high-mobility channel layer material and an interface buffer layer configuration, which improves the electric field control capability and interface charge stability. The emitting layer and transport layer in the multilayer organic light-emitting unit adopt a multi-color phosphorescent doped material system and a stepped hole / electron transport structure, respectively, to achieve red, green and blue integrated output with clear color distinction and precise positioning of the emission area.

[0027] Furthermore, OLET adopts a 1T1C driving architecture, which can maintain the image display state with a single gating without continuous refreshing, thus reducing driving power consumption. The device has a clear electrical isolation structure between pixels, supporting pattern control, array scalability, and a unified fabrication process. The device as a whole has driving logic matching and structural hierarchy compatibility for static display systems, and can complete display tasks without increasing the number of additional driving transistors. It integrates the functions of light emission response, electric field control, and array gating, providing engineering feasibility for next-generation integrated organic display devices.

[0028] Furthermore, the present invention adopts a combination of a three-terminal control structure and a vertical emission mechanism, and the emission position is determined by the carrier injection path, which has the ability to control regional emission and precisely adjust the pixel contour. The vertical structure and the horizontal driving electrode in the present invention work together to construct a single pixel emission stack, which significantly improves the emission area utilization efficiency and is suitable for dense pixel layout and display panel size scaling.

[0029] Furthermore, the functional layers of the device of the present invention are integrated using a standard organic material deposition method, which is compatible with existing thin film processes and has the feasibility of large-area manufacturing under a unified material system; the display array of the invention has pattern loading capability and electrical signal holding characteristics, and is suitable for static image output and programmable display scenarios with low update frequency.

[0030] This invention also discloses a method for fabricating the aforementioned asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels. This method, by introducing both horizontal and vertical transmission channels into the same device structure, avoids the strictly aligned photolithography patterning steps required in traditional planar devices, thus reducing the dependence on process precision. Furthermore, by employing controllable deposition and interface modulation techniques, compatible integration of functional layers with different channel orientations on the same substrate is achieved, simplifying the interlayer stacking process. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the structure of the asymmetric organic light-emitting transistor of the present invention, which combines horizontal and vertical transmission channels;

[0032] Figure 2 This is a photograph of the asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels in Embodiment 1 of the present invention emitting light under gate voltage drive.

[0033] Figure 3 This is a photograph of a display array based on an asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels, as described in Embodiment 1 of the present invention.

[0034] Wherein: 1-substrate; 2-gate electrode; 3-dual gate dielectric layer; 4-organic channel semiconductor layer; 5-source electrode layer; 6-multilayer organic light-emitting unit; 61-hole injection layer; 62-hole transport layer; 63-light-emitting layer; 64-electron transport layer; 65-electron injection layer; 7-drain electrode. Detailed Implementation

[0035] To enable those skilled in the art to understand the features and effects of the present invention, the terms and expressions used in the specification and claims are explained and defined in general below. Unless otherwise specified, all technical and scientific terms used herein have the ordinary meaning understood by those skilled in the art regarding the present invention, and in case of conflict, the definitions in this specification shall prevail.

[0036] The theories or mechanisms described and disclosed herein, whether right or wrong, should not in any way limit the scope of the invention, that is, the contents of the invention can be implemented without being limited by any particular theory or mechanism.

[0037] In this document, all features defined by numerical ranges or percentage ranges, such as numerical values, quantities, contents, and concentrations, are for the sake of brevity and convenience only. Accordingly, descriptions of numerical ranges or percentage ranges should be considered as covering and specifically disclosing all possible sub-ranges and individual numerical values ​​(including integers and fractions) within those ranges.

[0038] In this article, unless otherwise specified, “contains,” “includes,” “containing,” “has,” or similar terms cover the meanings of “composed of” and “mainly composed of,” for example, “A contains a” covers the meanings of “A contains a and others” and “A contains only a.”

[0039] For the sake of brevity, not all possible combinations of the technical features in each implementation scheme or embodiment are described herein. Therefore, as long as there is no contradiction in the combination of these technical features, the technical features in each implementation scheme or embodiment can be combined arbitrarily, and all possible combinations should be considered within the scope of this specification.

[0040] This invention provides an asymmetric organic light-emitting transistor (OLED) with both horizontal and vertical transmission channels. Based on the basic structure of an organic field-effect transistor, this device vertically integrates organic light-emitting unit modules, thereby achieving integrated transistor functionality and organic electroluminescence functionality. Figure 1As shown, the structure includes, from bottom to top, a substrate 1, a gate electrode 2, a dual-gate dielectric layer 3, and an organic channel semiconductor layer 4; it also includes a source electrode layer 5 and a drain electrode 7; a multilayer organic light-emitting unit 6 is disposed between the source electrode layer 5 and the organic channel semiconductor layer 4; the multilayer organic light-emitting unit 6 has a vertically stacked structure; the source electrode layer 5 is disposed on one side of the organic channel semiconductor layer 4, forming a lateral contact with the organic channel semiconductor layer 4; the drain electrode 7 is disposed on the top of the multilayer organic light-emitting unit 6; the source electrode layer 5, the drain electrode 7, and the gate electrode 2 are arranged in a spatially non-coplanar manner, constructing a novel structure that combines lateral driving and vertical light emission.

[0041] Preferably, the multilayer organic light-emitting unit 6 includes a hole injection layer 61, a hole transport layer 62, a light-emitting layer 63, an electron transport layer 64, and an electron injection layer 65 stacked vertically from bottom to top.

[0042] Preferably, the substrate 1 comprises a transparent substrate and a gate electrode 2 disposed thereon. The substrate 1 is an inorganic glass or organic polymer film, specifically selected from soda-lime glass, alkali-free glass, quartz glass, polyethylene terephthalate (PET), polynaphthalene dicarboxylate (PEN), or polyimide (PI) film. The gate electrode 2 is selected from one or more of the following materials: indium tin oxide (ITO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), zinc tin oxide (ZTO), and indium zinc oxide (IZO). The gate electrode 2 is formed by magnetron sputtering, electron beam evaporation, or chemical vapor deposition. Alternatively, it is a metal nanostructure, including silver nanowires, copper nanowire networks, or metal mesh pattern structures, formed by solution coating, transfer printing, or laser patterning. Or it is a carbon-based conductive material, including... The graphene film or carbon nanotube network film, wherein the carbon-based material is formed by chemical vapor deposition, solution transfer printing or spray deposition process; or it is a conductive polymer material selected from poly(3,4-ethylenedioxythiophene) / polystyrene sulfonic acid (PEDOT:PSS), wherein the polymer conductive layer is formed by spin coating, inkjet printing or blade coating; the gate electrode 2 is a single-layer structure, or it can be a composite structure formed by multiple conductive materials, wherein the composite structure includes but is not limited to the stack of silver nanowires and PEDOT:PSS, the combination structure of ITO and metal mesh or the composite structure of graphene and metal thin film; the transparent conductive substrate is used to construct the gate electrode in an organic field-effect light-emitting transistor device, wherein the conductive layer faces inward of the device, and a double gate dielectric layer 3, an organic channel semiconductor layer 4 and a multilayer organic light-emitting unit 6 are sequentially disposed thereon, and connected to an external electrode to introduce a driving voltage.

[0043] Preferably, the dual-gate dielectric layer 3 is disposed above the conductive layer of the transparent conductive substrate, used to isolate the gate electrode from the organic field-effect channel layer and provide a gate-controlled electric field. The dual-gate dielectric layer 3 can be a single-layer structure or a multi-layer composite structure. The material of the single-layer structure is selected from inorganic dielectric materials, organic polymer dielectric materials, or organic-inorganic composite dielectrics. The inorganic dielectric materials include silicon dioxide (SiO2), aluminum oxide (Al2O3), silicon nitride (Si3N4), or tantalum oxide (Ta2O5), formed by processes such as thermal oxidation, sol-gel, sputtering, or atomic layer deposition. The organic polymer dielectric materials are selected from polymethyl methacrylate (PMMA), polystyrene (PS), polyvinyl alcohol (PVA), polyimide (PI), or polyaryletherketone materials, formed by spin coating, blade coating, or printing. Formed by brushing; the composite dielectric material includes a mixture of organic and inorganic materials, or a mixture of two or more polymer materials, used to optimize the dielectric constant, surface energy, or interface trap density; in a specific structure, the dual-gate dielectric layer 3 is composed of a lower polymer dielectric layer and an upper hydrophobic polymer layer, wherein the lower layer is PVA with a thickness controlled between 100 nm and 200 nm, formed by spin coating and cross-linking through heat treatment, and the upper layer is a fluorinated polymer CYTOP or AF1600, used to reduce surface polarity and hygroscopicity, deposited and cured by spin coating or spray coating. The overall dielectric constant, leakage current density, and surface roughness of the dual-gate dielectric layer 3 can be designed to match the device voltage window and the characteristics of organic semiconductor materials to form a stable gate-controlled electric field and provide interface charge regulation function.

[0044] Preferably, the organic channel semiconductor layer 4 comprises an organic semiconductor material with high carrier mobility. The organic semiconductor material with high carrier mobility can be selected from conjugated polymer materials, small molecule materials, organometallic hybrid materials, or combinations thereof. The conjugated polymer materials include copolymers based on units such as dioxenonopyrrolopyrrole (DPP), thiopheneisoindole (TIIG), and peryleneimide (PDI), such as DTT-DPP, PDPPMT-2T, and PTIIG-Np. The small molecule materials include polycyclic aromatic hydrocarbons, sulfur-containing heterocyclic hydrocarbons, and their alkyl-substituted derivatives, such as 2,6-diphenylanthracene (2,6-DPA), dinaphthothiophene (DNTT), alkylated benzothiophene (BTBT), and their derivatives such as C8-BTBT-C8 and C10-DNTT-C10. The organometallic hybrid materials include materials such as [Cu3(C6S6)]. nTwo-dimensional π-d conjugated structure materials are used. In device fabrication, the organic channel semiconductor layer 4 is preferably a single crystal or a highly oriented polycrystalline thin film, which can be constructed by methods such as physical vapor transport, solution shearing, liquid-solid interface assembly, or weak epitaxial growth. The thickness of the organic channel semiconductor layer 4 can be controlled within the range of 5-100 nanometers according to the device structure to meet the requirements of field effect control and luminous efficiency. To further improve the interface contact performance and injection efficiency, an interface induction layer or surface modification layer, such as alkylsilane, fluoropolymer, or π-conjugated intermediate layer, can be selected below the organic channel semiconductor layer 4 to reduce carrier trap density and improve crystal orientation.

[0045] Preferably, the hole transport layer 62 is disposed above the organic channel semiconductor layer 4 and between the light-emitting layer 63, and the material used is an organic small molecule with an aromatic amine, carbazole or polycyclic aromatic hydrocarbon structure, specifically including tris(4-trimethylphenyl)amine (TAPC), tris(4-methoxyphenyl)amine (m-MTDATA), 4,4'-bis[N-(1-naphthyl)-N-phenylamino]biphenyl (NPB), N,N'-di(3-methylphenyl)-N,N'-diphenylbiphenyldiamine (TPD), 4,4'-di(N,N-diphenylamino)diphenylethylene (DPVBi), 4,4',4”-tris(N-carbazolyl)triphenylamine (TCTA), 1,3-bis(N-carbazolyl)benzene (mCP), 9,9'-diphenyl-9H The material can be composed of 9'H-bicarbazole (DPCz), 3,6-bis(9H-carbazole-9-yl)-9-(2-ethylhexyl)carbazole (EH-Cz), 9-phenyl-3,6-bis(triphenylamino)-9H-carbazole (PTPA-Cz), benzothiophene-thiophene (BTBT), and carbazole-dithiophene conjugated structures, etc., any one or more of which can be used alone or in combination to form a multilayer structure; the HOMO energy level range of the material is -5.2 to -6.0 eV, which is used to match the energy level difference between the material and the emitter layer to realize hole injection and transport functions; the hole transport layer 62 is formed by thermal evaporation, and the film thickness is 10 to 60 nm. The specific thickness and material arrangement order can be optimized according to the device structure, electric field distribution, and exciton recombination position requirements.

[0046] Preferably, the light-emitting layer 63 comprises a phosphorescent guest material and a bipolar host material. The phosphorescent doped guest material includes: tris[1-phenylisoquinoline-C2,N]iridium(III) (Ir(piq)3), bis(2-phenylpyridine)iridium acetylacetonate (Ir(piq)2(acac)), bis(2-methyldibenzo[f,h]quinoxaline)(acetylacetonate)iridium(III) (Ir(MDQ)2(acac)), bis(2,3-diphenylpyrazine-C2,N)iridium acetylacetonate (Ir(DPP)2(acac)), and bis(2-(2'-benzothiophene)pyridine-N,C3')(acetylacetonate)iridium acetylacetonate (Ir(Btp)2(a)). cac), bis[2-(3,5-dimethylphenyl)-4-methylquinoline](acetylacetone)iridium(III))(Ir(mphmq)2(acac)), bis(4,4'-difluoro-2,3-diphenylquinoxaline)iridium acetylacetonate(Ir(dpqf)2(acac)), tris(2-phenylpyridine)iridium(III))(Ir(ppy)3), bis(2-phenylpyridine-C2,N)iridium(III)(Ir(ppy)2(acac)), tris(2-(3-methylphenyl)pyridine)iridium(III))(Ir(mppy)3), bis(4,6-difluorophenylpyridine-C2,N)(pyridinecarboxylate) At least one of iridium(III) (Firpic), bis(2,4-difluorophenylpyridino)tetra(1-pyrazolyl)boronate (FIr6), and (4,6-difluorophenylpyridine)(5-(pyridin-2-yl)-tetraazole)iridium (FIrN4); the bipolar host material used is such as 4,4'-bis(carbazole-9-yl)biphenyl (CBP), its derivatives such as 2,2'-dimethyl-4,4'-bis(carbazole-9-yl)biphenyl (CDBP), bis(4-carbazoleylphenyl)phenyldimethylsilane (SimCP), bis(carbazoleyl)tetraphenylsilane (SimCP2), and bis(diphenylphosphoxy)biphenyl based on the phosphophosphate oxygen structure. At least one of the following: (PO1), bis(diphenylphosphoxy)-9,9-dimethylfluorene (PO6), bis(diphenylphosphoxy)dibenzofuran (PODBF), triazine 2,4,6-tris(biphenyl-3-yl)-1,3,5-triazine (T2T), tris(triphenylphenyl)-1,3,5-triazine (T3T), heterocyclic carbazole-oxadiazole (o-CzOXD), carbazole-benzimidazole (e.g., TPBI-Cz), carbazole-pyridine (26DCzPPy), fluorene-phosphoxy (e.g., BCPO), 9,9-diphenylfluorene-bridged phosphoxy-carbazole materials (PCF, PPO21, etc.), and benzophenanthrene-carbazole (m-CZBP, m-TPAP).

[0047] Preferably, the electron transport layer 64 is disposed between the light-emitting layer 63 and the electron injection layer 65, providing an injection and vertical transport channel for electrons in the device, and blocking hole injection into the light-emitting layer 63 to form an exciton confinement structure. The material of the electron transport layer 64 is selected from small organic molecule compounds with electron-withdrawing structures, including one or more of the following: 8-hydroxyquinoline aluminum (Alq3), 2,2',2”-(1,3,5-phenyl)tris(1-phenyl-1H-benzimidazole) (TPBi), 2,9-dimethyl-4,7-diphenyl-1,10-o-phenanthroline (Bphen), 2,9-dimethyl-4,7-di(3-methylphenyl)-1,10-o-phenanthroline (BCP), 1,3,5-tris(3-pyridyl)benzene (TmPyPB), 1,3,5-tris(4-pyridyl)benzene (TpPyPB), B3PYMPM Materials such as B4PYPPM, B4PYMPM, DPPS, 3TPYMB, TSPO1, PO-T2T, and T3PySS contain electron-withdrawing groups such as pyridine, pyrimidine, triazine, triazole, phosphoroxane, fluorene, spirofluorene, and benzimidazole. These materials possess low LUMO levels (-2.5 eV to -3.5 eV) to match the cathode work function and suppress the electron injection barrier, while their deep HOMO levels (-6.0 to -7.5 eV) effectively block hole reverse injection. Some materials have higher triplet energy levels (T1 > 2.7 eV) to construct exciton confinement layers and prevent triplet excitons from leaking into the electron transport layer 64.

[0048] Preferably, the electron transport layer 64 material can be used alone, or it can be designed in multiple layers or in a blend according to the requirements of electron injection / transport and exciton confinement functions. For example, a high triplet energy level material (such as TmPyPB, TSPO1) can be used near the emitter layer, combined with a high mobility material (such as TpPyPB, Bphen) to form a stepped electron injection structure. This layer is deposited by thermal evaporation, with the film thickness controlled between 10-60 nm and the deposition rate... The thickness and position can be controlled based on the simulation results of electrode work function, LUMO energy level of emitter layer and exciton distribution, so as to further improve the device's electron injection capability, charge balance and luminescence efficiency.

[0049] Preferably, the electron injection layer 65 is disposed between the electron transport layer 64 and the drain electrode 7, used to reduce the work function difference between the drain electrode 7 and the organic channel semiconductor layer 4, improve the contact characteristics of the electron injection interface, and enhance the electron injection efficiency; the material of the electron injection layer 65 can be selected from alkali metal fluorides, alkaline earth metal compounds, organometallic complexes, or n-type doped materials, including lithium fluoride (LiF), calcium fluoride (CaF2), barium oxide (BaO), magnesium oxide (MgO), metallic magnesium (Mg), and metallic calcium (C). a) Strontium (Sr) or its co-evaporated alloy structure with aluminum (such as Ca:Al, LiF:Al); the electron injection layer 65 can also use n-type organic molecules containing heterocyclic nitrogen as dopants, such as 2-methyl-9,10-anthraquinone (2-MAQ), 1,3,5-tris(trifluoromethyl)benzene, N-DMBI, etc., to co-dop with the electron transport layer 64 material to form a doped interface structure; this layer can be deposited by thermal evaporation process, with the thickness controlled between 0.2 nm and 5 nm, to form an ultrathin control layer or an injection interface dipole layer.

[0050] Preferably, the drain electrode 7 is an aluminum electrode, disposed above the electron injection layer 65, and formed by thermal evaporation deposition. It is used to inject and transfer electrons to the light-emitting layer 63 during device operation. The work function of aluminum matches that of commonly used electron injection layer 65 materials, which can form a low barrier contact interface. At the same time, it has high reflectivity and has a reflective effect on upward light in the bottom emission structure.

[0051] Preferably, the source electrode 7 is disposed on one side of the organic channel semiconductor layer 4 for injecting holes and establishing a lateral electric field. Its material requires low resistivity and good thin-film continuity to ensure uniform carrier injection and device driving stability. The source electrode can be a highly conductive metal, such as gold (Au), silver (Ag), molybdenum (Mo), aluminum (Al), or a multilayer structure thereof. An interface modulation layer can be introduced according to the energy level structure of the organic semiconductor to reduce the injection barrier, improve interface contact, and promote effective hole injection from the source electrode to the organic layer.

[0052] Preferably, the material of the hole injection layer 61 can be selected from inorganic oxides, organometallic complexes, or p-type doped systems, specifically including molybdenum trioxide (MoO3), osmium tetroxide (OsO4), vanadium oxide (V2O5), tungsten oxide (WO3), 1,4,5,8,9,11-hexacyanotriazine (HAT-CN), tetrafluoronitrile quinone (F4-TCNQ) doped organic small molecules, iodine-doped polymers, or other hole-selective materials with high work function. This layer can be deposited by thermal evaporation, spin coating, or inkjet printing, and its thickness is usually between 0.5 nm and 10 nm. It is adjusted according to the energy level difference between the electrode and the organic semiconductor to form ohmic or quasi-ohmic contacts and reduce the hole injection barrier.

[0053] This invention also discloses a method for fabricating the above-mentioned asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels, comprising the following steps:

[0054] 1) Fabrication and cleaning of substrate 1 / gate electrode 2

[0055] Flexible or rigid substrates are selected and ultrasonically cleaned sequentially with organic solvents and deionized water to remove surface impurities and organic residues, followed by drying in a nitrogen gas flow or vacuum oven. Subsequently, a transparent conductive film is deposited on the surface of substrate 1 using physical vapor deposition, chemical vapor deposition, or sputtering methods to serve as the gate electrode. By adjusting the atmosphere composition, deposition power, and substrate temperature, an electrode layer with uniform thickness and a smooth surface can be obtained.

[0056] 2) Fabrication of the dual-gate dielectric layer 3

[0057] Two dielectric layers are deposited sequentially on a clean substrate 1 / gate electrode 2, which can be accomplished by atomic layer deposition, magnetron sputtering or solution spin coating, etc. The first layer is used to improve the interface flatness and electrical properties, and the second layer enhances the insulation and mechanical stability. Temperature needs to be controlled during the deposition process to avoid damaging the substrate 1 or the electrode. After deposition, low-temperature annealing can be performed to improve the interface bonding and thin film density.

[0058] 3) Fabrication of organic channel semiconductor layer 4

[0059] On the double dielectric layer, organic semiconductor materials are deposited by vacuum evaporation or solution processing to form a channel layer; the vacuum degree, evaporation rate and substrate temperature need to be controlled in the process to obtain an organic channel semiconductor layer with larger grains, flat surface and controllable thickness 4.

[0060] 4) Fabrication of source electrode layer 5

[0061] On the channel layer, the source electrode is patterned using a metal mask, and the electrode is formed by vacuum thermal evaporation or sputtering to deposit a metal layer; during deposition, an appropriate vacuum and deposition rate are maintained, and the thickness is controlled within the range of 100 nanometers; at the same time, excessively high substrate temperature must be avoided to protect the organic channel semiconductor layer 4.

[0062] 5) Fabrication of multilayer organic light-emitting unit 6 and drain electrode 7

[0063] After changing the photomask, multiple organic functional layers are sequentially deposited under high vacuum conditions, including a hole injection layer 61, a hole transport layer 62, a light-emitting layer 63, an electron transport layer 64, and an electron injection layer 65. Each layer forms a vertical stacked structure by precisely controlling its thickness and deposition rate. Finally, a metal drain electrode 7 is deposited to complete the device structure. Throughout the process, a stable deposition rate and low substrate temperature are maintained to ensure film quality and interface stability.

[0064] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0065] The following examples use instruments and equipment conventional in the art. Experimental methods in the following examples, unless otherwise specified, are generally performed under conventional conditions or as recommended by the manufacturer. All raw materials used in the following examples are conventional commercially available products with specifications conventional in the art. In this specification and the following examples, unless otherwise specified, "%" refers to weight percentage, "parts" refers to parts by weight, and "ratio" refers to weight proportion.

[0066] Example 1

[0067] A method for fabricating an asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels includes the following steps:

[0068] 1) Cleaning and preparation of substrate 1 / gate electrode 2:

[0069] High-purity quartz glass with a thickness of approximately 0.5 mm was selected as substrate 1. It was ultrasonically cleaned in acetone and isopropanol for 10 min each, followed by rinsing with deionized water for 5 min to remove surface oil and particulate impurities. After cleaning, substrate 1 was dried under a nitrogen flow and subjected to ultraviolet ozone treatment for 20 min to increase surface energy and hydrophilicity. Subsequently, an indium tin oxide thin film (gate electrode 2) was deposited using magnetron sputtering. The target material was In₂O₃:SnO₂ (90:10 wt%), the sputtering power was 100 W, and the sputtering gas was a mixture of argon and oxygen (oxygen accounting for 10%). The substrate temperature was maintained at 120 °C, the deposition rate was 0.8 nm / s, and the deposition reached a thickness of 150 nm. After deposition, substrate 1 was annealed at 120 °C for 15 min to improve the thin film crystal structure and conductivity.

[0070] 2) Fabrication of the dual-gate dielectric layer 3:

[0071] Polyvinyl alcohol (PVA, Mw 124k) was dissolved in deionized water (8wt%), magnetically stirred at 90℃ and aged to remove bubbles. After filtration through a 0.22μm filter membrane, it was spin-coated on a clean substrate at 4000rpm for 60s and heated on a hot stage at 110℃ for 20min to obtain a bottom PVA dielectric layer (target thickness 80nm). To improve swelling resistance and dielectric stability, 0.5wt% glutaraldehyde was added and crosslinked and cured at 100℃. After cooling, an anisotropic solvent system of PMMA (Mw 495k) (such as chlorobenzene or toluene, 5wt%) was prepared, filtered through a 0.22μm filter membrane, spin-coated at 4000rpm for 60s, and then heated on a hot stage at 180℃ for 30min to form a double-gate dielectric layer 3 (target thickness 300nm) with an upper PMMA layer and a lower PVA layer.

[0072] 3) Fabrication of organic channel semiconductor layer 4:

[0073] C8-BTBT was dissolved in chlorobenzene or toluene (8 mg / mL) under a nitrogen atmosphere, stirred and heated until completely dissolved, and then filtered through a 0.22 μm filter membrane. The substrate with the prepared PVA / PMMA bilayer was preheated and the surface was cleaned. A film was formed by spin coating (3000 rpm, 60 s) with a film thickness of about 40 nm. Subsequently, it was annealed at 90 °C for 30 min to promote crystallization and remove residual solvent, thereby obtaining an organic channel semiconductor layer 4 with a smooth surface and good crystal orientation.

[0074] 4) Fabrication of source electrode layer 5

[0075] On a substrate with an organic channel semiconductor layer 4 already formed, a patterned area is created using a metal mask, and aluminum metal is deposited via vacuum thermal evaporation. The vacuum level of the deposition environment is controlled at 5 × 10⁻⁶. -6 Torr, evaporation rate remains The electrode thickness is 100 nm; the substrate temperature is kept below 60 °C during the deposition process to avoid thermal damage to the organic channel layer, and the source electrode layer 5 is finally prepared.

[0076] 5) Fabrication of multilayer organic light-emitting unit 6 and drain electrode 7

[0077] The mask was changed, and a 10nm HAT-CN layer was vacuum deposited as the hole injection layer 61 to improve the interfacial work function and reduce the hole injection barrier; then, a 30nm TCTA layer was spin-coated or thermally evaporated as the hole transport layer 62; next, mCP:FIrpic (10wt%) was deposited as the light-emitting layer 63, with a thickness of approximately 25nm; then, a 40nm TPBi layer was deposited as the electron transport layer 64; then, a 1nm LiF layer was deposited as the electron injection layer 65, and finally, Al (100nm) was thermally evaporated as the drain electrode 7; throughout the process, the evaporation rate was controlled at [value missing]. The substrate temperature should not exceed 60℃.

[0078] Example 2

[0079] A method for fabricating an asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels includes the following steps:

[0080] 1) Cleaning and preparation of substrate 1 / gate electrode 2

[0081] After cleaning the flexible PI thin film substrate 1, an FTO thin film is deposited on its surface as the gate electrode 2 using vacuum magnetron sputtering or chemical vapor deposition (CVD). The process parameters can be controlled as follows: sputtering power of 150W, sputtering gas of Ar / O2 mixture (O2 flow rate of 5%), substrate temperature maintained at 150℃ to take into account the heat resistance of PI; deposition rate of 1.0nm / s, and the final FTO gate electrode thickness of about 200nm. Then, it is ultrasonically cleaned in acetone for 15min to remove oil and particulate impurities. Subsequently, it is ultrasonically cleaned in isopropanol or ethanol for 10min. It is then thoroughly rinsed with deionized water to remove residual solvent and water-soluble impurities. Finally, it is dried under nitrogen flow or placed in a vacuum oven at 100℃.

[0082] 2) Fabrication of the dual-gate dielectric layer 3

[0083] On a clean PI / FTO substrate, an Al2O3 thin film dielectric layer with a thickness of 30 nm was first deposited by atomic layer deposition to provide a high dielectric constant and interface flatness. Subsequently, a Si3N4 thin film with a thickness of 50 nm was deposited on the Al2O3 surface by magnetron sputtering to finally obtain a double-gate layer 3. The substrate temperature (≤200℃) must be strictly controlled during the deposition process to ensure that the film is dense and free of pinholes. After deposition, low-temperature annealing (150℃, 30 min) is performed to improve the interfacial bonding and overall flatness of the film.

[0084] 3) Fabrication of organic channel semiconductor layer 4

[0085] The DNTT feedstock was placed in a thermal evaporation source under a vacuum of 5 × 10⁻⁶. -6 Torr A thin film of 40 nm was deposited by evaporation at a rate of 40 nm; the substrate temperature was controlled at 60 °C to obtain an organic channel semiconductor layer with large grains, flatness, and low roughness.

[0086] 4) Fabrication of source electrode layer 5

[0087] On a substrate with an existing DNTT organic channel layer, regions were patterned using a metal mask, and metallic silver was deposited via vacuum thermal evaporation. The vacuum level of the deposition environment was controlled at 1×10⁻⁶. -5 Torr, evaporation rate remains The source electrode layer 5 is 100 nm thick; the substrate temperature is kept below 60 °C during deposition to avoid thermal damage to the organic channel layer;

[0088] 5) Fabrication of multilayer organic light-emitting unit 6 and drain electrode 7

[0089] After changing the mask, the functional layers were deposited sequentially under high vacuum conditions: First, a 3nm layer of MoO3 was deposited as a hole injection layer 61 to improve the interfacial work function and reduce the hole injection barrier; then, a 40nm layer of TAPC was deposited as a hole transport layer 62; a 25nm layer of CBP:Ir(MDQ)2(acac) (8wt%) was deposited on top as a light-emitting layer 63; next, a 50nm layer of BPhen was deposited as an electron transport layer 64; then, a 2nm layer of Liq was deposited as an electron injection layer 65; finally, a 100nm layer of aluminum was thermally evaporated as a drain electrode 7; the evaporation rate was controlled throughout the deposition process.

[0090] Example 3

[0091] A method for fabricating an asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels includes the following steps:

[0092] 1) Cleaning and preparation of substrate 1 / gate electrode 2

[0093] A PEN substrate with a thickness of approximately 125 micrometers was selected as the flexible substrate 1. The substrate was pre-treated with plasma cleaning to remove organic contaminants and increase surface energy. Subsequently, a silver nanowire solution uniformly dispersed in an alcohol solvent was spin-coated onto the surface of substrate 1. By controlling the spin-coating speed and time, a dense and continuous silver nanowire conductive network gate electrode 2 was obtained. To improve the uniformity and transparency of the conductive network, multiple spin-coatings or a combination of spraying and blade coating were used to control the film thickness. After film formation, the film was annealed at 120°C for 20 minutes to promote close contact between the nanowires and reduce contact resistance.

[0094] 2) Fabrication of the dual-gate dielectric layer 3

[0095] Silicon oxide films were prepared at 120 °C using a sol-gel method and then subjected to low-temperature aging and curing to reduce defect density. PMMA was then dissolved in an anisotropic solvent (such as anisotropic toluene or a toluene / butyl acetate mixture, concentration 2 wt%), filtered through a 0.22 μm filter, and spin-coated (4000 rpm, 60 s) onto a substrate at room temperature or with slight heating to obtain a PMMA coating of approximately 100 nm. This was followed by a short-term heat treatment at 120 °C (20 min) to remove residual solvent and densify the film, ultimately forming a dual-gate dielectric layer 3. To avoid miscibility or interfacial stress between the oxide layer and PMMA, the silicon suboxide was purged with nitrogen and activated briefly with plasma or UV ozone (10 s) after deposition to improve wettability and adhesion.

[0096] 3) Fabrication of organic channel semiconductor layer 4

[0097] Perylene imide powder was dissolved in a high-boiling-point organic solvent such as chlorobenzene or chloroform, with the concentration generally controlled at 10 mg / mL. The solution was stirred thoroughly at 60°C for several hours to ensure a homogeneous and transparent solution. After filtering the solution through a polytetrafluoroethylene (PTFE) membrane to remove large particulate impurities, it was dropwise added to the surface of a pretreated dielectric layer and spin-coated at 2000 rpm for 60 seconds to allow the solution to spread uniformly and form the organic channel semiconductor layer 4. After spin-coating, the sample was placed in a vacuum or nitrogen-protected environment and annealed at 120°C for 60 minutes.

[0098] 4) Fabrication of source electrode layer 5

[0099] On a substrate with an existing PDI organic channel layer, a patterned region was created using a metal mask, and gold was deposited as the source electrode layer 5 via vacuum thermal evaporation. The vacuum level of the deposition environment was controlled at 1×10⁻⁶. -5 Torr, evaporation rate remains The electrode thickness is 100 nm. During deposition, the substrate temperature is kept below 60°C to avoid thermal damage to the organic channel layer.

[0100] 5) Fabrication of multilayer organic light-emitting unit 6 and drain electrode 7

[0101] After changing the mask, a 10nm layer of F4-TCNQ was vacuum-deposited as the hole injection layer 61 to improve the interface work function; subsequently, a 30nm layer of NBP was deposited as the hole transport layer 62; SimCP-doped iridium complex Ir(ppy)3 (doping concentration 10-12wt%, thickness approximately 20nm) was selected as the light-emitting layer 63, and a 40nm layer of TmPyPB was used as the electron transport layer 64; then, a 1nm layer of Cs2CO3 was deposited as the electron injection layer 65, and finally, a 100nm layer of aluminum was thermally evaporated as the drain electrode 7; the deposition rate was controlled at [missing information]. The substrate temperature is kept below 60°C.

[0102] Example 4

[0103] A method for fabricating an asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels includes the following steps:

[0104] 1) Cleaning and preparation of substrate 1 / gate electrode 2

[0105] A PET film substrate 1 with a thickness of approximately 125 μm was selected. It was first soaked in deionized water, then ultrasonically cleaned in ethanol and isopropanol for 10 minutes each to remove surface contaminants and particulate impurities. Subsequently, it was dried with nitrogen and treated with low-power plasma or ultraviolet ozone for 10 minutes to improve surface hydrophilicity. For electrode preparation, a PEDOT:PSS aqueous dispersion was thoroughly stirred and filtered through a 0.22 μm filter membrane before spin-coating onto the surface of substrate 1 at a spin speed of 4000 rpm for 30 seconds to form a uniform film. After spin-coating, it was annealed at 100℃ for 10 minutes to remove moisture and obtain a dense, continuous conductive thin-film gate electrode 2.

[0106] 2) Fabrication of the dual-gate dielectric layer 3

[0107] PS powder was dissolved in a suitable organic solvent (such as chlorobenzene or toluene), with a concentration generally controlled at 2 wt%. The solution was thoroughly stirred and filtered through a 0.22 μm filter to remove particulate impurities. The treated solution was then spin-coated onto the surface of substrate 1 at a spin speed of 4000 rpm for 60 seconds. After spin-coating, the PS film was heated at 120°C for 20 minutes to dry and solidify, forming a uniform and dense bottom dielectric layer (approximately 50 nm thick). Subsequently, CYTOP polymer was dissolved in a suitable fluorine-based solvent (approximately 5 wt%), filtered, and then spin-coated onto the PS layer surface at a spin speed of 2000 rpm for 30 seconds. After spin-coating, the CYTOP film was annealed at 120°C for 20 minutes to evaporate the solvent and solidify, forming an upper dielectric layer approximately 100 nm thick, ultimately forming the dual-gate dielectric layer 3.

[0108] 3) Fabrication of 2,6-DPA organic channel semiconductor layer 4

[0109] The purified 2,6-diphenylanthracene (2,6-DPA) organic semiconductor material was loaded into a thermal evaporation source and placed in a vacuum deposition chamber, where a vacuum of 5 × 10⁻⁶ was applied. -6 Torr; Preheat substrate 1 to 60°C to improve molecular alignment and crystal growth; Control the evaporation source temperature to ensure material evaporation at a stable rate; Set the evaporation rate to [value missing]. Simultaneously, the substrate 1 is rotated to ensure uniform film thickness. After vapor deposition to the required thickness of 40 nm, heating is stopped and the film is allowed to cool naturally under nitrogen protection to obtain a 2,6-DPA organic channel semiconductor layer 4 with a smooth surface, moderate grain size, and good crystal orientation.

[0110] 4) Fabrication of source electrode layer 5

[0111] On a substrate with an existing PDI organic channel layer, a patterned region was created using a metal mask, and a copper electrode was deposited as the source electrode layer 5 via vacuum thermal evaporation. The vacuum level of the deposition environment was controlled at 5 × 10⁻⁶. -6Torr, evaporation rate remains Electrode thickness 100nm; During deposition, the substrate temperature is kept below 60℃ to avoid thermal damage to the organic channel layer;

[0112] 5) Fabrication of multilayer organic light-emitting unit 6 and drain electrode 7

[0113] After changing the mask, a 5nm layer of V₂O₅ is vacuum-deposited as a hole injection layer 61 to improve the interfacial work function; subsequently, a 30nm layer of TPD is deposited as a hole transport layer 62; an o-CzOXD-doped iridium complex Ir(dmp)₃ (doping concentration 10wt%, thickness approximately 18nm) is selected as the light-emitting layer 63, and a 40nm layer of B₃PYMPM is used as the electron transport layer 64; then, a 1nm layer of Li₂CO₃ is deposited as the electron injection layer 65, and finally, a 100nm layer of aluminum is thermally evaporated as the drain electrode 7; the deposition rate is controlled within the specified range throughout the entire deposition process. The substrate temperature is kept below 60°C.

[0114] Figure 2 This image shows the operational state of an asymmetric organic light-emitting transistor (OLED) with both horizontal and vertical transmission channels at a constant drain voltage of -20V. Under low gate bias, the device exhibits only weak localized emission. As the gate voltage increases, the channel gradually conducts, carrier injection is enhanced, and the emission intensity significantly increases and becomes more uniform, demonstrating a continuously controllable process from weak to strong light. A magnified emission view further illustrates that the device can achieve amplification and modulation of current and light even at low gate voltage. The results demonstrate that this structure achieves a unified approach to current amplification and emission modulation by utilizing the efficient carrier control of the horizontal channel and the effective optical coupling of the vertical channel.

[0115] Figure 3 This image shows a display array based on an asymmetric organic light-emitting transistor with a combined horizontal and vertical transmission channel. Each pixel in the array can be independently illuminated under gate voltage regulation, clearly displaying the letter "NPU," demonstrating the device's excellent current amplification and light output modulation capabilities. The uniform illumination and clear boundaries of the letters in different areas indicate that this structure maintains good pixel controllability and consistency in large-area integration, validating its potential in high-resolution display and driving integrated applications.

[0116] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. An asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels, characterized in that, The structure includes, from bottom to top, a substrate (1), a gate electrode (2), a double-gate dielectric layer (3), and an organic channel semiconductor layer (4); it also includes a source electrode layer (5) and a drain electrode (7); a multilayer organic light-emitting unit (6) is disposed between the source electrode layer (5) and the organic channel semiconductor layer (4); the multilayer organic light-emitting unit (6) has a vertically stacked structure; The source electrode layer (5) is disposed on one side of the organic channel semiconductor layer (4) and forms a lateral contact with the organic channel semiconductor layer (4); the drain electrode (7) is disposed on the top of the multilayer organic light-emitting unit (6); the electrode layer (5), the drain electrode (7) and the gate electrode (2) are arranged in a spatially non-coplanar manner.

2. An asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels according to claim 1, characterized in that, The multilayer organic light-emitting unit (6) includes a hole injection layer (61), a hole transport layer (62), a light-emitting layer (63), an electron transport layer (64), and an electron injection layer (65) stacked vertically from bottom to top.

3. An asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels according to claim 1, characterized in that, The material of the dual-gate dielectric layer (3) is a combination of high dielectric constant inorganic material and low dielectric constant inorganic material; the material of the dual-gate dielectric layer (3) is a combination of high dielectric constant inorganic material and low dielectric constant polymer material; the high dielectric constant is greater than 3.9; the low dielectric constant is less than 3.

9.

4. An asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels according to claim 1, characterized in that, The organic channel semiconductor layer (4) is an organic semiconductor thin film deposited by spin coating or thermal evaporation; the mobility of the organic semiconductor thin film is greater than 1 cm⁻¹. 2 V -1 s -1 .

5. An asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels according to claim 1, characterized in that, The hole injection layer (61) is made of inorganic oxides or organic electron acceptor materials; the hole transport layer (62) is made of small organic molecules with aromatic amine, carbazole or polycyclic aromatic hydrocarbon structures.

6. An asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels according to claim 1, characterized in that, The light-emitting layer (63) is an organic bipolar host material doped with an organic phosphorescent guest structure; the electron transport layer (64) is an electron-withdrawing organic small molecule compound. The electron injection layer (65) is an alkaline earth metal compound or an organic complex; The drain electrode (7) is an aluminum film; the reflectivity of the aluminum film is greater than 95%.

7. An asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels according to claim 1, characterized in that, The substrate (1) is made of inorganic glass or organic polymer film.

8. A method for fabricating an asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels as described in any one of claims 1 to 7, characterized in that, Includes the following steps: A double-gate dielectric layer (3) and an organic channel semiconductor layer (4) are sequentially fabricated on the surface of the gate electrode (2) on the substrate (1); A source electrode layer (5) is prepared on one side of the organic channel semiconductor layer (4), and a multilayer organic light-emitting unit (6) is prepared on the other side; finally, a drain electrode (7) is prepared on the top of the multilayer organic light-emitting unit (6).

9. The method for fabricating an asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels according to claim 8, characterized in that, The method for preparing the dual-gate dielectric layer (3) is spin coating, atomic deposition or vacuum evaporation; The organic channel semiconductor layer (4) is prepared by spin coating or vacuum evaporation. The method for preparing the multilayer organic light-emitting unit (6) is vacuum evaporation. The drain electrode (7) is prepared by vapor deposition.

10. The application of an asymmetric organic light-emitting transistor with both horizontal and vertical transmission channels as described in any one of claims 1 to 7 in the construction of pixel units in a static light-emitting array.

Images