Method and apparatus for sensing isolation status in gate driver circuitry

Abstract

The invention relates to a method and apparatus for sensing an isolation state in gate driver circuitry. An example apparatus includes charge injection circuitry (160, 204) having a first terminal, a second terminal, and a control terminal; a first inductor-capacitor (LC) circuitry (248, 250, 252) having a first terminal and a second terminal, the first terminal of the first LC circuitry coupled to the first terminal of the charge injection circuitry, the second terminal of the first LC circuitry coupled to the second terminal of the charge injection circuitry; a second LC circuitry (256, 258, 260) magnetically coupled to the first LC circuitry; and current sensing circuitry (180, 208) having an input terminal coupled to the control terminal of the charge injection circuitry.

Description

Technical Field

[0001] This specification generally relates to gate driver circuit systems, and more specifically, to methods and apparatus for sensing the state of isolated gate driver circuit systems. Background Technology

[0002] A gate driver circuit system generates a relatively high-power signal that controls a transistor circuit system in response to a relatively low-power signal. The gate driver circuit system allows a programmable circuit system to use digital signals to control a wide range of transistors, the power of which is lower than the higher-power signal required to drive the gate of some transistors. An isolated gate driver circuit system includes isolation circuitry for isolating the voltage of the relatively low-power digital signal from the voltage of the relatively high-power signal. Summary of the Invention

[0003] For a method and apparatus for sensing the state of an isolated gate driver circuit system, one example apparatus includes: a charge injection circuit system having a first terminal, a second terminal, and a control terminal; a first inductor-capacitor (LC) circuit system having a first terminal and a second terminal, the first terminal of the first LC circuit system being coupled to the first terminal of the charge injection circuit system, and the second terminal of the first LC circuit system being coupled to the second terminal of the charge injection circuit system; a second LC circuit system magnetically coupled to the first LC circuit system; and a current sensing circuit system having an input terminal coupled to the control terminal of the charge injection circuit system. Other examples are described.

[0004] For a method and apparatus for sensing the state of an isolated gate driver circuit system, an example apparatus includes: a charge injection circuit system having a first terminal, a second terminal, and a control terminal; a transformer having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first input terminal of the transformer being coupled to the first terminal of the charge injection circuit system, and the second input terminal of the transformer being coupled to the second terminal of the charge injection circuit system; a current sensing circuit system having an input terminal coupled to the control terminal of the charge injection circuit system; and a receiver circuit system having a first input terminal and a second input terminal, the first input terminal of the receiver circuit system being coupled to the first output terminal of the transformer, and the second input terminal of the receiver circuit system being coupled to the second output terminal of the transformer. Other examples are described.

[0005] For a method and apparatus for sensing the state of an isolated gate driver circuit system, an example apparatus includes: an example gate driver circuit system configured to: receive a pulse width modulation (PWM) signal, generate a current based on a logic state of the PWM signal, and generate a sinusoidal signal in response to the current; and a current sensing circuit system configured to: sense the generation of the current by the isolated gate driver circuit system, and set a logic state of a safety signal in response to sensing the generation of the current. Other examples are described. Attached Figure Description

[0006] Figure 1 It is a block diagram and schematic diagram of an example control system that includes an example isolated gate driver circuit system and an example programmable circuit system.

[0007] Figure 2 It includes an example charge injection circuit system and an example current sensing circuit system. Figure 1 A schematic diagram of an example of an isolated gate driver circuit system.

[0008] Figure 3A It includes an example output stage circuit system. Figure 1 A schematic diagram of another example of a control system.

[0009] Figure 3B It includes Figure 3A Another example of an output stage circuit system Figure 1 A schematic diagram of another example of a control system.

[0010] Figure 4 This is a flowchart illustrating example machine-readable instructions or example operations that can be used... Figure 1 and 2 Isolated gate driver circuit system Figure 1 Programmable circuit systems or more generally Figure 1 , 3A The example implementation of the 3B control system is used to carry out, instantiate, or execute at least one of them.

[0011] Figure 5 It is used to sense safety status indications. Figure 1 and 2 Timing diagram of an example operation of an isolated gate driver circuit system.

[0012] Figure 6 It is used for sensing Figure 1 and 2 Safety status indication of isolated gate driver circuit system Figure 1 A block diagram of an example implementation of a programmable circuit system.

[0013] Figure 7 This is a flowchart illustrating example machine-readable instructions or example operations that can be used... Figure 1 and 6 At least one of the example implementations, instantiations, or executions of the programmable circuit system is carried out to verify Figure 1 and 2 The safety status of the isolated gate driver circuit system.

[0014] Figure 8 It is used for sensing Figure 1 and 2 The safety status of the isolated gate driver circuit system Figure 1 and 6 Timing diagrams of example operations of a programmable circuit system.

[0015] Figure 9 This is a block diagram of an example processing platform containing a programmable circuit system configured to execute, instantiate, or perform example machine-readable instructions or execute... Figure 4 and 7 Example operations to implement Figure 1 and 6 Programmable circuit systems Figure 1 and 2 Isolated gate driver circuitry or more generally Figure 1 , 3A And the control system of 3B.

[0016] Figure 10 yes Figure 9 A block diagram of an example implementation of a programmable circuit system.

[0017] Figure 11 yes Figure 9 A block diagram of another example implementation of a programmable circuit system.

[0018] The figures are not necessarily drawn to scale. Generally, the same reference numerals in the figures and this specification refer to the same or similar features and / or parts (functionally and / or structurally). Although the figures show areas with clearly defined lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, boundaries or lines may be invisible, mixed, or irregular. Detailed Implementation

[0019] A gate driver circuit system generates a relatively high-power signal that controls a transistor circuit system in response to a relatively low-power signal. The gate driver circuit system allows a programmable circuit system to control a wide range of transistors with relatively low-power digital signals. An isolated gate driver circuit system includes an isolation circuit system for isolating the voltage of the relatively low-power digital signal from the voltage of the relatively high-power signal.

[0020] An electric motor converts electrical energy into torque, causing the shaft to rotate. Motor control systems control the amount of torque, direction of rotation, and speed of rotation by changing the power supply to the motor windings. Some control systems use pulse width modulation (PWM) signals to power the motor. The control system modifies the duty cycle of the PWM signal to adjust the power supply to the motor, thereby adjusting the torque. Some motors, called multiphase motors, use a series of PWM signals to cause the motor to rotate. The control system regulates the power supply to a multiphase motor by adjusting the phase of a reference PWM signal. Multiphase motors allow the control system to control the position of the multiphase motor by sequentially controlling the power supply with one or more PWM signals with different phases. The control system can control the motor's rotational speed by adjusting the frequency of the PWM signal. Adjusting the frequency of the PWM signal to adjust the rotational speed is called frequency conversion control.

[0021] The control system includes a driver circuitry that allows the control system to accurately control relatively high-power components, such as motors, using relatively low-power PWM signals. The driver circuitry includes high-side transistors, low-side transistors, a high-side gate driver circuitry, and a low-side gate driver circuitry. The high-side transistors control the supply of power from a power source (e.g., a positive DC bus power supply) to the load based on the high-side gate driver circuitry. The low-side transistors control the supply of power from the load to a common potential (e.g., ground) or a negative DC bus power supply based on the low-side gate driver circuitry. In operation, the high-side gate driver circuitry causes the high-side transistors to conduct current in response to a logic high state of the PWM signal. In such operation, the low-side gate driver circuitry causes the low-side transistors to conduct current in response to a logic low state of the PWM signal. However, to support transistor switching at increasingly larger supply voltages, the gate driver circuitry needs to generate increasingly larger gate control voltages.

[0022] An opto-isolated gate driver circuit system may include a load switch, a Schottky diode, a capacitor, a light-emitting diode (LED), a photosensor, and a programmable circuit system. The load switch couples a supply voltage (VCC) to the Schottky diode based on pulses from the programmable circuit system. The Schottky diode supplies current to the capacitor and the anode of the LED in response to the programmable circuit system closing the load switch. The LED transmits data to the photosensor based on a PWM signal. The opto-isolated gate driver circuit system operates on the primary side, which includes the load switch, Schottky diode, capacitor, and LED, using a first voltage. The secondary side of the opto-isolated gate driver circuit system with photosensor operates using a second voltage greater than the first voltage. The opto-isolated gate driver circuit system uses the photosensor to sense light from the LED, which represents data from the PWM signal. During a safe shutdown event, such as a Safe Torque Off (STO) event, the programmable circuit system disconnects the load switch to prevent current from being supplied to the LED, thereby preventing the secondary-side control transistor from operating. However, in systems requiring additional safety features, the opto-isolated gate driver circuit system cannot sense unsafe operating conditions following the load switch.

[0023] A complementary metal-oxide-semiconductor (CMOS) isolated gate driver circuit system includes a load switch, a Schottky diode, a capacitor, a charge injection circuit system, a transformer, and a programmable circuit system. The load switch couples the supply voltage (VCC) to the Schottky diode based on pulses from the programmable circuit system. The Schottky diode supplies power to the charge injection circuit system in response to the programmable circuit system closing the load switch. The charge injection circuit system excites the primary side of the transformer's LC circuit to generate a sinusoidal signal based on the logic state of a PWM signal. The charge injection circuit system represents a logic one of the PWM signal by exciting the LC circuit and a logic zero by not exciting the LC circuit. The sinusoidal signal induces a current in the secondary side of the transformer, which has another LC circuit. The induced current drives the gate of a transistor. During a safe shutdown event, such as an STO event, the programmable circuit system disconnects the load switch to prevent power supply to the charge injection circuit system, thereby preventing the secondary side from driving the transistor. However, in systems requiring additional safety features, the CMOS isolated gate driver circuit system cannot sense unsafe operating conditions following the load switch.

[0024] Some gate driver circuit systems include a clamping circuit system between the Schottky diode and the charge injection circuit system. During a shutdown event, the clamping circuit system couples the input of the charge injection circuit system or the anode side of the LED to a common potential (e.g., ground). This redundant safety feature reduces the likelihood that adverse operating conditions will cause the gate driver circuit system to continue operating after a shutdown event.

[0025] Some gate driver circuitry includes a comparator and additional isolation paths to sense safe operating conditions. The comparator generates a safety signal in response to a comparison of the gate driver circuitry's output with a reference voltage. The comparator supplies the safety signal to a programmable circuitry across the additional isolation path. The programmable circuitry determines whether the gate driver circuitry is operating safely in response to a comparison of the safety signal with a PWM signal. This sensing using opto-isolated gate driver circuitry requires additional LEDs and light sensors to isolate the secondary-side safety signal from the primary-side voltage. CMOS-isolated gate driver circuitry requires additional transformers and current injection circuitry to isolate the secondary-side safety signal from the primary side. This additional circuitry increases the system-on-chip (SoC) size of the gate driver circuitry.

[0026] The examples described herein include methods and apparatus for sensing the state of an isolated gate driver circuit system. In some of the described examples, the isolated gate driver circuit system includes a charge injection circuit system, a transformer circuit system, a receiver circuit system, and a current sensing circuit system. The charge injection circuit system supplies current to the transformer in response to a PWM signal. In example operation, the charge injection circuit system supplies current to the transformer circuit system in response to a logic-1 state of the PWM signal. In such example operation, the current from the charge injection circuit system excites the primary-side LC circuit of the transformer circuit system, which generates a sinusoidal signal to pass through an isolation barrier. The secondary-side LC circuit of the transformer circuit system conducts current in response to the sinusoidal signal from the primary-side LC circuit. The receiver circuit system generates a gate control signal in response to the current from the secondary-side LC circuit of the transformer circuit system.

[0027] A current sensing circuit system is coupled to a control terminal of a charge injection circuit system, which controls the current supply to the transformer circuit system. The current sensing circuit system generates a safety signal based on the current conduction in the charge injection circuit system. In such instances, the programmable circuit system can determine the operating state of the isolated gate driver circuit system in response to a comparison of the safety signal and a PWM signal. For example, the programmable circuit system senses that the isolated gate driver circuit system is not in a safe operating state in response to a safety signal indicating that the current injection circuit system is supplying current to the transformer circuit system. In such instances, the logic state of the PWM signal should not result in the supply of current to the transformer circuit system. Advantageously, the isolated gate driver circuit system described herein senses the current in the transformer circuit system to determine the state of the isolated gate driver circuit system.

[0028] Figure 1 This is a block diagram of an example control system 100. Figure 1In one example, the control system 100 includes a programmable circuit system 105, a first driver circuit system 110, a second driver circuit system 115, a third driver circuit system 120, a motor 125, and an output stage circuit system 130. Figure 1 The example driver circuit system 110 includes a first example transistor 135, a second example transistor 140, a first example isolated gate driver circuit system 145, and a second example isolated gate driver circuit system 150. Figure 1 The example isolated driver circuit system 145 includes an example logic circuit system 155, an example charge injection circuit system 160, an example transformer circuit system 165, an example receiver circuit system 170, an example deglitch circuitry 175, and an example current sensing circuit system 180.

[0029] Programmable circuit system 105 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of programmable circuit system 105 is coupled to a Safe Torque Off (STO) input terminal of control system 100, which supplies an STO signal. The STO signal indicates the removal of torque-generating power from motor 125. The second terminal of programmable circuit system 105 is coupled to driver circuit system 110. The third terminal of programmable circuit system 105 is coupled to driver circuit system 115. The fourth terminal of programmable circuit system 105 is coupled to driver circuit system 120. The fifth terminal of programmable circuit system 105 is coupled to output stage circuit system 130. In some instances, programmable circuit system 105 is shown or described as a safety microcontroller unit (MCU), programmable logic device, or logic circuit system that includes redundant safety features. Redundant safety features reduce the likelihood of inaccurate control of driver circuit systems 110, 115, and 120, and improve safety by reducing the inaccuracy of control system 100. The following is in conjunction with… Figure 6 , 9 Examples of programmable circuit system 105 are further shown and described in 10 and 11. The following is in conjunction with... Figure 4 and 7 Example operations of a programmable circuit system are shown and described.

[0030] The driver circuit system 110 has a first terminal, a second terminal, and a third terminal. The first terminal of the driver circuit system 110 is coupled to the programmable circuit system 105. The second terminal of the driver circuit system 110 is coupled to the motor 125. The third terminal of the driver circuit system 110 is coupled to the output stage circuit system 130.

[0031] The driver circuit system 115 has a first terminal, a second terminal, and a third terminal. The first terminal of the driver circuit system 115 is coupled to the programmable circuit system 105. The second terminal of the driver circuit system 115 is coupled to the motor 125. The third terminal of the driver circuit system 115 is coupled to the output stage circuit system 130.

[0032] The driver circuit system 120 has a first terminal, a second terminal, and a third terminal. The first terminal of the driver circuit system 120 is coupled to the programmable circuit system 105. The second terminal of the driver circuit system 120 is coupled to the motor 125. The third terminal of the driver circuit system 120 is coupled to the output stage circuit system 130.

[0033] Motor 125 has a first terminal, a second terminal, and a third terminal. The first terminal of motor 125 is coupled to driver circuit system 110. The second terminal of motor 125 is coupled to driver circuit system 115. The third terminal of motor 125 is coupled to driver circuit system 120. In some embodiments, motor 125 is configured to convert electrical power from driver circuit systems 110, 115, and 120 into mechanical power. Although in Figure 1 In one instance, the control system 100 is configured to control the motor 125, but in other instances, the control system 100 may be modified to supply power to alternative components.

[0034] The output stage circuit system 130 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the output stage circuit system 130 is coupled to the driver circuit system 110. The second terminal of the output stage circuit system 130 is coupled to the driver circuit system 115. The third terminal of the output stage circuit system 130 is coupled to the driver circuit system 120. The fourth terminal of the output stage circuit system 130 is coupled to the programmable circuit system 105. (The following is in conjunction with...) Figure 3A and 3B An example of the output stage circuit system 130 is further shown and described.

[0035] Transistor 135 has a first terminal, a second terminal, and a control terminal. Figure 1 In one example, transistor 135 further includes an example body diode 135A, a feature of transistor 135 implemented in a die. In other examples, the body diode 135A may not be shown or described. The first terminal of transistor 135 is coupled to the supply power supply voltage (V). DD The power supply terminal of transistor 135 is connected to motor 125 and transistor 140. The control terminal of transistor 135 is connected to isolated gate driver circuit system 145.

[0036] Transistor 140 has a first terminal, a second terminal, and a control terminal. Figure 1In one example, transistor 140 further includes an example body diode 140A, a feature of transistor 140 implemented in a die. In other examples, the body diode 140A may not be shown or described. A first terminal of transistor 140 is coupled to motor 125 and transistor 135. A second terminal of transistor 140 is coupled to a common terminal supplying a common potential (e.g., ground, AVDD, etc.). A control terminal of transistor 140 is coupled to an isolated gate driver circuit system 150. Figure 1 In this example, transistors 135 and 140 form a half-bridge circuit system that drives the output of driver circuit system 110 in response to the switching of transistors 135 and 140. In this example, transistor 135 and isolated gate driver circuit system 145 are referred to as the high-side component, which controls the power supply from the power supply terminal to motor 125. Additionally, transistor 140 and isolated gate driver circuit system 150 are referred to as the low-side component, which controls the power supply from motor 125 to a common terminal.

[0037] exist Figure 1 In the examples, transistors 135 and 140 are NPN bipolar junction transistors (BJTs). Alternatively, transistors 135 and 140 can be n-channel field-effect transistors (FETs), n-channel insulated-gate bipolar transistors (IGBTs), n-channel junction field-effect transistors (JFETs), n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), or slightly modified p-type equivalent devices. Transistors 135 and 140 can be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 135 and 140 can be implemented on / above a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0038] An isolated gate driver circuit system 145 has a first terminal, a second terminal, and a third terminal. The first terminal of the isolated gate driver circuit system 145 is coupled to a programmable circuit system 105. The second terminal of the isolated gate driver circuit system 145 is coupled to a transistor 135. The third terminal of the isolated gate driver circuit system 145 is coupled to an output stage circuit system 130. In some embodiments, the isolated gate driver circuit system 145 further has a fourth terminal coupled to the programmable circuit system 105. In such embodiments, the programmable circuit system 105 is configured to supply an enable signal (EN) that prevents (e.g., disables) the isolated gate driver circuit system 145 from controlling the transistor 135.

[0039] An isolated gate driver circuit system 150 has a first terminal, a second terminal, and a third terminal. The first terminal of the isolated gate driver circuit system 150 is coupled to a programmable circuit system 105. The second terminal of the isolated gate driver circuit system 150 is coupled to a transistor 140. The third terminal of the isolated gate driver circuit system 150 is configured to be coupled to an output stage circuit system, such as an output stage circuit system 130. In some instances, the control system 100 includes multiple instances of the output stage circuit system 130. For example, the control system 100 includes a first instance and a second instance of the output stage circuit system 130. In such instances, the first instance of the output stage circuit system 130 is specifically for the high-side isolated gate driver circuit system 145 of driver circuit systems 110, 115, 120, and the second instance of the output stage circuit system 130 is specifically for the low-side isolated gate driver circuit system 150 of driver circuit systems 110, 115, 120. In some instances, the isolated gate driver circuit system 150 further has a fourth terminal coupled to the programmable circuit system 105. In such an example, the programmable circuit system 105 is configured to supply an enable signal (EN) that prevents the isolated gate driver circuit system 150 from controlling the transistor 140.

[0040] Logic circuit system 155 has a first terminal and a second terminal. The first terminal of logic circuit system 155 is coupled to programmable circuit system 105. The second terminal of logic circuit system 155 is coupled to charge injection circuit system 160. In some embodiments, logic circuit system 155 further has a third terminal coupled to programmable circuit system 105. In such embodiments, programmable circuit system 105 supplies an enable signal to logic circuit system 155. The following is in conjunction with... Figure 2 Further examples of the logic circuit system 155 are shown and described.

[0041] The charge injection circuit system 160 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the charge injection circuit system 160 is coupled to a logic circuit system 155. The second and third terminals of the charge injection circuit system 160 are coupled to a transformer circuit system 165. The fourth terminal of the charge injection circuit system 160 is coupled to a current sensing circuit system 180. (The following is in conjunction with...) Figure 2 An example of the charge injection circuit system 160 is further shown and described below. Figure 4 Example operation of the charge injection circuit system 160 is shown and described.

[0042] Transformer circuit system 165 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of transformer circuit system 165 are coupled to charge injection circuit system 160. The third and fourth terminals of transformer circuit system 165 are coupled to receiver circuit system 170. In some instances, transformer circuit system 165 is referred to as an isolation transformer, which uses current isolation to electrically isolate charge injection circuit system 160 from receiver circuit system 170. The following description... Figure 2 An example of transformer circuit system 165 is further shown and described.

[0043] Receiver circuitry 170 has a first terminal, a second terminal, and a third terminal. The first and second terminals are coupled to transformer circuitry 165. The third terminal of receiver circuitry 170 is coupled to de-glitch circuitry 175. In some instances, receiver circuitry 170 is an amplifier circuitry configured to generate an output in response to current from transformer circuitry 165.

[0044] The degluing circuit system 175 has a first terminal and a second terminal. The first terminal of the degluing circuit system 175 is coupled to the receiver circuit system 170. The second terminal of the degluing circuit system 175 is coupled to the transistor 135. In some embodiments, the degluing circuit system 175 is configured as a filter that removes relatively high-frequency signals from the output of the isolated gate driver circuit system 145. Figure 7 Example operation of the deburring circuit system 175 is further shown and described.

[0045] The current sensing circuit system 180 has a first terminal and a second terminal. The first terminal of the current sensing circuit system 180 is coupled to the charge injection circuit system 160. The second terminal of the current sensing circuit system 180 is coupled to the output stage circuit system 130. Figure 1 In this example, the current sensing circuitry 180 is configured to generate a safety signal (SAFE) in response to the current in the charge injection circuitry 160. The safety signal indicates the state of the isolated gate driver circuitry 145. The following is in conjunction with... Figure 5 and 8 Examples of safety signals are shown and described below. (The following text is combined with...) Figure 2 An example of a current sensing circuit system 180 is shown and described.

[0046] In the example operation, the programmable circuit system 105 generates a first PWM signal with different phases. U ), second PWM signal (PWM) V ) and the third PWM signal (PWM) WProgrammable circuit system 105 supplies one of the PWM signals to each of driver circuit systems 110, 115, and 120. Different phases of the PWM signals sequentially control the power supply to driver circuit systems 110, 115, and 120 to rotate motor 125. Figure 1 In this example, control system 100 is configured as a three-phase motor control system that uses three signals to drive motor 125. Alternatively, control system 100 can be modified to support any number of phases to control the motor.

[0047] In example operation, isolated gate driver circuitry 145 receives a PWM signal from programmable circuitry 105. Logic circuitry 155 logically combines an enable signal with the PWM signal to control charge injection circuitry 160. In some instances, logic circuitry 155 generates a combined logic signal and an inverted combined logic signal. In such instances, logic circuitry 155 uses the combined logic signal to control charge injection circuitry 160. Charge injection circuitry 160 supplies current to transformer circuitry 165 based on the state of the combined logic signal. For example, in response to both the PWM signal and the enable signal being logic high, charge injection circuitry 160 supplies current to transformer circuitry 165. Transformer circuitry 165 generates an oscillating current that crosses an isolation barrier. This isolation is called current isolation. Receiver circuitry 170 receives the oscillating current that crosses the isolation barrier. Advantageously, transformer circuitry 165 isolates the voltages of charge injection circuitry 160 and programmable circuitry 105 from the voltages of receiver circuitry 170 and transistors 135, 140. Advantageously, the transformer circuit system 165 allows the isolated gate driver circuit system 145 to generate a control signal with a relatively high voltage based on a signal with a relatively low voltage.

[0048] In example operation, current sensing circuitry 180 monitors charge injection circuitry 160. Current sensing circuitry 180 generates a safety signal based on the current supplied by charge injection circuitry 160 to transformer circuitry 165. For example, current sensing circuitry 180 sets the safety signal to logic low in response to sensing that charge injection circuitry 160 is supplying current. In such an example, current sensing circuitry 180 sets the safety signal to logic high in response to sensing that charge injection circuitry 160 is not supplying current. Alternatively, in other examples, the safety signal may be an active low signal (nSAFE). Output stage circuitry 130 logically combines the safety signals from driver circuitry 110, 115, and 120 to generate a system fault signal. Programmable circuitry 105 determines that control system 100 is operating safely in response to a comparison of the system fault signal with a PWM signal. In such example operation, programmable circuitry 105 detects an unsafe condition of control system 100 in response to a match between the PWM signal and the safety signal. The following is combined with... Figure 4 and 7 Further examples of operation of the control system 100 are shown and described.

[0049] Figure 2 This is a schematic diagram of an example isolated gate driver circuit system 200, which is... Figure 1 Examples of isolated gate driver circuit systems 145 and 150. In Figure 2 In one example, the isolated gate driver circuit system 200 includes a logic circuit system 202, a charge injection circuit system 204, a transformer circuit system 206, and a current sensing circuit system 208. Figure 2 The example logic circuit system 202 includes an example logic device 210, a first example inverter 212, and a second example inverter 214. Figure 2 The example charge injection circuit system 204 includes an example current source circuit system 216, a first example transistor 218, a second example transistor 220, a third example transistor 222, a fourth example transistor 224, a fifth example transistor 226, a sixth example transistor 228, a seventh example transistor 230, an example transmission gate 232, an eighth example transistor 234, a ninth example transistor 236, a tenth example transistor 238, an eleventh example transistor 240, a twelfth example transistor 242, a thirteenth example transistor 244, and a fourteenth example transistor 246. Figure 2 The example transformer circuit system 206 includes a first example capacitor 248, a second example capacitor 250, a first example inductor 252, an example isolation barrier 254, a second example inductor 256, a third example capacitor 258, and a fourth example capacitor 260. Figure 2 The example current sensing circuit system 208 includes an example transistor 262, an example resistor 264, an example comparator circuit system 266, an example level shifter circuit system 268, an example buffer circuit system 270, and an example inverter 272.

[0050] The isolated gate driver circuit system 200 has a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a third output terminal. The first input terminal of the isolated gate driver circuit system 200 is configured to couple to... Figure 1 The programmable circuit system 105 supplies a PWM signal. The second input terminal of the isolated gate driver circuit system 200 is configured to couple to... Figure 1 The programmable circuit system 105 supplies an enable signal (EN). The first and second output terminals of the isolated gate driver circuit system 200 are configured to couple to... Figure 1 The receiver circuit system 170 receives the oscillating current. The third output terminal of the isolated gate driver circuit system 200 is configured to couple to... Figure 1 The output stage circuit system 130 receives a safety signal (SAFE). (The following is in conjunction with...) Figure 5 Examples of the inputs and outputs of an isolated gate driver circuit system 200 are shown and described below. Figure 4 An example operation of the isolated gate driver circuit system 200 is shown and described.

[0051] The logic circuit system 202 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the logic circuit system 202 is coupled to a first input terminal of the isolated gate driver circuit system 200, which supplies a PWM signal. The second terminal of the logic circuit system 202 is coupled to a second input terminal of the isolated gate driver circuit system 200, which supplies an enable signal. The third and fourth terminals of the logic circuit system 202 are coupled to a charge injection circuit system 204. Figure 2 In this example, logic circuit system 202 is configured to supply a combinational control signal (InZ) and an inverted combinational control signal (InZZ) to charge injection circuit system 204. Logic circuit system 202 is... Figure 1 An example of logic circuit system 155.

[0052] The charge injection circuit system 204 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first and second terminals of the charge injection circuit system 204 are coupled to a logic circuit system 202, which supplies a combined control signal and an inverted combined control signal. The third and fourth terminals of the charge injection circuit system 204 are coupled to a transformer circuit system 206. The fifth terminal of the charge injection circuit system 204 is coupled to a current sensing circuit system 208. The charge injection circuit system 204 is... Figure 1 An example of a charge injection circuit system 160.

[0053] The transformer circuit system 206 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the transformer circuit system 206 are coupled to a charge injection circuit system 204. The third and fourth terminals of the transformer circuit system 206 are coupled to a first and a second output terminal of an isolated gate driver circuit system 200, the first and second output terminals being configured to supply oscillating current to a receiver circuit system 170. The transformer circuit system 206 is... Figure 1 An example of a transformer circuit system 165.

[0054] The current sensing circuit system 208 has a first terminal and a second terminal. The first terminal of the current sensing circuit system 208 is coupled to the charge injection circuit system 204. The second terminal of the current sensing circuit system 208 is coupled to a third output terminal of the isolated gate driver circuit system 200, which supplies a safety signal to the output stage circuit system 130. The current sensing circuit system 208 is... Figure 1 An example of a current sensing circuit system 180.

[0055] Logic device 210 has a first terminal, a second terminal, and a third terminal. The first terminal of logic device 210 is coupled to a first input terminal of isolated gate driver circuitry 200, which receives a PWM signal from programmable circuitry 105. The second terminal of logic device 210 is coupled to a second input terminal of isolated gate driver circuitry 200, which receives an enable signal from programmable circuitry 105. The third terminal of logic device 210 is coupled to inverter 212. Figure 2 In this example, logic device 210 is an AND gate. In other examples, logic device 210 may be implemented using one or more alternative logic devices.

[0056] Inverter 212 has a first terminal and a second terminal. The first terminal of inverter 212 is coupled to logic device 210. The second terminal of inverter 212 is coupled to charge injection circuit system 204 and inverter 214. Figure 2In this example, inverter 212 generates a combination control signal based on the output of logic device 210.

[0057] Inverter 214 has a first terminal and a second terminal. The first terminal of inverter 214 is coupled to charge injection circuit system 204 and inverter 212. The second terminal of inverter 214 is coupled to charge injection circuit system 204. Figure 2 In this example, inverter 214 generates an inverted combined control signal based on the combined control signal from inverter 212.

[0058] The current source circuit system 216 has a first terminal and a second terminal. The first terminal of the current source circuit system 216 is coupled to a power supply terminal supplying the power supply voltage (VDD). The second terminal of the current source circuit system 216 is coupled to transistors 218, 220, and 222.

[0059] Transistor 218 has a first terminal, a second terminal, and a control terminal. The first terminal and the control terminal of transistor 218 are coupled to current source circuit system 216 and transistors 220 and 222. The second terminal of transistor 218 is coupled to a common terminal supplying a common potential (e.g., ground, AVSS, etc.).

[0060] Transistor 220 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 220 is coupled to current source circuit system 216 and transistors 218 and 222. The second terminal of transistor 220 is coupled to a common terminal supplying a common potential. The control terminal of transistor 220 is coupled to a first output terminal of logic circuit system 202, the first output terminal supplying a combined control signal.

[0061] Transistor 222 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 222 is coupled to transistor 224. The second terminal of transistor 222 is coupled to a common terminal supplying a common potential. The control terminal of transistor 222 is coupled to current source circuit system 216 and transistors 218 and 220.

[0062] Transistor 224 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 224 is coupled to current sensing circuit system 208 and transistors 226, 228, and 242. The second terminal of transistor 224 is coupled to transistor 222. The control terminal of transistor 224 is coupled to the second output terminal of logic circuit system 202, the second output terminal supplying an inverted combinational control signal.

[0063] Transistor 226 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 226 is coupled to a power supply terminal that supplies the power supply voltage. The second terminal of transistor 226 is coupled to current sensing circuit system 208 and transistors 224, 228, and 242. The control terminal of transistor 226 is coupled to a second output terminal of logic circuit system 202, the second output terminal supplying an inverted combination control signal.

[0064] Transistor 228 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 228 is coupled to a power supply terminal that supplies the power supply voltage. The second terminal of transistor 228 is coupled to current sensing circuit system 208 and transistors 224, 226, and 242. The control terminal of transistor 228 is coupled to transistors 230 and 236 and transmission gate 232.

[0065] Transistor 230 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 230 is coupled to a power supply terminal that supplies the power supply voltage. The second terminal of transistor 230 is coupled to transistors 228, 236, and transmission gate 232. The control terminal of transistor 230 is coupled to a second output terminal of logic circuit system 202, the second output terminal supplying an inverted combinational control signal.

[0066] Transmission gate 232 has a first terminal, a second terminal, a first control terminal, and a second control terminal. The first terminal of transmission gate 232 is coupled to transistors 228, 230, and 236. The second terminal of transmission gate 232 is coupled to transistors 234, 236, 238, and 240. The first control terminal of transmission gate 232 is coupled to a first output terminal of logic circuit system 202, which supplies a combined control signal. The second control terminal of transmission gate 232 is coupled to a second output terminal of logic circuit system 202, which supplies an inverted combined control signal. In some instances, transmission gate 232 is shown or described as a pair of transistors configured to control the direction of current.

[0067] Transistor 234 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 234 is coupled to transmission gate 232 and transistors 236, 238, and 240. The second terminal of transistor 234 is coupled to a common terminal supplying a common potential. The control terminal of transistor 234 is coupled to a first output terminal of logic circuit system 202, the first output terminal supplying a combination control signal.

[0068] Transistor 236 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 236 is coupled to a power supply terminal that supplies the power supply voltage. The second terminal 232 of transistor 236 is coupled to transmission gates 234, 238, and 240. The control terminal of transistor 236 is coupled to transistors 228 and 230 and transmission gate 232.

[0069] Transistor 238 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 238 is coupled to transmission gate 232 and transistors 234, 236, and 240. The second terminal of transistor 238 is coupled to transformer circuit system 206 and transistors 240, 244, and 246. The control terminal of transistor 238 is coupled to transformer circuit system 206 and transistors 240, 244, and 246.

[0070] Transistor 240 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 240 is coupled to transmission gate 232 and transistors 234, 236, and 238. The second terminal of transistor 240 is coupled to transformer circuit system 206 and transistors 238, 244, and 246. The control terminal of transistor 240 is coupled to transformer circuit system 206 and transistors 238, 244, and 246.

[0071] Transistor 242 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 242 is coupled to a power supply terminal that supplies the power supply voltage. The second terminal of transistor 242 is coupled to transistors 244 and 246. The control terminal of transistor 242 is coupled to current sensing circuit system 208 and transistors 224, 226, and 228.

[0072] Transistor 244 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 244 is coupled to transistors 242 and 246. The second terminal of transistor 244 is coupled to transformer circuit system 206 and transistors 238, 240, and 246. The control terminal of transistor 244 is coupled to transformer circuit system 206 and transistors 238, 240, and 246.

[0073] Transistor 246 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 246 is coupled to transistors 242 and 244. The second terminal of transistor 246 is coupled to transformer circuit system 206 and transistors 238, 240, and 244. The control terminal of transistor 246 is coupled to transformer circuit system 206 and transistors 238, 240, and 244.

[0074] Capacitor 248 has a first terminal and a second terminal. The first terminal of capacitor 248 is coupled to transistors 238, 240, 244, 246 and inductor 252. The second terminal of capacitor 248 is coupled to capacitor 250 and a common terminal supplying a common potential.

[0075] Capacitor 250 has a first terminal and a second terminal. The first terminal of capacitor 250 is coupled to transistors 238, 240, 244, 246 and inductor 252. The second terminal of capacitor 250 is coupled to a common terminal supplying a common potential.

[0076] Inductor 252 has a first terminal and a second terminal. The first terminal of inductor 252 is coupled to transistors 238, 240, 244, 246 and capacitor 248. The second terminal of inductor 252 is coupled to transistors 238, 240, 244, 246 and capacitor 250. Inductor 252 is magnetically coupled to inductor 256 across isolation barrier 254. Figure 2 In this example, capacitors 248 and 250 and inductor 252 form a first inductor-capacitor (LC) circuit system, which may be referred to as an LC tank. In example operation, the current oscillating between capacitors 248 and 250 and inductor 252 in the LC circuit system generates a sinusoidal signal that passes through isolation barrier 254. In this type of example operation, the LC circuit system begins to generate a sinusoidal signal in response to current from charge injection circuit systems 160 and 204.

[0077] An isolation barrier 254 is coupled between inductors 252 and 256. Isolation barrier 254 is an illustrative representation of the separation of inductors 252 and 256. Figure 2 In some instances, the circuitry above the line representing isolation barrier 254 is considered the primary side, and the circuitry below isolation barrier 254 is considered the secondary side. In some instances, isolation barrier 254 is shown as part of a transformer (e.g., a shared core), with inductors 252, 256 wound around said portion.

[0078] Inductor 256 has a first terminal and a second terminal. The first terminal of inductor 256 is coupled to capacitor 258 and a first output terminal of isolated gate driver circuitry 200, the first output terminal being configured to be coupled to receiver circuitry 170. The second terminal of inductor 256 is coupled to capacitor 260 and a second output terminal of isolated gate driver circuitry 200, the second output terminal being configured to be coupled to receiver circuitry 170. Inductor 256 is magnetically coupled to inductor 252.

[0079] Capacitor 258 has a first terminal and a second terminal. The first terminal of capacitor 258 is coupled to inductor 256 and a first output terminal of isolated gate driver circuitry 200, the first output terminal being configured to be coupled to receiver circuitry 170. The second terminal of capacitor 258 is coupled to capacitor 260 and a common terminal supplying a common potential.

[0080] Capacitor 260 has a first terminal and a second terminal. The first terminal of capacitor 260 is coupled to the inductor 256 and the second output terminal of the isolated gate driver circuit system 200, the second output terminal being configured to be coupled to the receiver circuit system 170. The second terminal of capacitor 260 is coupled to capacitor 258 and a common terminal supplying a common potential. Figure 2 In this example, inductor 256 and capacitors 258, 260 form a second LC circuit system, which may be referred to as an LC tank. In example operation, the current oscillates between inductor 256 and capacitors 258, 260 in response to a sinusoidal signal generated by inductor 252 of the first LC circuit system. In this example operation, the sinusoidal signal passes through isolation barrier 254 to induce a current in inductor 256, thereby generating a secondary sinusoidal signal in inductor 256 and capacitors 258, 260.

[0081] Transistor 262 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 262 is coupled to a power supply terminal that supplies the power supply voltage. The second terminal of transistor 262 is coupled to resistor 264 and comparator circuit system 266. The control terminal of transistor 262 is coupled to transistors 224, 226, 228, and 242 of charge injection circuit system 204.

[0082] Resistor 264 has a first terminal and a second terminal. The first terminal of resistor 264 is coupled to transistor 262 and comparator circuit system 266. The second terminal of resistor 264 is coupled to a common terminal supplying a common potential.

[0083] Comparator circuit system 266 has a first terminal and a second terminal. The first terminal of comparator circuit system 266 is coupled to transistor 262 and resistor 264. The second terminal of comparator circuit system 266 is coupled to level shifter circuit system 268. In some instances, comparator circuit system 266 is shown or described as an amplifier circuit system.

[0084] The level shifter circuit system 268 has a first terminal and a second terminal. The first terminal of the level shifter circuit system 268 is coupled to the comparator circuit system 266. The second terminal of the level shifter circuit system 268 is coupled to the buffer circuit system 270.

[0085] The buffer circuit system 270 has a first terminal and a second terminal. The first terminal of the buffer circuit system 270 is coupled to the level shifter circuit system 268. The second terminal of the buffer circuit system 270 is coupled to the inverter 272.

[0086] Inverter 272 has a first terminal and a second terminal. The first terminal of inverter 272 is coupled to buffer circuitry 270. The second terminal of inverter 272 is coupled to a third output terminal of isolated gate driver circuitry 200, which is configured to couple to output stage circuitry 130. Alternatively, in some embodiments, current sensing circuitry 208 may be modified to remove or replace inverter 272. In such embodiments, current sensing circuitry 208 generates a low-level active signal.

[0087] exist Figure 2 In the examples, transistors 218, 220, 222, 224, 234, 238, and 240 are n-channel MOSFETs. Alternatively, transistors 218, 220, 222, 224, 234, 238, and 240 can be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or slightly modified p-type equivalents. Figure 2 In the examples, transistors 226, 228, 230, 236, 242, 244, 246, and 262 are p-channel MOSFETs. Alternatively, transistors 226, 228, 230, 236, 242, 244, 246, and 262 can be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or slightly modified N-type equivalent devices. Transistors 218, 220, 222, 224, 226, 228, 230, 234, 236, 238, 240, 242, 244, 246, and 262 can be depletion-mode devices, extended-drain devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 218, 220, 222, 224, 226, 228, 230, 234, 236, 238, 240, 242, 244, 246, and 262 can be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0088] Figure 3A This is a schematic diagram of an example control system 300, which is... Figure 1 Another example of a control system 100. In Figure 3A In one example, the control system 300 includes a first driver circuit system 305, a second driver circuit system 310, a third driver circuit system 315, and an output stage circuit system 320. Figure 3AThe example output stage circuit system 320 includes an example logic device 325.

[0089] The control system 300 has a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal. The first input terminal, the second input terminal, and the third input terminal of the control system 300 are configured to couple to... Figure 1 The programmable circuit system 105 supplies a first PWM signal (PWM signal). U ), second PWM signal (PWM) V ) and the third PWM signal (PWM) W The first, second, and third output terminals of the control system 300 are configured to couple to... Figure 1 The motor 125. A fourth output terminal of the control system 300 is configured to couple to a programmable circuit system 105, which receives a system fault signal (nFAULT). The system fault signal indicates the state of the driver circuit systems 305, 310, and 315. For example, the system fault signal is cleared in response to current supplied across transformer circuit systems 165 and 206 to one or more of the driver circuit systems 305, 310, and 315.

[0090] The driver circuit system 305 has an input terminal, a first output terminal, and a second output terminal. The input terminal of the driver circuit system 305 is coupled to the first input terminal of the control system 300, which supplies a first PWM signal from the programmable circuit system 105. The first output terminal of the driver circuit system 305 is coupled to the motor 125. The second output terminal of the driver circuit system 305 is coupled to the output stage circuit system 320. The driver circuit system 305 is... Figure 1 An example of a driver circuit system 110.

[0091] The driver circuit system 310 has an input terminal, a first output terminal, and a second output terminal. The input terminal of the driver circuit system 310 is coupled to the second input terminal of the control system 300, which supplies a second PWM signal from the programmable circuit system 105. The first output terminal of the driver circuit system 310 is coupled to the motor 125. The second output terminal of the driver circuit system 310 is coupled to the output stage circuit system 320. The driver circuit system 310 is... Figure 1 An example of the driver circuit system 115.

[0092] The driver circuit system 315 has an input terminal, a first output terminal, and a second output terminal. The input terminal of the driver circuit system 315 is coupled to the first input terminal of the control system 300, which supplies a third PWM signal from the programmable circuit system 105. The first output terminal of the driver circuit system 315 is coupled to the motor 125. The second output terminal of the driver circuit system 315 is coupled to the output stage circuit system 320. The driver circuit system 315 is... Figure 1 An example of a driver circuit system 120.

[0093] The output stage circuit system 320 has a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal of the output stage circuit system 320 is coupled to supply a first safety signal (SAFE). U The driver circuit system 305. The safety signal indicates the state of the driver circuit system 305. In a first state, the driver circuit system 305 supplies current to the transformer circuit systems 165 and 206. In a second state, the driver circuit system 305 does not supply current to the transformer circuit systems 165 and 206. The second input terminal of the output stage circuit system 320 is coupled to supply the second safety signal (SAFE). V The second safety signal indicates the state of the driver circuit system 310. The third input terminal of the output stage circuit system 320 is coupled to supply a third safety signal (SAFE). W The third safety signal indicates the state of the driver circuit system 315. The output terminal of the output stage circuit system 320 is coupled to the fourth output terminal of the control system 300, which supplies a system fault signal to the programmable circuit system 105.

[0094] Logic device 325 has a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal of logic device 325 is coupled to a driver circuit system 305 supplying a first safety signal. The second input terminal of logic device 325 is coupled to a driver circuit system 310 supplying a second safety signal. The third input terminal of logic device 325 is coupled to a driver circuit system 315 supplying a third safety signal. The output terminal of logic device 325 is coupled to a fourth output terminal of control system 300, which supplies a system fault signal to programmable circuit system 105. Figure 3A In this example, logic device 325 is an AND gate. Alternatively, logic device 325 can be a logic device of an alternative type or a combination of logic devices.

[0095] Figure 3B This is a schematic diagram of an example control system 330, which is... Figure 1 and 3A Another example of control systems 100 and 300. In Figure 3B In one example, the control system 330 includes a first driver circuit system 335, a second driver circuit system 340, a third driver circuit system 345, and an output stage circuit system 350. Figure 3B The example output stage circuit system 350 includes an example resistor 355.

[0096] The control system 330 has a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal. The first input terminal, the second input terminal, and the third input terminal of the control system 330 are configured to couple to... Figure 1 The programmable circuit system 105 supplies a first PWM signal (PWM signal). U ), second PWM signal (PWM) V ) and the third PWM signal (PWM) W The first, second, and third output terminals of the control system 330 are configured to couple to... Figure 1 The motor 125. A fourth output terminal of the control system 330 is configured to couple to a programmable circuit system 105, which receives a system fault signal (nFAULT). The system fault signal indicates the state of the driver circuit systems 335, 340, 345. For example, the system fault signal is cleared in response to the supply of current across transformer circuit systems 165, 206 to one or more of the driver circuit systems 335, 340, 345.

[0097] The driver circuit system 335 has an input terminal, a first output terminal, and a second output terminal. The input terminal of the driver circuit system 335 is coupled to the first input terminal of the control system 330, which supplies a first PWM signal from the programmable circuit system 105. The first output terminal of the driver circuit system 335 is coupled to the motor 125. The second output terminal of the driver circuit system 335 is coupled to driver circuit systems 340 and 345 and the output stage circuit system 350. The driver circuit system 335 is... Figure 1 An example of a driver circuit system 110.

[0098] The driver circuit system 340 has an input terminal, a first output terminal, and a second output terminal. The input terminal of the driver circuit system 340 is coupled to the second input terminal of the control system 330, which supplies a second PWM signal from the programmable circuit system 105. The first output terminal of the driver circuit system 340 is coupled to the motor 125. The second output terminal of the driver circuit system 340 is coupled to driver circuit systems 335 and 345 and the output stage circuit system 350. The driver circuit system 340 is... Figure 1 An example of the driver circuit system 115.

[0099] Driver circuit system 345 has an input terminal, a first output terminal, and a second output terminal. The input terminal of driver circuit system 345 is coupled to the first input terminal of control system 330, which supplies a third PWM signal from programmable circuit system 105. The first output terminal of driver circuit system 345 is coupled to motor 125. The second output terminal of driver circuit system 345 is coupled to driver circuit systems 335 and 340 and output stage circuit system 350. Driver circuit system 345 is... Figure 1 An example of a driver circuit system 120.

[0100] The output stage circuit system 350 has input terminals and output terminals. The input terminals of the output stage circuit system 350 are coupled to the supply of the first safety signal (SAFE). U ), second safety signal (SAFE) V ) and third safety signal (SAFE) W The driver circuit systems 335, 340, and 345 are described. A safety signal indicates the state of driver circuit system 335. In a first state, driver circuit system 335 supplies current to transformer circuit systems 165 and 206. In a second state, driver circuit system 335 does not supply current to transformer circuit systems 165 and 206. The output terminal of output stage circuit system 350 is coupled to a fourth output terminal of control system 330, which supplies a system fault signal to programmable circuit system 105.

[0101] Resistor 355 has a first terminal and a second terminal. The first terminal of resistor 355 is coupled to a power supply terminal that supplies the power supply voltage. The second terminal of resistor 355 is coupled to a fourth output terminal of driver circuit systems 335, 340, and 345, and control system 330, which supply first, second, and third safety signals. Figure 3B In this example, resistor 355 is a pull-up resistor.

[0102] Figure 4This is a flowchart illustrating example machine-readable instructions or example operations 400, which can be used... Figure 1 and 2 Isolated gate driver circuit systems 145, 200, Figure 1 Programmable circuit system 105 or more generally Figure 1 , 3A At least one of the example implementations of the 3B control systems 100, 300, and 330 shall be carried out, instantiated, or executed. Figure 4 In the example, operation 400 is shown and described as an active high signal for the SAFE signal. Alternatively, operation 400 can be modified to support an active low signal.

[0103] Figure 4 Example operation 400 begins at block 405, where programmable circuitry 105 generates a PWM signal (block 405). In this example operation, programmable circuitry 105 uses a first voltage representing logic one and a second voltage representing logic zero to generate the PWM signal. In this type of example operation, programmable circuitry 105 sets the duty cycle of the PWM signal based on the duration for which driver circuitry 110 supplies power to motor 125. The following is in conjunction with... Figure 5 Examples of PWM signals are shown and described. In some instances, the programmable circuit system 105 also generates an enable signal, which further controls the driver circuit system 110. In some such instances, the enable signal is redundant, which improves the likelihood of accurately powering the motor 125. The following description, in conjunction with... Figure 5 Examples of enable signals are shown and described.

[0104] Figure 1 and 2 The logic circuit systems 155 and 202 determine whether the PWM signal is logic one (Box 410). In example operation, the logic circuit systems 155 and 202 generate a combined control signal and an inverted combined control signal in response to at least one of the PWM signal and an enable signal. In this type of example operation, the logic circuit systems 155 and 202 logically combine the PWM signal with the enable signal. For example, Figure 2 The logic device 210 performs a logical AND operation on the PWM and enable signals from the programmable circuit system 105. In such an example, Figure 2 Inverters 212 and 214 generate a combined control signal and an inverted control signal by inverting the output of logic device 210.

[0105] If logic circuitry 155 and 202 determine that the PWM signal is logic one (for example, if block 410 returns a result), then Figure 1 and2 The charge injection circuit systems 160 and 204 inject current into the inductor-capacitor circuit system (box 415). In example operation, the charge injection circuit systems 160 and 204 begin conducting current in response to a combination of a control signal and an inverted combination of a control signal from the logic circuit systems 155 and 202. For example, Figure 2 Transistors 222, 224, and 226 form a first current path in response to a combined control signal that is logic zero and an inverted combined control signal that is logic one. In such an example, transistor 222... Figure 2 The current of transistor 218 is mirrored and reflected, thereby pulling down. Figure 2 The control terminals of transistors 242 and 262. Transistors 242 and 262 begin conducting current by pulling the voltage at their control terminals towards a common potential in response to the current flowing from transistors 222 and 224. In this example operation, Figure 2 Transistors 238, 240, 244, and 246 supply current to capacitors 248 and 250 and inductor 252, which form the primary-side LC circuit system.

[0106] Figure 1 and 2 The transformer circuit systems 165 and 206 use an inductor-capacitor circuit to generate a sinusoidal signal (Box 420). In example operation, the transformer circuit systems 165 and 206 receive current from transistors 238, 240, 244, and 246 by turning on transistors 236 and 242 in response to a combined control signal and an inverted combined control signal. In some instances, capacitors 248 and 250 and inductor 252 generate a sinusoidal signal by driving cross-coupled control terminals of transistors 238, 240, 244, and 246. In such instances, the current from transistors 238, 240, 244, and 246 compensates for charge loss in capacitors 248, 250, and inductor 252 due to non-ideal components such as parasitic resistance. In such example operation, capacitors 248, 250, and inductor 252 generate a sinusoidal signal in response to current oscillations between capacitors 248, 250, and inductor 252.

[0107] Transformer circuit system 165, 206 spans isolation barrier to transmit sinusoidal signals (Box 425). In example operation, inductor 252 spans... Figure 2 The isolation barrier 254 magnetically coupled to Figure 2Inductor 256. In some instances, inductors 252 and 256 are magnetically coupled via a core. In such instances, inductor 252 generates a magnetic field in response to a sinusoidal alternating current, which induces a current in inductor 256. In such example operation, inductor 256 and capacitors 258 and 260 generate an induced sinusoidal signal in response to the current induced in inductor 256 by inductor 252. Figure 1 The receiver circuit system 170 determines the PWM signal in response to receiving the induced sinusoidal signal.

[0108] Figure 1 and 2 The current sensing circuit systems 180 and 208 determine whether current is being injected into the inductor-capacitor circuit (box 430). In example operation, transistors 244 and 246 inject current into the LC circuit system formed by capacitors 248 and 250 and inductor 252 in response to transistor 242 conducting current. In such example operation, transistor 262 mirrors the current passing through transistor 242 in response to the coupling of the control terminals of transistors 242 and 262. Advantageously, transistor 262 of the current sensing circuit system 208 conducts current in response to the charge injection circuit system 204 configuring transistor 242 to conduct current.

[0109] If the current sensing circuitry 180, 208 determines that current is being injected into the inductor-capacitor circuit (e.g., the result returned by box 430), then the current sensing circuitry 180, 208 sets the safety signal to logic zero (box 435). In example operation, Figure 2 Resistor 264 generates a reference voltage in response to charge injection circuit system 204 configuring transistor 262 to conduct current. In this example operation, Figure 2 The comparator circuit system 266 generates logic one in response to the detection of the reference voltage of resistor 264. Figure 2 The level shifter circuit system 268 converts the voltage of the comparator circuit system 266 into the logic level of the programmable circuit system 105. For example, under the condition that the power supply voltage is twelve volts and the programmable circuit system 105 is configured for a five-volt signal, the level shifter circuit system 268 converts the voltage of the comparator circuit system 266 for the programmable circuit system 105. Figure 2 The buffer circuit system 270 buffers the signal from the level shifter circuit system 268 to increase the signal strength. Figure 2 The inverter 272 generates a safety signal (SAFE) by inverting the logic state of the output of the buffer circuit system 270. In some instances, the current sensing circuit systems 180, 208 set the safety signal to logic zero in response to the conduction of current by the transistor 262.

[0110] If current sensing circuitry 180, 208 determines that current is not injected into the inductor-capacitor circuitry (e.g., block 430 returns a negative result), then current sensing circuitry 180, 208 sets a safety signal to logic one (block 440). In example operation, resistor 264 sets the input of comparator circuitry 266 to a common potential in response to charge injection circuitry 204 failing to configure transistor 262 to conduct current. In such example operation, level shifter circuitry 268 translates the voltage of comparator circuitry 266 to a logic level of programmable circuitry 105. In some instances, current sensing circuitry 180, 208 sets a safety signal to logic one in response to resistor 264 setting the input of comparator circuitry 266 to a common potential.

[0111] Programmable circuit system 105 determines whether a safety signal is opposite to a PWM signal (box 445). In example operation, programmable circuit system 105 determines whether isolated gate driver circuit systems 145, 200 are operating safely in response to a comparison of the safety signal from current sensing circuit systems 180, 208 with the PWM signal. In such example operation, programmable circuit system 105 determines that isolated gate driver circuit systems 145, 200 are operating safely in response to the PWM signal having a logic state opposite to the logic state of the safety signal. In some instances, Figure 1 , 3A The output stage circuitry 130, 320, and 350 of the 3B system combine multiple safety signals from multiple instances of the isolated gate driver circuitry 145 and 200. In such instances, the programmable circuitry 105 compares a system fault signal with one or more PWM signals to determine whether all instances of the isolated gate driver circuitry 145 and 200 are operating safely. Figure 3A In the example, under the condition that all PWM signals are logic zero, in response to a system fault signal being logic zero, the programmable circuit system 105 determines... Figure 3A One or more of the driver circuit systems 305, 310, and 315 are not operating safely. In this example, logic device 325 indicates that at least one safety signal from driver circuit systems 305, 310, and 315 corresponds to current conduction. Figure 3B In the examples, Figure 3B Resistor 355 allows any safety signal from driver circuitry 335, 340, 345 to set a system fault signal.

[0112] If the programmable circuit system 105 determines that the safety signal is the opposite of the PWM signal (e.g., block 445 returns a result), then the programmable circuit system 105 verifies the accuracy of the SAFE signal. Figure 7 (Operation 700). In an example operation, programmable circuit system 105 supplies test pulses to isolated gate driver circuit systems 145, 200 to verify the accuracy of a safety signal. For example, in response to a safety signal being logic zero for an extended duration, programmable circuit system 105 supplies a test pulse that modifies the state of the safety signal for the duration of the test pulse. In such instances, in response to a test pulse duration shorter than a minimum duration, Figure 1 The deglitch circuit system 175 deglitches the pulses output from the receiver circuit system 170. Advantageously, the deglitch circuit system 175 allows the programmable circuit system 105 to test the state of the safety signal without affecting the control of the transistor 135.

[0113] If programmable circuitry 105 determines that the safety signal is the same as the PWM signal (e.g., block 445 returns a no result), then programmable circuitry 105 shuts down the driver circuitry (block 450). In example operation, programmable circuitry 105 sets at least one of the PWM signal or the enable signal to a safe state in response to determining that the isolated gate driver circuitry 145, 200 has unintentionally conducted current. Control ends.

[0114] refer to Figure 4 The flowchart shown illustrates the example method. However, implementations may also be used in this specification. Figure 1 and 2 Isolated gate driver circuit systems 145, 200, Figure 1 Programmable circuit system 105 or more generally Figure 1 , 3A And many other methods of the control systems 100, 300, 330 of 3B. For example, the execution order of the blocks can be changed, or some of the described blocks can be changed, eliminated, or combined. Similarly, additional operations may be included before, between, or after the blocks shown in the illustrated examples during the manufacturing process.

[0115] Figure 5 yes Figure 1 and 2 Timing diagram 500 for example operation of isolated gate driver circuit systems 145, 200. Figure 5 In this example, timing diagram 500 shows an example PWM signal 510 (PWM), an example enable signal 520 (EN), and an example safety signal 530 (SAFE).

[0116] PWM signal 510 indicates that it comes from Figure 1 The programmable circuit system 105 provides signals for controlling the power supply from the driver circuit systems 110, 115, and 120. In example operation, the programmable circuit system 105 can modify the duty cycle of the PWM signal 510 to adjust the power supply from the driver circuit systems 110, 115, and 120. Figure 1 The amount of electricity supplied by motor 125.

[0117] Enable signal 520 represents a signal from programmable circuit system 105 used to control driver circuit systems 110, 115, and 120. Figure 1 and 2 The logic circuit systems 155 and 202 allow the isolated gate driver circuit systems 145 and 200 to control the logic circuit systems 155 and 202 in response to the enable signal 520 being set (e.g., set to logic 1, logic high, etc.). Figure 1 Transistor 135.

[0118] Safety signal 530 indicates that it comes from Figure 1 and 2 The current sensing circuit systems 180 and 208 provide signals. Safety signal 530 indicates whether charge injection circuit systems 160 and 204 are supplying current to transformer circuit systems 165 and 206. Current sensing circuit systems 180 and 208 clear safety signal 530 in response to charge injection circuit systems 160 and 204 being configured to supply current to transformer circuit systems 165 and 206.

[0119] At the first time 540, logic circuit systems 155 and 202 configure charge injection circuit systems 160 and 204 to supply current to transformer circuit systems 165 and 206 in response to the setting of PWM signal 510 and enable signal 520. At the first time 540, current sensing circuit systems 180 and 208 clear safety signal 530 in response to the charge injection circuit systems 160 and 204 being configured to supply current to transformer circuit systems 165 and 206.

[0120] At the second time 550, programmable circuit system 105 simulates unsafe operating conditions by clearing enable signal 520. At the second time 550, logic circuit systems 155, 202 configure charge injection circuit systems 160, 204 to prevent current supply to transformer circuit systems 165, 206. At the second time 550, current sensing circuit systems 180, 208 set safety signal 530 in response to charge injection circuit systems 160, 204 being configured to prevent current flow. However, if at the second time 550… Figure 2 If transistor 242 continues to conduct current, programmable circuit system 105 can detect a system fault in response to safety signal 530 being cleared.

[0121] At the third time 560, logic circuit systems 155 and 202 configure charge injection circuit systems 160 and 204 to supply current to transformer circuit systems 165 and 206 in response to the setting of PWM signal 510 and enable signal 520. At the third time 560, current sensing circuit systems 180 and 208 clear safety signal 530 in response to the charge injection circuit systems 160 and 204 being configured to supply current to transformer circuit systems 165 and 206.

[0122] Advantageously, between times 550 and 560, the current sensing circuit systems 180 and 208 generate a pulse on the safety signal 530 in response to a pulse of the enable signal 520. In some instances, as further described below, the programmable circuit system 105 may test the accuracy of the safety signal 530 in response to the generation of a relatively short pulse (e.g., a pulse between times 550 and 560). Advantageously, using a relatively short pulse to test the safety signal 530 allows the programmable circuit system 105 to detect adverse conditions, such as when the terminals of the charge injection circuit systems 160 and 204 or the current sensing circuit systems 180 and 208 are pulled high or low.

[0123] At the fourth time 570, logic circuit systems 155 and 202 configure charge injection circuit systems 160 and 204 to prevent current from being supplied to transformer circuit systems 165 and 206 in response to the clearing of PWM signal 510. At the fourth time 570, current sensing circuit systems 180 and 208 set a safety signal 530 in response to the charge injection circuit systems 160 and 204 being configured not to supply current to transformer circuit systems 165 and 206.

[0124] At the fifth time 580, logic circuit systems 155 and 202 configure charge injection circuit systems 160 and 204 to supply current to transformer circuit systems 165 and 206 in response to the setting of PWM signal 510 and enable signal 520. At the fifth time 580, current sensing circuit systems 180 and 208 clear safety signal 530 in response to the charge injection circuit systems 160 and 204 being configured to supply current to transformer circuit systems 165 and 206.

[0125] At the sixth time 590, logic circuit systems 155 and 202 configure charge injection circuit systems 160 and 204 to prevent current from being supplied to transformer circuit systems 165 and 206 in response to the clearing of PWM signal 510. At the sixth time 590, current sensing circuit systems 180 and 208 set a safety signal 530 in response to charge injection circuit systems 160 and 204 being configured not to supply current to transformer circuit systems 165 and 206.

[0126] Figure 6 This is a block diagram of an example programmable circuit system 600, which is... Figure 1 Example implementation of programmable circuit system 105 for sensing Figure 1 and 2 The isolated gate driver circuitry 145, 200 provides safety signals. The programmable circuitry 600 can be instantiated (e.g., created, generated, implemented, etc.) by a programmable circuitry system, such as a central processing unit (CPU) executing the first instruction. Alternatively, the programmable circuitry 600 can be instantiated (e.g., created, generated, implemented, etc.) by (i) an application-specific integrated circuit (ASIC) or (ii) a field-programmable gate array (FPGA) constructed or configured to perform operations corresponding to the first instruction in response to the execution of a second instruction. Therefore, Figure 6 Some or all of the circuit systems can be instantiated at the same or different times. Figure 6 Some or all of the circuit system can be instantiated, for example, in one or more threads that are implemented in parallel or serially on hardware. Furthermore, in some instances, Figure 6 Some or all of the circuitry in the system can be implemented by a microprocessor circuitry that executes instructions or an FPGA circuitry that performs operations, to implement one or more virtual machines or containers. Figure 6 In one example, the programmable circuit system 600 includes a safety timer circuit system 610, a pulse generator circuit system 620, a PWM source circuit system 630, a logic device 640, and a safety monitor circuit system 650.

[0127] The programmable circuit system 600 has an input terminal, a first output terminal, and a second output terminal. The input terminal of the programmable circuit system 600 is configured to couple to... Figure 1 and 2 The current sensing circuit systems 180 and 208 supply safety signals (e.g., Figure 5 (Safety signal 530). In some instances, the input terminals of the programmable circuit system 600 are configured to couple to... Figure 1 , 3A The output stage circuitry systems 130, 320, and 350 of the 3B system supply system fault signals. In both instances, the input terminals of the programmable circuitry system 600 receive indications. Figure 1 , 3A The signals indicating the safety status of the control systems 100, 300, and 330 of 3B. The first and second output terminals of the programmable circuit system 600 are configured to couple to... Figure 1 and 2The logic circuit system 155, 202, or more generally, the isolated gate driver circuit system 145, 200. The programmable circuit system 600 supplies a PWM signal (e.g., ...) at the first output terminal. Figure 5 The PWM signal 510) is used to supply an enable signal (e.g., at the second output terminal) Figure 5 Enable signal 520).

[0128] The safety timer circuit system 610 has a first terminal and a second terminal. The first terminal of the safety timer circuit system 610 is coupled to the input terminals of the safety monitor circuit system 650 and the programmable circuit system 600, which supply safety signals from the isolated gate driver circuit systems 145, 200 or the output stage circuit systems 130, 320, 350. The second terminal of the safety timer circuit system 610 is coupled to the pulse generator circuit system 620. In some instances, the safety timer circuit system 610 is instantiated by a programmable circuit system that executes safety timer instructions to perform, for example, by... Figure 7 The flowchart represents the operation.

[0129] The pulse generator circuit system 620 has a first terminal and a second terminal. The first terminal of the pulse generator circuit system 620 is coupled to a safety timer circuit system 610. The second terminal of the pulse generator circuit system 620 is coupled to a logic device 640. In some instances, the pulse generator circuit system 620 is instantiated by a programmable circuit system that executes pulse generator instructions to perform, for example, actions... Figure 7 The flowchart represents the operation.

[0130] The PWM source circuit system 630 has a first terminal, a second terminal, and a third terminal. The first terminal of the PWM source circuit system 630 is coupled to a second output terminal of a programmable circuit system 600, which supplies an enable signal to isolated gate driver circuit systems 145 and 200. The second terminal of the PWM source circuit system 630 is coupled to a logic device 640. The third terminal of the PWM source circuit system 630 is coupled to a safety monitor circuit system 650. In some instances, the PWM source circuit system 630 is instantiated by a programmable circuit system that executes PWM source instructions to perform, for example, by... Figure 7 The flowchart represents the operation.

[0131] Logic device 640 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of logic device 640 is coupled to pulse generator circuitry 620. The second input terminal of logic device 640 is coupled to PWM source circuitry 630. The output terminal of logic device 640 is coupled to a safety monitor circuitry 650 and a first output terminal of a programmable circuitry 600, which supplies PWM signals to isolated gate driver circuitry systems 145 and 200. Figure 6 In this example, logic device 640 is an AND gate with an inverting input. In some instances, logic device 640 may be replaced by a logic device of an alternative type.

[0132] The safety monitor system circuitry 650 has a first terminal, a second terminal, and a third terminal. The first terminal of the safety monitor circuitry 650 is coupled to the input terminals of a safety timer circuitry 610 and a programmable circuitry 600, the programmable circuitry receiving safety signals from isolated gate driver circuitry 145, 200. The second terminal of the safety monitor circuitry 650 is coupled to a PWM source circuitry 630. The third terminal of the safety monitor circuitry 650 is coupled to the first output terminal of a logic device 640 and a programmable circuitry 600, the programmable circuitry supplying PWM signals to the isolated gate driver circuitry 145, 200. In some instances, the safety monitor circuitry 650 is instantiated by a programmable circuitry that executes safety monitor instructions to perform, for example, actions... Figure 7 The flowchart represents the operation.

[0133] Figure 7 This is a flowchart illustrating example machine-readable instructions or example operations 700, which can be used... Figure 1 and 6 At least one of the example implementations, instantiations, or executions of the programmable circuit systems 105 and 600 is carried out to... Figure 1 and 2 The isolated gate driver circuit system 145, 200 is deburred in a safe state. Figure 7 In this example, operation 700 is illustrated and described by using a PWM signal to verify the SAFE signal. Alternatively, in other examples, operation 700 may be modified to use an enable signal to verify the SAFE signal.

[0134] Example operation 700 begins at box 705, where, Figure 6The safety timer circuitry 610 determines whether the safety state has changed within a time period shorter than a threshold duration (box 705). In example operation, the safety timer circuitry 610 determines the duration since the safety signal changed the logic state. In such example operation, the safety timer circuitry 610 determines whether the state of the safety signal needs to be verified based on a comparison of the determined duration with the threshold duration. If the safety timer circuitry 610 determines that the safety state has changed within a time period shorter than the threshold duration (e.g., box 705 returns a result), control proceeds to return.

[0135] If the safety timer circuitry 610 determines that the safety state has not changed for a period shorter than the threshold duration (e.g., box 705 returns a negative result), then Figure 6 The pulse generator circuit system 620 generates a test pulse (box 710). In example operation, in response to the safety timer circuit system 610 determining the state of the safety signal to be verified, the pulse generator circuit system 620 generates a test pulse with a test duration. In some instances, the test duration of the test pulse is based on... Figure 1 The deglitch circuit system 175 is configured for this purpose. In such instances, the test duration is shorter than the minimum duration allowed by the deglitch circuit system 175 to control the transistor 135.

[0136] Figure 6 The logic device 640 combines the test pulse with the PWM pulse (Box 715). In example operation, the logic device 640 combines the test pulse with the PWM pulse from... Figure 6 The PWM signals of the PWM source circuit system 630 are logically combined. In this example operation, the logic device 640 supplies the combined PWM signals to the isolated gate driver circuit systems 145, 200.

[0137] Figure 1 and 2 The current sensing circuit systems 180 and 208 determine whether current is being injected into the inductor-capacitor circuit (box 720). In example operation, the current sensing circuit systems 180 and 208 respond to the operation of the charge injection circuit systems 160 and 204 (e.g., Figure 4 (Example operation of box 430) and set the state of the safety signal.

[0138] If the current sensing circuitry 180, 208 determines that current is being injected into the inductor-capacitor circuit (e.g., the result returned by box 720), then the current sensing circuitry 180, 208 sets the SAFE signal to logic zero (box 725). In example operation, Figure 2Resistor 264 generates a reference voltage in response to charge injection circuit system 204 configuring transistor 262 to conduct current. In this example operation, Figure 2 The comparator circuit system 266 generates logic one in response to the detection of the reference voltage of resistor 264. Figure 2 The level shifter circuit system 268 converts the voltage of the comparator circuit system 266 into the logic level of the programmable circuit system 105. For example, when the power supply voltage is 12 volts and the programmable circuit system 105 is configured for a 5-volt signal, the level shifter circuit system 268 converts the voltage of the comparator circuit system 266 for the programmable circuit system 105. Figure 2 The buffer circuit system 270 buffers the signal from the level shifter circuit system 268 to increase the signal strength. Figure 2 The inverter 272 generates a safety signal (SAFE) by inverting the logic state of the output of the buffer circuit system 270. In some instances, the current sensing circuit systems 180, 208 set the safety signal to logic zero in response to the conduction of current by the transistor 262.

[0139] If the current sensing circuitry 180, 208 determines that current is not injected into the inductor-capacitor circuitry (e.g., block 720 returns a negative result), the current sensing circuitry 180, 208 sets the SAFE signal to logic one (block 730). In example operation, resistor 264 sets the input of comparator circuitry 266 to a common potential in response to charge injection circuitry 204 failing to configure transistor 262 to conduct current. In such example operation, level shifter circuitry 268 translates the voltage of comparator circuitry 266 to a logic level of programmable circuitry 105. In some instances, current sensing circuitry 180, 208 sets the safety signal to logic one in response to resistor 264 setting the input of comparator circuitry 266 to a common potential.

[0140] Figure 6 The safety monitoring circuitry 650 determines whether a safety signal is opposite to a PWM signal (box 735). In example operation, the programmable circuitry 105 determines whether the isolated gate driver circuitry 145, 200 is operating safely in response to a comparison of the safety signal from the current sensing circuitry 180, 208 with the combined PWM signal. In such example operation, the programmable circuitry 105 determines that the isolated gate driver circuitry 145, 200 is operating safely in response to the PWM signal having a logic state opposite to the logic state of the safety signal. In some instances, Figure 1 , 3AThe output stage circuitry 130, 320, and 350 of the 3B system combine multiple safety signals from multiple instances of the isolated gate driver circuitry 145 and 200. In such instances, the programmable circuitry 105 compares a system fault signal with one or more PWM signals to determine whether all instances of the isolated gate driver circuitry 145 and 200 are operating safely. Figure 3A In the example, under the condition that all PWM signals are logic zero, in response to a system fault signal being logic zero, the programmable circuit system 105 determines... Figure 3A One or more of the driver circuit systems 305, 310, and 315 are not operating safely. In this example, logic device 325 indicates that at least one safety signal from driver circuit systems 305, 310, and 315 corresponds to current conduction. Figure 3B In the examples, Figure 3B Resistor 355 allows any safety signal from driver circuitry 335, 340, 345 to set a system fault signal.

[0141] If the safety monitor circuitry 650 determines that the safety signal is not opposite to the PWM signal (e.g., block 735 returns a negative result), then the PWM source circuitry 630 of FIG3 shuts down the driver circuitry (block 740). In example operation, the programmable circuitry 105 sets at least one of the PWM signal or the enable signal to a safe state in response to determining that the isolated gate driver circuitry 145, 200 has unintentionally conducted current.

[0142] Figure 1 The deglitch circuitry 175 filters the test pulses on the secondary side (box 745). In example operation, the deglitch circuitry 175 removes pulses with durations shorter than the minimum duration to prevent the isolated gate driver circuitry 145, 200 from switching transistor 135. In this type of example operation, the pulse generator circuitry 620 sets the test duration of the test pulse to be shorter than the minimum duration of the deglitch circuitry 175 to prevent the test pulse from modifying the operation of the isolated gate driver circuitry 145, 200. Control proceeds to return.

[0143] refer to Figure 4 The flowchart shown illustrates the example method. However, implementations may also be used in this specification. Figure 1 and 2 Isolated gate driver circuit systems 145, 200, Figure 1 and 6Many other methods exist for the programmable circuit systems 105, 600. For example, the execution order of the blocks can be changed, or some of the described blocks can be changed, eliminated, or combined. Similarly, additional operations may be included before, between, or after the blocks shown in the illustrated examples during the manufacturing process.

[0144] Figure 8 yes Figure 1 and 6 Programmable circuit systems 105, 600 pairs Figure 1 and 2 Timing diagram 800 shows an example operation of deglitching in a safe state for the isolated gate driver circuit system 145, 200. Figure 8 In this example, timing diagram 800 shows an example safety signal 810 and an example gate control signal 820.

[0145] Safety signal 810 indicates that it comes from Figure 1 and 2 The current sensing circuit systems 180 and 208 provide signals. Safety signal 810 indicates whether the charge injection circuit systems 160 and 204 are supplying current to the transformer circuit systems 165 and 206. Current sensing circuit systems 180 and 208 clear safety signal 810 in response to the charge injection circuit systems 160 and 204 being configured to supply current to the transformer circuit systems 165 and 206.

[0146] The gate control signal 820 represents a signal from the control transistor 135 of the isolated gate driver circuitry 145, 200. In example operation, transistor 135 supplies current to motor 125 in response to the gate control signal 820 being set. In such example operation, transistor 135 prevents current from flowing from the power supply terminal to motor 125 in response to the gate control signal 820 being cleared.

[0147] At the first time 830, the logic circuit systems 155, 202 configure the charge injection circuit systems 160, 204 to respond to the PWM signal (e.g., Figure 5 The PWM signal 510) and the enable signal (e.g., Figure 5 The enable signal 520 is set to supply current to the transformer circuit systems 165 and 206. At the first time 830, the current sensing circuit systems 180 and 208 clear the safety signal 810 in response to the charge injection circuit systems 160 and 204 being configured to supply current to the transformer circuit systems 165 and 206.

[0148] Between the first time 830 and the second time 840, in response to Figure 6 The safety timer circuit system 610 determines that the safety signal remains unchanged within the threshold duration. Figure 6The pulse generator circuit system 620 generates test pulses (e.g., Figure 7 (Operation of box 705). Figure 6 The logic device 640 will come from Figure 6 The reference PWM signal and test pulse of the PWM source circuit system 630 are combined into a PWM signal, wherein the test pulse is sent to the isolated gate driver circuit systems 145, 200. At a second time 840, the logic circuit systems 155, 202 configure the charge injection circuit systems 160, 204 to prevent current from being supplied to the transformer circuit systems 165, 206. At a second time 840, the current sensing circuit systems 180, 208 set a safety signal 530 in response to the charge injection circuit systems 160, 204 being configured to prevent current flow. However, if at a second time 840, Figure 2 If transistor 242 continues to conduct current, programmable circuit systems 105 and 600 can detect a system fault in response to safety signal 810 remaining in a cleared state. Advantageously, the test pulse at the second time 840 allows programmable circuit systems 105 and 600 to test the accuracy of safety signal 810.

[0149] Between the second time 840 and the third time 850, the programmable circuit systems 105 and 600 continue to supply test pulses to the isolated gate driver circuit systems 145 and 200. Between the second time 840 and the third time 850, the gate control signal 820 responds to... Figure 1 The degluing circuitry 175 filters out test pulses while maintaining settings. In example operation, the degluing circuitry 175 is configured to filter pulses with a duration shorter than the maximum switching time. In such example operation, if the programmable circuitry 105, 600 sets the duration of the test pulse to be shorter than the minimum duration corresponding to the maximum switching frequency, the test pulse will not cause the isolated gate driver circuitry 145, 200 to modify the state of transistor 135. Advantageously, the degluing circuitry 175 allows the programmable circuitry 105, 600 to verify the accuracy of the safety signal 810 without affecting transistor 135.

[0150] At the fourth time 860, logic circuit systems 155 and 202 configure charge injection circuit systems 160 and 204 to prevent current supply to transformer circuit systems 165 and 206. At the fourth time 860, current sensing circuit systems 180 and 208 set a safety signal 810 in response to the charge injection circuit systems 160 and 204 being configured not to supply current to transformer circuit systems 165 and 206.

[0151] Figure 9 This is a block diagram of an example programmable circuit system platform 900, which is configured to support... Figure 4 and 7 To implement or instantiate one or more of the example machine-readable instructions or example operations to perform Figure 6 The programmable circuit system 600. The programmable circuit system platform 900 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), or a mobile device (e.g., a mobile phone, a smartphone, such as an iPad). TM Tablet computers, personal digital assistants (PDAs), internet devices, DVD players, CD players, digital video recorders, Blu-ray players, game consoles, personal video recorders, set-top boxes, headphones (e.g., augmented reality (AR) headphones, virtual reality (VR) headphones, etc.) or other wearable devices, or any other type of computing or electronic device.

[0152] The programmable circuit system platform 900 of the illustrated example includes a programmable circuit system 912. The programmable circuit system 912 of the illustrated example is hardware. For example, the programmable circuit system 912 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, or microcontrollers from any desired series or manufacturer. The programmable circuit system 912 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 912 implements a safety timer circuit system 610, a pulse generator circuit system 620, a PWM source circuit system 630, and a safety monitor circuit system 650.

[0153] The programmable circuit system 912 of the illustrated example includes local memory 913 (e.g., cache, registers, etc.). The programmable circuit system 912 of the illustrated example communicates with main memories 914 and 916 via bus 918, the main memories including volatile memory 914 and non-volatile memory 916. The volatile memory 914 may be one or more synchronous dynamic random access memories (SDRAM) and dynamic random access memories (DRAM). Dynamic Random Access Memory Or any other type of RAM device. The non-volatile memory 916 may be implemented by flash memory or one or a combination of any other desired type of memory device. Access to the main memory 914, 916 in the illustrated examples is controlled by a memory controller 917. In some instances, the memory controller 917 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired series or manufacturer, or any other type of circuit system to manage the flow of data to and from the main memory 914, 916.

[0154] The programmable circuit system platform 900 of the illustrated example also includes an interface circuit system 920. The interface circuit system 920 can be implemented in hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, etc. Interfaces include Near Field Communication (NFC) interfaces, Peripheral Component Interconnect (PCI) interfaces, and Peripheral Component Interconnect High Speed ​​(PCIe) interfaces.

[0155] In the illustrated example, one or more input devices 922 are connected to the interface circuitry system 920. The input devices 922 allow a user (e.g., a human user, a machine user, etc.) to input one or a combination of data or commands into the programmable circuitry system 912. The input devices 922 may be implemented as one or a combination of, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touchscreen, a trackpad, a trackball, a dot device, or a speech recognition system.

[0156] One or more output devices 924 are also connected to the interface circuitry system 920 of the illustrated example. The output devices 924 may be implemented, for example, by one or a combination of a display device (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, a flat panel display (IPS), a touchscreen, etc.), a haptic output device, a printer, or a speaker. Therefore, the interface circuitry system 920 of the illustrated example includes one or a combination of a graphics driver card, a graphics driver chip, or a graphics processor circuitry system such as a GPU.

[0157] The interface circuit system 920 of the illustrated example also includes communication devices, such as one or a combination of a transmitter, receiver, transceiver, modem, residential gateway, wireless access point, or network interface, to facilitate the exchange of data with external machines (e.g., any kind of computing device) via network 926. Communication can be carried out via, for example, Ethernet connection, Digital Subscriber Line (DSL) connection, telephone line connection, coaxial cable system, satellite system, beyond-line-of-sight wireless system, line-of-sight wireless system, cellular telephone system, optical connection, etc.

[0158] The programmable circuit system platform 900 of the illustrated example also includes one or more mass storage disks or devices 928 for storing one or more of firmware, software, or data. Examples of such mass storage disks or devices 928 include one or more magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, or solid-state storage disks or devices, such as flash memory devices and SSDs.

[0159] can be Figure 4 and 7The machine-readable instructions 932 implemented by the machine-readable instructions may be stored in one or a combination of the following locations: in a mass storage device 928, in volatile memory 914, in non-volatile memory 916, or on at least one non-transitory computer-readable storage medium (e.g., a removable CD or DVD).

[0160] Figure 10 yes Figure 9 A block diagram of an example implementation of the programmable circuit system 912. In this example, Figure 9 The programmable circuit system 912 is implemented by the microprocessor 1000. For example, the microprocessor 1000 may be a general-purpose microprocessor (e.g., a general-purpose microprocessor circuit system). The microprocessor 1000 implements... Figure 4 and 7 The flowchart contains some or all of the machine-readable instructions to effectively translate... Figure 6 The circuit system is instantiated as a logic circuit to perform operations corresponding to those machine-readable instructions. In some such instances, Figure 6 The circuit system is instantiated by the hardware circuitry of the microprocessor 1000 combined with machine-readable instructions. For example, the microprocessor 1000 may be implemented by a multi-core hardware circuitry system such as a CPU, DSP, GPU, or XPU. Although it may contain any number of example cores 1002 (e.g., one core), this instance of the microprocessor 1000 is a multi-core semiconductor device containing N cores. The cores 1002 of the microprocessor 1000 may operate independently or collaboratively to execute machine-readable instructions. For example, machine code corresponding to firmware, embedded software, or software programs may be executed by one of the cores 1002, or by multiple cores 1002 at the same or different times. In some instances, the machine code corresponding to firmware, embedded software, or software programs is split into threads and executed in parallel by two or more of the cores 1002. Software programs may correspond to... Figure 4 and 7 A flowchart represents part or all of machine-readable instructions or operations.

[0161] Core 1002 can communicate via a first example bus 1004. In some instances, the first bus 1004 may be implemented as a communication bus to enable communication associated with one or more of the cores 1002. For example, the first bus 1004 may be implemented via at least one of an Interconnect Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Alternatively, the first bus 1004 may be implemented by any other type of computing or electrical bus. Core 1002 can obtain data, instructions, and signals from one or more external devices via example interface circuitry 1006. Core 1002 can output data, instructions, and signals to one or more external devices via interface circuitry 1006. Although the core 1002 of this example includes example local memory 1020 (e.g., a Level 1 (L1) cache, which can be divided into an L1 data cache and an L1 instruction cache), the microprocessor 1000 also includes example shared memory 1010 (e.g., a Level 2 (L2) cache) that can be shared by the core for high-speed access to data and instructions. Data and instructions can be transferred (e.g., shared) by writing to or reading from the shared memory 1010. The local memory 1020 and the shared memory 1010 of each of the cores 1002 may be multi-level cache memory and main memory (e.g., Figure 9 The cache is part of the memory device hierarchy (914, 916) of the main memory. In some cases, higher-level memories in the hierarchy exhibit shorter access times and smaller storage capacities compared to lower-level memories. Changes to the various levels of the cache hierarchy are managed by cache coherence strategies (e.g., reconciliation).

[0162] Each core 1002 may be referred to as a CPU, DSP, GPU, or any other type of hardware circuit system. Each core 1002 includes a control unit circuit system 1014, an arithmetic and logic (AL) circuit system (sometimes referred to as an ALU) 1016, multiple registers 1018, local memory 1020, and a second example bus 1022. Other structures may exist. For example, each core 1002 may include a vector unit circuit system, a single instruction multiple data (SIMD) unit circuit system, a load / store unit (LSU) circuit system, a branch / jump unit circuit system, a floating-point unit (FPU) circuit system, etc. The control unit circuit system 1014 includes semiconductor-based circuitry configured to control (e.g., coordinate) the movement of data within the corresponding core 1002. The AL circuit system 1016 includes semiconductor-based circuitry configured to perform one or more mathematical or logical operations on the data within the corresponding core 1002. Some instances of the AL circuit system 1016 perform integer-based operations. In other instances, the AL circuit system 1016 also performs floating-point arithmetic. In still other instances, the AL circuit system 1016 may comprise a first AL circuit system that performs integer-based arithmetic and a second AL circuit system that performs floating-point arithmetic. In some instances, the AL circuit system 1016 may be referred to as an arithmetic logic unit (ALU).

[0163] Register 1018 is a semiconductor-based structure used to store data and instructions, such as the results of one or more operations performed by the AI ​​circuit system 1016 corresponding to core 1002. For example, register 1018 may contain vector registers, SIMD registers, general-purpose registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Register 1018 can be arranged in groups, such as... Figure 10 As shown. Alternatively, register 1018 can be organized in any other arrangement, format, or structure, for example, distributed throughout core 1002 to reduce access time. The second bus 1022 can be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0164] Each core 1002, or more generally, the microprocessor 1000, may include additional or alternative structures to those shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergence / common grid sites (CMS), one or more shifters (e.g., one or more barrel shifters), or other circuitry may be present. The microprocessor 1000 is a semiconductor device fabricated to include a plurality of interconnected transistors for implementing the structures described above in one or more integrated circuits (ICs) contained in one or more packages.

[0165] The microprocessor 1000 may include or cooperate with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some instances, accelerators are implemented by logic circuitry to perform certain tasks faster and more efficiently than a general-purpose processor. Examples of accelerators include, for example, ASICs and FPGAs described herein. GPUs, DSPs, or other programmable devices may also be accelerators. Accelerators may be on the microprocessor 1000, in the same chip package as the microprocessor 1000, or in one or more separate packages from the microprocessor 1000.

[0166] Figure 11 yes Figure 9 A block diagram of another example embodiment of the programmable circuit system 912 is shown. In this example, the programmable circuit system 912 is implemented by an FPGA circuit system 1100. For example, the FPGA circuit system 1100 may be implemented by an FPGA. The FPGA circuit system 1100 can be used, for example, to execute instructions that would otherwise be implemented by a machine-readable controller. Figure 10 The example microprocessor 1000 performs the operations. However, once configured, the FPGA circuit system 1100 instantiates operations and functions corresponding to machine-readable instructions in hardware, and therefore, operations / functions are typically performed faster than those that can be performed by a general-purpose microprocessor implementing the corresponding software.

[0167] More specifically, as described above Figure 10 The microprocessor 1000 (which can be programmed to execute by) Figure 4 and 7 In contrast, a flowchart representing some or all of the general-purpose devices in machine-readable instructions, but whose interconnections and logic circuitry are fixed once manufactured, Figure 11 The FPGA circuit system 1100 of the example includes interconnects and logic circuits that can be configured, constructed, programmed, and interconnected in different ways or in combination after manufacturing to instantiate, for example, those corresponding to those made by... Figure 4 and 7The flowchart represents some or all of the operations / functions of machine-readable instructions. Specifically, the FPGA circuit system 1100 can be considered as an array of logic gates, interconnects, and switches. Switches can be programmed to change the way logic gates are interconnected via interconnects, thereby effectively forming one or more dedicated logic circuits (unless and until the FPGA circuit system 1100 is reprogrammed). The configured logic circuits enable logic gates to cooperate in different ways to perform different operations on data received by the input circuit system. Those operations can correspond to those performed by… Figure 4 and 7 The flowchart represents some or all of the instructions (e.g., software and / or firmware). Therefore, the FPGA circuit system 1100 can be configured or constructed in at least one of the following ways to effectively utilize the corresponding... Figure 4 and 7 The flowchart instantiates some or all of the machine-readable instructions' operations / functions into dedicated logic circuits, thereby performing the operations / functions corresponding to those software instructions in a dedicated manner similar to that of an ASIC. Therefore, it is comparable to the general-purpose microprocessor that can implement operations / functions corresponding to those software instructions. Figure 4 and 7 Compared to some or all of the operations / functions in machine-readable instructions, the FPGA circuit system 1100 can execute the operations / functions faster.

[0168] exist Figure 11 In some instances, the FPGA circuit system 1100 is configured or constructed in response to being programmed (or reprogrammed one or more times) based on a binary file. In some instances, the binary file may be compiled or generated based on instructions in, for example, a hardware description language (HDL) such as Lucid, a Very High Speed ​​Integrated Circuit (VHSIC) hardware description language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) may write code or programs corresponding to one or more operations / functions in the HDL; the code / program may be translated into a low-level language as needed; and the code / program (e.g., code / program in a low-level language) may be translated into a binary file (e.g., by a compiler, software application, etc.). In some instances, Figure 11 The FPGA circuit system 1100 can access or load at least one of binary files, so that... Figure 11 The FPGA circuit system 1100 is configured or constructed to perform at least one of the following operations / functions: (For example, a binary file may be generated by...) Figure 11 The FPGA circuit system 1100 can access one or a combination of bit streams (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) or machine-readable instructions to perform operations on... Figure 11At least one of the FPGA circuit system 1100 or a portion thereof is configured or constructed.

[0169] In some instances, at least one of the following operations is performed on the binary file: compiling, generating, transforming, or otherwise outputting it from a unified software platform used for programming FPGAs. For example, the unified software platform can transform a first instruction (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into a second instruction corresponding to one or more operations / functions in HDL. In some such instances, at least one of the following operations is performed on the binary file: compiling, generating, or otherwise outputting it from the unified software platform based on the second instruction. In some instances, Figure 11 The FPGA circuit system 1100 can access or load at least one of binary files, so that... Figure 11 The FPGA circuit system 1100 is configured or constructed to perform at least one of the following operations / functions: (For example, a binary file may be generated by...) Figure 11 The FPGA circuit system 1100 can access one or a combination of bit streams (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) or machine-readable instructions to perform operations on... Figure 11 At least one of the FPGA circuit system 1100 or a portion thereof is configured or constructed.

[0170] Figure 11 The FPGA circuit system 1100 includes an example input / output (I / O) circuit system 1102 to perform at least one of the following operations: obtaining data from at least one of the example configuration circuit system 1104 or external hardware 1106, or outputting data to at least one of the example configuration circuit system or the external hardware. For example, the configuration circuit system 1104 may be implemented by an interface circuit system that provides a binary file, which may be implemented by one or more of bitstreams, data, or machine-readable instructions to configure the FPGA circuit system 1100 or a portion thereof. In some such instances, the configuration circuit system 1104 may obtain the binary file from a user, a machine (e.g., a hardware circuit system (e.g., a programmable or dedicated circuit system) that can implement an artificial intelligence / machine learning (AI / ML) model to generate a binary file), or any combination thereof. In some instances, the external hardware 1106 may be implemented by an external hardware circuit system. For example, the external hardware 1106 may be implemented by... Figure 10 The microprocessor 1000 is implemented.

[0171] FPGA circuit system 1100 also includes an array of example logic gate circuit systems 1108, a plurality of example configurable interconnects 1110, and an example memory circuit system 1112. The logic gate circuit systems 1108 and the configurable interconnects 1110 can be configured to instantiate corresponding to... Figure 4 and 7 One or more operations / functions and / or other desired operations in at least some of the machine-readable instructions. Figure 11 The logic gate system 1108 shown is manufactured in blocks or groups. Each block contains semiconductor-based electrical structures that can be configured into logic circuits. In some instances, the electrical structures contain logic gates (e.g., AND gates, OR gates, Nor gates, etc.) that provide basic building blocks for the logic circuits. Electrically controlled switches (e.g., transistors) are present in each of the logic gate system 1108 to enable the configuration of one or a combination of electrical structures or logic gates to form circuitry for performing desired operations / functions. The logic gate system 1108 may include other electrical structures such as lookup tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

[0172] The configurable interconnect 1110 of the example shown is a conductive path, trace, via, etc., that may contain electrically controlled switches (e.g., transistors), the state of which can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuit system 1108 to program the desired logic circuit.

[0173] The storage circuit system 1112 of the illustrated example is configured to store the result of one or more of the operations performed by the corresponding logic gates. The storage circuit system 1112 may be implemented by registers, etc. In the illustrated example, the storage circuit system 1112 is distributed within the logic gate circuit system 1108 to facilitate access and improve execution speed.

[0174] Figure 11The example FPGA circuit system 1100 also includes an example dedicated computing circuit system 1114. In this example, the dedicated computing circuit system 1114 includes a dedicated circuit system 1116 that can be invoked to implement common functions, thus eliminating the need for on-site programming of those functions. Examples of such dedicated circuit systems 1116 include memory (e.g., DRAM) controller circuit systems, PCIe controller circuit systems, clock circuit systems, transceiver circuit systems, memory and multiplier-accumulator circuit systems. Other types of dedicated circuit systems may exist. In some instances, the FPGA circuit system 1100 may also include an example general-purpose programmable circuit system 1118, such as an example CPU 1120 or an example DSP 1122. Alternatively or additionally, other general-purpose programmable circuit systems 1118 that can be programmed to perform other operations may exist, such as GPUs, XPUs, etc.

[0175] although Figure 10 and 11 It shows Figure 9 The two example implementations of the programmable circuit system 912 are provided, but many other approaches are conceivable. For example, the FPGA circuit system may include an onboard CPU, such as... Figure 10 One or more of the example CPUs 1120. Therefore, Figure 9 The programmable circuit system 912 can also be combined with at least Figure 10 Example microprocessor 1000 and Figure 11 Example FPGA circuit system 1100 is used for implementation. In some such hybrid instances, Figure 10 One or more cores 1002 can be implemented by Figure 4 and 7 The flowchart represents the first part of machine-readable instructions to perform a first operation / function. Figure 11 The FPGA circuit system 1100 can be configured or constructed to perform at least one of the following functions: Figure 4 and 7 The flowchart represents the second operation / function of the second part of the machine-readable instructions, and / or at least one of the ASICs can be configured or constructed to perform the corresponding operation / function. Figure 4 and 7 The flowchart represents the third operation / function of the third part of the machine-readable instruction.

[0176] therefore, Figure 6 Some or all of the circuitry in a system can be instantiated at the same or different times. For example, Figure 10 The same and / or different parts of the microprocessor 1000 can be programmed to execute one or more parts of machine-readable instructions at the same and / or different times. In some instances, Figure 11At least one of the same and / or different parts of the FPGA circuit system 1100 may be configured or constructed to perform operations / functions corresponding to machine-readable instructions at the same and / or different times.

[0177] In some instances, Figure 6 Some or all of the circuit system can be instantiated, for example, in one or more threads implemented in parallel and / or serial. Figure 10 The microprocessor 1000 can execute machine-readable instructions in one or more threads, in parallel and / or serial execution. In some instances, Figure 11 The FPGA circuit system 1100 can be configured or constructed to operate / function in parallel and / or serially. Furthermore, in some instances, Figure 6 Some or all of the circuit systems can be in Figure 10 It is implemented within one or more virtual machines or containers on a microprocessor 1000.

[0178] In some instances, Figure 9 The programmable circuit system 912 can be housed in one or more packages. For example, Figure 10 microprocessor 1000 or Figure 11 At least one of the FPGA circuitry systems 1100 may be housed in one or more packages. In some instances, the XPU may be derived from... Figure 9 The programmable circuit system 912 is implemented, and the programmable circuit system may be in one or more packages. For example, the XPU may contain a CPU in one package (e.g., Figure 10 microprocessor 1000, Figure 11 CPU 1120, etc.), and DSP in another package (e.g., Figure 11 DSP 1122), GPU in another package, and FPGA in yet another package (e.g., Figure 11 FPGA circuit system 1100).

[0179] Although Figure 6 The implementation is shown in the figure. Figure 1 An example of a programmable circuit system 105, but Figure 6 One or more of the elements, processes, or apparatuses shown may be combined, divided, rearranged, omitted, eliminated, or implemented in any other way. Furthermore, the safety timer circuit system 610, pulse generator circuit system 620, PWM source circuit system 630, and safety monitor circuit system 650, or more generally... Figure 6The example programmable circuit system 600 can be implemented by hardware alone or by hardware in combination with software and firmware. Thus, for example, any of the safety timer circuit system 610, pulse generator circuit system 620, PWM source circuit system 630, and safety monitor circuit system 650, or more generally, the example programmable circuit system 600, can be implemented by a programmable circuit system in combination with one or more machine-readable instructions (e.g., firmware or software), processor circuit system, analog circuitry, digital circuitry, logic circuitry, programmable processor, programmable microcontroller, graphics processing unit (GPU), digital signal processor (DSP), ASIC, programmable logic device (PLD), or field-programmable logic device (FPLD) (e.g., FPGA). Additionally, besides or instead of Figure 6 In addition to the components shown, Figure 6 The example programmable circuit system 600 may include one or more elements, processes or devices, or may include more than one of any or all of the elements, processes and devices shown.

[0180] Figure 4 and 7 A flowchart is shown representing example machine-readable instructions or example operations, which can be implemented by a programmable circuit system to... Figure 6 At least one of the programmable circuit system 600 is implemented or instantiated, and the example operation can be performed by the programmable circuit system to... Figure 6 At least one of the programmable circuit system 600 is implemented or instantiated. Machine-readable instructions may be provided to the programmable circuit system (e.g., in conjunction with the following). Figure 9 The example processor platform 900 shown in the programmable circuit system 912 implements one or more executable programs or portions of one or more executable programs, and may be incorporated herein by reference. Figure 10 Or, as described in section 11, one or more functions or functional portions performed by the example programmable circuit system (e.g., an FPGA). In some instances, machine-readable instructions cause operations, tasks, etc., to be performed or executed automatically in the real world. As used herein, “automatic” means without human intervention.

[0181] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as one or a combination of the following: cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or optical discs (e.g., Blu-ray discs, optical discs (CDs), digital versatile discs (DVDs), etc.), redundant arrays of independent disks (RAID), registers, ROM, solid-state drives (SSDs), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), or any other storage device or storage disk. The instructions of the non-transitory computer-readable and / or machine-readable media may be programmed or executed by a programmable circuit system located in one or more hardware devices, but the entire program or a portion thereof may alternatively be executed or instantiated by one or more hardware devices other than the programmable circuit system or embodied in dedicated hardware. Machine-readable instructions can be distributed across multiple hardware devices or executed by two or more hardware devices (e.g., server and client hardware devices). For example, client hardware devices can be executed by endpoint client hardware devices (e.g., hardware devices associated with human and / or machine users) or intermediate client hardware device gateways (e.g., radio access networks (RAN)) that facilitate communication between the server and endpoint client hardware devices. Similarly, non-transitory computer-readable storage media can contain one or more media. Furthermore, although references... Figure 4 and 7 The flowchart shown describes the example program, but an implementation can be used instead. Figure 6The example programmable circuit system 600 has many other methods. For example, the execution order of the flowchart blocks can be changed, or some of the described blocks can be changed, eliminated, or combined. Alternatively or additionally, any or all of the flowchart blocks can be implemented by one or more hardware circuits (e.g., processor circuit systems, discrete, integrated analog and / or digital circuit systems, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured to perform corresponding operations without implementing software or firmware. The programmable circuit system can be distributed in different network locations or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.)). For example, the programmable circuit system can be one or a combination of the following: a CPU or FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers across server racks, multiple processors distributed across one or more server racks, etc., or any combination thereof.

[0182] The machine-readable instructions described herein can be stored in one or more of the following formats: compressed format, encrypted format, segmented format, compiled format, executable format, and encapsulated format. The machine-readable instructions described herein can be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), bit streams (e.g., computer-readable bit streams, machine-readable bit streams, etc.)) or data structures (e.g., portions of instructions, codes, representations of codes, etc.), which can be used to create, manufacture, or generate machine-executable instructions. For example, machine-readable instructions can be segmented and stored on one or more storage devices, disks, or computing devices (e.g., servers) located in the same or different locations (e.g., in the cloud, edge devices, etc.) within a network or network set. Machine-readable instructions may require one or more of the following processes: installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, decapsulation, distribution, reallocation, compilation, etc., so that the machine-readable instructions can be directly read, interpreted, or executed by a computing device or other machine. For example, machine-readable instructions may be stored individually in multiple parts compressed, encrypted, or stored on separate computing devices. When these parts are decrypted, decompressed, or combined, they form a set of one or more computer-executable or machine-executable instructions that perform one or more functions or operations, which together may form a program, as described herein.

[0183] In another instance, machine-readable instructions may be stored in a state where they can be read by a programmable circuit system, but libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., need to be added to execute the machine-readable instructions on a particular computing device or another device. In yet another instance, the machine-readable instructions or corresponding programs may need to be configured (e.g., storage settings, data inputs, recorded network addresses, etc.) before they can be executed in whole or in part. Therefore, as used herein, machine-readable, computer-readable, or machine-readable media may contain one or a combination of instructions and programs, regardless of the specific format or state of the machine-readable instructions or programs.

[0184] The machine-readable instructions described in this article can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0185] As mentioned above, Figure 4 and 7Example operations can be performed using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and non-transitory machine-readable storage media are explicitly defined as comprising any type of computer-readable storage device or disk that does not contain propagation signals and does not contain transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, or non-transitory machine-readable storage media include one or more optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, or any other storage device or disk in which information is stored for any duration (e.g., extended time period, permanent, transient, temporary buffer, cached information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined as comprising any physical (mechanical, magnetic, electromechanical, or electrical) hardware for retaining information for a period of time, but excluding the propagation of signals and the transmission medium. Examples of non-transitory computer-readable storage devices or non-transitory machine-readable storage devices include one or a combination of the following: any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disk, magnetic disk, disk drive, or redundant array of independent disks (RAID) system. As used herein, the term "device" refers to a physical structure, such as one or a combination of the following: mechanical, electromechanical, or electrical equipment, hardware, or circuitry that may or may not be configured by, or manufactured to execute, computer-readable instructions, machine-readable instructions, etc.

[0186] "Including" and "comprises" (and all their forms and tenses) are used herein as open-ended terms. Therefore, whenever a technical solution uses any form of "including" or "comprises" (e.g., includes, encompassing, including, having, etc.) as a preposition or within any type of technical solution citation, additional elements, terms, etc., may exist without exceeding the scope of the corresponding technical solution or citation. As used herein, the phrase "at least" is open-ended when used as a transitional term, for example, in a technical solution preposition, in the same way as the terms "including" and "comprises". The term "and / or" when used, for example, in the form of A, B, and / or C, refers to any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, projects, objects, and things, the phrase “at least one of A and B” means an implementation that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, projects, objects, and things, the phrase “at least one of A or B” means an implementation that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the execution or implementation of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” means an implementation that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or implementation of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” means an implementation scheme that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0187] As used herein, singular references (e.g., "a(a)", "an(an)", "first", "second", etc.) do not exclude plurals. As used herein, the term "a(a)" or "an(an)" refers to one or more of the objects mentioned. The terms "a(a)" (or "an(an)"), "one or more", and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple components, elements, or actions may be implemented by, for example, the same entity or object. Moreover, while individual features may be contained in different instances or technical solutions, these features may be combined, and their inclusion in different instances or technical solutions does not imply that the combination of features is infeasible or disadvantageous at least one of them.

[0188] As used herein, unless otherwise stated, the term "above" describes the relationship of two parts relative to the earth. The first part is above the second part if at least one portion of the second part lies between the earth and the first part. Similarly, as used herein, the first part is "below" the second part when the first part is closer to the earth than the second part. As mentioned above, the first part may be above or below the second part, having one or more of the following conditions: there are other parts between them, there are no other parts between them, the first and second parts are in contact, or the first and second parts are not in direct contact with each other.

[0189] As used herein, a statement that any part (e.g., layer, film, region, area, or plate) is situated on another part in any manner (e.g., positioned thereon, located on thereon, placed thereon, or formed thereon, etc.) indicates that the referenced part is in contact with said other part, or that the referenced part is above said other part, with one or more intermediate parts positioned therebetween.

[0190] As used herein, unless otherwise indicated, a connection reference (e.g., attachment, coupling, connection, and engagement) may include an intermediate member between elements referenced by the connection reference between those elements or by at least one element in relative movement. Thus, a connection reference does not necessarily imply that two elements are directly connected to each other or are in a fixed relationship. As used herein, the statement that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.

[0191] Unless otherwise specifically stated, this document uses descriptive terms such as “first,” “second,” and “third” without intending or otherwise indicating priority, physical order, arrangement, or any sorting in the list, but merely as markers or arbitrary names to distinguish elements for ease of understanding of the described instances. In some instances, the descriptive term “first” may be used to refer to an element in a particular embodiment, while the same element may be referred to in the technical solution by different descriptive terms such as “second” or “third.” In such cases, such descriptive terms are used only to clearly identify those elements within the context of the discussion (e.g., within the technical solution), in which elements may otherwise share the same name.

[0192] As used herein, “approximately” and “about” modify their objects / values ​​to identify the potential for variation in real-world applications. For example, “approximately” and “about” may modify dimensions that may be imprecise due to at least one of manufacturing tolerances or other real-world defects. For example, unless otherwise specified herein, “approximately” and “about” may indicate that such dimensions are within a tolerance of + / - 10%.

[0193] As used herein, the phrase “communication” includes its variations, encompassing one or a combination of direct communication or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication or constant communication, but also includes selective communication at at least one of periodic intervals, predetermined intervals, non-periodic intervals, or one-off events.

[0194] As used herein, a “programmable circuit system” is defined as comprising at least one of the following: (i) one or more special-purpose circuits (e.g., application-specific integrated circuits (ASICs)) that are structured to perform specific operations and comprise one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more general-purpose semiconductor-based circuits that can be programmed with instructions to perform one or more specific functions or operations and comprise one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include programmable microprocessors, such as: a central processing unit (CPU) that can execute a first instruction to perform one or more operations or functions; a field-programmable gate array (FPGA) that can be programmed with a second instruction to configure or structure at least one of the FPGAs, thereby instantiating one or more operations or functions corresponding to the first instruction; a graphics processing unit (GPU) that can execute a first instruction to perform one or more operations or functions; a digital signal processor (DSP) that can execute a first instruction to perform one or more operations or functions; an XPU; a network processing unit (NPU); one or more microcontrollers that can execute a first instruction to perform one or more operations or functions; or an integrated circuit, such as an application-specific integrated circuit (ASIC). For example, an XPU can be implemented by a heterogeneous computing system that includes a variety of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any combination thereof) and configuration technologies (e.g., application programming interfaces (APIs)) that can distribute computing tasks to any or more of the various types of programmable circuit systems that are suitable and can be used to perform computing tasks.

[0195] As used herein, an integrated circuit / circuit system is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, FPGA, chip, microchip, programmable circuit system, semiconductor substrate coupling multiple circuit elements, system-on-a-chip (SoC), etc.

[0196] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0197] A device “configured” to perform a task or function may be configured during manufacturing by the manufacturer (e.g., by programming or hardwiring at least one of) to perform at least one of the following: perform the function, or may be configured (or reconfigured) by the user after manufacturing to perform the function and / or other additional or alternative functions. The configuration may be performed by at least one of firmware or software programming of the device, by at least one of the construction or layout of the device’s hardware components and interconnects, or by a combination thereof.

[0198] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0199] In this specification and claims, the described "circuit system" may comprise one or more circuits. Circuits or devices described herein as including certain components may alternatively be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., one or a combination of resistors, capacitors, or inductors), or one or more sources (e.g., voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., at least one in a semiconductor die or integrated circuit (IC) package) and may be adapted to be coupled, during or after manufacturing, for example by at least one of an end user or a third party, to at least some of the passive elements or sources to form the described structure.

[0200] The circuits described herein can be reconfigured to include the replaced components, thereby providing functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in at least one of series or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor. While some elements in the described examples are included in the integrated circuit and others are outside the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features shown as outside the integrated circuit may be included in the integrated circuit, and some features shown as inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are at least one of the following: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; or (iv) incorporated in / on the same printed circuit board.

[0201] The use of the phrase “ground” in the foregoing description includes at least one of chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, or any other form of grounding connection applicable to or suited to the teachings of this specification. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value indicates + / - 10% of said value, or, if the value is zero, a reasonable range of values ​​near zero.

[0202] Within the scope of the claims, modifications to the described embodiments are possible, and other embodiments are also possible.

Claims

1. An apparatus comprising: A charge injection circuit system having a first terminal, a second terminal, and a control terminal; A first inductor-capacitor LC circuit system has a first terminal and a second terminal, wherein the first terminal of the first LC circuit system is coupled to the first terminal of the charge injection circuit system, and the second terminal of the first LC circuit system is coupled to the second terminal of the charge injection circuit system. The second LC circuit system is magnetically coupled to the first LC circuit system; as well as A current sensing circuit system having an input terminal coupled to the control terminal of the charge injection circuit system.

2. The device of claim 1, wherein the charge injection circuit system comprises: A current source circuit system having a first terminal and a control terminal; A first transistor having a first terminal, a second terminal, and a control terminal; and The second transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor is coupled to the first terminal of the current source circuit system and the first terminal of the first transistor. The second terminal of the second transistor is coupled to the first terminal of the first LC circuit system and the control terminal of the first transistor. The control terminal of the second transistor is coupled to the second terminal of the first LC circuit system and the second terminal of the first transistor.

3. The device according to claim 2, wherein the current source circuit system is a third transistor having a first terminal and a control terminal, the first terminal of the third transistor being coupled to the first terminal of the first transistor and the first terminal of the second transistor, and the control terminal of the third transistor being coupled to the input terminal of the current sensing circuit system.

4. The device according to claim 1, wherein the first LC circuit system comprises: An inductor having a first terminal and a second terminal; and A capacitor having a first terminal and a second terminal, the first terminal of the capacitor being coupled to a first terminal of the charge injection circuit system and a first terminal of the inductor, and the second terminal of the capacitor being coupled to a second terminal of the charge injection circuit system and a second terminal of the inductor.

5. The device of claim 1, wherein the current sensing circuit system comprises: A transistor having a first terminal and a control terminal, the control terminal of the transistor being coupled to the control terminal of the charge injection circuit system; A comparator circuit system having an input terminal and an output terminal, wherein the input terminal of the comparator circuit system is coupled to the first terminal of the transistor; as well as An inverter having an input terminal coupled to the output terminal of the comparator circuit system.

6. The device of claim 5, wherein the current sensing circuit system further comprises: A resistor having a terminal coupled to the first terminal of the transistor and the input terminal of the comparator circuit system; A level shifter circuit system having an input terminal and an output terminal, the input terminal of the level shifter circuit system being coupled to the output terminal of the comparator circuit system; and A buffer circuit system having an input terminal and an output terminal, wherein the input terminal of the buffer circuit system is coupled to the output terminal of the level shifter circuit system, and the output terminal of the buffer circuit system is coupled to the input terminal of the inverter.

7. The device of claim 1, wherein the second LC circuit system has a first terminal and a second terminal, and the device further comprises: A receiver circuit system having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the receiver circuit system is coupled to the first terminal of the second LC circuit system, and the second input terminal of the receiver circuit system is coupled to the second terminal of the second LC circuit system. A deburring circuit system having an input terminal and an output terminal, wherein the input terminal of the deburring circuit system is coupled to the output terminal of the receiver circuit system; as well as A transistor having a control terminal coupled to the output terminal of the deburring circuit system.

8. An apparatus comprising: A charge injection circuit system having a first terminal, a second terminal, and a control terminal; A transformer having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal of the transformer is coupled to the first terminal of the charge injection circuit system, and the second input terminal of the transformer is coupled to the second terminal of the charge injection circuit system; A current sensing circuit system having an input terminal coupled to the control terminal of the charge injection circuit system; as well as A receiver circuit system having a first input terminal and a second input terminal, the first input terminal of the receiver circuit system being coupled to the first output terminal of the transformer, and the second input terminal of the receiver circuit system being coupled to the second output terminal of the transformer.

9. The device of claim 8, wherein the charge injection circuit system comprises: A current source circuit system having a first terminal and a control terminal; A first transistor having a first terminal, a second terminal, and a control terminal; and The second transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor is coupled to the first terminal of the current source circuit system and the first terminal of the first transistor. The second terminal of the second transistor is coupled to the first input terminal of the transformer and the control terminal of the first transistor. The control terminal of the second transistor is coupled to the second input terminal of the transformer and the second terminal of the first transistor.

10. The device of claim 9, wherein the current source circuit system is a third transistor having a first terminal and a control terminal, the first terminal of the third transistor being coupled to the first terminal of the first transistor and the first terminal of the second transistor, and the control terminal of the third transistor being coupled to the input terminal of the current sensing circuit system.

11. The apparatus of claim 8, wherein the transformer comprises: A first inductor-capacitor LC circuit system has a first terminal and a second terminal, wherein the first terminal of the first LC circuit system is coupled to the first terminal of the charge injection circuit system, and the second terminal of the first LC circuit system is coupled to the second terminal of the charge injection circuit system; and A second LC circuit system has a first terminal and a second terminal. The first terminal of the second LC circuit system is coupled to the first input terminal of the receiver circuit system, and the second terminal of the second LC circuit system is coupled to the second input terminal of the receiver circuit system. The second LC circuit system is magnetically coupled to the first LC circuit system.

12. The device of claim 8, wherein the charge injection circuit system, the transformer, and the receiver circuit system are a first gate driver circuit system having an output terminal, and the device further comprises: The second gate driver circuit system has an output terminal; The third gate driver circuit system has an output terminal; as well as An electric motor having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the electric motor is coupled to the output terminal of a first gate driver circuit system, the second terminal of the electric motor is coupled to the output terminal of a second gate driver circuit system, and the third terminal of the electric motor is coupled to the output terminal of a third gate driver circuit system.

13. The device of claim 8, wherein the current sensing circuit system comprises: A transistor having a first terminal and a control terminal, the control terminal of the transistor being coupled to the control terminal of the charge injection circuit system; A comparator circuit system having an input terminal and an output terminal, wherein the input terminal of the comparator circuit system is coupled to the first terminal of the transistor; as well as An inverter having an input terminal coupled to the output terminal of the comparator circuit system.

14. The device of claim 8, wherein the receiver circuitry further has an output terminal, and the device further comprises: A deburring circuit system having an input terminal and an output terminal, wherein the input terminal of the deburring circuit system is coupled to the output terminal of the receiver circuit system; as well as A transistor having a control terminal coupled to the output terminal of the deburring circuit system.

15. An apparatus comprising: The gate driver circuit system is configured as follows: Receive pulse width modulation (PWM) signals; The current is generated based on the logic state of the PWM signal; and A sinusoidal signal is generated in response to the current; and The current sensing circuit system is configured as follows: Sensing the generation of the current by the gate driver circuit system; and A logic state for setting a safety signal in response to sensing the generation of the current.

16. The device of claim 15, wherein the gate driver circuitry is further configured to inject the current into the inductor-capacitor (LC) circuitry to generate the sinusoidal signal.

17. The device of claim 15, wherein the current sensing circuit system is further configured to: In response to the gate driver circuitry generating the current, the logic state of the safety signal is set to a first logic state; and In response to the gate driver circuit system not generating the current, the logic state of the safety signal is set to the second logic state.

18. The device of claim 15, wherein the current sensing circuitry is further configured to invert the safety signal.

19. The device of claim 15, wherein the current sensing circuitry is further configured to disable the gate driver circuitry in response to setting the safety signal to a logic state that matches the logic state of the PWM signal.

20. The device of claim 15, wherein the PWM signal is a first PWM signal, and the gate driver circuitry is further configured to: Transmit the sinusoidal signal across the isolation barrier; A second PWM signal is generated in response to the sinusoidal signal passing through the isolation barrier; and De-glitching is performed on pulses of the second PWM signal whose duration is shorter than the shortest duration.

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