Management method, device, system and equipment of test board card

Abstract

The invention provides a test board card management method, device, system and equipment, and the method comprises the steps: determining a corresponding relation between a server and a test board card through a system bus scanning operation, and carrying out the scanning operation based on the corresponding relation between a slot position and a test channel; the method comprises the following steps: controlling a test channel corresponding to each slot to perform level switching and detecting an output level change condition of each test board card to determine a corresponding relationship between the slot and the test board card, thereby generating a target corresponding relationship table capable of representing the corresponding relationship among a server, the slot and the test board card; compared with a mode of manually checking and recording the mapping relation in the prior art, an automatic identification scheme for the mapping relation in combination with software operation and hardware electric signals is provided, automation of mapping relation confirmation can be achieved, the labor cost is reduced, the accuracy of configuration records is improved, an unsupervised batch configuration mode can be supported, and the user experience is improved. The method is suitable for a large-scale production environment.

Description

Technical Field

[0001] This disclosure relates to automated testing technology, and in particular to a method, apparatus, system and device for managing test boards. Background Technology

[0002] In modern electronic product manufacturing and testing, the Mobile Industry Processor Interface (MIPI) protocol, as the mainstream interface standard for mobile devices, is widely used for the connection and data transmission of components such as cameras, displays, and RF transceivers. With the increasing complexity of products, testing systems often need to be configured with multiple MIPI boards to meet the testing requirements of different functional modules.

[0003] Currently, the mapping relationship between MIPI boards and machine slots in related technologies is mainly configured and recorded manually by technicians. Specifically, technicians manually record the slot into which each MIPI board is inserted based on the hardware connection diagram and configure it accordingly in the testing software.

[0004] However, manually configuring and recording mapping relationships is inefficient. Every time the MIPI board configuration is changed or adjusted, technicians need to re-record and verify the mapping relationships. Moreover, the manual configuration and recording process is prone to oversights, resulting in incorrect recorded mapping relationships. This method is difficult to adapt to complex testing environments with large scale and multiple boards. Summary of the Invention

[0005] To address the aforementioned technical problems, this disclosure provides a method, apparatus, system, and device for managing test boards.

[0006] One aspect of this disclosure provides a method for managing test boards, comprising: The system bus scan operation reads the board identifier of the test board connected to the server, and generates a first correspondence table based on the board identifier and the server identifier of the server. The first correspondence table is used to characterize the correspondence between the server and the test board. Based on the correspondence between slots and test channels, the test channels corresponding to each slot are controlled to perform level switching operations, and the output level of each test board is monitored. Based on the changes in the output level, the correspondence between the test board and the slot is determined, and a second correspondence table is generated. Based on the first correspondence table and the second correspondence table, a target correspondence table is obtained, which includes the correspondence between the server, the test board, and the slot.

[0007] Optionally, the step of controlling the test channels corresponding to each slot to perform level switching operations based on the correspondence between slots and test channels, and monitoring the output level of each test board, and determining the correspondence between the test board and the slot based on the changes in the output level, includes: Obtain the resource configuration list, which includes the number of test boards to be managed, the slot identifiers of the slots to be managed, and the channel configuration parameters. The channel configuration parameters represent the correspondence between the slots and the test channels. For each slot to be managed in the resource configuration list, a control command is sent to the digital input / output board based on the channel configuration parameters to control the test channel corresponding to the slot to be managed to perform the level switching operation and output a preset high level. The pin precision measurement unit continuously monitors the output level of each test board. Based on the changes in the output level of each test board and the timestamp of each level switching operation, the test board that responds to each level switching operation is identified, and the correspondence between the test board and the slot is obtained.

[0008] Optionally, after obtaining the resource configuration list, the method further includes: The validity of the slot to be managed is verified to determine whether the slot exists and is in an idle state. In response to the existence and idle state of the slot to be managed, the digital input / output board is initialized and the level of each test channel is reset to low level.

[0009] Optionally, the method further includes: In response to a level switching operation corresponding to any slot satisfying a preset condition, the level switching operation satisfying the preset condition is repeatedly executed. The preset condition includes at least one of the following: no test board is detected to generate a response and at least two test boards are detected to generate a response. In response to the level switching operation corresponding to any slot reaching a preset number of times and all satisfying the preset conditions, the slot identifier of any slot is written into the abnormal slot list.

[0010] Optionally, the step of reading the board identifier of the test board connected to the server through the system bus scan operation includes: The system connects to the server via a network communication protocol using the Internet Protocol address and sends a board scan command to the server. The server then performs a system bus scan operation based on the board scan command and reads the board identifier of the test board connected to the server. Receive the board identifier sent by the server.

[0011] Optionally, the first correspondence table includes a first key-value pair corresponding to each test board, wherein the first key-value pair includes the board identifier and the server identifier; the second correspondence table includes a second key-value pair corresponding to each test board, wherein the second key-value pair includes the board identifier and the slot identifier. The step of obtaining the target correspondence table based on the first correspondence table and the second correspondence table includes: Using a hash table lookup algorithm, the first key-value pair and the second key-value pair are analyzed for data association using the board identifier as the association key, and a ternary array is constructed. The ternary array includes a slot identifier, a server identifier, and a board identifier with a mapping relationship. Perform data verification on each ternary array and detect abnormal arrays. The abnormal arrays include at least one of the ternary arrays with the same slot identifier and the ternary arrays with the same board identifier. The target correspondence table is generated based on the ternary array that has passed data verification.

[0012] Optionally, after obtaining the target correspondence table based on the first correspondence table and the second correspondence table, the method further includes: Read the historical correspondence table and compare the contents of the target correspondence table with the historical correspondence table to determine whether the correspondence recorded in the target correspondence table is consistent with the correspondence recorded in the historical correspondence table; In response to the fact that the correspondence recorded in the target correspondence table is consistent with the correspondence recorded in the historical correspondence table, a prompt message indicating that the board configuration verification has passed is displayed; In response to the inconsistency between the correspondence recorded in the target correspondence table and the correspondence recorded in the historical correspondence table, a prompt message indicating a board configuration error is displayed, and after receiving a configuration file update operation, the historical correspondence table is replaced with the target correspondence table.

[0013] Another aspect of this disclosure provides a management device for a test board, comprising: The first generation module is used to read the board identifier of the test board connected to the server through a system bus scanning operation, and generate a first correspondence table based on the board identifier and the server identifier of the server. The first correspondence table is used to characterize the correspondence between the server and the test board. The determination module is used to control the test channels corresponding to each slot to perform level switching operations based on the correspondence between slots and test channels, monitor the output level of each test board, determine the correspondence between the test board and the slot based on the changes in the output level, and generate a second correspondence table. The second generation module is used to obtain a target correspondence table based on the first correspondence table and the second correspondence table. The target correspondence table includes the correspondence between the server, the test board, and the slot.

[0014] In another aspect of the present disclosure, a chip testing system is provided, including a host computer, a server, and a chip testing machine, wherein the chip testing machine is provided with at least one slot for loading a test board. The host computer is used for: The system bus scan operation reads the board identifier of the test board connected to the server, and generates a first correspondence table based on the board identifier and the server identifier of the server. The first correspondence table is used to characterize the correspondence between the server and the test board. Based on the correspondence between slots and test channels, the test channels corresponding to each slot are controlled to perform level switching operations, and the output level of each test board is monitored. Based on the changes in the output level, the correspondence between the test board and the slot is determined, and a second correspondence table is generated. Based on the first correspondence table and the second correspondence table, a target correspondence table is obtained, which includes the correspondence between the server, the test board, and the slot.

[0015] In another aspect of this disclosure, an electronic device is provided, comprising: Memory, used to store computer programs; A processor is configured to execute a computer program stored in the memory, wherein, when the computer program is executed, it implements the methods described above.

[0016] In another aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the methods described above.

[0017] In another aspect of this disclosure, a computer program is provided, including computer program instructions that, when executed by a processor, implement the method described above.

[0018] Based on the embodiments of this disclosure, the correspondence between the server and the test board is determined through system bus scanning operations, as well as the correspondence between the slot and the test channel. By controlling the level switching of the test channel corresponding to each slot and detecting the output level changes of each test board, the correspondence between the slot and the test board is determined, thereby generating a target correspondence table that can characterize the correspondence between the server, slot, and test board. Compared with the manual checking and recording of mapping relationships in related technologies, this provides an automatic identification scheme for mapping relationships that combines software operation and hardware electrical signals. It can automate the confirmation of mapping relationships, reduce labor costs and improve the accuracy of configuration records. It can support unsupervised batch configuration mode and is suitable for large-scale production environments.

[0019] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0020] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0021] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein: Figure 1 A flowchart illustrating one embodiment of the management method for the test board disclosed herein; Figure 2 A flowchart illustrating another embodiment of the management method for the test board disclosed herein; Figure 3 A flowchart illustrating another embodiment of the management method for the test board disclosed herein; Figure 4 This is a schematic diagram of the structure of a management device for a test board according to an embodiment of the present disclosure; Figure 5 This is a schematic diagram of another embodiment of the management device for the test board of this disclosure; Figure 6 This is a schematic diagram of the structure of an application embodiment of the electronic device disclosed herein. Detailed Implementation

[0022] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0023] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0024] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0025] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0026] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0027] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0028] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0029] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0030] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0031] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0032] Figure 1 This is a flowchart illustrating a test board management method provided in an exemplary embodiment of the present disclosure. The test board management method of this embodiment can be implemented via a host computer in a chip testing system. The method provided in this embodiment includes the following steps: Step 101: Read the board identifier of the test board connected to the server through the system bus scan operation, and generate a first correspondence table based on the board identifier and the server identifier.

[0033] The first correspondence table mentioned above is used to represent the correspondence between the server and the test board.

[0034] In one possible implementation, the host computer in the chip testing system is communicatively connected to at least one server. In response to receiving a board relationship confirmation command (e.g., a command generated based on a user's board relationship confirmation operation), a system bus scan operation is triggered to read the board identifier of the test board corresponding to each server. Then, the correspondence between the server and the test board is recorded through a first correspondence table, for example, by associating and storing the server identifier and board identifier with the corresponding relationship in the first correspondence table.

[0035] For illustrative purposes, server identifiers may include, but are not limited to, server number, server Internet Protocol address (IP address), etc., and board identifiers may include, but are not limited to, board serial number.

[0036] Optionally, when reading the board identifier of the test board connected to the server through the system bus scanning operation, auxiliary identifiers such as the hardware version and firmware version of the test board connected to the server can also be read and associated with the corresponding board identifier and stored in the first correspondence table.

[0037] Step 102: Based on the correspondence between slots and test channels, control the test channels corresponding to each slot to perform level switching operations, monitor the output level of each test board, determine the correspondence between the test board and the slot based on the changes in the output level, and generate a second correspondence table.

[0038] The second correspondence table mentioned above is used to characterize the correspondence between slots and test boards.

[0039] In a chip testing system, a slot refers to the physical location on the chip testing machine where a test board is inserted, and a test channel is the specific test resource provided by the test board, which may include, but is not limited to, digital signal input / output channels and analog signal measurement channels. In this embodiment, the host computer pre-stores the correspondence between slots and test channels. For example, "slot1.16" indicates that slot 1 corresponds to test channel 16.

[0040] In one possible implementation, by controlling the level switching operation of the test channels corresponding to each slot and monitoring the output level of each test board, the correspondence between the test channels and the test boards can be determined based on the test boards that respond to the level switching operation of each test channel. Then, based on the correspondence between the slots and the test channels, the correspondence between the slots and the test boards can be determined, resulting in a second correspondence table.

[0041] Optionally, the output level of each test board can be monitored by a signal monitoring device, and an identifier reading request can be sent to the test board that generates a response to read the board identifier of the test board, and then a second correspondence table can be generated based on the slot identifier and the board identifier.

[0042] Optionally, the mapping relationship can be confirmed sequentially for each slot in a serial manner. That is, the test channel corresponding to the i-th slot is controlled to perform a level switching operation to determine the test board that generates the response and obtain its board identifier, and then the test channel corresponding to the (i+1)-th slot is controlled to perform a level switching operation, where i is a positive integer. Alternatively, the mapping relationship can be confirmed in parallel for each slot. For example, for different slots, the test channel can be set to output a high level for different durations, and then the response duration can be determined based on the output signal of each test board, thereby determining the correspondence between the test board and the slot.

[0043] Step 103: Based on the first correspondence table and the second correspondence table, obtain the target correspondence table, which includes the correspondence between the server, the test board, and the slot.

[0044] Since step 101 above generates a first correspondence table recording the correspondence between the server and the test board, and step 102 above generates a second correspondence table recording the correspondence between the slot and the test board, data can be integrated using the board identifier as the keyword to obtain the ternary mapping relationship between the slot, the server, and the test board, and generate the target correspondence table.

[0045] Based on the embodiments of this disclosure, the correspondence between the server and the test board is determined through system bus scanning operations, as well as the correspondence between the slot and the test channel. By controlling the level switching of the test channel corresponding to each slot and detecting the output level changes of each test board, the correspondence between the slot and the test board is determined, thereby generating a target correspondence table that can characterize the correspondence between the server, slot, and test board. Compared with the manual checking and recording of mapping relationships in related technologies, this provides an automatic identification scheme for mapping relationships that combines software operation and hardware electrical signals. It can automate the confirmation of mapping relationships, reduce labor costs and improve the accuracy of configuration records. It can support unsupervised batch configuration mode and is suitable for large-scale production environments.

[0046] Optionally, level switching can be achieved by controlling the preset level output of the test channel. Correspondingly, such as... Figure 2 As shown, step 102 above may further include the following steps: Step 201: Obtain the resource configuration list, which includes the number of test boards to be managed, the slot identifiers of the slots to be managed, and the channel configuration parameters.

[0047] The above channel configuration parameters are used to characterize the correspondence between slots and test channels.

[0048] In one possible implementation, the host computer receives a resource configuration list input by the user through an application, automatically parses and extracts information from the resource configuration list, namely the number of test boards to be managed, the slot identifiers of the slots to be managed, and the channel configuration parameters.

[0049] Step 202: For each slot to be managed in the resource configuration list, send a control command to the digital input / output board based on the channel configuration parameters to control the test channel corresponding to the slot to be managed to perform a level switching operation and output a preset high level.

[0050] In one possible implementation, based on the channel configuration parameters in the resource configuration list, a control command is sent to the Digital Input / Digital Output (DIO) board via a digital interface to control the specified digital output pin to output a preset high level (e.g., 5V), causing the digital output pin to switch from a low level to a high level. This signal is transmitted to the input port of the corresponding slot through the printed circuit board (PCB) traces.

[0051] Optionally, the above-mentioned preset high level can be set to a signal holding duration, for example, the signal holding duration can be set to 50 milliseconds, so as to avoid failing to detect the response signal of the test board in time.

[0052] In another possible implementation, the test channel corresponding to the slot to be managed can also be controlled to perform a level switching operation, outputting a preset low level (e.g., 0V), so that the digital output pin of the DIO board generates a level switch from high level to low level.

[0053] Step 203: The output level of each test board is continuously monitored by the pin precision measurement unit. Based on the changes in the output level of each test board and the timestamp of each level switching operation, the test board that responds to each level switching operation is identified, and the correspondence between the test board and the slot is obtained.

[0054] Optionally, a Per Pin Measurement Unit (PPMU) can be used to continuously monitor the output level of each test board, and the acquired level signals can be filtered to eliminate noise interference. The test board that responds to each level switching operation is determined based on the changes in the output level. Specifically, the correspondence between the test board and the slot can be determined based on the timestamps of each level switching operation and the transition time of the output level of each test board. For example, for slot 1, its test channel is controlled to output a preset high level from 0ms to 50ms; for slot 2, its test channel is controlled to output a preset high level from 50ms to 100ms. If a transition in the output level of a certain test board is detected at 10ms, then that test board is determined to correspond to slot 1.

[0055] In one possible implementation, after obtaining the resource configuration list, the records in the resource configuration list can be verified first to avoid invalid operations. Following step 201 above, the method provided in this disclosure may further include the following steps; The validity of the slot to be managed is verified to determine whether the slot exists and is in an idle state; in response to the existence and idle state of the slot to be managed, the digital input / output board is initialized and the level of each test channel is reset to low level.

[0056] Optionally, the slot identifiers of the slots to be managed in the resource configuration list can be compared with the slot identifiers in the pre-stored chip testing system to determine whether the slots to be managed belong to the slots supported by the chip testing system, and the status of each slot to be managed can be read to determine whether it is in an idle state. If the slot to be managed exists and is in an idle state, the validity verification of the slot to be managed passes; if the slot to be managed does not exist or is not in an idle state, the validity verification of the slot to be managed fails.

[0057] Correspondingly, if the level switching operation is to control the test channel to output a preset high level, then the level of each test channel is first reset to a low level; if the level switching operation is to control the test channel to output a preset low level, then the level of each test channel is first set to a high level.

[0058] Based on the embodiments of this disclosure, before performing a level switching operation to confirm the correspondence between the slot and the test chip, the data in the resource configuration list is first validated to avoid invalid operations on slots that do not exist in the system or are not in an idle state.

[0059] In one possible implementation, when monitoring the output level of the test board, abnormal responses can be further processed, and the method provided in this disclosure may also include the following steps; In response to a level switching operation corresponding to any slot satisfying a preset condition, the level switching operation satisfying the preset condition is repeatedly executed. The preset condition includes no test board that generates a response and at least one of at least two test boards that generate a response. In response to a level switching operation corresponding to any slot reaching a preset number of times and all satisfying the preset condition, the slot identifier of any slot is written to the abnormal slot list.

[0060] For any given slot, if there is no response or multiple responses (at least two test boards respond) during the level switching of the corresponding test channel (i.e., switching from low level to high level and then back to low level), the level switching of the test channel corresponding to that slot can be attempted again. If the above abnormal response still occurs after a preset number of times (e.g., 3 times), or if the number of times the above abnormal response occurs reaches the preset number of abnormal responses, then the connection relationship of that slot is determined to be abnormal. The slot identifier of that slot is written into the abnormal slot list and displayed through the application interface.

[0061] Based on the embodiments of this disclosure, by setting an abnormal response identification mechanism, slots and test boards with abnormal connection relationships can be automatically identified, thereby improving the accuracy of the target correspondence table.

[0062] In one possible implementation, the host computer can control the server to perform a system bus scan operation and read the board identifier of the corresponding connected test board. Accordingly, step 101 above can further include the following steps: The system connects to the server's IP address via a network communication protocol and sends a board scan command to the server. The server then performs a system bus scan based on the board scan command, reads the board identifier of the test board connected to the server, and receives the board identifier sent by the server.

[0063] Specifically, the host computer connects to the IP address of a designated server via a network communication protocol and sends a board scan command to the corresponding server. In response to this command, the server sends a board identifier read request to the corresponding connected test board, or directly reads the board identifier from a pre-stored board configuration list on the server. Once the server obtains the board identifier, it sends it back to the host computer. Optionally, the host computer can simultaneously connect to at least one server.

[0064] In one possible implementation, the first correspondence table includes first key-value pairs corresponding to each test board, each key-value pair including a board identifier and a server identifier. The second correspondence table includes second key-value pairs corresponding to each test board, each second key-value pair including a board identifier and a slot identifier. Correspondingly, as... Figure 3 As shown, step 103 above may further include the following steps: Step 301: Using a hash table lookup algorithm, perform data association analysis on the first key-value pair and the second key-value pair with the board identifier as the association key to construct a ternary array.

[0065] This ternary array includes slot identifiers, server identifiers, and board identifiers that have a mapping relationship.

[0066] For illustration, assume that at least one first key-value pair {Server IP: [MIPI_SN]} in the first mapping table is as follows: (Server IP is the server identifier, MIPI_SN is the board identifier) 192.168.0.100—["SN001", "SN002", "SN003"] 192.168.0.101—["SN004", "SN005", "SN006"] 192.168.0.102—["SN007", "SN008", "SN009"] Suppose that at least one second key-value pair {Site ID: MIPI_SN} (Site ID is the slot identifier, MIPI_SN is the board identifier) ​​in the second correspondence table is as follows: Site_A—“SN001” Site_B—“SN002” Site_C—“SN003” Site_D—“SN004” Site_E—“SN005” Site_F—“SN009” Based on the first and second key-value pairs mentioned above, the resulting triple array {Site ID, Server IP, MIPI_SN} is as follows: Site_A—192.168.0.100—“SN001” Site_B—192.168.0.100—“SN002” Site_C—192.168.0.100—“SN003” Site_D—192.168.0.101—“SN004” Site_E—192.168.0.101—“SN005” Site_F—192.168.0.102—"SN009" Step 302: Perform data validation on each triplet array and detect abnormal arrays.

[0067] The exception array includes at least one of the following: a ternary array with the same slot identifier and a ternary array with the same board identifier.

[0068] Step 303: Generate a target correspondence table based on the ternary array that has passed data verification.

[0069] After constructing the ternary arrays corresponding to each test board, the consistency and completeness of the ternary arrays are further verified. Abnormal arrays include at least one of the following: ternary arrays with the same slot identifier and ternary arrays with the same board identifier. Furthermore, it can be determined whether the number of ternary arrays matches the number of test boards to be managed in the resource configuration list. If the number of ternary arrays is less than the number of test boards to be managed in the resource configuration list, the ternary arrays are determined to be incomplete. The board identifiers that failed to generate ternary arrays can be queried based on the first or second correspondence table and displayed through the application interface.

[0070] In one possible implementation, the host computer can periodically confirm the mapping relationship between the server, test board, and slot; or, after detecting a configuration update operation, it can confirm the mapping relationship between the server, test board, and slot, and compare the mapping relationship based on the obtained target mapping relationship table and the historical mapping relationship table to detect changes in the mapping relationship. Following step 103 above, the method provided in this disclosure may further include the following steps: The system reads the historical mapping table and compares the contents of the target mapping table with those of the historical mapping table to determine if the mappings recorded in the target mapping table are consistent with those recorded in the historical mapping table. If the mappings in the target mapping table are consistent with those in the historical mapping table, a message indicating successful board configuration verification is displayed. If the mappings in the target mapping table are inconsistent with those in the historical mapping table, a message indicating a board configuration error is displayed. Furthermore, upon receiving a configuration file update operation, the system replaces the historical mapping table with the target mapping table.

[0071] Optionally, if the correspondence recorded in the target correspondence table is consistent with the correspondence recorded in the historical correspondence table, the historical correspondence table can be directly replaced with the target correspondence table; if the correspondence recorded in the target correspondence table is inconsistent with the correspondence recorded in the historical correspondence table, a prompt message indicating a board configuration error will be displayed, and the inconsistent correspondence can also be displayed so that users can manually check and modify the connection relationship between the server, slot and test board, or perform a configuration file update operation to replace the historical correspondence table with the target correspondence table.

[0072] Based on the above-disclosed embodiments, a multi-verification mechanism is provided. Before the level switching operation, the data in the resource configuration list is validated for validity. During the level switching operation and after the target correspondence table is generated, abnormal data is validated. This can ensure the accuracy of the target correspondence table to a certain extent. Furthermore, the use of a dynamic update mechanism can significantly reduce repetitive configuration work.

[0073] Please refer to Figure 4 This illustration shows a structural block diagram of a test board management device provided in an exemplary embodiment of the present disclosure. The test board management device provided in this embodiment includes: The first generation module 401 is used to read the board identifier of the test board connected to the server through the system bus scanning operation, and generate a first correspondence table based on the board identifier and the server identifier of the server. The first correspondence table is used to characterize the correspondence between the server and the test board. The determination module 402 is used to control the test channels corresponding to each slot to perform level switching operations based on the correspondence between slots and test channels, monitor the output level of each test board, determine the correspondence between test boards and slots based on the changes in output level, and generate a second correspondence table. The second generation module 403 is used to obtain a target correspondence table based on the first correspondence table and the second correspondence table. The target correspondence table includes the correspondence between servers, test boards and slots.

[0074] Optionally, the aforementioned determining module 402 can be further used for: Get the resource configuration list, which includes the number of test boards to be managed, the slot identifiers of the slots to be managed, and the channel configuration parameters. The channel configuration parameters represent the correspondence between the slots and the test channels. For each slot to be managed in the resource configuration list, control commands are sent to the digital input / output board based on the channel configuration parameters to control the test channel corresponding to the slot to be managed to perform level switching operation and output a preset high level. The pin precision measurement unit continuously monitors the output level of each test board. Based on the changes in the output level of each test board and the timestamp of each level switching operation, the test board that responds to each level switching operation is identified, and the correspondence between the test board and the slot is obtained.

[0075] Optional, such as Figure 5 As shown, the management device for the test board provided in this embodiment may further include: The verification module 501 is used to verify the validity of the slots to be managed, and to determine whether the slots to be managed exist and are in an idle state. The initialization module 502 is used to initialize the digital input / output board in response to the existence and idle state of the slot to be managed, and to reset the level of each test channel to a low level.

[0076] Optionally, the management device for the test board provided in this embodiment may further include: The verification module is used to repeatedly execute the level switching operation that meets the preset conditions in response to any level switching operation corresponding to any slot. The preset conditions include no test board that generates a response and at least one of at least two test boards that generate a response. The first anomaly identification module is used to write the slot identifier of any slot into the abnormal slot list when the level switching operation corresponding to any slot reaches a preset number of times and all preset conditions are met.

[0077] Optionally, the first generation module 401 described above can be further used for: The system connects to the server via the Internet Protocol address using a network communication protocol and sends a board scan command to the server. The server then performs a system bus scan based on the board scan command and reads the board identifier of the test board connected to the server. Receive the board identifier sent by the server.

[0078] Optionally, the first correspondence table includes a first key-value pair corresponding to each test board, which includes a board identifier and a server identifier. The second correspondence table includes a second key-value pair corresponding to each test board, which includes a board identifier and a slot identifier. The second generation module 403 described above can be further used for: Using a hash table lookup algorithm, the first key-value pair and the second key-value pair are analyzed for data association using the board identifier as the association key, and a ternary array is constructed. This ternary array includes slot identifier, server identifier, and board identifier with a mapping relationship. Perform data validation on each ternary array and detect abnormal arrays. The abnormal arrays include at least one of the ternary arrays with the same slot identifier and the ternary arrays with the same board identifier. A target correspondence table is generated based on the ternary array that has passed data validation.

[0079] Optionally, the management device for the test board provided in this embodiment may further include: The comparison module is used to read the historical correspondence table and compare the contents of the target correspondence table with the historical correspondence table to determine whether the correspondence recorded in the target correspondence table is consistent with the correspondence recorded in the historical correspondence table. The first display module is used to display a prompt message indicating that the board configuration verification has passed when the correspondence recorded in the target correspondence table matches the correspondence recorded in the historical correspondence table. The second display module is used to display a prompt message indicating a card configuration error when the correspondence recorded in the target correspondence table is inconsistent with the correspondence recorded in the historical correspondence table, and to replace the historical correspondence table with the target correspondence table after receiving a configuration file update operation.

[0080] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar, identical, or corresponding parts between embodiments can be referred to mutually. Since the method, apparatus, and device embodiments are basically corresponding, relevant parts can be referred to the corresponding descriptions. The methods, apparatus, and devices in the embodiments of this disclosure also correspond to each other in specific implementation and beneficial technical effects; related content can be referred to mutually and will not be repeated here.

[0081] In addition, this disclosure also provides an electronic device, including: Memory, used to store computer programs; A processor is configured to execute a computer program stored in the memory, and when the computer program is executed, to implement the test board management method described in any of the above embodiments of this disclosure.

[0082] Figure 6 This is a schematic diagram illustrating the structure of an application embodiment of the electronic device disclosed herein. Below, reference is made to… Figure 6 This describes an electronic device according to embodiments of the present disclosure. The electronic device may be either or both of a first device and a second device, or a standalone device independent of them, which may communicate with the first device and the second device to receive acquired input signals from them.

[0083] like Figure 6 As shown, the electronic device includes one or more processors and memory.

[0084] A processor can be a central processing unit (CPU) or other form of processing unit with data processing and / or instruction execution capabilities, and can control other components in an electronic device to perform desired functions.

[0085] The memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and a processor may execute the program instructions to implement the test board management methods of the various embodiments of this disclosure described above, and / or other desired functions.

[0086] In one example, the electronic device may also include input devices and output devices, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0087] In addition, the input device may include, for example, a keyboard, a mouse, etc.

[0088] This output device can output various information to the outside, including determined distance information, direction information, etc. The output device may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0089] Of course, for the sake of simplicity, Figure 6 Only some of the components of the electronic device relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device may include any other suitable components depending on the specific application.

[0090] In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products, including computer program instructions that, when executed by a processor, cause the processor to perform the steps in the methods for managing test boards according to various embodiments of this disclosure as described in the foregoing sections of this specification.

[0091] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0092] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the management method of the test board according to various embodiments of this disclosure described in the foregoing portion of this specification.

[0093] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0094] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as ROM, RAM, magnetic disk, or optical disk.

[0095] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0096] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0097] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0098] The methods and apparatus of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the methods according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the methods according to this disclosure.

[0099] It should also be noted that in the apparatus, devices, and methods of this disclosure, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions to this disclosure.

[0100] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0101] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A method of managing test board cards, characterized by, The method comprises the following steps: reading the board card identifier of the test board card connected with the server through the system bus scanning operation, generating a first correspondence table based on the board card identifier and the server identifier of the server, and the first correspondence table is used to represent the correspondence between the server and the test board card; controlling the test channel corresponding to each slot to perform a level switching operation based on the correspondence between the slot and the test channel, and monitoring the output level of each test board card, determining the correspondence between the test board card and the slot based on the change of the output level, and generating a second correspondence table; based on the first correspondence table and the second correspondence table, a target correspondence table is obtained, which includes the correspondence between the server, the test board card and the slot.

2. The method of claim 1, wherein, The method further comprises the following steps: obtaining a resource configuration list, the resource configuration list including the number of test board cards to be managed, the slot identifier of the slot to be managed, and the channel configuration parameter, the channel configuration parameter representing the correspondence between the slot and the test channel; for each of the slots to be managed in the resource configuration list, sending a control instruction to the digital input and output board card based on the channel configuration parameter, controlling the test channel corresponding to the slot to be managed to perform the level switching operation, and outputting a preset high level; continuously monitoring the output level of each test board card through the pin accurate measurement unit, identifying the test board card responding to each level switching operation based on the change of the output level of each test board card and the timestamp of each level switching operation, and obtaining the correspondence between the test board card and the slot.

3. The method of claim 2, wherein, After obtaining the resource configuration list, the method further comprises the following steps: validating the effectiveness of the slot to be managed, and determining whether the slot to be managed exists and is in an idle state; in response to the slot to be managed existing and being in an idle state, initializing the digital input and output board card, and resetting the level of each test channel to a low level.

4. The method of claim 2, wherein, The method further comprises the following steps: in response to any slot corresponding level switching operation satisfying a preset condition, repeating the level switching operation satisfying the preset condition, the preset condition including at least one of not monitoring the responding test board card and monitoring at least two responding test board cards; in response to the level switching operation of any slot reaching a preset number and all satisfying the preset condition, writing the slot identifier of the any slot into an abnormal slot list.

5. The method according to any one of claims 1 to 4, characterized in that, The method further comprises the following steps: An Internet protocol address of the server is connected through a network communication protocol, a board card scanning instruction is sent to the server, the server is used for executing the system bus scanning operation based on the board card scanning instruction, and a board card identifier of a test board card connected with the server is read; The server sends the board card identifier.

6. The method according to any one of claims 1 to 4, characterized in that, The first correspondence table includes a first key-value pair corresponding to each test board card, the first key-value pair includes the board card identifier and the server identifier, and the second correspondence table includes a second key-value pair corresponding to each test board card, the second key-value pair includes the board card identifier and a slot identifier of the slot; The target correspondence table is obtained based on the first correspondence table and the second correspondence table, including: Through a hash table search algorithm, the first key-value pair and the second key-value pair are associated and analyzed based on the board card identifier as an associated key, a three-element array is constructed, and the three-element array includes a slot identifier, a server identifier and a board card identifier having a mapping relationship; Data verification is performed on each three-element array, and an abnormal array is detected, the abnormal array includes at least one of a three-element array with the same slot identifier and a three-element array with the same board card identifier; The target correspondence table is generated based on the three-element array that passes the data verification.

7. The method according to any one of claims 1 to 4, characterized in that, After the target correspondence table is obtained based on the first correspondence table and the second correspondence table, the method further includes: A historical correspondence table is read, and the target correspondence table and the historical correspondence table are compared in content to determine whether the correspondence relationship recorded in the target correspondence table is consistent with the correspondence relationship recorded in the historical correspondence table; In response to the correspondence relationship recorded in the target correspondence table being consistent with the correspondence relationship recorded in the historical correspondence table, prompt information that the board card configuration verification is passed is displayed; In response to the correspondence relationship recorded in the target correspondence table being inconsistent with the correspondence relationship recorded in the historical correspondence table, prompt information that the board card configuration is incorrect is displayed, and after receiving a configuration file update operation, the historical correspondence table is replaced by the target correspondence table.

8. A management apparatus of a test board card, characterized by, Including: A first generation module is configured to read a board card identifier of a test board card connected with a server through a system bus scanning operation, generate a first correspondence table based on the board card identifier and a server identifier of the server, and the first correspondence table is used to represent a correspondence relationship between the server and the test board card; A determination module is configured to control a test channel corresponding to each slot to perform a level switching operation based on a correspondence relationship between the slot and the test channel, monitor an output level of each test board card, determine a correspondence relationship between the test board card and the slot based on a change of the output level, and generate a second correspondence table; A second generation module is configured to obtain a target correspondence table based on the first correspondence table and the second correspondence table, and the target correspondence table includes a correspondence relationship between the server, the test board card and the slot.

9. A chip testing system, characterized by comprising: The chip testing machine is arranged with at least one slot position for loading a test board card. The host computer is used for: reading the board card identification of the test board card connected with the server through the system bus scanning operation, generating a first corresponding relation table based on the board card identification and the server identification of the server, and the first corresponding relation table is used for representing the corresponding relation between the server and the test board card; controlling the test channel corresponding to each slot position to perform a level switching operation based on the corresponding relation between the slot position and the test channel, monitoring the output level of each test board card, determining the corresponding relation between the test board card and the slot position based on the change of the output level, and generating a second corresponding relation table; obtaining a target corresponding relation table based on the first corresponding relation table and the second corresponding relation table, and the target corresponding relation table includes the corresponding relation among the server, the test board card and the slot position.

10. An electronic device, comprising: It includes: a memory for storing a computer program; a processor for executing the computer program stored in the memory, and when the computer program is executed, the method of any one of claims 1-7 is implemented.

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