Data processing device

Abstract

The invention provides a data processing device, which belongs to the technical field of wireless communication, and comprises an FPGA (Field Programmable Gate Array) chip and a data memory for storing air interface IQ (Intelligence Quotient) data, the FPGA chip further comprises a storage interface module; the frequency band digital down-conversion module is used for performing sampling rate conversion on the digital signal input into the FPGA chip to obtain air interface IQ data and storing the air interface IQ data to the data memory; the frequency point digital down-conversion module is used for responding to the starting instruction of the central processing unit, extracting target air interface IQ data according to pre-configured data reading parameters, and performing sampling rate recovery on the target air interface IQ data to obtain output IQ data; and the post-stage processing module is used for processing the output IQ data and returning a processing result to the central processing unit. On the whole, on the basis of a collaborative architecture combining FPGA hardware acceleration and CPU non-real-time scheduling, multi-system multi-cell data unified storage and dynamic processing which are flexible in expansion and easy to maintain are supported.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and more particularly to a data processing device. Background Technology

[0002] Existing multi-standard (4G / 5G / NB-IoT, etc.) and multi-antenna data processing systems often require independent hardware and computing resources for each standard when supporting different standards. This leads to significant architecture modifications when adding standards or cells, resulting in poor scalability. Furthermore, cell synchronization in existing data processing largely relies on FPGAs (Field Programmable Gate Arrays) for maintenance. When scaling to multiple cells, the underlying synchronization maintenance of the FPGA becomes extremely complex.

[0003] Therefore, it is necessary to provide a data processing device that effectively supports multi-standard and multi-antenna data processing. Summary of the Invention

[0004] This invention provides a data processing device to address the shortcomings of existing technologies, such as poor expansion effect of multi-standard and multi-antenna data processing and complex synchronous maintenance, and to achieve a data processing solution with a unified storage architecture and hardware-software co-design.

[0005] This invention provides a data processing device, the data processing device comprising: an FPGA chip and a data storage device for storing air interface IQ data; The FPGA chip also includes: The storage interface module connected to the data storage device; The frequency band digital downconversion module connected to the storage interface module is used to perform sampling rate conversion on the digital signal input to the FPGA chip to obtain the air interface IQ data, and store the air interface IQ data in the data memory. The frequency point digital downconversion module connected to the storage interface module is used to respond to the start command of the central processing unit, extract the target air interface IQ data from the data memory according to the pre-configured data reading parameters, and perform sampling rate recovery on the target air interface IQ data to obtain the output IQ data. The subsequent processing module connected to the frequency point digital downconversion module is used to process the output IQ data and return the processing result to the central processing unit.

[0006] According to a data processing apparatus provided by the present invention, the data processing apparatus further includes: The antenna radio frequency module is used to receive 4G signals from 4G cells and 5G signals from 5G cells. An analog-to-digital converter module connected to the antenna radio frequency module is used to convert 4G signals into digital signals and 5G signals into digital signals. The FPGA chip also includes: The switching control module is used to send an RF switching signal to the antenna RF module according to a pre-configured RF switching cycle; The radio frequency switching signal is used to instruct the antenna radio frequency module to switch to the 5G band when the frequency band is 4G, and also to instruct the antenna radio frequency module to switch to the 4G band when the frequency band is 5G; the radio frequency switching cycle is predetermined by the central processing unit.

[0007] According to a data processing apparatus provided by the present invention, the switching control module is further configured to send an address switching signal to the IQ storage channel of the storage interface module according to the radio frequency switching cycle. The address switching signal is used to instruct the IQ storage channel to switch the target storage address to the 5G address space when the target storage address belongs to the 4G address space; it is also used to instruct the IQ storage channel to switch the target storage address to the 4G address space when the target storage address belongs to the 5G address space.

[0008] According to a data processing apparatus provided by the present invention, the step of switching the target storage address to a 5G address space includes: The target storage address is switched to a first target address in the 5G address space; the first target address is determined based on the 5G base address corresponding to the IQ storage channel, the number of times the IQ storage channel receives the address switching signal, and the radio frequency switching cycle; The step of switching the target storage address to a 4G address space includes: The target storage address is switched to a second target address in the 4G address space; the second target address is determined based on the 4G base address corresponding to the IQ storage channel, the number of times the IQ storage channel receives the address switching signal, and the radio frequency switching cycle.

[0009] According to a data processing apparatus provided by the present invention, the antenna radio frequency module includes at least two sets of dual-mode signal channel groups for receiving uplink 4G signals and uplink 5G signals; the dual-mode signal channel group includes four uplink 4G signal channels and four uplink 5G signal channels; The analog-to-digital conversion module includes at least two sets of uplink analog-to-digital conversion channel groups; each uplink analog-to-digital conversion channel group includes four uplink analog-to-digital conversion channels; each uplink analog-to-digital conversion channel group corresponds one-to-one with the dual-mode signal channel group. The frequency band digital downconversion module includes at least two sets of uplink frequency band digital downconversion channel groups; the uplink frequency band digital downconversion channel group includes 4 uplink frequency band digital downconversion channels. The storage interface module includes at least 8 uplink IQ storage channels; the uplink frequency band digital downconversion channels correspond one-to-one with the uplink analog-to-digital conversion channels and the uplink IQ storage channels; The uplink frequency band digital downconversion channel is pre-configured with base address parameters, and the pre-configured base address parameters are different for different uplink frequency band digital downconversion channels; the base address parameters include the 4G base address and the 5G base address.

[0010] According to a data processing apparatus provided by the present invention, the FPGA chip further includes: The synchronization maintenance module is used to send data storage signals to the digital downconverter module of the frequency band at a specified transmission time; The specified transmission time is determined based on the starting storage location specified by the central processing unit; the data storage signal is used to trigger the frequency band digital downconversion module to store the air interface IQ data into the data memory through the storage interface module, so that the air interface IQ data is stored into the starting storage location.

[0011] According to a data processing apparatus provided by the present invention, the analog-to-digital conversion module includes one downlink analog-to-digital conversion channel; the frequency band digital downconversion module includes one downlink frequency band digital downconversion channel; the storage interface module includes one downlink IQ storage channel; the downlink frequency band digital downconversion channel corresponds one-to-one with the downlink analog-to-digital conversion channel and the downlink IQ storage channel; The data storage device includes downlink IQ data storage space; The antenna radio frequency module is also used to receive downlink 4G signals from 4G cells and downlink 5G signals from 5G cells; The analog-to-digital conversion module is further configured to convert the downlink 4G signal into a downlink digital signal through the downlink analog-to-digital conversion channel, and to convert the downlink 5G signal into a downlink digital signal through the downlink analog-to-digital conversion channel; The downlink frequency band digital downconversion channel is also used to store downlink air interface IQ data in the downlink IQ data storage space through the downlink IQ storage channel.

[0012] According to a data processing apparatus provided by the present invention, the frequency point digital down-conversion module includes: The timing advance frequency point digital downconversion unit is used to extract orthogonal frequency division multiplexing symbols, including demodulation reference signals, from the uplink IQ data storage space of the data storage device under the scheduling of the central processing unit. The post-processing module includes: The timing advance calculation module is used to calculate the timing advance based on the orthogonal frequency division multiplexing symbol.

[0013] According to a data processing apparatus provided by the present invention, the frequency point digital down-conversion module includes: Four digital downconversion units with time-frequency conversion points are used to extract time-domain data from the uplink IQ data storage space based on the initial channel positions of the four antennas of the antenna RF module. The post-processing module includes: The dual-mode time-frequency conversion module is used to convert the time-domain data into frequency-domain data and send the frequency-domain data to the central processing unit, so that the central processing unit can calculate the azimuth angle of the 4G cell and the 5G cell based on the frequency-domain data.

[0014] According to a data processing apparatus provided by the present invention, the frequency point digital down-conversion module includes: The first synchronization frequency point digital downconversion unit is used to search for the main synchronization signal in the downlink IQ data storage space and extract the cell NID2. The second synchronization frequency point digital downconversion unit is used to perform auxiliary synchronization signal search in the downlink IQ data storage space and extract cell NID1; The third synchronization frequency digital down-conversion unit is used to perform physical layer broadcast channel search in the downlink IQ data storage space and extract the main information block; The post-processing module includes: The dual-mode synchronization search module is used to determine cell synchronization parameters from the main information block, and to realize 4G cell synchronization and 5G cell synchronization based on the cell synchronization parameters, the cell NID2 and the cell NID1.

[0015] The data processing device provided by this invention utilizes a unified storage architecture that stores air interface IQ data in a data storage device and a hardware-software co-design between the FPGA chip and the CPU. The FPGA chip's Band DDC module stores the air interface IQ data into a data storage device, and then the FPGA chip's Frequency DDC module, under CPU scheduling, reads the target air interface IQ data from the data storage device. This supports frequency-modulated extraction of air interface IQ data to match different hardware-accelerated post-processing modules. Overall, based on a non-real-time scheduling co-design architecture combining FPGA hardware acceleration and CPU, the FPGA achieves high-speed preprocessing and hardware acceleration through the Band DDC module, Frequency DDC module, and post-processing module. The CPU is responsible for task scheduling, data transfer, synchronization location calculation, and maintenance, achieving flexibility in resource expansion and high deployment efficiency. This lays the foundation for supporting flexible expansion and simple maintenance of unified storage and dynamic processing of multi-standard, multi-cell data, significantly improving data processing compatibility, scalability, and computational efficiency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is one of the structural schematic diagrams of the data processing device provided by the present invention.

[0018] Figure 2 This is the second schematic diagram of the data processing device provided by the present invention.

[0019] Figure 3 This is an example diagram of the 4 / 5G cross-connection storage provided by the present invention.

[0020] Figure 4 This is a structural example diagram of the antenna radio frequency module provided by the present invention.

[0021] Figure 5 This is an example diagram of the data read / write flow provided by the present invention.

[0022] Figure 6 This is a flowchart illustrating the process of implementing the direction finding function based on a data processing device, as provided by the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0024] It should be noted that, in the description of this invention, the term "comprising" or any other variations thereof is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two elements. Those skilled in the art will understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0025] The terms "first," "second," etc., used in this invention are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects; for example, a first object can be one or more. Furthermore, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0026] The following is combined Figures 1-6 The present invention describes the data processing apparatus provided by the present invention.

[0027] Existing multi-standard, multi-antenna data processing systems often face the following problems when supporting different standards: (1) Poor scalability, that is, each standard often requires independent hardware and computing resources, which often requires major architecture changes when adding standards or cells, resulting in poor scalability. (2) Inefficient, that is, the real-time processing task and the computing task are coupled during data processing, making it difficult to adapt to dynamic load; and a problem with a single module can easily cause system blockage. (3) Multi-cell synchronization maintenance is complex. In the case that cell synchronization in existing data processing mostly relies on FPGA maintenance, when it is extended to multiple cells, the FPGA underlying synchronization maintenance becomes very complex. In addition, when data processing is directed to multi-antenna multi-channel direction finding system, the phase and amplitude calibration of multi-channel data depends on hardware, which is not flexible enough.

[0028] In view of this, the present invention provides a data processing apparatus to solve at least one of the aforementioned problems such as poor expansion effect, low efficiency, and complex maintenance of multi-cell synchronization.

[0029] Figure 1 This is one of the structural schematic diagrams of the data processing device provided by the present invention, such as... Figure 1 As shown, the data processing device includes, but is not limited to, an FPGA chip 110 and a data memory 120 for storing air interface IQ data. Solid lines represent signal and data transmission directions, while dashed lines represent command transmission directions.

[0030] The FPGA chip 110 also includes, but is not limited to, a storage interface module 111, a frequency band digital downconversion module 112, a frequency point digital downconversion module 113, and a post-processing module 114.

[0031] The storage interface module 111 is connected to the data storage device 120.

[0032] The Band Digital Down Converter (Band DDC) module 112 is connected to the storage interface module 111 and is used to convert the sampling rate of the digital signal input to the FPGA chip 110 to obtain the air interface IQ data and store the air interface IQ data in the data memory 120.

[0033] The Digital Down Converter (DDC) module 113 is connected to the storage interface module 111. It is used to respond to the start command of the Central Processing Unit (CPU) 200, extract the target air interface IQ data from the data memory 120 according to the pre-configured data reading parameters, and perform sampling rate recovery on the target air interface IQ data to obtain the output IQ data.

[0034] The post-processing module 114 is connected to the frequency point digital down-conversion module 113 and is used to process the output IQ data and return the processing result to the central processing unit 200.

[0035] The target air interface IQ data is the air interface IQ data that needs to be read from the data memory 120 in response to the start instruction of the central processing unit 200.

[0036] The data reading parameters are parameters that the central processing unit 200 pre-determines through operations such as synchronization position calculation and maintenance, and configures to the frequency point digital downconversion module 113. These parameters include, but are not limited to, the starting storage position and reading length, which are composed of the target starting system frame and the target starting sampling point, and other parameters for reading the target air interface IQ data.

[0037] The data storage device can be any of the following: Double Data Rate Memory (DDR), Graphics DDR (GDDR), Low Power DDR (LPDDR), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM). This invention does not limit the type of data storage device.

[0038] Specifically, when the data processing device is working, the antenna radio frequency module outside the FPGA chip 110 collects and processes airborne wireless signals (4G signals, 5G signals, uplink signals, downlink signals, etc.), and sends the wireless signals to the analog-to-digital converter (ADC) module for sampling and conversion into digital signals, which are then input to the FPGA chip 110. The frequency band digital down-conversion module 112 receives the digital signals input to the FPGA chip 110, performs sampling rate conversion based on a uniform sampling rate or a combined sampling rate, obtains air interface IQ data, and stores the air interface IQ data in the data memory 120 through the storage interface module 111.

[0039] After receiving a start command from the central processing unit 200 based on service requirements, the frequency point digital downconversion module 113 initiates a read of the data memory 120 in response to the start command. According to the data reading parameters pre-configured in the frequency point digital downconversion module 113, it determines the starting storage location, read length, internal offset address, and other information of the target air interface IQ data. Then, it extracts the target air interface IQ data of the same read length from the starting storage location of the data memory 120, and performs sampling rate recovery on the read target air interface IQ data to obtain the output IQ data, ensuring that the output IQ data meets the sampling rate requirements of different bandwidths and different physical layer channels under multiple standards. The physical layer channels include, but are not limited to, at least one of the following: Physical Broadcast Channel (PBCH), Physical Downlink Shared Channel (PDSCH), and Physical Uplink Shared Channel (PUSCH).

[0040] After receiving the output IQ data from the frequency point digital downconverter module 113, the post-processing module 114 processes it and returns the processing result to the central processing unit 200.

[0041] The data processing device provided by this invention utilizes a unified storage architecture that stores air interface IQ data in a data storage device and a hardware-software co-design between the FPGA chip and the CPU. The FPGA chip's Band DDC module stores the air interface IQ data into a data storage device, and then the FPGA chip's Frequency DDC module, under CPU scheduling, reads the target air interface IQ data from the data storage device. This supports frequency-modulated extraction of air interface IQ data to match different hardware-accelerated post-processing modules. Overall, based on a non-real-time scheduling co-design architecture combining FPGA hardware acceleration and CPU, the FPGA achieves high-speed preprocessing and hardware acceleration through the Band DDC module, Frequency DDC module, and post-processing module. The CPU is responsible for task scheduling, data transfer, synchronization location calculation, and maintenance, achieving flexibility in resource expansion and high deployment efficiency. This lays the foundation for supporting flexible expansion and simple maintenance of unified storage and dynamic processing of multi-standard, multi-cell data, significantly improving data processing compatibility, scalability, and computational efficiency.

[0042] Figure 2 This is a second structural schematic diagram of the data processing device provided by the present invention, as shown below. Figure 2 As shown, the data processing device also includes an antenna radio frequency module 130 and an analog-to-digital conversion module 140, and the FPGA chip 110 also includes a switching control module 115.

[0043] Among them, the antenna radio frequency module 130 is used to receive 4G signals from 4G cells and 5G signals from 5G cells.

[0044] The analog-to-digital converter module 140 is connected to the antenna radio frequency module 130 and is used to convert 4G signals into digital signals and 5G signals into digital signals.

[0045] The switching control module 115 is used to send an RF switching signal to the antenna RF module 130 according to a pre-configured RF switching cycle.

[0046] The radio frequency switching signal is used to instruct the antenna radio frequency module 130 to switch to the 5G frequency band when the frequency band is 4G, and also to instruct the antenna radio frequency module 130 to switch to the 4G frequency band when the frequency band is 5G; the radio frequency switching cycle is predetermined by the central processing unit 200 and configured to the switching control module 115.

[0047] Specifically, the air interface IQ data storage of the data processing device has 4 / 5G cross-switching storage function, the key of which is that the switching is performed by the switching control module 115.

[0048] Specifically, the antenna radio frequency module 130 can collect and receive wireless signals, including 4G signals from 4G cells and 5G signals from 5G cells (both including uplink and downlink signals), and the analog-to-digital converter module 140 has the ability to convert wireless signals into digital signals, that is, to convert 4G signals and 5G signals into digital signals.

[0049] When the data processing device cross-switches and stores 4G / 5G air interface IQ data, taking the initial storage of 4G air interface IQ data as an example, the initial frequency band of the antenna RF module 130 is the 4G band. After storing enough 4G air interface IQ data for a sufficient RF switching cycle, the FPGA chip's switching control module 115 sends an RF switching signal to the antenna RF module 130 to control the RF switching. The antenna RF module 130 receives and responds to the RF switching signal, switching from the 4G band to the 5G band to store the 5G air interface IQ data in the data memory 120. After storing enough 5G air interface IQ data for a sufficient RF switching cycle, the FPGA chip's switching control module 115 sends another RF switching signal to the antenna RF module 130. The antenna RF module 130 receives and responds to the RF switching signal, switching from the 5G band back to the 4G band to store the 4G air interface IQ data in the data memory 120.

[0050] The data processing device provided by this invention, through a unified storage architecture and hardware-software co-design, sets a switching control module in the FPGA chip to control the 4G and 5G radio frequency switching of the antenna radio frequency module, thereby enabling the cross-storage of multi-standard data and significantly improving data processing compatibility and scalability.

[0051] Based on the above embodiments, as an optional embodiment, combined with Figure 2 As shown, the switching control module 115 is also used to send an address switching signal to the IQ storage channel of the storage interface module 111 according to the radio frequency switching cycle. The address switching signal is used to instruct the IQ storage channel to switch the target storage address to the 5G address space when the target storage address belongs to the 4G address space; it is also used to instruct the IQ storage channel to switch the target storage address to the 4G address space when the target storage address belongs to the 5G address space.

[0052] The IQ storage channel includes an uplink IQ storage channel and a downlink IQ storage channel; the storage interface module 111 includes multiple IQ storage channels, each with an independent cross-storage switch; for any IQ storage channel, the same IQ data storage channel is used for 4 / 5G cross-storage, while the storage address spaces are separate.

[0053] Optionally, the 4G address space is the low-order address space, and the 5G address space is the high-order address space.

[0054] Specifically, when the data processing device implements the 4 / 5G cross-connection storage function, the switching control module 115 of the FPGA chip 110 not only sends the radio frequency switching signal to the antenna radio frequency module 130 according to the pre-configured radio frequency switching cycle, but also sends the address switching signal to the IQ storage channel of the storage interface module 111 at the same time as sending the radio frequency switching signal.

[0055] When the data processing device cross-switches and stores 4G / 5G air interface IQ data, taking the storage of 4G air interface IQ data first as an example, the initial frequency band of the antenna RF module 130 is the 4G frequency band, and the initial target storage address of the IQ storage channel in the data memory 120 belongs to the 4G address space. After storing enough 4G air interface IQ data for the RF switching cycle, the switching control module 115 of the FPGA chip 110 sends an RF switching signal to the antenna RF module 130 and an address switching signal to the IQ storage channel of the storage interface module 111 at the same time. The antenna RF module 130 receives and responds to the RF switching signal, switching the 4G frequency band to the 5G frequency band. The IQ storage channel of the storage interface module 111 receives and responds to the address switching signal, switching the target storage address from the 4G address space to the 5G address space, so as to store the 5G air interface IQ data into the 5G address space of the data memory 120.

[0056] After storing enough 5G air interface IQ data for the RF switching cycle, the switching control module 115 of the FPGA chip 110 sends an RF switching signal to the antenna RF module 130 and simultaneously sends an address switching signal to the IQ storage channel of the storage interface module 111. The antenna RF module 130 receives and responds to the RF switching signal, switching the 5G frequency band to the 4G frequency band. The IQ storage channel of the storage interface module 111 receives and responds to the address switching signal, switching the target storage address from the 5G address space to the 4G address space, so as to store the 4G air interface IQ data into the 4G address space of the data memory 120.

[0057] The data processing device provided by this invention, under a unified storage architecture and hardware-software co-design, sets a switching control module in the FPGA chip to control the 4G and 5G radio frequency switching of the antenna radio frequency module, and simultaneously controls the 4G address space and 5G address space switching of the IQ storage channel in the storage interface module, thereby enabling cross-storage of multi-standard data and significantly improving data processing compatibility and scalability.

[0058] Based on the above embodiments, as an optional embodiment, switching the target storage address to the 5G address space includes: The target storage address is switched to a first target address in the 5G address space; the first target address is determined based on the 5G base address corresponding to the IQ storage channel, the number of times the IQ storage channel receives the address switching signal, and the radio frequency switching cycle; The step of switching the target storage address to a 4G address space includes: The target storage address is switched to a second target address in the 4G address space; the second target address is determined based on the 4G base address corresponding to the IQ storage channel, the number of times the IQ storage channel receives the address switching signal, and the radio frequency switching cycle.

[0059] The 5G base address corresponding to the IQ storage channel is the 5G base address configured in the Band DDC module for the corresponding frequency band digital downconversion channel (including the uplink and downlink digital downconversion channels); the 4G base address corresponding to the IQ storage channel is the 4G base address configured in the Band DDC module for the corresponding frequency band digital downconversion channel.

[0060] Specifically, when the data processing device cross-switches storage of 4G / 5G air interface IQ data, taking the storage of 4G air interface IQ data first as an example, the initial target storage address of the IQ storage channel in the data storage device is the 4G base address corresponding to the IQ storage channel, which belongs to the 4G address space.

[0061] After storing enough 4G air interface IQ data for a radio frequency switching cycle, the FPGA chip's switching control module sends an address switching signal to the IQ storage channel of the storage interface module. The IQ storage channel of the storage interface module receives and responds to the address switching signal, determines the first target address based on the 5G base address, the number of times the IQ storage channel receives the address switching signal, and the radio frequency switching cycle, and switches the target storage address from the 4G address space to the first target address in the 5G address space, so as to store the 5G air interface IQ data into the first target address of the data memory.

[0062] After storing enough 5G air interface IQ data for the RF switching cycle, the FPGA chip's switching control module sends an address switching signal to the IQ storage channel of the storage interface module again. The IQ storage channel of the storage interface module receives and responds to the address switching signal, determines the second target address based on the 4G base address, the number of times the IQ storage channel receives the address switching signal, and the RF switching cycle, and switches the target storage address from the 5G address space to the second target address in the 4G address space, so as to store the 4G air interface IQ data into the second target address of the data memory.

[0063] Figure 3 This is an example diagram of the 4 / 5G cross-connection storage provided by the present invention, such as... Figure 3 As shown, the switching cycle radio frequency period is 0.5ms; the address space allocated to one IQ storage channel is 256MB, of which 4G data is stored in the lower 128MB segment of the 4G address space, and 5G data is stored in the upper 128MB segment of the 5G address space; when the storage time exceeds 1 second (i.e., 100 frames of data, 1 frame time = 10 milliseconds), the write address of the IQ storage channel will return to the beginning of the address space for cyclic storage.

[0064] Taking the example of storing 4G IQ data first after the start of air interface IQ data storage, after the storage starts, the IQ storage channel has not yet received the address switching signal, so the 4G IQ data is stored first to the 4G base address 0, which is the starting address of the storage offset.

[0065] After storing for 0.5ms (500 microseconds), the switching control module sends an RF switching signal to the antenna RF module and an address switching signal to the IQ storage channel. The antenna RF module switches to the 5G band in response to the RF switching signal. The frequency and channel order of each analog-to-digital conversion channel (such as ADC CH1~CH8) in the analog-to-digital conversion module do not need to be changed.

[0066] After receiving the address switching signal, the IQ storage channel has received one address switching signal in total. Therefore, it determines the first target address as 128MB+0.5ms×1, which is the spatial address corresponding to the 128MB+0.5ms position, and stores the 5G data in the first target address corresponding to the 128MB+0.5ms position.

[0067] After storing 0.5ms of 5G data, the switching control module sends another RF switching signal to the antenna RF module, and simultaneously sends an address switching signal to the IQ storage channel. The antenna RF module then switches to the 4G band in response to the RF switching signal.

[0068] After receiving the address switching signal, the IQ storage channel has received two address switching signals in total. Therefore, it determines the second target address to be 0MB + 0.5ms × 2, which is the spatial address corresponding to the position 0MB + 1ms, and stores the 4G data in the second target address corresponding to the position 0MB + 1ms. This process is repeated, switching the radio frequency and storage addresses until storage is complete.

[0069] The target address for storage is determined by the base address, the number of times the address switching signal is received by the IQ storage channel, and the radio frequency switching cycle. After the address space is switched, the address in the previous radio frequency switching cycle in the address space will be left blank. For example, the first 0.5ms of the 5G address space is left blank during the first switch, which is convenient for debugging and easy to align the time order of 4G and 5G data.

[0070] It should be noted that when the RF switching cycle is configured by the CPU, it must be an integer multiple of 0.5ms; otherwise, there will be 4G / 5G data crossover during switching. The total duration of IQ data storage is also configured by the CPU within the allocated address space. When both the 4G and 5G address spaces allocated to an IQ storage channel are 128MB, approximately 1 second of IQ data can be stored. If there are 9 IQ storage channels, at least 9*2*128MB of storage space is required, which means the data storage space of the data store must be at least 2304MB.

[0071] The data processing device provided by the present invention determines the target address for storage based on the base address, the number of times the address switching signal is received by the IQ storage channel, and the radio frequency switching cycle. After the address space is switched, the address in the previous radio frequency switching cycle in the address space will be left empty, which facilitates debugging and makes it easy to align the time sequence of 4G and 5G data.

[0072] Based on the above embodiments, as an optional embodiment, the antenna radio frequency module includes at least two sets of dual-mode signal channel groups for receiving uplink 4G signals and uplink 5G signals; the dual-mode signal channel group includes 4 uplink 4G signal channels and 4 uplink 5G signal channels; The analog-to-digital conversion module includes at least two sets of uplink analog-to-digital conversion channel groups; each uplink analog-to-digital conversion channel group includes four uplink analog-to-digital conversion channels; each uplink analog-to-digital conversion channel group corresponds one-to-one with the dual-mode signal channel group. The frequency band digital downconversion module includes at least two sets of uplink frequency band digital downconversion channel groups; the uplink frequency band digital downconversion channel group includes 4 uplink frequency band digital downconversion channels. The storage interface module includes at least 8 uplink IQ storage channels; the uplink frequency band digital downconversion channels correspond one-to-one with the uplink analog-to-digital conversion channels and the uplink IQ storage channels; The uplink frequency band digital downconversion channel is pre-configured with base address parameters, and the pre-configured base address parameters are different for different uplink frequency band digital downconversion channels; the base address parameters include the 4G base address and the 5G base address.

[0073] Specifically, Figure 4 This is a structural example diagram of the antenna radio frequency module provided by the present invention. Figure 5 This is an example diagram of the data read / write flow provided by the present invention, such as... Figure 4 and Figure 5 As shown, the antenna radio frequency module 130 includes two sets of dual-mode signal channel groups. Each set of dual-mode signal channel groups includes four uplink 4G signal channels and four uplink 5G signal channels, which are used to receive uplink 4G signals and uplink 5G signals.

[0074] The analog-to-digital conversion module 140 includes two sets of uplink analog-to-digital conversion channel groups, which correspond one-to-one with two sets of dual-mode signal channel groups. Each set of uplink analog-to-digital conversion channel groups includes four uplink analog-to-digital conversion channels, namely ADC CH1~CH4 and ADC CH5~CH8.

[0075] The frequency band digital downconversion module includes two sets of uplink frequency band digital downconversion channel groups. Each set of uplink frequency band digital downconversion channel groups includes 4 uplink frequency band digital downconversion channels, namely Band DDC0~Band DDC3 and Band DDC4~Band DDC7.

[0076] Band DDC sampling supports output sampling rates from 30.72MHz to 245.76MHz, and can output four rates: 204.8MHz, 122.88MHz, 61.44MHz, and 30.72MHz. Under the unified 4G / 5G direction finding conditions, the Band DDC for writing to DDR is 30.72MHz, and the DDR write is divided into 9 blocks, each block being 128MB (1 second @ 30.72MHz data storage).

[0077] The storage interface module includes at least 8 uplink IQ storage channels, with each uplink frequency band digital downconversion channel corresponding to an uplink analog-to-digital conversion channel and an uplink IQ storage channel.

[0078] Combination Figure 4 and Figure 5 As shown, the analog-to-digital conversion module 140 includes 9 analog-to-digital conversion channels, 1 downlink analog-to-digital conversion channel (ADC CH0), and 8 uplink analog-to-digital conversion channels (8 channels = ADC CH1~CH8).

[0079] The downlink data from ADC CH0 passes through Band DDCx and is mainly used for downlink synchronization. This involves performing PSS and SSS searches and PBCH processing to obtain the base station cell number and the Master Information Block (MIB). The system frame number and the storage location of synchronization-related information in DDR are obtained from the MIB message and used for subsequent synchronization maintenance to achieve downlink synchronization.

[0080] The 8 uplink analog-to-digital converter (ADC) channels CH1~CH8 correspond to Band DDC0~Band DDC7. Four ADC CHx channels are used as one cell for direction finding or positioning. Each of the four channels interleave the storage of 4G and 5G data; therefore, the four channels actually support one 4G cell and one 5G cell in time-division multiplexing. Ultimately, the eight uplink ADC CHx channels can support two 4G cells and two 5G cells. In Time Division Duplex (TDD) mode, downlink and uplink data are stored in time-division multiplexing, retrieving only the target uplink subframe (4G) or target time slot (NR). In Frequency Division Duplex (FDD) mode, only uplink data is stored. This data is used only for calculating TA (Target Aspect Ratio) and direction finding or calibration. Time-division multiplexing supports two cells, with four antennas per group for direction finding.

[0081] Taking DDR as an example, the data source for writing to DDR is the Band DDC output, and the writing method is continuous periodic overwrite writing with a writing cycle of 1 second. Assuming the sampling rate of the written data is 30.72MHz, one sampled data IQ = 32 bits = 4 bytes, 30.72 * 4 * Byte / 1 second = 122.88MB / second. Therefore, a 128MB space is allocated in DDR to store this 1 second of data. One Band DDC corresponds to one upstream IQ data storage space in DDR, and the base address of the upstream IQ data storage space can be configured.

[0082] The Band DDC input source can be selected from 1 downlink and 8 uplink, and the pingpang cache between the Band DDC output and DDR can also be configured to be written to increase system flexibility.

[0083] The Band DDC output sampling can be written to DDR at a uniform sampling rate, or different Band DDCs can output different sampling rates to DDR.

[0084] A total of 9 Band DDCs are written to DDR. Time-division arbitration writes data to the 9 Band DDCs sequentially, and data is periodically written to 9 different IQ data storage spaces every 1 second.

[0085] Finally, each uplink frequency band digital downconversion channel is pre-configured with base address parameters, and the pre-configured base address parameters are different for different uplink frequency band digital downconversion channels; the base address parameters include 4G base address and 5G base address.

[0086] Table 1 is an example table of base addresses for the 8-channel Band DDC provided by this invention. As shown in Table 1, if the RF switching period for cross-storage is configured to be 500ms, the 4G base address for storing 4G data starts at 0x00000000 (random data storage from 0 to 1 second) starting 1 second initially. After storing 500ms of 4G data, the RF switches to 5G reception, jumps to the 5G base address 0x02000000 for 5G data storage, and considers the RF switching period and the number of address switching signals received by the IQ storage channel to determine the final target address. After 500ms of 5G storage, the RF switches back to 4G reception, and starts jumping to the 4G base address again to store 4G data, repeating the switching and storage steps until 1 second of 4 / 5G cross-storage is completed.

[0087] Table 1

[0088] The Band DDC base address is the starting address for writing output data from a certain Band DDC channel into the data storage. The data is written to the storage in units of time, with a fixed data size of 1 second. Each Band DDC channel supports 4 / 5G cross-storage.

[0089] The data processing device provided by this invention samples 4G and 5G data through an antenna and radio frequency, then converts the analog-to-digital signal into a multi-channel digital signal. The Band DDC module of the FPGA chip stores the 4G and 5G air interface IQ data into the data memory. It supports unified storage and dynamic processing of multi-standard and multi-cell data with flexible expansion and simple maintenance, which can significantly improve data processing compatibility, scalability and computing efficiency.

[0090] Based on the above embodiments, as an optional embodiment, the FPGA chip further includes: The synchronization maintenance module is used to send data storage signals to the digital downconverter module of the frequency band at a specified transmission time; The specified transmission time is determined based on the starting storage location specified by the central processing unit; the data storage signal is used to trigger the frequency band digital downconversion module to store the air interface IQ data into the data memory through the storage interface module, so that the air interface IQ data is stored into the starting storage location.

[0091] Specifically, in combination Figure 2 As shown, before data processing, synchronization with the base station is required. The CPU will determine the starting storage position of each uplink IQ data storage space in the data memory based on the synchronized timing information. The specified transmission time can be determined based on the starting storage position, so that the uplink IQ data is always stored at the starting storage position of each uplink IQ data storage space.

[0092] Therefore, the synchronization maintenance module 116 of the FPGA chip 110 has an IQ data storage trigger function. After cell synchronization, the CPU specifies the frame number and subframe number to determine the starting storage position, thereby determining the specified transmission time. When the synchronization maintenance module 116 reaches the specified transmission time, it sends a data storage signal to the frequency band digital downconversion module 112, triggering the frequency band digital downconversion module 112 to automatically store the air interface IQ data into the corresponding uplink IQ data storage space in the data memory through the uplink IQ storage channel of the storage interface module, ensuring that the starting position of the stored IQ data is determined.

[0093] It is understandable that the starting storage location is the CPU configuration air interface target starting frame and sample point alignment, that is, the starting position of the target starting frame, subframe 0, time slot 0, and symbol 0. When the CPU reads the uplink IQ data storage space later, at the beginning of a certain base address, that is, the beginning of a certain system frame, if the CPU wants to read a certain time slot in a certain system frame, it can directly calculate the read address, that is, the offset address to read.

[0094] The data processing device provided by this invention, through a unified storage architecture and a hardware-software co-design between the FPGA chip and the CPU, utilizes the synchronization maintenance module of the FPGA chip to realize the IQ data storage trigger function, maintains the timing consistency between the receiver and the base station, supports flexible expansion and simple maintenance of unified storage and dynamic processing of multi-standard and multi-cell data, and significantly improves data processing compatibility, scalability and computing efficiency.

[0095] Based on the above embodiments, as an optional embodiment, the analog-to-digital conversion module includes one downlink analog-to-digital conversion channel; the frequency band digital downconversion module includes one downlink frequency band digital downconversion channel; the storage interface module includes one downlink IQ storage channel; the downlink frequency band digital downconversion channel corresponds one-to-one with the downlink analog-to-digital conversion channel and the downlink IQ storage channel; The data storage device includes downlink IQ data storage space; The antenna radio frequency module is also used to receive downlink 4G signals from 4G cells and downlink 5G signals from 5G cells; The analog-to-digital conversion module is further configured to convert the downlink 4G signal into a downlink digital signal through the downlink analog-to-digital conversion channel, and to convert the downlink 5G signal into a downlink digital signal through the downlink analog-to-digital conversion channel; The downlink frequency band digital downconversion channel is also used to store downlink air interface IQ data in the downlink IQ data storage space through the downlink IQ storage channel.

[0096] Specifically, in combination Figure 5 As shown, the analog-to-digital conversion module includes one downlink analog-to-digital conversion channel ADC CH0, the frequency band digital downconversion module includes one downlink frequency band digital downconversion channel Band DDCx, and the data memory also includes a downlink IQ data storage space. There is a one-to-one correspondence between ADC CH0, Band DDCx, the downlink IQ storage channel in the storage interface module, and the downlink IQ data storage space.

[0097] After the antenna RF module receives the downlink 4G signal from the 4G cell and the downlink 5G signal from the 5G cell, the downlink analog-to-digital conversion channel ADC CH0 converts the downlink 4G signal and downlink 5G signal into downlink digital signal and inputs it to the FPGA chip. The downlink frequency band digital downconversion channel Band DDCx in the frequency band digital downconversion module of the FPGA chip stores the downlink air interface IQ data in the downlink IQ data storage space through the downlink IQ storage channel.

[0098] The downlink air interface IQ data stored via ADC CH0 and Band DDCx is the data source for the Synchronization Signal Block (SSB) and System Information Block (SIB), where SSB specifically refers to the combined block of PSS, SSS, and PBCH in NR. By performing an SSB search on the downlink air interface IQ data, the system frame and word frame or time slot location of the target SIB can be obtained, thus yielding the air interface system frame number and sample offset. Optionally, the SIB is solved only once, while the SSB synchronization search is performed periodically, typically with a period of 10 seconds.

[0099] The data processing device provided by this invention, through a unified storage architecture and a hardware-software co-design between the FPGA chip and the CPU, supports a maximum of nine channels for simultaneous storage of 4 / 5G uplink and downlink air interface IQ data via a Band DDC. Specifically, it includes one downlink channel and eight uplink channels. This facilitates further 4 / 5G air interface synchronization based on downlink data and acceleration of subsequent functions based on uplink data. It supports unified storage and dynamic processing of multi-standard and multi-cell data with flexible expansion and simple maintenance, significantly improving data processing compatibility, scalability, and computational efficiency.

[0100] Based on the above embodiments, as an optional embodiment, the frequency point digital down-conversion module includes: The Timing Advance (TA) frequency point digital down-conversion unit is used to extract Orthogonal Frequency Division Multiplexing (OFDM) symbols, including the Demodulation Reference Signal (DMRS), from the uplink IQ data storage space of the data storage device under the scheduling of the central processing unit. The post-processing module includes: The timing advance calculation module is used to calculate the timing advance based on the orthogonal frequency division multiplexing symbol.

[0101] Specifically, in combination Figure 2 and Figure 5 As shown, the frequency point DDC module includes a total of 8 DDC units, one of which is the TA frequency point DDC unit (Freq point DDC3). Under the scheduling of the central processing unit, it extracts OFDM symbols including DMRS from the uplink IQ data storage space of the data storage device and sends these OFDM symbols to the timing advance calculation module 1141. The timing advance calculation module 1141 then calculates the timing advance based on the OFDM symbols. Therefore, the timing advance calculation module 1141 can support 4 / 5G PUSCH TA calculation.

[0102] The data processing device provided by this invention, through a unified storage architecture and a hardware-software co-design between the FPGA chip and the CPU, supports the acceleration of back-end TA calculation function based on uplink data, supports unified storage and dynamic processing of multi-standard and multi-cell data with flexible expansion and simple maintenance, and significantly improves data processing compatibility, scalability and computing efficiency.

[0103] Based on the above embodiments, as an optional embodiment, the frequency point digital down-conversion module includes: Four digital downconversion units with time-frequency conversion points are used to extract time-domain data from the uplink IQ data storage space based on the initial channel positions of the four antennas of the antenna RF module. The post-processing module includes: The dual-mode time-frequency conversion module is used to convert the time-domain data into frequency-domain data and send the frequency-domain data to the central processing unit, so that the central processing unit can calculate the azimuth angle of the 4G cell and the 5G cell based on the frequency-domain data.

[0104] The initial channel position includes the initial PUSCH position and / or the initial PDSCH position; the time domain data includes the time domain data of PUSCH and / or the time domain data of PDSCH; and the frequency domain data includes the frequency domain data of PUSCH and / or the frequency domain data of PDSCH.

[0105] Specifically, in combination Figure 2 and Figure 5 As shown, the frequency point DDC module includes four time-frequency conversion frequency point digital down-conversion units (Freq point DDC4~Freq point DDC7), which are used to extract time-domain data from the uplink IQ data storage space based on the initial channel positions of the four antennas of the antenna RF module, and send the time-domain data to the dual-mode time-frequency conversion module 1142. The dual-mode time-frequency conversion module 1142 converts the time-domain data into frequency-domain data and sends the frequency-domain data to the CPU. The CPU calculates the azimuth angle of the 4G cell and the 5G cell based on the frequency-domain data. Thus, the dual-mode time-frequency conversion module 1142 can support time-frequency conversion of 4G / 5G PDSCH and PUSCH, and can be used to realize the direction finding or positioning of a certain 4G or 5G cell.

[0106] The dual-mode time-frequency conversion module 1142 is scheduled independently by the CPU. The scheduling prerequisite is that the preceding time-frequency conversion point DDC unit has read the target location data from the data memory and temporarily stored it in the local cache of the time-frequency conversion point DDC unit. The CPU performs time-division scheduling of the four time-frequency conversions of the four time-frequency conversion point DDC units and the four time-frequency conversion modules 1142 to complete the direction finding or positioning of two 4G cells and two 5G cells.

[0107] Optionally, the dual-mode time-frequency conversion module is also used for direction finding amplitude calibration and direction finding phase calibration; during calibration, a single-tone signal is used, and after being acquired, the amplitude and phase can be calculated by the dual-mode time-frequency conversion module.

[0108] The data processing device provided by this invention, through a unified storage architecture and a hardware-software co-design between the FPGA chip and the CPU, supports the acceleration of the subsequent time-frequency conversion function based on uplink data, supports unified storage and dynamic processing of multi-standard and multi-cell data with flexible expansion and simple maintenance, and significantly improves data processing compatibility, scalability and computing efficiency.

[0109] Based on the above embodiments, as an optional embodiment, the frequency point digital down-conversion module includes: The first synchronization frequency point digital downconversion unit is used to search for the main synchronization signal in the downlink IQ data storage space and extract the cell NID2. The second synchronization frequency digital downconversion unit is used to perform auxiliary synchronization signal search in the downlink IQ data storage space and extract cell NID1. The third synchronization frequency point digital downconversion unit is used to perform physical layer broadcast channel search in the downlink IQ data storage space and extract the main information block; The post-processing module includes: The dual-mode synchronization search module is used to determine cell synchronization parameters from the main information block, and to realize 4G cell synchronization and 5G cell synchronization based on the cell synchronization parameters, the cell NID2 and the cell NID1.

[0110] Specifically, in combination Figure 2 and Figure 5 As shown, the frequency point DDC module includes three synchronization frequency point DDC units, namely the first synchronization frequency point DDC unit, the second synchronization frequency point DDC unit, and the third synchronization frequency point DDC unit.

[0111] Specifically, the first synchronization point DDC unit (Freq point DDC0) is used to search for the Primary Synchronization Signal (PSS) in the downlink IQ data storage space to extract the cell NID2. The second synchronization point DDC unit (Freq point DDC1) is used to search for the Secondary Synchronization Signal (SSS) in the downlink IQ data storage space to extract the cell NID1. The third synchronization point DDC unit (Freq point DDC2) is used to search for the Physical Layer Broadcast Channel (PBCH) in the downlink IQ data storage space to extract the MIB.

[0112] After the dual-mode synchronization search module 1143 receives cell NID2, cell NID1, and MIB, it determines the cell number based on NID1*3+NID2, extracts the cell synchronization parameters from the MIB information carried by the PBCH, and finally obtains the final cell synchronization based on the cell number and cell synchronization parameters. Therefore, the dual-mode synchronization search module 1143 supports air interface synchronization of 4G and 5G cells under independent CPU scheduling.

[0113] The data processing device provided by this invention, through a unified storage architecture and a hardware and software co-design between the FPGA chip and the CPU, sets up three synchronization frequency point DDC units, which can be simultaneously scheduled by the CPU to accelerate the processing speed. This supports the acceleration of the air interface synchronization function of the downstream cell based on downlink data, supports unified storage and dynamic processing of multi-standard and multi-cell data with flexible expansion and simple maintenance, and significantly improves data processing compatibility, scalability and computing efficiency.

[0114] In another embodiment, combined Figure 5 As shown, the frequency point DDC module has a total of 8 frequency point DDC units, which correspond to the synchronized PSS, SSS and PBCH respectively, the TA to find the precise uplink position, and the 4-way PUSCH for direction finding or positioning data; in addition, DMA (test mode), GSM (2G) and WCDMA (3G) are used as three-way extension backups, which can also be scheduled by the CPU to initiate reads from the data memory (such as DDR space).

[0115] Taking DDR as an example, DDR read operations are triggered by the frequency point DDC module. The CPU schedules and triggers the frequency point DDC module to start working. The frequency point DDC module triggers the read of DDR space according to the pre-configured data reading parameters (such as read band selection, internal offset address / starting position, read length, etc.).

[0116] When writing DDR data at a uniform 30.72MHz, the main function of the frequency point DDC module is to read 30.72MHz data from the DDR and restore the sampling rate according to the different down-conversion sampling rate conversion requirements (e.g., NR SSB is 7.68MHz / 3.84MHz, LTE is 1.92MHz, PUSCH and PDSCH are both 30.72MHz, etc.). For example, if the NR PSS search symbol rate is 7.68MHz, the frequency point DDC needs to read data with a length of 4 times the sampling rate of 7.68MHz to form a symbol.

[0117] In other words, the frequency point DDC module can extract target air interface IQ data and convert it to a specified output sampling rate based on the CPU-configured input sampling rate. The input sampling rates are 245.76 / 122.88 / 61.44 / 30.72MHz, and the output sampling rates are 30.72 / 15.36 / 7.68 / 3.84 / 1.92MHz. The extracted target air interface IQ data is used for subsequent functions such as PSS / SSS search, PBCH / SSB / PDSCH / PUSCH time-frequency conversion, etc. The frequency point DDC module is designed as a general-purpose module, usable in both 4 / 5G synchronization and 4 / 5G time-frequency conversion, to meet the sampling rate requirements of different bandwidths and different physical layer channels (PBCH / SSB / PDSCH / PUSCH, etc.) under multiple standards.

[0118] To better illustrate the data processing device provided by the present invention, the following provides a complete description of the workflow of the data processing device by providing an embodiment for direction finding and positioning based on the data processing device.

[0119] Figure 6 This is a flowchart illustrating the implementation of direction finding functionality based on a data processing device, as provided by the present invention. Figure 6 As shown, before direction finding begins, the data processing device must first synchronize with the base station via the air interface. Using the downlink analog-to-digital conversion channel of ADC CH0, the base station stores downlink air interface IQ data, including the system frame number and subframe number, into the downlink IQ data storage space of the data storage device. The dual-mode synchronization search module further searches and retrieves timing information from the downlink IQ data storage space and configures this timing information into the (4 / 5G) synchronization maintenance module, ensuring synchronization with the base station for a period of time. Specifically, the CPU configures the (4 / 5G) synchronization maintenance module's self-triggered storage of air interface data function based on the acquired UE information. The CPU specifies the frame number and subframe number as the starting storage position and configures them into the synchronization maintenance module. When the specified transmission time corresponding to the starting storage position is reached, a data storage signal is sent to the Band DDC module to automatically store the PUSCH air interface data. Before configuring the trigger function, the parameters of the Band DDC and DDR interfaces need to be configured. Furthermore, if the self-triggered function is not used, air interface synchronization is required after storing the PUSCH data to calculate the base station timing.

[0120] After the data is stored in the uplink IQ data storage space, another spatial synchronization can be performed to verify whether the local timing of the FPGA chip is consistent with the air interface. After the consistency is verified, the cells on the same frequency point do not need to be verified again.

[0121] The TA frequency point DDC unit is configured to retrieve OFDM symbols with DMRS from DDR to further start the TA calculation module to calculate the TA value, that is, to determine the TA value based on the deviation of the position of the maximum frequency value from the theoretical position.

[0122] Further, the starting positions of the PUSCH of the four antennas of the target UE are calculated based on the TA value. The starting position of the PUSCH of the first antenna is configured to the frequency point DDC unit corresponding to the time-frequency conversion, so as to extract the PUSCH time domain data and temporarily store it in the local cache of the DDC.

[0123] The dual-mode (4 / 5G) synchronous search module is activated to perform time-frequency conversion on the 14 OFDM symbols of the PUSCH, and then the CPU retrieves the frequency domain data of one antenna.

[0124] After all the frequency domain data of the four antennas (corresponding to four frequency point DDCs and four time-frequency conversion modules) have been calculated, the CPU can retrieve the PUSCH frequency domain data of all antennas and then perform azimuth calculation.

[0125] Overall, the data processing device provided by this invention is particularly geared towards dual-mode, multi-cell, non-real-time data processing in multi-antenna, multi-channel direction finding systems in the field of wireless communication technology. It is applicable to scenarios involving non-real-time data processing of multiple standards (4G, 5G) and multiple cells, and is especially suitable for multi-antenna, multi-channel direction finding or positioning systems targeting 4G or 5G users. First, wireless signals are sampled via antennas and radio frequency, then analog-to-digital conversion is performed to obtain multi-channel digital signals. For rate signals with different sampling rates, multiple sets of digital signals are stored in DDR (data memory) using a unified or combined sampling rate. The CPU schedules and reads the DDR data to meet the needs of dynamic matching of different subsequent hardware acceleration modules for frequency conversion decimation. Combined with the FPGA hardware acceleration and CPU non-real-time scheduling collaborative architecture, it achieves flexibility in resource expansion and high deployment efficiency. Specifically, the FPGA is responsible for high-speed preprocessing and hardware acceleration, while the CPU performs task scheduling, data transfer, and synchronous position calculation and maintenance, ultimately significantly improving the data processing compatibility, scalability, and computational efficiency of multi-cell, multi-antenna direction finding systems.

[0126] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0127] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0128] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data processing apparatus, characterized by, The data processing device comprises: an FPGA chip and a data storage for storing air interface IQ data; The FPGA chip further comprises: a storage interface module connected with the data storage; a frequency band digital down-conversion module connected with the storage interface module, configured to perform sampling rate conversion on a digital signal input into the FPGA chip, to obtain the air interface IQ data, and to store the air interface IQ data into the data storage; a frequency point digital down-conversion module connected with the storage interface module, configured to extract target air interface IQ data from the data storage according to a pre-configured data reading parameter in response to a start instruction of a central processing unit, and to perform sampling rate recovery on the target air interface IQ data to obtain output IQ data; a post-processing module connected with the frequency point digital down-conversion module, configured to process the output IQ data and return a processing result to the central processing unit.

2. The data processing apparatus according to claim 1, characterized in that, The data processing device further comprises: an antenna radio frequency module configured to receive 4G signals of a 4G cell and 5G signals of a 5G cell; an analog-to-digital conversion module connected with the antenna radio frequency module, configured to convert the 4G signals into the digital signals and to convert the 5G signals into the digital signals; The FPGA chip further comprises: a switching control module configured to send a radio frequency switching signal to the antenna radio frequency module according to a pre-configured radio frequency switching period; The radio frequency switching signal is configured to instruct the antenna radio frequency module to switch from a 4G frequency band to a 5G frequency band when the frequency band is the 4G frequency band, and to instruct the antenna radio frequency module to switch from the 5G frequency band to the 4G frequency band when the frequency band is the 5G frequency band; and the radio frequency switching period is pre-determined by the central processing unit.

3. The data processing apparatus according to claim 2, characterized in that, The switching control module is further configured to send an address switching signal to an IQ storage channel of the storage interface module according to the radio frequency switching period; The address switching signal is configured to instruct the IQ storage channel to switch a target storage address from a 4G address space to a 5G address space when the target storage address belongs to the 4G address space, and to instruct the IQ storage channel to switch the target storage address from a 5G address space to a 4G address space when the target storage address belongs to the 5G address space.

4. The data processing apparatus according to claim 3, characterized by The switching of the target storage address to the 5G address space comprises: switching the target storage address to a first target address of the 5G address space; the first target address is determined based on a 5G base address corresponding to the IQ storage channel, a number of times that the IQ storage channel receives the address switching signal, and the radio frequency switching period; The switching of the target storage address to the 4G address space comprises: switching the target storage address to a second target address of the 4G address space; the second target address is determined based on a 4G base address corresponding to the IQ storage channel, a number of times that the IQ storage channel receives the address switching signal, and the radio frequency switching period.

5. The data processing apparatus according to claim 4, characterized in that, The antenna radio frequency module comprises at least two groups of dual-mode signal channel groups for receiving uplink 4G signals and uplink 5G signals; each dual-mode signal channel group comprises four uplink 4G signal channels and four uplink 5G signal channels. The analog-to-digital conversion module comprises at least two groups of uplink analog-to-digital conversion channel groups; each uplink analog-to-digital conversion channel group comprises four uplink analog-to-digital conversion channels; and each uplink analog-to-digital conversion channel group corresponds to one of the dual-mode signal channel groups; The frequency band digital down-conversion module comprises at least two groups of uplink frequency band digital down-conversion channel groups; each uplink frequency band digital down-conversion channel group comprises four uplink frequency band digital down-conversion channels; The storage interface module comprises at least eight uplink IQ storage channels; each uplink frequency band digital down-conversion channel corresponds to one of the uplink analog-to-digital conversion channels and one of the uplink IQ storage channels; The uplink frequency band digital down-conversion channels are pre-configured with base address parameters, and the base address parameters pre-configured for different uplink frequency band digital down-conversion channels are different; the base address parameters comprise the 4G base address and the 5G base address.

6. The data processing apparatus according to claim 5, characterized in that, The FPGA chip further comprises: A synchronization maintenance module configured to send a data storage signal to the frequency band digital down-conversion module at a specified sending time; The specified sending time is determined according to a starting storage position specified by the central processing unit; the data storage signal is configured to trigger the frequency band digital down-conversion module to store the air interface IQ data to the data storage device through the storage interface module, so that the air interface IQ data is stored to the starting storage position.

7. The data processing apparatus according to claim 5, characterized by The analog-to-digital conversion module comprises one downlink analog-to-digital conversion channel; the frequency band digital down-conversion module comprises one downlink frequency band digital down-conversion channel; the storage interface module comprises one downlink IQ storage channel; and the downlink frequency band digital down-conversion channel corresponds to the downlink analog-to-digital conversion channel and the downlink IQ storage channel respectively; The data storage device comprises a downlink IQ data storage space; The antenna radio frequency module is further configured to receive downlink 4G signals of a 4G cell and downlink 5G signals of a 5G cell; The analog-to-digital conversion module is further configured to convert the downlink 4G signals into downlink digital signals through the downlink analog-to-digital conversion channel, and convert the downlink 5G signals into downlink digital signals through the downlink analog-to-digital conversion channel; The downlink frequency band digital down-conversion channel is further configured to store downlink air interface IQ data in the downlink IQ data storage space through the downlink IQ storage channel.

8. The data processing apparatus according to claim 7, characterized in that, The frequency point digital down-conversion module comprises: A time advance frequency point digital down-conversion unit configured to extract, under the scheduling of the central processing unit, quadrature frequency division multiplexing symbols comprising a demodulation reference signal from an uplink IQ data storage space of the data storage device; The post-processing module comprises: A time advance calculation module configured to calculate a time advance according to the quadrature frequency division multiplexing symbols.

9. The data processing apparatus according to claim 8, characterized in that, The frequency point digital down-conversion module comprises: Four time-frequency conversion frequency point digital down-conversion units configured to extract time domain data from the uplink IQ data storage space according to channel initial positions of four antennas of the antenna radio frequency module; The post-processing module comprises: A dual-mode time-frequency conversion module is configured to convert the time-domain data into frequency-domain data and send the frequency-domain data to the central processor to calculate the azimuth angle of the 4G cell and the 5G cell according to the frequency-domain data.

10. The data processing apparatus according to claim 7, characterized by The frequency point digital down conversion module comprises: A first synchronization frequency point digital down conversion unit is configured to search for a primary synchronization signal in the downlink IQ data storage space and extract a cell NID2; A second synchronization frequency point digital down conversion unit is configured to search for a secondary synchronization signal in the downlink IQ data storage space and extract a cell NID1; A third synchronization frequency point digital down conversion unit is configured to search for a physical layer broadcast channel in the downlink IQ data storage space and extract a master information block; The post-processing module comprises: A dual-mode synchronization search module is configured to determine cell synchronization parameters from the master information block and achieve 4G cell synchronization and 5G cell synchronization based on the cell synchronization parameters, the cell NID2 and the cell NID1.

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