Compiler for generating reconfigurable executable programs

Abstract

The invention discloses a compiler for generating reconfigurable executable programs, and particularly discloses apparatuses, systems, and techniques for executing a compiler to generate one or more executable programs that can be configured to be executed by one or more of a plurality of different processor architectures. In at least one embodiment, a compiler generates one or more executable programs based at least in part on the original uncompiled executable programs, which may be configured to be executed by one or more of a plurality of different processor architectures.

Description

[0001] Cross-references to related applications

[0002] For all purposes, this application incorporates by reference the full disclosure of co-pending U.S. Patent Application No. 18 / 766,441, entitled "Software to Reconfigure Excipient Programs," which was filed concurrently with this application. Technical Field

[0003] At least one embodiment relates to a compiler for generating one or more executable programs configured to execute on one or more different processor architectures. For example, at least one embodiment relates to software for generating one or more executable programs configured to execute on one or more different processor architectures. Background Technology

[0004] Some executables are compiled to execute on a specific processor architecture, but some executables compiled for a specific processor architecture cannot execute on different processor architectures. To execute these executables on these different processor architectures, the original uncompiled executable must be bundled with the compiled executable, and the executable must be retargeted or recompiled to be compatible with the specific different processor architectures, which takes a significant amount of time. As a result, the size of the transferred executable increases dramatically due to the dramatic increase in processing time and computational resources required to perform the conversion. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating an exemplary compilation system for generating one or more executable instructions and one or more instruction annotations, according to at least one embodiment;

[0006] Figure 2A This is a block diagram illustrating an exemplary compilation system according to at least one embodiment for generating one or more corresponding instructions by decoding one or more raw instructions;

[0007] Figure 2B This is a block diagram illustrating an exemplary compilation system according to at least one embodiment for generating one or more corresponding instructions by decoding one or more raw instructions;

[0008] Figure 2C This is a block diagram illustrating an exemplary compilation system for generating one or more executable instructions by decoding a bundled capsule, according to at least one embodiment;

[0009] Figure 2D This is a block diagram illustrating an exemplary compilation system, according to at least one embodiment, for generating one or more corresponding instructions based at least in part on decoding one or more instructions and one or more annotations;

[0010] Figure 3 This is a block diagram illustrating an exemplary compilation system according to at least one embodiment;

[0011] Figure 4A This is a block diagram illustrating an exemplary driver according to at least one embodiment;

[0012] Figure 4B This is a block diagram illustrating an exemplary driver according to at least one embodiment;

[0013] Figure 5 This is a block diagram illustrating a bundled capsule generated from the original instructions, according to at least one embodiment;

[0014] Figure 6A This is a block diagram illustrating an exemplary system for performing on-target load according to at least one embodiment;

[0015] Figure 6B It is a block diagram illustrating an exemplary system for performing loading on a target by finalizing one or more compiled instructions, according to at least one embodiment;

[0016] Figure 6C This is a block diagram illustrating an exemplary compilation system for loading and generating one or more bundled capsules on one or more targets, according to at least one embodiment;

[0017] Figure 7A This is a block diagram illustrating an exemplary compilation system for generating one or more bundled capsules from one or more text files, according to at least one embodiment.

[0018] Figure 7B This is a block diagram illustrating an exemplary compilation system for generating one or more bundled capsules from one or more executable instructions, according to at least one embodiment.

[0019] Figure 8A This is a block diagram illustrating an exemplary compilation system for generating one or more executable instructions and one or more instruction annotations, according to at least one embodiment;

[0020] Figure 8B This is a block diagram illustrating an exemplary compilation system for generating one or more executable instructions and one or more instruction annotations, according to at least one embodiment;

[0021] Figure 9 An exemplary process for generating one or more reconfigurable executable programs according to at least one embodiment is shown;

[0022] Figure 10 An exemplary process is illustrated for configuring one or more executable programs to a processor architecture based on one or more annotations, according to at least one embodiment;

[0023] Figure 11 An exemplary data center according to at least one embodiment is shown;

[0024] Figure 12 A processing system according to at least one embodiment is shown;

[0025] Figure 13 A computer system according to at least one embodiment is shown;

[0026] Figure 14 A system according to at least one embodiment is shown;

[0027] Figure 15 An exemplary integrated circuit according to at least one embodiment is shown;

[0028] Figure 16 A computing system according to at least one embodiment is shown;

[0029] Figure 17 An APU according to at least one embodiment is shown;

[0030] Figure 18 A CPU according to at least one embodiment is shown;

[0031] Figure 19 An exemplary accelerator integration slice according to at least one embodiment is shown;

[0032] Figure 20A and Figure 20B An exemplary graphics processor according to at least one embodiment is shown;

[0033] Figure 21A A graphics core according to at least one embodiment is shown;

[0034] Figure 21B A GPGPU according to at least one embodiment is shown;

[0035] Figure 22A A parallel processor according to at least one embodiment is shown;

[0036] Figure 22B A processing cluster according to at least one embodiment is shown;

[0037] Figure 22C A graphics multiprocessor according to at least one embodiment is shown;

[0038] Figure 23 A graphics processor according to at least one embodiment is shown;

[0039] Figure 24 A processor according to at least one embodiment is shown;

[0040] Figure 25 A processor according to at least one embodiment is shown;

[0041] Figure 26 A graphics processor core according to at least one embodiment is shown;

[0042] Figure 27 A PPU according to at least one embodiment is shown;

[0043] Figure 28 A GPC according to at least one embodiment is shown;

[0044] Figure 29 A streaming multiprocessor according to at least one embodiment is illustrated;

[0045] Figure 30 A software stack of a programming platform according to at least one embodiment is shown;

[0046] Figure 31 The illustration shows an embodiment according to at least one of the embodiments. Figure 30 The CUDA implementation of the software stack;

[0047] Figure 32 The illustration shows an embodiment according to at least one of the embodiments. Figure 30 The ROCm implementation of the software stack;

[0048] Figure 33 The illustration shows an embodiment according to at least one of the embodiments. Figure 30 The OpenCL implementation of the software stack;

[0049] Figure 34 Software supported by a programming platform according to at least one embodiment is shown;

[0050] Figure 35 The illustration shows an embodiment of at least one of the following: Figures 30-33 Compiled code executed on the programming platform;

[0051] Figure 36 The illustration shows an embodiment of at least one of the following: Figures 30-33 More detailed compiled code executed on the programming platform;

[0052] Figure 37 This illustrates the transformation of source code before compilation, according to at least one embodiment;

[0053] Figure 38A A system configured to compile and execute CUDA source code using different types of processing units, according to at least one embodiment, is shown;

[0054] Figure 38B The diagram illustrates a configuration, according to at least one embodiment, to compile and execute using a CPU and a CUDA-enabled GPU. Figure 38A The system of CUDA source code;

[0055] Figure 38C The diagram illustrates a configuration, according to at least one embodiment, to compile and execute using a CPU and a GPU with CUDA disabled. Figure 38A The system of CUDA source code;

[0056] Figure 39 The diagram illustrates a method according to at least one embodiment. Figure 38C An example kernel converted by the CUDA to HIP conversion tool;

[0057] Figure 40 A more detailed description is provided according to at least one embodiment. Figure 38C GPUs without CUDA enabled;

[0058] Figure 41 This illustrates how threads of an exemplary CUDA grid, according to at least one embodiment, are mapped to... Figure 40 Different computational units;

[0059] Figure 42 This illustrates how to migrate existing CUDA code to data-parallel C++ code according to at least one embodiment; and

[0060] Figure 43 Components of a system for accessing a large language model according to at least one embodiment are shown. Detailed Implementation

[0061] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, those skilled in the art will understand that the inventive concept can be practiced without one or more of these specific details.

[0062] In at least one embodiment, when an instruction (e.g., Mercury) is one of a plurality of instructions that can be compiled (e.g., Mercury) into executable instructions, the compiler generates executable instructions and instruction comments corresponding to the original instructions. In at least one embodiment, the compiler is a software program. In at least one embodiment, the executable program is a collection of one or more executable instructions. In at least one embodiment, the finalizer is a compiler and / or includes a compiler. In at least one embodiment, the compiler is a finalizer and / or includes a finalizer. In at least one embodiment, the finalizer is separate from the compiler. In at least one embodiment, the finalizer is software for executing the compiler. In at least one embodiment, the compiler is software for executing the finalizer. In at least one embodiment, the processor architecture includes x64, x32, ARM, and any other relevant processor architecture types described herein.

[0063] Figure 1 This is a block diagram illustrating an exemplary compiler system 100 for generating one or more executable instructions 111 and one or more instruction annotations 109 according to at least one embodiment. In at least one embodiment, the raw instructions 101 are a set of instructions including one or more operations to be executed by one or more processors. In at least one embodiment, the raw instructions 101 are written by one or more software developers. In at least one embodiment, the raw instructions 101 are an intermediate format of a software program, including object code, intermediate representation (IR), or any other form of software instruction representation further described herein. In at least one embodiment, the raw instructions 101 are input to the compiler system 100. In at least one embodiment, the raw instructions 101 are parallel thread execution (PTX) instructions. In at least one embodiment, the raw instructions 101 include one or more instructions represented as ASCII text. In at least one embodiment, the raw instructions 101 include instructions for a GPU. In at least one embodiment, the raw instructions 101 include instructions for a CPU. In at least one embodiment, the raw instructions 101 will be compiled by a finalizer 110 into executable instructions (e.g., binary code). In at least one embodiment, the raw instructions 101 are compiled into an executable program configured to be executed by one or more of a plurality of different processor architectures. In at least one embodiment, the plurality of different processor architectures include at least one or more GPUs. In at least one embodiment, the plurality of different processor architectures include at least one or more CPUs.

[0064] In at least one embodiment, the finalizer 110 is a set of software instructions that, when executed, cause one or more processors to perform one or more computational operations, such as... Figure 1 As shown. In at least one embodiment, finalizer 110 is finalizer 316 or otherwise corresponds to finalizer 316, for example, as described below in conjunction with Figure 3 Finalizer 316 is described. In at least one embodiment, finalizer 110 is finalizer 410 or otherwise corresponds to finalizer 410, for example, as described below in conjunction with Figure 4A Finalizer 410 is described. In at least one embodiment, finalizer 110 is finalizer 612 and finalizer 620 or otherwise corresponds to finalizer 612 and finalizer 620, for example, as described below. Figure 6B and Figure 6C Finalizers 612 and 620 are described. In at least one embodiment, finalizer 110 is an offline finalizer 708, 718 or corresponds to an offline finalizer 708, 718, for example, as described below. Figure 7A and Figure 7B The offline finalizers 708 and 718 are described. In at least one embodiment, finalizer 110 is finalizer 810 or 820 or otherwise corresponds to finalizer 810 or 820, for example, as described below. Figure 8A and Figure 8B The finalizers 810 and 820 are described.

[0065] In at least one embodiment, decoder 102 is a set of software instructions that, when executed, cause one or more processors to generate one or more sets of executable instructions 111 and instruction annotations 109 from the original instructions 101. In at least one embodiment, finalizer 110 and / or decoder 102 generate one or more sets of any other type of instructions and instruction annotations as further described herein. In at least one embodiment, finalizer 110 is a back-end optimization (BO) finalizer or BO compiler. In at least one embodiment, finalizer 110 is any other type of finalizer or compiler as further described herein. In at least one embodiment, finalizer 110 finalizes instructions 101 into executable instructions 111 by compiling, transforming, or otherwise altering instructions 101. In at least one embodiment, finalizer 110 finalizes instructions 101 into annotations 109 by performing one or more steps (e.g., those further described herein) to generate one or more annotations 109 from the instructions 101. In at least one embodiment, finalizer 110 finalizes instruction 101 into one or more sets of compiled executable instructions 111 and instruction comments 109. In at least one embodiment, finalizer 110 separately finalizes each instruction into intermediate code, such as intermediate representation (IR). In at least one embodiment, finalizer 110 combines one or more IR nodes into a large set of compiled executable instructions 111 and instruction comments 109. In at least one embodiment, finalizer 110 detects errors between separately compiled instruction modules. In at least one embodiment, finalizer 110 includes expander 104. In at least one embodiment, expander is a set of software instructions that, if executed, cause one or more processors to generate one or more instructions that include updated comments about one or more instructions, such as the best corresponding instruction among multiple corresponding instructions that match a single original instruction 101, or any intermediate data (e.g., IR) generated by finalizer 110. In at least one embodiment, expander 104 is part of finalizer 110. In at least one embodiment, expander 104 is separate from finalizer 110. In at least one embodiment, expander 104 is expander 212 or otherwise corresponds to expander 212, for example, as described below. Figure 2A The described extender 212.

[0066] In at least one embodiment, expander 104 updates instruction annotation 103. In at least one embodiment, expander 104 expands the instruction annotation to include additional information about the original executable instructions 101. In at least one embodiment, expander 104 generates information that can be used by finalizer 110 and optimizer 105 to indicate which of the original instructions 101 can be optimized, transformed, or otherwise altered into one or more formats to be optimized by optimizer 105.

[0067] In at least one embodiment, optimizer 105 updates instruction annotation 109. In at least one embodiment, optimizer 105 optimizes instruction annotation 109 to include additional information about the original instruction 101. In at least one embodiment, optimizer 105 generates updated instruction annotation 109 to include additional information about the memory location used by the original instruction 101 and its dependencies. In at least one embodiment, finalizer 110 includes optimizer 105. In at least one embodiment, optimizer 105 is a set of software instructions that, if executed, cause one or more processors to generate one or more instructions that include updated annotations about one or more instructions, such as the memory location used by the original instruction 101, or any intermediate data (e.g., IR) generated by finalizer 110. In at least one embodiment, optimizer 105 is part of finalizer 110.

[0068] In at least one embodiment, optimizer 105 optimizes instructions to reduce the overhead of the control code loop. In at least one embodiment, optimizer 105 optimizes instructions to evaluate constants at compile time rather than at runtime. In at least one embodiment, optimizer 105 optimizes instructions to remove code that does not affect the program's outcome. In at least one embodiment, optimizer 105 optimizes instructions to efficiently use CPU registers to store variables. In at least one embodiment, optimizer 105 optimizes instructions to identify and reuse the results of expressions that are evaluated multiple times. In at least one embodiment, optimizer 105 is decoupled from finalizer 110. In at least one embodiment, optimizer 105 corresponds to optimizer 214, for example, as described below. Figure 2A The optimizer 214 is described.

[0069] In at least one embodiment, optimizer 105 updates instruction annotation 109. In at least one embodiment, optimizer 105 expands instruction annotation 109 to include additional information about the original executable instructions 101. In at least one embodiment, optimizer 105 generates information that can be used by finalizer 110 and optional block (OB) 106 to indicate which of one or more original instructions will be optimized, transformed, or otherwise altered into one or more formats to be analyzed by OB 106.

[0070] In at least one embodiment, OB 106 updates instruction comments. In at least one embodiment, OB 106 optimizes instruction comments to include additional information about the original instruction 101. In at least one embodiment, OB 106 generates updated instruction comments to include additional information about potential warnings, and / or code improvements, and / or code recommendations, and / or code suggestions. In at least one embodiment, OB 106 is a set of software instructions that, if executed, cause one or more processors to generate one or more instructions that include updated comments about one or more instructions, such as warnings and / or improvements and / or recommendations and / or suggestions about the original instruction 101, or any intermediate data (e.g., IR) generated by finalizer 110. In at least one embodiment, OB 106 is part of finalizer 110. In at least one embodiment, OB 106 is separate from finalizer 110. In at least one embodiment, OB 106 corresponds to OB 216, for example, as described below. Figure 2A OB 216 is described.

[0071] In at least one embodiment, OB 106 expands the instruction comments to include additional information about the original executable instructions 101. In at least one embodiment, OB 106 generates information that can be used by finalizer 110 and HazardScheduler (HS) 107 to indicate which of one or more original instructions can be optimized, transformed, or otherwise converted into one or more formats that can be analyzed by HS 107.

[0072] In at least one embodiment, HS107 updates executable instructions. In at least one embodiment, HS107 optimizes instructions to reduce overhead. In at least one embodiment, HS107 updates executable instructions. In at least one embodiment, HS107 optimizes instructions to reduce overhead. In at least one embodiment, HS107 is a set of software instructions that, if executed, cause one or more processors to generate one or more updated instructions, or any intermediate data, such as IR, generated by finalizer 110. In at least one embodiment, HS107 handles timing differences between instruction executions. In at least one embodiment, HS107 annotates the order in which instructions should be executed. In at least one embodiment, HS107 is part of finalizer 110. In at least one embodiment, HS107 is separate from finalizer 110. In at least one embodiment, HS107 corresponds to HS218, for example, in conjunction with the following. Figure 2A The HS218 is described.

[0073] In at least one embodiment, HS107 extends the instructions to include additional information about the original executable instructions 101. In at least one embodiment, HS107 generates information that can be used by finalizer 110 and encoder 108 to indicate which of one or more original instructions can be optimized, transformed, or otherwise converted into one or more formats to be encoded by encoder 108.

[0074] In at least one embodiment, encoder 108 updates executable instructions 111 and instruction comments 109. In at least one embodiment, encoder 108 encodes instructions into an executable program that can be configured to be executed by one or more processor architectures. In at least one embodiment, the plurality of different processor architectures includes one or more GPUs. In at least one embodiment, the plurality of different processor architectures includes one or more CPUs.

[0075] In at least one embodiment, encoder 108 is a set of software instructions that, when executed, cause one or more processors to generate one or more updated instructions and / or one or more updated instruction comments, or any intermediate data, such as IR, generated by finalizer 110. In at least one embodiment, encoder 108 is part of finalizer 110. In at least one embodiment, encoder 108 is separate from finalizer 110. In at least one embodiment, encoder 108 corresponds to encoder 220, for example, as described below. Figure 2A Encoder 220 as described.

[0076] In at least one embodiment, encoder 108 generates a bundled capsule 120. In at least one embodiment, the bundled capsule 120 is data comprising a bundled set of one or more compiled executable instructions and a set of one or more executable program annotations. In at least one embodiment, the bundled capsule 120 includes instruction annotations 109 and compiled executable instructions 111. In at least one embodiment, the bundled capsule 120 includes executable programs that can be configured to be executed by one or more processor architectures. In at least one embodiment, software is executed such that the bundled capsule 120 is configured to be executed by one or more processor types. In at least one embodiment, the bundled capsule 120 includes executable programs that can be configured to be executed by one or more processor architectures. In at least one embodiment, the multiple different processor architectures include one or more GPUs. In at least one embodiment, the multiple different processor architectures include one or more CPUs. In at least one embodiment, the bundled capsule 120 is generated at least in part based on one or more of the plurality of different processor architectures and a set of one or more executable instructions incompatible with one or more of the plurality of different processor architectures. In at least one embodiment, the original instruction 101 is incompatible with one or more of the plurality of different processor architectures. In at least one embodiment, the original instruction 101 incompatible with one or more of the plurality of different processor architectures is compiled to generate a set of one or more compiled executable instructions compatible with one or more of the plurality of different processor architectures. In at least one embodiment, instruction annotation 109 is generated corresponding to the set of executable instructions incompatible with one or more of the plurality of different processor architectures. In at least one embodiment, instruction annotation 109 and / or compiled executable instructions 111 compatible with one or more of the plurality of different architecture types are decoded to generate finalization information and / or reconstituted text. In at least one embodiment, the finalized information and / or reconstructed text are used to verify the behavior of the set of one or more compiled executable instructions.In at least one embodiment, finalization information and / or reconstructed text are used by finalizer 110 to verify whether the behavior of the compiled executable instructions 111 mirrors the behavior of the original instructions 101.

[0077] Figure 2A This is a block diagram illustrating an exemplary compilation system for generating one or more executable instructions by decoding a bundled capsule 202, according to at least one embodiment. In at least one embodiment, instruction 206 is a set of instructions comprising one or more operations to be executed by one or more processors. In at least one embodiment, instruction 206 is written by one or more software developers. In at least one embodiment, instruction 206 is an intermediate format of a software program, including object code, intermediate representation (IR), or any other form of software instruction representation further described herein. In at least one embodiment, instruction 206 is input to compilation system 200. In at least one embodiment, instruction 206 is parallel thread execution (PTX) instructions. In at least one embodiment, instruction 206 includes one or more instructions represented as ASCII text. In at least one embodiment, instruction 206 includes instructions for a GPU. In at least one embodiment, instruction 206 includes instructions for a CPU. In at least one embodiment, instruction 206 is compiled into an executable program that can be configured to be executed by one or more processor architectures of a plurality of different processor architectures. In at least one embodiment, the plurality of different processor architectures include one or more GPUs. In at least one embodiment, the plurality of different processor architectures include one or more CPUs.

[0078] In at least one embodiment, decoding 208 is a set of software instructions that, if executed, cause one or more processors to generate one or more sets of corresponding instructions 210 based on instruction annotation 204 and instruction 206. In at least one embodiment, decoding 208 generates one or more sets of any other type of instructions and instruction annotations further described herein. In at least one embodiment, decoding 208 is a back-end optimization (BO) decoder. In at least one embodiment, decoding 208 is any other type of decoding further described herein. In at least one embodiment, decoding 208 finalizes instruction 206 into one or more sets of instructions and instruction annotations. In at least one embodiment, decoding 208 decodes each instruction individually into intermediate code. In at least one embodiment, decoding 208 combines one or more IR nodes into a large set of compiled executable instructions and instruction annotations. In at least one embodiment, decoding 208 detects errors between individually compiled instruction modules. In at least one embodiment, corresponding instructions 210 are passed to extender 212. In at least one embodiment, the expander 212 is a set of software instructions that, if executed, cause one or more processors to generate one or more instructions, including updated annotations about one or more instructions, such as the best corresponding instruction among a plurality of corresponding instructions that match a single original instruction, or any intermediate data generated by the decoder 208, such as IR.

[0079] In at least one embodiment, extension 212 updates one or more corresponding instructions 210. In at least one embodiment, extension 212 expands the instructions to include additional information about the bundled instructions 206. In at least one embodiment, extension 212 generates information that can be used by optimizer 214 to indicate which of the one or more corresponding instructions can be optimized, transformed, or otherwise converted into one or more formats to be optimized by optimizer 214.

[0080] In at least one embodiment, optimizer 214 updates instructions. In at least one embodiment, optimizer 214 optimizes instructions to include additional information about the original instruction 206. In at least one embodiment, optimizer 214 generates updated instructions to include additional information about the memory location used by the original instruction 206 and its dependencies. In at least one embodiment, optimizer 214 is a set of software instructions that, if executed, cause one or more processors to generate one or more instructions that include updated instructions (e.g., the memory location used by the original instruction 206) or any intermediate data generated by optimizer 214, such as IR. In at least one embodiment, optimizer 214 optimizes instructions to reduce the overhead of the control code loop. In at least one embodiment, optimizer 214 optimizes instructions to evaluate constants at compile time rather than at runtime. In at least one embodiment, optimizer 214 optimizes instructions to remove code that does not affect the program's outcome. In at least one embodiment, optimizer 214 optimizes instructions to efficiently use CPU registers to store variables. In at least one embodiment, optimizer 214 optimizes instructions to identify and reuse the results of expressions that have been calculated multiple times.

[0081] In at least one embodiment, optimizer 214 updates one or more corresponding instructions 206. In at least one embodiment, optimizer 214 expands the instructions to include additional information about the bundled instructions 206. In at least one embodiment, optimizer 214 generates information that can be used by optional block (OB) 216 to indicate which of the one or more original instructions can be optimized, transformed, or otherwise converted into one or more formats to be analyzed by OB 216.

[0082] In at least one embodiment, OB 216 updates the instructions. In at least one embodiment, OB 216 optimizes the instructions to include additional information about the original instruction 206. In at least one embodiment, OB 216 generates updated instructions to include additional information about potential warnings, and / or code improvements, and / or code recommendations, and / or code suggestions. In at least one embodiment, OB 216 is a set of software instructions that, if executed, cause one or more processors to generate one or more instructions that include updated instructions, such as warnings and / or improvements and / or recommendations and / or suggestions about the original instruction 206, or any intermediate data generated by OB 216, such as IR.

[0083] In at least one embodiment, OB 216 updates the instructions. In at least one embodiment, OB 216 expands the instructions to include additional information about the original executable instructions 206. In at least one embodiment, OB 216 generates information that can be used by the risk scheduler (HS) 218 ​​to indicate which of one or more instructions 206 can be optimized, transformed, or otherwise converted into one or more formats to be analyzed by the HS 218.

[0084] In at least one embodiment, the HS218 updates executable instructions. In at least one embodiment, the HS218 optimizes instructions to reduce overhead. In at least one embodiment, the HS218 is a set of software instructions that, if executed, cause one or more processors to generate one or more updated instructions, or any intermediate data, such as IR, generated by the HS218. In at least one embodiment, the HS218 handles timing differences between instruction executions. In at least one embodiment, the HS218 annotates the order in which instructions should be executed.

[0085] In at least one embodiment, the HS218 extends the instructions to include additional information about the original executable instructions 206. In at least one embodiment, the HS218 generates information that can be used by the encoder 220 to indicate which of one or more instructions can be optimized, transformed, or otherwise converted into one or more formats to be encoded by the encoder 220.

[0086] In at least one embodiment, encoder 220 updates executable instructions. In at least one embodiment, encoder 220 encodes instructions to be compatible with one or more specific processor architectures and information about the original executable instructions. In at least one embodiment, encoder 220 is a set of software instructions that, if executed, cause one or more processors to generate one or more updated instructions and / or one or more updated instruction comments, or any intermediate data, such as IR, generated by encoder 220.

[0087] In at least one embodiment, encoder 220 generates executable instructions 222. In at least one embodiment, executable instructions 222 include one or more executable programs that can be configured to be executed by one or more processor architectures. In at least one embodiment, software is executed such that executable instructions 222 are configured to be executed by one or more processor types. In at least one embodiment, the multiple different processor architectures include one or more GPUs. In at least one embodiment, the multiple different processor architectures include one or more CPUs. In at least one embodiment, executable instructions 222 are an intermediate format of a software program, including object code, intermediate representation (IR), or any other form of software instruction representation further described herein. In at least one embodiment, executable instructions 222 are parallel thread execution (PTX) instructions. In at least one embodiment, executable instructions 222 include one or more instructions represented as ASCII text. In at least one embodiment, corresponding instruction 234 includes instructions for the GPU. In at least one embodiment, instruction 206 includes instructions for the CPU. In at least one embodiment, instruction 206 is compiled into executable binary code that will be executed on the GPU. In at least one embodiment, executable instructions 222 are compiled into executable binary code that will execute on a CPU. In at least one embodiment, executable instructions 222 include a bundled set of one or more compiled executable instructions and a set of one or more executable program comments. In at least one embodiment, executable instructions 222 consist of instruction comments and compiled executable instructions. In at least one embodiment, executable instructions 222 include one or more executable programs that can be configured to be executed by one or more processor architectures from a plurality of different processor architectures. In at least one embodiment, the plurality of different processor architectures include one or more GPUs. In at least one embodiment, the plurality of different processor architectures include one or more CPUs. In at least one embodiment, executable instructions 222 are generated at least in part based on the one or more processor architectures from the plurality of different processor architectures and a set of one or more executable instructions that are incompatible with the one or more processor architectures from the plurality of different processor architectures. In at least one embodiment, the bundled capsule 202 contains instructions 208 that are incompatible with the one or more processor architectures from the plurality of different processor architectures.In at least one embodiment, the bundled capsule 202 includes annotations 204 indicating instructions incompatible with one or more of the plurality of different processor architectures. These annotations 204 are decoded to generate a set of one or more executable instructions compatible with the one or more of the plurality of different processor architectures. In at least one embodiment, executable instructions 222 are generated corresponding to the set of executable instructions incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, annotations 204 and instructions 206 compatible with one or more of the plurality of different architecture types are decoded to generate finalization information and / or reconstructed text. In at least one embodiment, the finalization information and / or reconstructed text are used to verify the behavior of the set of one or more compiled executable instructions. In at least one embodiment, the finalization information and / or reconstructed text are used by a finalizer to verify whether the behavior of the compiled executable instructions mirrors the behavior of the original instructions.

[0088] Figure 2B This is a block diagram illustrating an exemplary compilation system for generating one or more corresponding instructions by decoding one or more original instructions, according to at least one embodiment. In at least one embodiment, a plurality of comments 224 are decoded 226, finalized, or otherwise converted into one or more corresponding instructions 228. For example, in at least one embodiment, one or more comments 224 are decoded, finalized, or otherwise converted as a group into one or more corresponding instructions 228. For example, in at least one embodiment, one or more comments 224 are converted according to the above combination. Figure 2A The described expanders, optimizers, optional blocks, risk schedulers, and encoders are decoded, finalized, or otherwise transformed individually or as a set. In at least one embodiment, the corresponding instruction 228 is executable instruction 222 or otherwise corresponds to executable instruction 222, as described above. Figure 2AIn at least one embodiment, the corresponding instruction 228 is an instruction configured to be executed by one or more processor architectures. In at least one embodiment, the corresponding instruction 228 is configured to be executed by one or more processor types. In at least one embodiment, the plurality of different processor architectures includes one or more GPUs. In at least one embodiment, the plurality of different processor architectures includes one or more CPUs. In at least one embodiment, the corresponding instruction 228 includes a bundle of one or more compiled executable instructions and a set of one or more executable program comments. In at least one embodiment, the corresponding instruction 228 includes instruction comments and compiled executable instructions. In at least one embodiment, the corresponding instruction 228 includes executable programs that can be configured to be executed by one or more processor architectures. In at least one embodiment, the plurality of different processor architectures includes one or more GPUs. In at least one embodiment, the plurality of different processor architectures includes one or more CPUs. In at least one embodiment, the corresponding instruction 228 is generated at least in part based on one or more of the plurality of different processor architectures and a set of one or more executable instructions incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, annotation 224 corresponds to an input instruction incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, annotation 224 indicating instructions incompatible with the one or more of the plurality of different processor architectures is decoded to generate a set of one or more executable instructions compatible with the one or more of the plurality of different processor architectures. In at least one embodiment, annotation 224 is generated to correspond to the set of executable instructions incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, annotation 224 and / or the corresponding executable instructions compatible with one or more of the plurality of different architecture types are decoded to generate finalized information and / or reconstructed text. In at least one embodiment, the finalized information and / or reconstructed text is used to verify the behavior of the set of one or more compiled executable instructions. In at least one embodiment, finalization information and / or reconstructed text are used by the finalizer to verify whether the behavior of the compiled executable instructions mirrors the behavior of the original instructions.

[0089] Figure 2CThis is a block diagram illustrating an exemplary compilation system for generating one or more corresponding instructions by decoding one or more original instructions, according to at least one embodiment. In at least one embodiment, a plurality of comments 230 are decoded and skipped 232, finalized, or otherwise converted into one or more corresponding instructions 234. For example, in at least one embodiment, one or more comments 230 are converted according to the combination described above. Figure 2A The expander, optimizer, optional block, risk scheduler, and encoder are decoded and skipped, finalized, or otherwise transformed individually or as a group. In at least one embodiment, the corresponding instruction 234 is combined as described above. Figure 2A The described executable instruction 222 or otherwise corresponds to the combination as described above. Figure 2A The described executable instructions 222. For example, in at least one embodiment, one or more comments 230 will be decoded, and no step or one or more steps will be skipped, finalized, or otherwise converted into one or more corresponding instructions 234. In at least one embodiment, the instructions 234 are executable programs that can be configured to be executed by one or more processor architectures. In at least one embodiment, software is executed such that the instructions 230 are configured to be executed by one or more processor types. In at least one embodiment, the multiple different processor architectures include one or more GPUs. In at least one embodiment, the multiple different processor architectures include one or more CPUs.

[0090] In at least one embodiment, instruction 230 includes a bundle of one or more compiled executable instructions and a set of one or more executable annotations. In at least one embodiment, instruction 234 includes instruction annotations and compiled executable instructions. In at least one embodiment, instruction 234 includes executable programs that can be configured to be executed by one or more processor architectures. In at least one embodiment, the multiple different processor architectures include one or more GPUs. In at least one embodiment, the multiple different processor architectures include one or more CPUs. In at least one embodiment, instruction 234 is generated at least in part based on the one or more processor architectures and a set of one or more executable instructions that are incompatible with the one or more processor architectures. In at least one embodiment, annotation 230 corresponds to input instructions that are incompatible with the one or more processor architectures. In at least one embodiment, annotation 230 indicating instructions incompatible with one or more of the plurality of different processor architectures is decoded to generate a set of one or more executable instructions compatible with one or more of the plurality of different processor architectures. In at least one embodiment, instructions 234 are generated corresponding to the set of executable instructions incompatible with one or more of the plurality of different processor architectures. In at least one embodiment, annotation 230 and / or the corresponding executable instructions compatible with one or more of the plurality of different architecture types are decoded to generate finalization information and / or reconstructed text. In at least one embodiment, the finalization information and / or reconstructed text is used to verify the behavior of the set of one or more compiled executable instructions. In at least one embodiment, the finalization information and / or reconstructed text is used by a finalizer to verify whether the behavior of the compiled executable instructions mirrors the behavior of the original instructions.

[0091] Figure 2DThis is a block diagram illustrating an exemplary compilation and / or decompilation system for generating one or more corresponding instructions, at least in part, based on decoding one or more instructions and one or more comments, according to at least one embodiment. In at least one embodiment, decoder 240 is a decompiler for generating one or more original instructions or corresponding instructions 242 from one or more executable instructions or other instructions 238 and one or more comments. In at least one embodiment, one or more comments 236 and one or more instructions 238 are a bundled set of one or more compiled executable instructions and a set of one or more executable program comments. In at least one embodiment, a plurality of instructions 238 and a plurality of comments 236 will be decoded 240, finalized, or otherwise converted into one or more corresponding instructions 242. For example, in at least one embodiment, one or more instructions 238 and one or more comments 236 will be decoded, finalized, or otherwise converted into one or more corresponding instructions 242 as a set. For example, in at least one embodiment, one or more comments 236 and / or one or more instructions 238 will be converted according to the above combination. Figure 2A The described expander, optimizer, optional block, risk scheduler, and encoder are decoded, finalized, or otherwise transformed individually or as a group. In at least one embodiment, the corresponding instruction 242 is as described above. Figure 2AThe described executable instructions 222 or otherwise correspond to executable instructions 222. In at least one embodiment, instructions 242 include one or more executable programs that can be configured to be executed by one or more processor architectures of a plurality of different processor architectures. In at least one embodiment, software is executed such that instructions 242 are configured to be executed by one or more processor types of a plurality of different processor types. In at least one embodiment, the plurality of different processor architectures include one or more GPUs. In at least one embodiment, the plurality of different processor architectures include one or more CPUs. In at least one embodiment, instructions 242 include a bundle of one or more compiled executable instructions and a set of one or more executable program comments. In at least one embodiment, instructions 242 include instruction comments and compiled executable instructions. In at least one embodiment, instructions 242 include a bundle of one or more compiled executable instructions and a set of one or more executable program comments. In at least one embodiment, instructions 242 include instruction comments and compiled executable instructions. In at least one embodiment, instruction 242 is generated at least in part based on one or more of the plurality of different processor architectures and a set of one or more executable instructions incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, instruction 238 is incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, note 236 indicates instructions incompatible with the one or more of the plurality of different processor architectures, which are decoded to generate a set of one or more executable instructions compatible with the one or more of the plurality of different processor architectures. In at least one embodiment, instruction 242 is generated corresponding to the set of executable instructions incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, note 236 and instruction 238 compatible with one or more of the plurality of different architecture types are decoded to generate finalized information and / or reconstructed text. In at least one embodiment, the finalized information and / or reconstructed text is used to verify the behavior of the set of one or more compiled executable instructions. In at least one embodiment, finalization information and / or reconstructed text are used by the finalizer to verify whether the behavior of the compiled executable instructions mirrors the behavior of the original instructions.

[0092] Figure 3This is a block diagram illustrating an exemplary compilation system according to at least one embodiment. In at least one embodiment, instructions and information 304 are received by a driver 318 for execution by a GPU 322. In at least one embodiment, instructions and information 304 are bundled into a capsule 310 and passed to a finalizer 316. In at least one embodiment, instructions 304 contain instructions incompatible with one or more of the plurality of different processor architectures. In at least one embodiment, instructions 304 contain annotations 306 indicating instructions incompatible with one or more of the plurality of different processor architectures, which are decoded to generate a set of one or more executable instructions compatible with one or more of the plurality of different processor architectures. In at least one embodiment, a driver 320 includes a finalizer 316. In at least one embodiment, the finalizer 316 is decoupled from the driver 320. In at least one embodiment, the finalizer 316 receives the capsule 310 to be executed by the GPU 324. In at least one embodiment, capsule 310 is data comprising a collection of one or more compiled executable instructions and one or more executable annotations, as further described herein. In at least one embodiment, capsule 310 includes instructions incompatible with one or more of the plurality of different processor architectures. In at least one embodiment, capsule 310 includes annotation 312 indicating instructions incompatible with one or more of the plurality of different processor architectures, which is decoded to generate a collection of one or more executable instructions compatible with one or more of the plurality of different processor architectures.

[0093] Figure 4AThis is a block diagram of an exemplary driver according to at least one embodiment. In at least one embodiment, instructions 408 are used by finalizer 410 to produce a bundled capsule 412. In at least one embodiment, a plurality of input instructions 402 are compiled 406 into instructions 408, and instructions 408 are sent to finalizer 410, or otherwise converted into one or more corresponding instructions 408. For example, in at least one embodiment, one or more instructions 402 are compiled, finalized, or otherwise converted as a set into one or more corresponding instructions 408. In at least one embodiment, the bundled capsule 412 includes one or more compiled executable instructions and a set of one or more executable annotations. In at least one embodiment, the bundled capsule 412 includes executable programs that are configured to be executed by one or more processor architectures of a plurality of different processor architectures. In at least one embodiment, the plurality of different processor architectures include at least one or more GPUs. In at least one embodiment, the plurality of different processor architectures include at least one or more CPUs. In at least one embodiment, driver 404 includes compiler 406, instructions 408, and / or finalizer 410. In at least one embodiment, driver 404 does not include compiler 406, instruction 408, and / or finalizer 410. In at least one embodiment, driver 404 is driver 416 or otherwise corresponds to driver 416, for example, as described below. Figure 4B As described above. In at least one embodiment, driver 404 is driver 604, driver 610, and driver 618, or otherwise corresponds to driver 604, driver 610, and driver 618, for example, as described below. Figures 6A-6C As described above. In at least one embodiment, driver 404 is driver 804 and driver 814 or otherwise corresponds to driver 804 and driver 814, for example, as described below. Figure 8A and Figure 8B As stated above.

[0094] In at least one embodiment, the bundled capsule 412 includes one or more executable programs configured to be executed by one or more processor architectures. In at least one embodiment, the executable program is configured to be executed by a processor including that processor architecture by compiling it into one or more executable instructions for that processor architecture. In at least one embodiment, one or more software programs are executed to configure the bundled capsule 412 to be executed by one or more processor types, such as the finalizer or other software programs described herein. In at least one embodiment, the multiple different processor architectures include one or more GPUs. In at least one embodiment, the multiple different processor architectures include one or more CPUs.

[0095] In at least one embodiment, the bundled capsule 412 includes a bundled set of one or more compiled executable instructions and a set of one or more executable comments. In at least one embodiment, the bundled capsule 412 includes instruction comments and compiled executable instructions. In at least one embodiment, the bundled capsule 412 includes a bundled set of one or more compiled executable instructions and a set of one or more executable comments. In at least one embodiment, the bundled capsule 412 includes instruction comments and compiled executable instructions. In at least one embodiment, the bundled capsule 412 is generated at least partially based on one or more of the plurality of different processor architectures and a set of one or more executable instructions incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, instruction 238 is incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, input instruction 402 includes annotations indicating instructions incompatible with one or more of the plurality of different processor architectures, and is decoded to generate a set of one or more executable instructions compatible with one or more of the plurality of different processor architectures. In at least one embodiment, a bundled capsule 412 is generated corresponding to the set of executable instructions incompatible with one or more of the plurality of different processor architectures. In at least one embodiment, instruction 402 compatible with one or more of the plurality of different architecture types is decoded to generate finalization information and / or reconstructed text. In at least one embodiment, the finalization information and / or reconstructed text is used to verify the behavior of the set of one or more compiled executable instructions. In at least one embodiment, the finalization information and / or reconstructed text is used to verify whether the behavior of the set of one or more compiled executable instructions compatible with one or more of the plurality of different processor architectures mirrors the behavior of the set of one or more executable instructions incompatible with one or more of the plurality of different architecture types.

[0096] Figure 4BThis is a block diagram illustrating an exemplary driver according to at least one embodiment. In at least one embodiment, instruction 420 is executable instruction 422. In at least one embodiment, a plurality of instructions 414 are compiled 418 into instruction 420, or otherwise converted into one or more corresponding instructions 420. For example, in at least one embodiment, one or more instructions 414 are compiled, finalized, or otherwise converted into one or more corresponding instructions 420 as a set. In at least one embodiment, executable instructions 422 include executable programs that are configured to be executed by one or more processor architectures of a plurality of different processor architectures. In at least one embodiment, the plurality of different processor architectures include at least one or more GPUs. In at least one embodiment, the plurality of different processor architectures include at least one or more CPUs. In at least one embodiment, driver 416 includes compilation 418 and / or instruction 420. In at least one embodiment, driver 416 does not include compilation 418 and / or instruction 420. In at least one embodiment, driver 416 is driver 604, driver 610, and driver 618, or otherwise corresponds to driver 604, driver 610, and driver 618, for example, as described below. Figures 6A-6C As described above. In at least one embodiment, driver 416 is driver 804 and / or driver 816 or otherwise corresponds to driver 804 and / or driver 816, for example, as described below. Figure 8A and / or Figure 8B As stated above.

[0097] In at least one embodiment, executable instructions 422 include one or more executable programs configured to be executed by one or more processor architectures of a plurality of different processor architectures. In at least one embodiment, executable instructions 422 are configured to be executed by one or more processor types of a plurality of different processor types. In at least one embodiment, the plurality of different processor architectures include at least one or more GPUs. In at least one embodiment, the plurality of different processor architectures include at least one or more CPUs. In at least one embodiment, executable instructions 422 include a bundle of one or more compiled executable instructions and a set of one or more executable program comments. In at least one embodiment, executable instructions 422 include instruction comments and compiled executable instructions. In at least one embodiment, the bundled capsule 412 includes a bundle of one or more compiled executable instructions and a set of one or more executable program comments. In at least one embodiment, executable instructions 422 include instruction comments and compiled executable instructions.

[0098] In at least one embodiment, executable instructions 422 are generated at least in part based on one or more of the plurality of different processor architectures and a set of one or more executable instructions incompatible with the one or more of the plurality of different processor architectures. In other words, in one embodiment, executable instructions 422 are generated by driver 416 at least in part based on decompiling and then recompiling 418 of a bundled capsule for one processor architecture into executable instructions 422 for another processor architecture. In at least one embodiment, input instructions 414 contain annotations indicating instructions incompatible with the one or more of the plurality of different processor architectures, which are decoded to generate a set of one or more executable instructions compatible with the one or more of the plurality of different processor architectures. In at least one embodiment, executable instructions 422 are generated corresponding to the set of executable instructions incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, instructions 402 compatible with one or more of the plurality of different architecture types are decoded to generate finalized information and / or reconstructed text. In at least one embodiment, the finalization information and / or refactored text are used to verify the behavior of the set of one or more compiled executable instructions. In at least one embodiment, the finalization information and / or refactored text are used to verify the behavior of the set of one or more compiled executable instructions. In at least one embodiment, the finalization information and / or refactored text are used by a finalizer to verify whether the behavior of the compiled executable instructions mirrors the behavior of the original instructions.

[0099] Figure 5 This is a block diagram illustrating a bundled capsule generated from raw instructions according to at least one embodiment. In at least one embodiment, the compiled instructions 504 include executable programs that can be configured to be executed by one or more processor architectures. In at least one embodiment, the plurality of different processor architectures include at least one or more GPUs. In at least one embodiment, the plurality of different processor architectures include at least one or more CPUs. In at least one embodiment, the annotated bundled executable instructions include one or more compiled executable instructions and one or more sets of executable annotations.

[0100] In at least one embodiment, compilation 502 is a set of software instructions that, if executed, cause one or more processors to translate, restore, or otherwise generate one or more compiled instructions from the original instructions 501. In at least one embodiment, compilation 502 converts one or more executable instructions 501 (as described above) into... Figure 1 The above is compiled as a compilation instruction 504.

[0101] In at least one embodiment, the annotation code 503 is a set of software instructions that, if executed, cause one or more processors to convert, restore, or otherwise generate one or more encoded instruction annotations 505 from executable instructions. In at least one embodiment, the annotation code 503 encodes one or more original instructions 501 into compiled instructions 504, as described above. Figure 1 As stated above.

[0102] In at least one embodiment, the bundled capsule 506 includes one or more executable programs that can be configured to be executed by one or more processor architectures of a plurality of different processor architectures. In at least one embodiment, software is executed to configure the bundled capsule 506 to be executed by one or more processor types of a plurality of different processor types. In at least one embodiment, the plurality of different processor architectures include one or more GPUs. In at least one embodiment, the plurality of different processor architectures include one or more CPUs. In at least one embodiment, the bundled capsule 506 includes a bundled set of one or more compiled executable instructions and a set of one or more executable annotations. In at least one embodiment, the bundled capsule 506 includes instruction annotations 505 and compiled executable instructions 504. In at least one embodiment, the bundled capsule 506 includes a bundled set of one or more compiled executable instructions and a set of one or more executable annotations. In at least one embodiment, the bundled capsule 506 includes instruction annotations and compiled executable instructions. In at least one embodiment, the compiled instructions 504 are generated at least in part based on one or more of the plurality of different processor architectures and a set of one or more executable instructions incompatible with the one or more of the plurality of different processor architectures, and may also be generated based on one or more comments within the one or more configured executable programs. In at least one embodiment, the executable instructions 501 are incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, the original instructions 501 include comments indicating instructions incompatible with the one or more of the plurality of different processor architectures, which are decoded to generate a set of one or more executable instructions compatible with the one or more of the plurality of different processor architectures. In at least one embodiment, the compiled instructions 504 are generated corresponding to the set of executable instructions incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, the compiled instructions 504 compatible with one or more of the plurality of different architecture types are decoded to generate finalized information and / or reconstructed text. In at least one embodiment, the finalization information and / or refactored text are used to verify the behavior of the set of one or more compiled executable instructions. In at least one embodiment, the finalization information and / or refactored text are used to verify the behavior of the set of one or more compiled executable instructions. In at least one embodiment, the finalization information and / or refactored text are used by a finalizer to verify whether the behavior of the compiled executable instructions mirrors the behavior of the original instructions.

[0103] In at least one embodiment, the encoded instruction annotation 505 includes metadata. In at least one embodiment, the metadata includes one or more executable instructions 505 in the encoded instruction annotation table 505. In at least one embodiment, the annotation table includes n first-level instruction streams, such as Mercury instructions, such as merc_instr_1, merc_instr_2, ..., merc_instr_n. In at least one embodiment, the annotation table includes k second-level instruction streams, such as SASS instructions, such as SASS_instr_1, SASS_instr_2, ..., SASS_instr_k. In at least one embodiment, the metadata includes 4-byte entries for simple first-level instructions, and text or other information indicating one or more raw instructions 501. In at least one embodiment, the entire executable instruction set will be used by compiler 502 to compile one or more compiled instructions 504. In at least one embodiment, the raw instructions 501 are Mercury instructions. In at least one embodiment, the raw instructions 501 are any other type of software instructions, such as, but not limited to, those further described herein. In at least one embodiment, the compiled instructions 504 are SASS instructions. In at least one embodiment, the compiled instruction 504 is any other type of software instruction, such as, but not limited to, those further described herein.

[0104] Figure 6A This is a block diagram illustrating an exemplary system for performing an on-target load according to at least one embodiment. In at least one embodiment, the on-target load 606 is an executable program that can be configured to be executed by one or more processor architectures of a plurality of different processor architectures. In at least one embodiment, the plurality of different processor architectures include at least one or more GPUs. In at least one embodiment, the plurality of different processor architectures include at least one or more CPUs. In at least one embodiment, executable instructions 602 are instructions 101, 206, 238, 308, 314, 402, 414, and 501 or otherwise correspond to instructions 101, 206, 238, 308, 314, 402, 414, and 501, for example, in conjunction with the above. Figures 1 to 5 Those described. In at least one embodiment, driver 604 is driver 416 or otherwise corresponds to driver 416, such as in conjunction with the above. Figure 4B The described driver 416. In at least one embodiment, driver 604 is driver 804, 814 or otherwise corresponds to driver 804, 814, for example, as described below. Figure 8A and Figure 8B Those described.

[0105] Figure 6B This is a block diagram illustrating an exemplary system for executing a target onload 614 by finalizing one or more compiled instructions 608 according to at least one embodiment. In at least one embodiment, the target onload 606 is an executable program configured to be executed by one or more processor architectures. In at least one embodiment, the plurality of different processor architectures include at least one or more GPUs. In at least one embodiment, the plurality of different processor architectures include at least one or more CPUs. In at least one embodiment, driver 610 includes a finalizer 612. In at least one embodiment, driver 610 does not include a finalizer 612. In at least one embodiment, driver 610 is driver 416 or otherwise corresponds to driver 416, for example, in conjunction with the above. Figure 4A Those described. In at least one embodiment, driver 610 is driver 804 and driver 814 or otherwise corresponds to driver 804 and driver 814, for example, as described below. Figure 8A and Figure 8B The driver described.

[0106] Figure 6C This is a block diagram illustrating an exemplary compilation system for executing on-loaded targets and generating one or more bundled capsules according to at least one embodiment. In at least one embodiment, on-loaded target 622 is an executable program configured to be executed by one or more processor architectures. In at least one embodiment, bundled capsules 616 and 624 comprise one or more compiled executable instructions and one or more sets of executable annotations. In at least one embodiment, bundled capsules 616 and 624 comprise an executable program configured to be executed by one or more processor architectures. In at least one embodiment, the multiple different processor architectures include at least one or more GPUs. In at least one embodiment, the multiple different processor architectures include at least one or more CPUs. In at least one embodiment, finalizer 620 is part of driver 618. In at least one embodiment, finalizer 620 is separate from driver 618. In at least one embodiment, driver 618 is driver 416 (e.g., in conjunction with the above). Figure 4A The driver 618 is, as described above, or otherwise corresponds to driver 416. In at least one embodiment, driver 618 is driver 804 and driver 814 (e.g., in conjunction with the following). Figure 8A and Figure 8B(as described above), or otherwise corresponding to driver 804 and driver 814. In at least one embodiment, the bundled capsule 616 is capsule 202, 310 (e.g., in conjunction with the above). Figures 2A to 3 (as described), or otherwise corresponding to capsules 202, 310.

[0107] Figure 7A This is a block diagram illustrating an exemplary compilation system for generating one or more bundled capsules from one or more text files, according to at least one embodiment. In at least one embodiment, text file 702 is data including compiled instructions 706 to be compiled 704 to produce bundled capsule 710. In at least one embodiment, bundled capsule 710 includes executable programs that can be configured to be executed by one or more processor architectures. In at least one embodiment, the multiple different processor architectures include one or more GPUs. In at least one embodiment, the multiple different processor architectures include one or more CPUs. In at least one embodiment, bundled capsule 710 includes one or more compiled executable instructions and a collection of one or more executable comments.

[0108] In at least one embodiment, multiple text files 702 are compiled 704 into compiled instructions 706, and the compiled instructions 706 are sent to an offline finalizer 708, or otherwise converted into one or more corresponding instructions 706. For example, in at least one embodiment, one or more text files 702 are a set of instructions that include one or more operations to be executed by one or more processors. In at least one embodiment, text files 702 are written by one or more software developers. In at least one embodiment, text files 702 are an intermediate format of a software program, including object code, intermediate representation (IR), or any other form of software instruction representation further described herein. In at least one embodiment, text files 702 are input to a compilation system 700A. In at least one embodiment, text files 702 include parallel thread execution (PTX) instructions. In at least one embodiment, text files 702 include one or more instructions represented as ASCII text. In at least one embodiment, text files 702 include GPU instructions. In at least one embodiment, text files 702 are compiled 704 into executable binary code. In at least one embodiment, the text file 702 will be compiled into executable binary code that will be executed on the GPU.

[0109] In at least one embodiment, compiler 704 is a set of software instructions (e.g., a compiler) that, if executed, causes one or more processors to generate one or more sets of compiled instructions 706 from text file 702. In at least one embodiment, compiler 704 generates one or more sets of compiled instructions 706. In at least one embodiment, compilation generates one or more sets of any other type of instructions further described herein. In at least one embodiment, compiler 704 is a backend optimization (BO) compiler. In at least one embodiment, compiler 704 is any other type of compiler further described herein. In at least one embodiment, compiler 704 compiles text file 702 into compiled instructions 706. In at least one embodiment, compiler 704 compiles each text file individually into intermediate code. In at least one embodiment, compiler 704 combines one or more IR nodes into a single large set of compiled instructions 706. In at least one embodiment, compiler 704 detects errors between individually compiled instruction modules. In at least one embodiment, compiler 704 includes a set of software instructions that, if executed, cause one or more processors to generate one or more instructions that include information about one or more instructions, such as input to offline finalizer 708 or any intermediate data (e.g., IR) generated by compiler 704. In at least one embodiment, compiler 704 is compiler 302 or otherwise corresponds to compiler 302, for example, as described above. Figure 3 The compiler 302 is described. In at least one embodiment, compilation 704 is compilation of 406 and 418 or otherwise corresponds to compilation of 406 and 418, for example, as described above in conjunction with... Figure 4A and Figure 4B Those described. In at least one embodiment, compilation 704 is compilation 502 or otherwise corresponds to compilation 502, for example, in conjunction with the above. Figure 5 The compiler error described is 502.

[0110] In at least one embodiment, the offline finalizer 708 generates a bundled capsule 710 from one or more compiled instructions 706, as described above. Figure 1 , Figure 3 and Figure 6C The discussion, and the following text in conjunction with Figure 8A and Figure 8B The discussion continues. In at least one embodiment, finalizer 708 generates one or more bundled capsules 710 at runtime. In at least one embodiment, finalizer 708 generates one or more bundled capsules 710 during compile time.

[0111] In at least one embodiment, the bundled capsule 710 includes one or more executable programs that can be configured to be executed by one or more processor architectures of a plurality of different processor architectures. In at least one embodiment, software is executed such that the bundled capsule 710 is configured to be executed by one or more processor types of a plurality of different processor types. In at least one embodiment, the plurality of different processor architectures include at least one or more GPUs. In at least one embodiment, the plurality of different processor architectures include at least one or more CPUs. In at least one embodiment, the bundled capsule 710 includes a bundled set of one or more compiled executable instructions and a set of one or more executable comments. In at least one embodiment, the bundled capsule 710 includes instruction comments and compiled executable instructions. In at least one embodiment, the bundled capsule 710 includes a bundled set of one or more compiled executable instructions and a set of one or more executable comments. In at least one embodiment, the bundled capsule 710 includes instruction comments and compiled executable instructions. In at least one embodiment, the bundled capsule 710 is generated at least partially based on one or more of the plurality of different processor architectures and a set of one or more executable instructions incompatible with the one or more of the plurality of different processor architectures, and may also be at least partially based on one or more comments within one or more configured executable programs. In at least one embodiment, the text file 702 is incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, the text file 702 contains comments indicating instructions incompatible with the one or more of the plurality of different processor architectures, which are decoded to generate a set of one or more executable instructions compatible with the one or more of the plurality of different processor architectures. In at least one embodiment, the bundled capsule 710 is generated corresponding to the set of executable instructions incompatible with the one or more of the plurality of different processor architectures, and the bundled capsule 710 may also be at least partially based on one or more comments within one or more configured executable programs. In at least one embodiment, a bundled capsule 710 compatible with one or more of the plurality of different architecture types is decoded to generate finalized information and / or reconstructed text. In at least one embodiment, the finalized information and / or reconstructed text is used to verify the behavior of the set of one or more compiled executable instructions. In at least one embodiment, the finalized information and / or reconstructed text is used to verify the behavior of the set of one or more compiled executable instructions.In at least one embodiment, finalization information and / or reconstructed text are used by the finalizer to verify whether the behavior of the compiled executable instructions mirrors the behavior of the original instructions.

[0112] Figure 7B This is a block diagram illustrating an exemplary compilation system 700B for generating one or more bundled capsules from one or more executable instructions, according to at least one embodiment. In at least one embodiment, the bundled capsule 720 includes executable programs that can be configured to be executed by one or more processor architectures. In at least one embodiment, the multiple different processor architectures include one or more GPUs. In at least one embodiment, the multiple different processor architectures include one or more CPUs. In at least one embodiment, the bundled capsule 720 includes one or more compiled executable instructions and one or more sets of executable annotations. In at least one embodiment, instructions 712 are used by compilation 714 to produce the bundled capsule 720 of compiled instructions. In at least one embodiment, the multiple instructions 712 are compiled 714 into compiled instructions 716, and the compiled instructions 716 are sent to an offline finalizer 718, or otherwise converted into one or more corresponding instructions 716. For example, in at least one embodiment, one or more instructions 712 are a set of instructions that include one or more operations to be executed by one or more processors. In at least one embodiment, instruction 712 is written by one or more software developers. In at least one embodiment, instruction 712 is an intermediate format of a software program, including object code, intermediate representation (IR), or any other form of software instruction representation further described herein. In at least one embodiment, instruction 712 is input to compiler system 700B. In at least one embodiment, instruction 712 is a parallel thread execution (PTX) instruction. In at least one embodiment, instruction 712 includes one or more instructions represented as ASCII text. In at least one embodiment, instruction 712 includes one or more instructions for a GPU. In at least one embodiment, instruction 712 will be compiled 714 by a compiler into executable binary code. In at least one embodiment, instruction 712 will be compiled 714 into executable binary code for execution by a GPU.

[0113] In at least one embodiment, compilation 714 is a set of software instructions (e.g., a compiler) that, if executed, causes one or more processors to generate one or more sets of compiled instructions 716 from instruction 712. In at least one embodiment, compilation 714 generates one or more sets of compiled instructions 716. In at least one embodiment, compilation generates one or more sets of any other type of instructions further described herein. In at least one embodiment, compilation 714 is a back-end optimization (BO) compiler. In at least one embodiment, compilation 714 is any other type of compiler further described herein. In at least one embodiment, compilation 714 compiles instruction 712 into compiled instructions 716. In at least one embodiment, compilation 714 compiles each instruction individually into intermediate code or representation (IR). In at least one embodiment, compilation 714 combines one or more IR nodes into a single large compiled instruction 716. In at least one embodiment, compilation 714 detects errors between individually compiled instruction modules. In at least one embodiment, compiler 714 includes a set of software instructions that, if executed, cause one or more processors to generate one or more instructions, which include information about one or more instructions, such as input to offline finalizer 718 or any intermediate data generated by compiler 714, such as IR. In at least one embodiment, compiler 714 is compiler 302 or otherwise corresponds to compiler 302, for example, as described above. Figure 3 The compiler 302 is described. In at least one embodiment, compilation 714 is compilation of 406 and 418 or otherwise corresponds to compilation of 406 and 418, for example, in conjunction with the above. Figure 4A and Figure 4B The compilation is described separately. In at least one embodiment, compilation 714 is compilation 502 or otherwise corresponds to compilation 502, for example, in conjunction with the above. Figure 5 The compilation described.

[0114] In at least one embodiment, the offline finalizer 718 generates a bundled capsule 720 from one or more compiled instructions 716, as described above. Figure 1 , Figure 3 and Figure 6C The discussion, and the following text in conjunction with Figure 8A and Figure 8B The discussion continues. In at least one embodiment, finalizer 718 generates one or more bundled capsules 720 at runtime. In at least one embodiment, finalizer 718 generates one or more bundled capsules 720 during compile time.

[0115] In at least one embodiment, the bundled capsule 720 includes one or more executable programs that can be configured to be executed by one or more processor architectures of a plurality of different processor architectures. In at least one embodiment, software is executed to configure the bundled capsule 720 to be executed by one or more processor types of a plurality of different processor types. In at least one embodiment, the plurality of different processor architectures include one or more GPUs. In at least one embodiment, the plurality of different processor architectures include one or more CPUs. In at least one embodiment, the bundled capsule 720 includes a bundled set of one or more compiled executable instructions and a set of one or more executable annotations. In at least one embodiment, the bundled capsule 720 includes instruction annotations and compiled executable instructions. In at least one embodiment, the bundled capsule 720 includes a bundled set of one or more compiled executable instructions and a set of one or more executable annotations. In at least one embodiment, the bundled capsule 720 includes instruction annotations and compiled executable instructions. In at least one embodiment, the bundled capsule 720 is generated at least in part based on one or more of the plurality of different processor architectures and a set of one or more executable instructions incompatible with the one or more of the plurality of different processor architectures, and may also be at least in part based on one or more comments within the one or more configured executable programs. In at least one embodiment, instruction 702 is incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, instruction 702 includes comments indicating instructions incompatible with the one or more of the plurality of different processor architectures, which are decoded to generate a set of one or more executable instructions compatible with the one or more of the plurality of different processor architectures. In at least one embodiment, the bundled capsule 720 is generated corresponding to the set of executable instructions incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, the bundled capsule 720 compatible with one or more of the plurality of different architecture types is decoded to generate finalized information and / or reconstructed text. In at least one embodiment, the finalization information and / or refactored text are used to verify the behavior of the set of one or more compiled executable instructions. In at least one embodiment, the finalization information and / or refactored text are used to verify the behavior of the set of one or more compiled executable instructions. In at least one embodiment, the finalization information and / or refactored text are used by a finalizer to verify whether the behavior of the compiled executable instructions mirrors the behavior of the original instructions.

[0116] Figure 8A This is a block diagram illustrating an exemplary compilation system for generating one or more executable instructions and one or more instruction annotations according to at least one embodiment. In at least one embodiment, the bundled capsule 812 includes an executable program that can be configured to be executed by one or more processor architectures of a plurality of different processor architectures. In at least one embodiment, the plurality of different processor architectures include one or more GPUs. In at least one embodiment, the plurality of different processor architectures include one or more CPUs. In at least one embodiment, the bundled capsule 812 includes a set of one or more compiled executable instructions and one or more executable annotations. In at least one embodiment, instructions 801 are used by a back-end optimization (BO) compiler 806 or any other compiler (e.g., but not limited to those further described herein) to produce the bundled capsule 812. In at least one embodiment, the plurality of instructions 801 are compiled 806 into compiled instructions 808, and the compiled instructions 808 are sent to an offline finalizer 810, or otherwise converted into one or more corresponding compiled instructions 808. For example, in at least one embodiment, one or more instructions 801 are data comprising an instruction set including one or more operations to be executed by one or more processors. In at least one embodiment, instructions 801 are written by one or more software developers. In at least one embodiment, instructions 801 are an intermediate format of a software program, including object code, intermediate representation (IR), or any other form of software instruction representation further described herein. In at least one embodiment, instructions 801 are input to a compilation and finalization system 800A. In at least one embodiment, instructions 801 are parallel thread execution (PTX) instructions. In at least one embodiment, instructions 801 include one or more instructions represented as ASCII text. In at least one embodiment, instructions 801 include instructions for a GPU. In at least one embodiment, instructions 801 will be compiled into executable binary code by a BO compiler 806. In at least one embodiment, instructions 801 will be compiled into executable binary code to be executed on a GPU.

[0117] In at least one embodiment, BO 806 is a compiler. In at least one embodiment, BO 806 is a BO compiler. In at least one embodiment, BO 806 is any other compiler, such as, but not limited to, those further described herein. In at least one embodiment, BO 806 is a set of software instructions (e.g., a compiler) that, if executed, causes one or more processors to generate one or more sets of compiled instructions 808 from instruction 801. In at least one embodiment, BO compiler 806 generates one or more sets of compiled instructions 808. In at least one embodiment, compilation generates one or more sets of any other type of instructions further described herein. In at least one embodiment, BO compiler 806 is a back-end optimization (BO) compiler. In at least one embodiment, BO compiler 806 is any other type of compiler further described herein. In at least one embodiment, BO compiler 806 compiles instruction 801 into compiled instructions 808. In at least one embodiment, BO compiler 806 compiles each instruction individually into intermediate code. In at least one embodiment, BO compiler 806 combines one or more IR nodes into a single large compiled instruction 808. In at least one embodiment, the BO compiler 806 detects errors between individually compiled instruction modules. In at least one embodiment, the BO compiler 806 includes a set of software instructions that, if executed, cause one or more processors to generate one or more instructions that include information about one or more instructions, such as input to the offline finalizer 810 or any intermediate data (e.g., IR) generated by the BO compiler 806. In at least one embodiment, the BO compiler 806 is compiler 302 or corresponds to compiler 302, for example, as described above. Figure 3 The compiler 302 is described. In at least one embodiment, the BO compiler 806 compiles 406 and 418 or corresponds to compiling 406 and 418, for example, as described above in conjunction with... Figure 4A and Figure 4B Those described. In at least one embodiment, the BO compiler is a compiler for 502 or corresponds to a compiler for 502, such as those described above. Figure 5 The compiler error described is 502.

[0118] In at least one embodiment, the offline finalizer 810 generates a bundled capsule 812 from one or more compiled instructions 808, as described above. Figure 1 , Figure 3 , Figure 6C , Figure 7A and Figure 7BThe above is discussed. In at least one embodiment, the offline finalizer 810 generates one or more bundled capsules 812 at runtime. In at least one embodiment, the offline finalizer 810 generates one or more bundled capsules 812 during compile time. In at least one embodiment, the BO compiler 806, the compiled instructions 808, and / or the offline finalizer 810 are part of the driver 804. In at least one embodiment, the BO compiler 806, the compiled instructions 808, and / or the offline finalizer 810 are separate from the driver 804.

[0119] In at least one embodiment, the bundled capsule 812 includes one or more executable programs that can be configured to be executed by one or more processor architectures of a plurality of different processor architectures. In at least one embodiment, software is executed such that the bundled capsule 812 is configured to be executed by one or more processor types of a plurality of different processor types. In at least one embodiment, the plurality of different processor architectures include one or more GPUs. In at least one embodiment, the plurality of different processor architectures include one or more CPUs. In at least one embodiment, the bundled capsule 812 includes a bundled set of one or more compiled executable instructions and a set of one or more executable comments. In at least one embodiment, the bundled capsule 812 includes instruction comments and compiled executable instructions. In at least one embodiment, the bundled capsule 812 includes a bundled set of one or more compiled executable instructions and a set of one or more executable comments. In at least one embodiment, the bundled capsule 812 includes instruction comments and compiled executable instructions. In at least one embodiment, the bundled capsule 812 is generated at least in part based on one or more of the plurality of different processor architectures and a set of one or more executable instructions incompatible with the one or more of the plurality of different processor architectures, and may also be at least in part based on one or more comments within the one or more configured executable programs. In at least one embodiment, instruction 801 is incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, instruction 801 includes comments indicating instructions incompatible with the one or more of the plurality of different processor architectures, which are decoded to generate a set of one or more executable instructions compatible with the one or more of the plurality of different processor architectures. In at least one embodiment, the bundled capsule 812 is generated corresponding to the set of executable instructions incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, the bundled capsule 812 compatible with one or more of the plurality of different architecture types is decoded to generate finalized information and / or reconstructed text. In at least one embodiment, the finalization information and / or refactored text are used to verify the behavior of the set of one or more compiled executable instructions. In at least one embodiment, the finalization information and / or refactored text are used to verify the behavior of the set of one or more compiled executable instructions. In at least one embodiment, the finalization information and / or refactored text are used by a finalizer to verify whether the behavior of the compiled executable instructions mirrors the behavior of the original instructions.

[0120] Figure 8B This is a block diagram illustrating an exemplary compilation system for generating one or more executable instructions and one or more instruction annotations, according to at least one embodiment. In at least one embodiment, instructions 802 are compiled into compiled instructions 818 using a back-end optimization (BO) compiler 816, and the compiled instructions 818 are otherwise converted into one or more corresponding compiled instructions 818. For example, in at least one embodiment, one or more instructions 802 are a set of instructions that include one or more operations to be executed by one or more processors. In at least one embodiment, instructions 802 are written by one or more software developers. In at least one embodiment, instructions 802 are an intermediate format of a software program, including object code, intermediate representation (IR), or any other form of software instruction representation further described herein. In at least one embodiment, instructions 802 are input to a compilation and finalization system 800B. In at least one embodiment, instructions 802 include parallel thread execution (PTX) instructions. In at least one embodiment, instructions 802 include one or more instructions represented as ASCII text. In at least one embodiment, instructions 802 include instructions to be executed by a GPU. In at least one embodiment, instruction 802 will be compiled into executable binary code by BO 816. In at least one embodiment, instruction 802 will be compiled into executable binary code that will be executed by the GPU.

[0121] In at least one embodiment, as described above Figure 8AThe back-end optimization (BO) compiler 816 is a set of software instructions that, when executed, cause one or more processors to generate one or more sets of compiled instructions 818 from instruction 802. In at least one embodiment, BO 816 is a compiler. In at least one embodiment, BO 816 is a BO compiler. In at least one embodiment, BO 816 is any other compiler, such as, but not limited to, those further described herein. In at least one embodiment, BO 816 generates one or more sets of compiled instructions 818. In at least one embodiment, compilation generates one or more sets of any other type of instructions further described herein. In at least one embodiment, BO 816 compiles instruction 802 into compiled instructions 818. In at least one embodiment, BO 816 compiles each instruction individually into intermediate code. In at least one embodiment, BO 816 combines one or more IR nodes into a single large compiled instruction 818. In at least one embodiment, BO 816 detects errors between individually compiled instruction modules. In at least one embodiment, BO 816 includes a set of software instructions that, when executed, cause one or more processors to generate one or more instructions, which include information about the one or more instructions, such as input to the offline finalizer 820 or any intermediate data generated by BO 816, such as IR. In at least one embodiment, BO 816 is compiler 302 or corresponds to compiler 302, such as those described above. Figure 3 The compiler described. In at least one embodiment, BO 816 is a compiler for 406 and 418 or corresponds to a compiler for 406 and 418, for example, as described above in conjunction with... Figure 4A and Figure 4B Those described. In at least one embodiment, BO 816 is compilation 502 or corresponds to compilation 502, for example, in conjunction with the above. Figure 5 The compilation described.

[0122] In at least one embodiment, the compiled instructions 818 are decoded 822 into compiled instruction text segments 824 and information for finalization 826. In at least one embodiment, the decoding step 822 involves parsing the compiled instructions 818 to extract meaningful text segments 824 that can be used for further analysis or documentation. In at least one embodiment, the finalization 826 information generated by the decoding step 822 includes metadata and other relevant details necessary for the final execution or deployment of the compiled instructions. In at least one embodiment, the decoding step 822 ensures that the compiled instruction text segments 824 are formatted and organized in a manner that facilitates easy interpretation and utilization by subsequent processes or the system. In at least one embodiment, the finalization 826 information is used to optimize the performance and efficiency of the compiled instructions during runtime.

[0123] In at least one embodiment, finalization 826 generates a bundled capsule 834 from one or more compiled instructions 808 of decoding 822, as described above. Figure 1 , Figure 3 , Figure 6C , Figure 7A and Figure 7B In at least one embodiment, the bundled capsule 834 includes executable programs that can be configured to be executed by one or more processor architectures. In at least one embodiment, the multiple different processor architectures include one or more GPUs. In at least one embodiment, the multiple different processor architectures include one or more CPUs. In at least one embodiment, the bundled capsule 834 includes one or more compiled executable instructions and one or more sets of executable annotations. In at least one embodiment, a finalizer 826 generates one or more bundled capsules 834 at runtime. In at least one embodiment, a finalizer 826 generates one or more bundled capsules 834 during compile time. In at least one embodiment, finalization 826 also provides information to refactoring 828. In at least one embodiment, refactoring 828 uses metadata provided by finalization 826 to accurately reconstruct the original text (reconstructed text 830) from information from decoding 822 of compiled instructions 818. In at least one embodiment, the metadata includes basic information such as variable names, data types, and control flow details that are essential to the refactoring process. In at least one embodiment, the metadata covers a wide range of data types, including but not limited to integers, floating-point numbers, characters, strings, arrays, structures, and pointers.

[0124] In at least one embodiment, refactoring 828 ensures that the refactored text retains the same logical structure and functionality as the original source code. In at least one embodiment, refactoring 828 includes parsing compiled instructions and using metadata to generate a human-readable representation of the code; for example, integer and floating-point data types are refactored with their original precision and format, while character and string data types are restored with their exact text content.

[0125] In at least one embodiment, the reconstruction 828 preserves the original layout and the relationships between the data. In at least one embodiment, the reconstruction 828 processes pointers by reconstructing the memory addresses and the references they point to, ensuring that the reconstructed text correctly represents the original memory management and data access patterns.

[0126] In at least one embodiment, refactoring 828 is designed to facilitate debugging, analysis, and further development by providing a clear and accurate textual representation of the compiled instructions. In at least one embodiment, refactoring 826 ensures the recovery of all data types in instructions 802 and compiled instructions 818.

[0127] In at least one embodiment, reconstruction 828 generates reconstructed text 830. In at least one embodiment, the reconstructed text 830 includes one or more text files. In at least one embodiment, the reconstructed text 830 includes binary data files or any combination of file types described herein.

[0128] In at least one embodiment, the reconstructed text 830 is saved to a bin text file 840. In at least one embodiment, the bin text file 840 includes one or more text files. In at least one embodiment, the bin text file 840 includes a binary data file. In at least one embodiment, the bin text file 840 includes a configuration file or any combination of file types described herein.

[0129] In at least one embodiment, the compiled text segment 824 is saved to a bin text file 838. In at least one embodiment, the bin text file 838 includes one or more text files. In at least one embodiment, the bin text file 838 includes a binary data file. In at least one embodiment, the bin text file 838 includes a configuration file or any combination of file types described herein.

[0130] In at least one embodiment, a difference check 832 is used to compare the reconstructed text 830 with the compiled instruction text segment 824 to generate a verification result 842.

[0131] In at least one embodiment, the backend optimization compiler 816, the compiled instructions 818, and / or the offline finalizer 820, and their respective components, are part of the driver 814. In at least one embodiment, the backend optimization compiler 816, the compiled instructions 818, and / or the offline finalizer 820, and their respective components, are separate from the driver 814.

[0132] In at least one embodiment, the bundled capsule 834 includes one or more executable programs that can be configured to be executed by one or more processor architectures of a plurality of different processor architectures. In at least one embodiment, software is executed to configure the bundled capsule 834 to be executed by one or more processor types of a plurality of different processor types. In at least one embodiment, the plurality of different processor architectures include one or more GPUs. In at least one embodiment, the plurality of different processor architectures include one or more CPUs. In at least one embodiment, the bundled capsule 834 includes a bundled set of one or more compiled executable instructions and a set of one or more executable annotations. In at least one embodiment, the bundled capsule 834 includes instruction annotations and compiled executable instructions. In at least one embodiment, the bundled capsule 834 includes a bundled set of one or more compiled executable instructions and a set of one or more executable annotations. In at least one embodiment, the bundled capsule 834 includes instruction annotations and compiled executable instructions. In at least one embodiment, the bundled capsule 834 is generated at least partially based on one or more of the plurality of different processor architectures and a set of one or more executable instructions incompatible with the one or more of the plurality of different processor architectures, and may also be at least partially based on one or more comments within the one or more configured executable programs. In at least one embodiment, instruction 802 is incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, instruction 802 includes comments indicating instructions incompatible with the one or more of the plurality of different processor architectures, which are decoded to generate a set of one or more executable instructions compatible with the one or more of the plurality of different processor architectures. In at least one embodiment, the bundled capsule 834 is generated corresponding to the set of executable instructions incompatible with the one or more of the plurality of different processor architectures. In at least one embodiment, the bundled capsule 834 compatible with one or more of the plurality of different architecture types is decoded to generate finalized information and / or reconstructed text 830. In at least one embodiment, finalization information and / or reconstructed text are used by the finalizer to verify whether the behavior of the compiled executable instructions mirrors the behavior of the original instructions.

[0133] Figure 9An exemplary process 900 for generating one or more reconfigurable executable programs 914 according to at least one embodiment is illustrated. In at least one embodiment, process 900 begins with a compiler, finalizer, transformer, driver, or any other software program further described herein receiving instructions 902, such as those in conjunction with the foregoing. Figures 1 to 8B Further instructions described herein. In at least one embodiment, the compiler, finalizer, converter, driver, or any other software program further described herein compiles, transforms, or otherwise generates a set of executable instructions based at least in part on the instructions received at 902, as described above. Figures 1 to 8B As stated above.

[0134] In at least one embodiment, a compiler, finalizer, transformer, driver, or any other software program further described herein generates annotation 904, which indicates information about one or more instructions, as described above. The annotation includes information that will be used in process 1000, and in one embodiment, for redirecting executable code to a different processor architecture, as described above. Figure 7A , Figure 7B , Figure 8A and Figure 8B In at least one embodiment, if process 900 completes 912, the compiler, finalizer, converter, driver, or any other software program further described herein generates one or more reconfigurable executable programs for execution by one or more processors (e.g., one or more GPUs and / or one or more CPUs). In at least one embodiment, if process 900 does not complete 912, the compiler, finalizer, converter, driver, or any other software program further described herein further compiles instructions, and process 900 continues at step 904.

[0135] Figure 10 An exemplary process 1000 is illustrated according to at least one embodiment for configuring or recompiling one or more executable programs 1010 to a processor architecture based on one or more comments. In at least one embodiment, process 1000 begins when a driver, compiler, or any other software further described herein receives an executable program 1004, which includes executable instructions, compiled instructions, and / or bundled capsules, as described above. Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 8A and Figure 8BAs further described herein. In at least one embodiment, if the executable program is compatible with or otherwise executable by a processor including the target architecture 1006, the processor or any other processor may optionally execute the executable program 1016.

[0136] In at least one embodiment, if the executable is incompatible with or otherwise cannot be executed by a processor including the target architecture 1006, the driver, compiler, or any other software further described herein decompiles or decodes the executable using note 1008, as described above. Figure 6A , Figure 6B , Figure 6C , Figure 8A and Figure 8B Further described. In at least one embodiment, after the executable program 1008 has been decompiled or otherwise decoded by a driver, compiler, or any other software further described herein, the decompiled or otherwise decoded program is recompiled to target a specific target processor architecture 1010, as described above. Figure 8A and Figure 8B As described herein. In at least one embodiment, if all executable instructions are decompiled or decoded 1008 and then recompiled 1010, the driver, compiler, or other software further described herein generates a new reconfigurable executable and bundles it with comment 1014, as described above. Figure 6C , Figure 8A and Figure 8B In at least one embodiment, if all executable instructions have not been decompiled or decoded 1008 and are then recompiled 1010, the driver, compiler, or other software further described herein further decompiles the executable program input by 1008. In at least one embodiment, once the driver, compiler, or other software program generates a new reconfigurable executable program 1014 with target platform-specific annotations, a processor including the target architecture 1006 optionally executes the executable program 1016, and process 1000 completes.

[0137] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, those skilled in the art will appreciate that the concepts of the invention can be practiced without one or more of these specific details.

[0138] Data Center

[0139] Figure 11An exemplary data center 1100 according to at least one embodiment is shown. In at least one embodiment, the data center 1100 includes, but is not limited to, a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0140] In at least one embodiment, such as Figure 11 As shown, the data center infrastructure layer 1110 may include a resource coordinator 1112, grouped computing resources 1114, and node computing resources (“nodes CR”) 1116(1)-1116(N), where “N” represents any complete positive integer. In at least one embodiment, nodes CR 1116(1)-1116(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (“FPGAs”), data processing units (“DPUs”) in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 1116(1)-1116(N) may be servers having one or more of the aforementioned computing resources.

[0141] In at least one embodiment, the grouped computing resources 1114 may include individual groups (not shown) of node CRs housed in one or more racks, or a plurality of racks (also not shown) housed in data centers in various geographical locations. The individual groups of node CRs within the grouped computing resources 1114 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0142] In at least one embodiment, resource coordinator 1112 may be configured or otherwise control one or more nodes CR1116(1)-1116(N) and / or grouped computing resources 1114. In at least one embodiment, resource coordinator 1112 may include a Software Design Infrastructure (“SDI”) management entity for data center 1100. In at least one embodiment, resource coordinator 1112 may include hardware, software, or some combination thereof.

[0143] In at least one embodiment, such as Figure 11 As shown, framework layer 1120 includes, but is not limited to, job scheduler 1132, configuration manager 1134, resource manager 1136, and distributed file system 1138. In at least one embodiment, framework layer 1120 may include a framework of software 1152 supporting software layer 1130 and / or one or more applications 1142 supporting application layer 1140. In at least one embodiment, software 1152 or application 1142 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1120 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark") which can utilize distributed file system 1138 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 1132 may include Spark drivers to facilitate the scheduling of workloads supported by the various layers of data center 1100. In at least one embodiment, configuration manager 1134 may be able to configure different layers, such as software layer 1130 and framework layer 1120 including Spark and distributed file system 1138 for supporting large-scale data processing. In at least one embodiment, resource manager 1136 is able to manage cluster or group computing resources mapped to or allocated to support distributed file system 1138 and job scheduler 1132. In at least one embodiment, cluster or group computing resources may include grouped computing resources 1114 on data center infrastructure layer 1110. In at least one embodiment, resource manager 1136 may coordinate with resource coordinator 1112 to manage these mapped or allocated computing resources.

[0144] In at least one embodiment, the software 1152 included in software layer 1130 may include software used by at least a portion of nodes CR1116(1)-1116(N), grouped computing resources 1114, and / or the distributed file system 1138 of framework layer 1120. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0145] In at least one embodiment, one or more applications 1142 included in application layer 1140 may include one or more types of applications used by at least a portion of nodes CR1116(1)-1116(N), grouped computing resources 1114, and / or the distributed file system 1138 of framework layer 1120. One or more types of applications may include, but are not limited to, CUDA applications.

[0146] In at least one embodiment, any of the configuration manager 1134, resource manager 1136, and resource coordinator 1112 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 1100 and can prevent underutilization and / or poor performance of the data center.

[0147] Computer-based systems

[0148] The following figures present, but are not limited to, exemplary computer-based systems that can be used to implement at least one embodiment.

[0149] Figure 12 A processing system 1200 according to at least one embodiment is illustrated. In at least one embodiment, the system 1200 includes one or more processors 1202 and one or more graphics processors 1208, and may be a single-processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors 1202 or processor cores 1207. In at least one embodiment, the processing system 1200 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices. In at least one embodiment, the processor core 1207 is referred to as a computing unit or arithmetic unit.

[0150] In at least one embodiment, the processing system 1200 may include or be integrated into a server-based gaming platform, including a game console, mobile game console, handheld game console, or online game console, which are game and media consoles. In at least one embodiment, the processing system 1200 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, the processing system 1200 may also include components coupled to or integrated into a wearable device, such as a smartwatch wearable device, smart glasses device, augmented reality device, or virtual reality device. In at least one embodiment, the processing system 1200 is a television or set-top box device having one or more processors 1202 and a graphical interface generated by one or more graphics processors 1208.

[0151] In at least one embodiment, each of the one or more processors 1202 includes one or more processor cores 1207 for processing instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 1207 is configured to process a specific instruction set 1209. In at least one embodiment, the instruction set 1209 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, the plurality of processor cores 1207 may each process a different instruction set 1209, which may include instructions that facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 1207 may also include other processing devices, such as digital signal processors (DSPs).

[0152] In at least one embodiment, processor 1202 includes cache memory 1204. In at least one embodiment, processor 1202 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among various components of processor 1202. In at least one embodiment, processor 1202 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 1207 using known cache coherence techniques. In at least one embodiment, processor 1202 further includes a register file 1206, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 1206 may include general-purpose registers or other registers.

[0153] In at least one embodiment, one or more processors 1202 are coupled to one or more interface buses 1210 to transmit communication signals, such as address, data, or control signals, between the processor 1202 and other components in the system 1200. In at least one embodiment, the interface bus 1210 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 1210 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 1202 includes an integrated memory controller 1216 and a platform controller hub 1230. In at least one embodiment, the memory controller 1216 facilitates communication between storage devices and other components of the processing system 1200, while the platform controller hub (PCH) 1230 provides connectivity to input / output (I / O) devices via a local I / O bus. In at least one embodiment, one or more peripheral component interconnect buses include PCIe Gen 5, which provides an interface for the processor.

[0154] In at least one embodiment, storage device 1220 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or a device with suitable performance for use as processor memory. In at least one embodiment, storage device 1220 may be used as system memory of processing system 1200 to store data 1222 and instructions 1221 for use when one or more processors 1202 execute an application or process. In at least one embodiment, memory controller 1216 is also coupled to an optional external graphics processor 1212, which may communicate with one or more graphics processors 1208 of processor 1202 to perform graph and media operations. In at least one embodiment, display device 1211 may be connected to processor 1202. In at least one embodiment, display device 1211 may include one or more internal display devices, such as those in mobile electronic devices or portable computer devices, or external display devices connected via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 1211 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) or augmented reality (AR) applications.

[0155] In at least one embodiment, the platform controller hub 1230 enables peripheral devices to connect to the storage device 1220 and the processor 1202 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 1246, a network controller 1234, a firmware interface 1228, a wireless transceiver 1226, a touch sensor 1225, and a data storage device 1224 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 1224 may be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 1225 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1226 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 1228 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 1234 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 1210. In at least one embodiment, audio controller 1246 is a multi-channel high-definition audio controller. In at least one embodiment, processing system 1200 includes an optional legacy I / O controller 1240 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to processing system 1200. In at least one embodiment, platform controller hub 1230 may also be connected to one or more Universal Serial Bus (USB) controllers 1242 that connect input devices, such as a keyboard and mouse combination 1243, a camera 1244, or other USB input devices.

[0156] In at least one embodiment, instances of the memory controller 1216 and platform controller hub 1230 may be integrated into a discrete external graphics processor, such as external graphics processor 1212. In at least one embodiment, the platform controller hub 1230 and / or memory controller 1216 may be external to one or more processors 1202. For example, in at least one embodiment, the processing system 1200 may include an external memory controller 1216 and a platform controller hub 1230, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset communicating with the processor 1202.

[0157] Figure 13A computer system 1300 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1300 may be a system having interconnected devices and components, a System-on-a-Chip (SoC), or some combination thereof. In at least one embodiment, the computer system 1300 is formed by a processor 1302, which may include execution units for executing instructions. In at least one embodiment, the computer system 1300 may include, but is not limited to, components such as the processor 1302, which employs execution units including logic to execute algorithms for process data. In at least one embodiment, the computer system 1300 may include a processor, such as one available from Intel Corporation of Santa Clara, California. Processor family, Xeon™ XScale™ and / or StrongARM™ Core TM or Nervana TM A microprocessor may be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, computer system 1300 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0158] In at least one embodiment, the computer system 1300 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system capable of executing one or more instructions according to at least one embodiment.

[0159] In at least one embodiment, the computer system 1300 may include, but is not limited to, a processor 1302, which may include, but is not limited to, one or more execution units 1308 configured to execute a Computational Unified Device Architecture (“CUDA”). The program is developed by NVIDIA Corporation in Santa Clara, California. In at least one embodiment, the CUDA program is at least a part of a software application written in the CUDA programming language. In at least one embodiment, the computer system 1300 is a single-processor desktop or server system. In at least one embodiment, the computer system 1300 may be a multiprocessor system. In at least one embodiment, the processor 1302 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing instruction set combinations, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1302 may be coupled to a processor bus 1310, which can transmit data signals between the processor 1302 and other components in the computer system 1300.

[0160] In at least one embodiment, processor 1302 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1304. In at least one embodiment, processor 1302 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1302. In at least one embodiment, processor 1302 may include a combination of internal and external caches. In at least one embodiment, register file 1306 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0161] In at least one embodiment, an execution unit 1308, including but not limited to logic for performing integer and floating-point operations, is also located within the processor 1302. The processor 1302 may also include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, the execution unit 1308 may include logic for processing a packaged instruction set 1309. In at least one embodiment, by including the packaged instruction set 1309 in the instruction set of the general-purpose processor 1302, along with the associated circuitry for executing the instructions, packaged data in the general-purpose processor 1302 can be used to perform operations used by many multimedia applications. In at least one embodiment, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor's data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor's data bus to perform one or more operations on a data element at a time.

[0162] In at least one embodiment, the execution unit 1308 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, the computer system 1300 may include, but is not limited to, the memory 1320. In at least one embodiment, the memory 1320 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. The memory 1320 may store instructions 1319 and / or data 1321 represented by data signals that can be executed by the processor 1302.

[0163] In at least one embodiment, the system logic chip may be coupled to the processor bus 1310 and the memory 1320. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1316, and the processor 1302 may communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 may provide a high-bandwidth memory path 1318 to the memory 1320 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1316 may initiate data signals between the processor 1302, the memory 1320, and other components in the computer system 1300, and bridge data signals between the processor bus 1310, the memory 1320, and the system I / O 1322. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1316 may be coupled to memory 1320 via high-bandwidth memory path 1318, and graphics / video card 1312 may be coupled to MCH 1316 via Accelerated Graphics Port (“AGP”) interconnect 1314.

[0164] In at least one embodiment, computer system 1300 may use system I / O 1322 as a proprietary hub interface bus to couple MCH 1316 to I / O controller hub (“ICH”) 1330. In at least one embodiment, ICH 1330 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1320, chipset, and processor 1302. Examples may include, but are not limited to, an audio controller 1329, a firmware hub (“Flash BIOS”) 1328, a wireless transceiver 1326, data storage 1324, a conventional I / O controller 1323 and keyboard interface including user input 1325, a serial expansion port 1327 (e.g., USB), and a network controller 1334. Data storage 1324 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

[0165] In at least one embodiment, Figure 13 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Figure 13 An exemplary SoC can be shown. In at least one embodiment, Figure 13 The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1300 are interconnected using a Compute Fast Link (CXL) interconnect.

[0166] Figure 14 A system 1400 according to at least one embodiment is illustrated. In at least one embodiment, system 1400 is an electronic device utilizing processor 1410. In at least one embodiment, system 1400 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, edge device communicatively coupled to one or more locations or cloud service providers, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0167] In at least one embodiment, system 1400 may include, but is not limited to, processor 1410 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1410 is coupled using a bus or interface, such as I... 2C-bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Accessory (“SATA”) bus, USB (versions 1, 2, and 3) or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment,

[0168] Figure 14 A system is illustrated, comprising interconnected hardware devices or "chips". In at least one embodiment, Figure 14 An exemplary SoC can be shown. In at least one embodiment, Figure 14 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof.

[0169] In at least one embodiment, Figure 14 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0170] In at least one embodiment, Figure 14 This may include a display 1424, a touchscreen 1425, a touchpad 1430, a near-field communication unit (“NFC”) 1445, a sensor hub 1440, a thermal sensor 1446, a fast chipset (“EC”) 1435, a trusted platform module (“TPM”) 1438, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1422, a DSP 1460, a solid-state drive (“SSD”) or hard disk drive (“HDD”) 1420, a wireless local area network unit (“WLAN”) 1450, a Bluetooth unit 1452, a wireless wide area network unit (“WWAN”) 1456, a global positioning system (GPS) 1455, a camera (“USB 3.0 camera”) 1454 (e.g., a USB 3.0 camera), or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1415 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0171] In at least one embodiment, other components may be communicatively coupled to processor 1410 via the components discussed above. In at least one embodiment, accelerometer 1441, ambient light sensor (“ALS”) 1442, compass 1443, and gyroscope 1444 may be communicatively coupled to sensor hub 1440. In at least one embodiment, thermal sensor 1439, fan 1437, keyboard 1446, and touchpad 1430 may be communicatively coupled to EC 1435. In at least one embodiment, speaker 1463, earphone 1464, and microphone (“mic”) 1465 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1464, which in turn may be communicatively coupled to DSP 1460. In at least one embodiment, audio unit 1464 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1457 may be communicatively coupled to WWAN unit 1456. In at least one embodiment, components such as WLAN unit 1450, Bluetooth unit 1452, and WWAN unit 1456 can be implemented as next-generation form factor (NGFF).

[0172] Figure 15 An exemplary integrated circuit 1500 according to at least one embodiment is illustrated. In at least one embodiment, the exemplary integrated circuit 1500 is a SoC (System-on-a-Chip) that can be fabricated using one or more IP cores. In at least one embodiment, the integrated circuit 1500 includes one or more application processors 1505 (e.g., CPU, DPU), at least one graphics processor 1510, and may additionally include an image processor 1515 and / or a video processor 1520, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1500 includes peripheral or bus logic, which includes a USB controller 1525, a UART controller 1530, an SPI / SDIO controller 1535, and an I... 2 S / I 2 C controller 1540. In at least one embodiment, integrated circuit 1500 may include display device 1545 coupled to one or more of high-definition multimedia interface (HDMI) controller 1550 and mobile industrial processor interface (MIPI) display interface 1555. In at least one embodiment, storage may be provided by flash memory subsystem 1560, including flash memory and flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 1565 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include embedded security engine 1570.

[0173] Figure 16A computing system 1600 according to at least one embodiment is illustrated. In at least one embodiment, the computing system 1600 includes a processing subsystem 1601 having one or more processors 1602 and a system memory 1604 communicating via an interconnect path that may include a memory hub 1605. In at least one embodiment, the memory hub 1605 may be a separate component within a chipset assembly or may be integrated within one or more processors 1602. In at least one embodiment, the memory hub 1605 is coupled to an I / O subsystem 1611 via a communication link 1606. In at least one embodiment, the I / O subsystem 1611 includes an I / O hub 1607 that enables the computing system 1600 to receive input from one or more input devices 1608. In at least one embodiment, the I / O hub 1607 may enable a display controller, which is included in one or more processors 1602, for providing output to one or more display devices 1610A. In at least one embodiment, one or more display devices 1610A coupled to the I / O hub 1607 may include local, internal, or embedded display devices.

[0174] In at least one embodiment, the processing subsystem 1601 includes one or more parallel processors 1612 coupled to a memory hub 1605 via a bus or other communication link 1613. In at least one embodiment, the communication link 1613 may be one of many standards-based communication link technologies or protocols, such as, but not limited to, PCIe, or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, the one or more parallel processors 1612 form a compute-intensive parallel or vector processing system that may include a large number of processing cores and / or processing clusters, such as multi-core processors or computing units. In at least one embodiment, the one or more parallel processors 1612 form a graphics processing subsystem capable of outputting pixels to one or more display devices 1610A coupled via an I / O hub 1607. In at least one embodiment, the one or more parallel processors 1612 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1610B.

[0175] In at least one embodiment, system storage unit 1614 may be connected to I / O hub 1607 to provide a storage mechanism for computing system 1600. In at least one embodiment, I / O switch 1616 may be used to provide an interface mechanism to enable connectivity between I / O hub 1607 and other components, such as network adapter 1618 and / or wireless network adapter 1619 that may be integrated into the platform, and various other devices that may be added via one or more additional devices 1620. In at least one embodiment, network adapter 1618 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1619 may include one or more Wi-Fi, Bluetooth, NFC, or other network devices comprising one or more radios.

[0176] In at least one embodiment, the computing system 1600 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., and may also be connected to the I / O hub 1607. In at least one embodiment, for Figure 16 The communication paths that interconnect the various components can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocols).

[0177] In at least one embodiment, one or more parallel processors 1612 include circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1612 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computing system 1600 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1612, memory hub 1605, processor 1602, and I / O hub 1607 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computing system 1600 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 1600 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computing system. In at least one embodiment, the I / O subsystem 1611 and display device 1610B are omitted from the computing system 1600. In at least one embodiment, one or more parallel processors 1612 include one or more tensor memory accelerator (TMA) units that can transfer data blocks between global memory and shared memory. In at least one embodiment, one or more processors use or access one or more TMAs to perform bidirectional copy operations, such as from global memory to shared memory and vice versa.

[0178] Processing system

[0179] The following figures illustrate, but are not limited to, exemplary processing systems that can be used to implement at least one embodiment.

[0180] Figure 17An accelerated processing unit (“APU”) 1700 according to at least one embodiment is illustrated. In at least one embodiment, the APU 1700 was developed by AMD Inc. of Santa Clara, California. In at least one embodiment, the APU 1700 can be configured to execute applications, such as CUDA programs. In at least one embodiment, the APU 1700 includes, but is not limited to, a core complex 1710, a graphics complex 1740, an architecture 1760, an I / O interface 1770, a memory controller 1780, a display controller 1792, and a multimedia engine 1794. In at least one embodiment, the APU 1700 can be, but is not limited to, any combination of any number of core complexes 1710, any number of graphics complexes 1740, any number of display controllers 1792, and any number of multimedia engines 1794. For illustrative purposes, multiple instances of similar objects are indicated herein by reference numerals, wherein the reference numerals identify the object, and the numbers in parentheses identify the desired instances.

[0181] In at least one embodiment, the core complex 1710 is a CPU, the graphics complex 1740 is a GPU, and the APU 1700 is a processing unit that is not limited to 1710 and 1740 integrated onto a single chip. In at least one embodiment, some tasks may be assigned to the core complex 1710, while other tasks may be assigned to the graphics complex 1740. In at least one embodiment, the core complex 1710 is configured to execute master control software associated with the APU 1700, such as an operating system. In at least one embodiment, the core complex 1710 is the master processor of the APU 1700, which controls and coordinates the operation of other processors. In at least one embodiment, the core complex 1710 issues commands to control the operation of the graphics complex 1740. In at least one embodiment, the core complex 1710 may be configured to execute host executable code derived from CUDA source code, and the graphics complex 1740 may be configured to execute device executable code derived from CUDA source code.

[0182] In at least one embodiment, the core complex 1710 includes, but is not limited to, cores 1720(1)-1720(4) and L3 cache 1730. In at least one embodiment, the core complex 1710 may include, but is not limited to, any combination of any number of cores 1720 and any number and type of cache. In at least one embodiment, the cores 1720 are configured to execute instructions of a specific instruction set architecture (“ISA”). In at least one embodiment, each core 1720 is a CPU core. In at least one embodiment, the core 1720 is referred to as a compute unit or arithmetic unit.

[0183] In at least one embodiment, each core 1720 includes, but is not limited to, a fetch / decode unit 1722, an integer execution engine 1724, a floating-point execution engine 1726, and an L2 cache 1728. In at least one embodiment, the fetch / decode unit 1722 fetches instructions, decodes these instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 1724 and the floating-point execution engine 1726. In at least one embodiment, the fetch / decode unit 1722 may simultaneously dispatch one micro-instruction to the integer execution engine 1724 and another micro-instruction to the floating-point execution engine 1726. In at least one embodiment, the integer execution engine 1724 performs operations not limited to integer and memory operations. In at least one embodiment, the floating-point engine 1726 performs operations not limited to floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1722 dispatches micro-instructions to a single execution engine, which replaces both the integer execution engine 1724 and the floating-point execution engine 1726.

[0184] In at least one embodiment, each core 1720(i) can access an L2 cache 1728(i) included in core 1720(i), where i is an integer representing a specific instance of core 1720. In at least one embodiment, each core 1720 included in core complex 1710(j) is connected to other cores 1720 included in core complex 1710(j) via an L3 cache 1730(j) included in core complex 1710(j), where j is an integer representing a specific instance of core complex 1710. In at least one embodiment, a core 1720 included in core complex 1710(j) can access all L3 caches 1730(j) included in core complex 1710(j), where j is an integer representing a specific instance of core complex 1710. In at least one embodiment, the L3 cache 1730 may include, but is not limited to, any number of slices.

[0185] In at least one embodiment, the graphics complex 1740 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the graphics complex 1740 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the graphics complex 1740 is configured to perform graphics-independent operations. In at least one embodiment, the graphics complex 1740 is configured to perform both graphics-related and graphics-independent operations.

[0186] In at least one embodiment, the graphics complex 1740 includes, but is not limited to, any number of computing units 1750 and an L2 cache 1742. In at least one embodiment, the computing units 1750 share the L2 cache 1742. In at least one embodiment, the L2 cache 1742 is partitioned. In at least one embodiment, the graphics complex 1740 includes, but is not limited to, any number of computing units 1750 and any number (including zero) and type of cache. In at least one embodiment, the graphics complex 1740 includes, but is not limited to, any number of dedicated graphics hardware.

[0187] In at least one embodiment, each computing unit 1750 includes, but is not limited to, any number of SIMD units 1752 and shared memory 1754. In at least one embodiment, each SIMD unit 1752 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each computing unit 1750 may execute any number of thread blocks, but each thread block executes on a single computing unit 1750. In at least one embodiment, a thread block includes, but is not limited to, any number of execution threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1752 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process different datasets based on a single instruction set. In at least one embodiment, prediction can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 1754. In at least one embodiment, each computing unit 1750 includes one or more thread block clusters, wherein the thread block clusters can provide local programming control at a larger granularity than a single thread block of a single streaming multiprocessor (SM). In at least one embodiment, the thread block cluster (also referred to as a “cluster”) enables multiple thread blocks running concurrently across a streaming multiprocessor to synchronously and cooperatively acquire, exchange, or otherwise use data.

[0188] In at least one embodiment, structure 1760 is a system interconnect that facilitates data and control transfers across core complex 1710, graphics complex 1740, I / O interface 1770, memory controller 1780, display controller 1792, and multimedia engine 1794. In at least one embodiment, in addition to or instead of structure 1760, APU 1700 may also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of components that may be directly or indirectly linked, either internally or externally to APU 1700. In at least one embodiment, I / O interface 1770 represents any number and type of I / O interface (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1770. In at least one embodiment, the peripheral device coupled to the I / O interface 1770 may include, but is not limited to, a keyboard, mouse, printer, scanner, joystick or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0189] In at least one embodiment, the display controller 1792 displays images on one or more display devices (e.g., liquid crystal display (LCD) devices). In at least one embodiment, the multimedia engine 1794 includes, but is not limited to, any number and type of multimedia-related circuitry, such as video decoders, video encoders, image signal processors, etc. In at least one embodiment, the memory controller 1780 facilitates data transfer between the APU 1700 and the unified system memory 1790. In at least one embodiment, the core complex 1710 and the graphics complex 1740 share the unified system memory 1790.

[0190] In at least one embodiment, the APU 1700 implements a memory subsystem, including but not limited to any number and type of memory controllers 1780 and memory devices (e.g., shared memory 1754) that can be dedicated to a single component or shared among multiple components. In at least one embodiment, the APU 1700 implements a cache subsystem, including but not limited to one or more cache memories (e.g., L2 cache 1828, L3 cache 1730, and L2 cache 1742), each cache memory being component-private or shared among any number of components (e.g., core 1720, core complex 1710, SIMD unit 1752, compute unit 1750, and graphics complex 1740).

[0191] Figure 18A CPU 1800 according to at least one embodiment is illustrated. In at least one embodiment, the CPU 1800 was developed by AMD Inc. of Santa Clara, California. In at least one embodiment, the CPU 1800 can be configured to execute an application. In at least one embodiment, the CPU 1800 is configured to execute host control software, such as an operating system. In at least one embodiment, the CPU 1800 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1800 can be configured to execute host executable code derived from CUDA source code, and the external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 1800 includes, but is not limited to, any number of core complexes 1810, architectures 1860, I / O interfaces 1870, and memory controllers AMAD80.

[0192] In at least one embodiment, the core complex 1810 includes, but is not limited to, cores 1820(1)-1820(4) and L3 cache 1830. In at least one embodiment, the core complex 1810 may include, but is not limited to, any combination of any number of cores 1820 and any number and type of cache. In at least one embodiment, the cores 1820 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 1820 is a CPU core.

[0193] In at least one embodiment, each core 1820 includes, but is not limited to, a fetch / decode unit 1822, an integer execution engine 1824, a floating-point execution engine 1826, and an L2 cache 1828. In at least one embodiment, the fetch / decode unit 1822 fetches instructions, decodes these instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 1824 and the floating-point execution engine 1826. In at least one embodiment, the fetch / decode unit 1822 may simultaneously dispatch one micro-instruction to the integer execution engine 1824 and another micro-instruction to the floating-point execution engine 1826. In at least one embodiment, the integer execution engine 1824 performs operations not limited to integer and memory operations. In at least one embodiment, the floating-point engine 1826 performs operations not limited to floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1822 dispatches micro-instructions to a single execution engine, which replaces both the integer execution engine 1824 and the floating-point execution engine 1826.

[0194] In at least one embodiment, each core 1820(i) can access an L2 cache 1828(i) included in core 1820(i), where i is an integer representing a specific instance of core 1820. In at least one embodiment, each core 1820 included in core complex 1810(j) is connected to other cores 1820 in core complex 1810(j) via an L3 cache 1830(j) included in core complex 1810(j), where j is an integer representing a specific instance of core complex 1810. In at least one embodiment, a core 1820 included in core complex 1810(j) can access all L3 caches 1830(j) included in core complex 1810(j), where j is an integer representing a specific instance of core complex 1810. In at least one embodiment, the L3 cache 1830 may include, but is not limited to, any number of slices.

[0195] In at least one embodiment, structure 1860 is a system interconnect that facilitates data and control transfers across core complexes 1810(1)-1810(N) (where N is a positive integer), I / O interface 1870, and memory controller 1880. In at least one embodiment, in addition to or instead of structure 1860, CPU 1800 may also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of components that may be directly or indirectly linked, either inside or outside CPU 1800. In at least one embodiment, I / O interface 1870 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1870. In at least one embodiment, peripheral devices coupled to I / O interface 1870 may include, but are not limited to, displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0196] In at least one embodiment, memory controller 1880 facilitates data transfer between CPU 1800 and system memory 1890. In at least one embodiment, core complex 1810 and graphics complex 1840 share system memory 1890. In at least one embodiment, CPU 1800 implements a memory subsystem, which includes, but is not limited to, any number and type of memory controllers 1880 and memory devices that may be dedicated to a component or shared among multiple components. In at least one embodiment, CPU 1800 implements a cache subsystem, which includes, but is not limited to, one or more cache memories (e.g., L2 cache 1828 and L3 cache 1830), each cache memory may be component-private or shared among any number of components (e.g., core 1820 and core complex 1810).

[0197] Figure 19 An exemplary accelerator integration slice 1990 according to at least one embodiment is illustrated. As used herein, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services for multiple graphics processing engines among multiple graphics acceleration modules. Each graphics processing engine may comprise a separate GPU. Optionally, the graphics processing engine may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0198] The application's effective address space 1982 within system memory 1914 stores process element 1983. In one embodiment, process element 1983 is stored in response to a GPU call 1981 from an application 1980 executing on processor 1907. Process element 1983 contains the processing state of the corresponding application 1980. A job descriptor (WD) 1984 contained in process element 1983 may be a single job requested by the application or may contain pointers to job queues. In at least one embodiment, WD 1984 is a pointer to a job request queue in the application's effective address space 1982.

[0199] The graphics acceleration module 1946 and / or individual graphics processing engines may be shared by all or some processes in the system. In at least one embodiment, infrastructure may be included for establishing a processing state and sending WD 1984 to the graphics acceleration module 1946 to begin operation in a virtualized environment.

[0200] In at least one embodiment, a dedicated process programming model is used for implementation. In this model, a single process owns the graphics acceleration module 1946 or an individual graphics processing engine. Since the graphics acceleration module 1946 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and the operating system initializes the accelerator integrated circuit for the owned partition when the graphics acceleration module 1946 is allocated.

[0201] During operation, the WD fetch unit 1991 in the accelerator integrated slice 1990 fetches the next WD 1984, which includes instructions for the work to be performed by one or more graphics processing engines of the graphics acceleration module 1946. Data from the WD 1984 can be stored in register 1945 and used by the memory management unit (MMU) 1939, interrupt management circuitry 1947, and / or environment management circuitry 1948, as shown. For example, one embodiment of the MMU 1939 includes segment / page roaming circuitry for accessing segment / page tables 1986 within the OS virtual address space 1985. The interrupt management circuitry 1947 can handle interrupt events (INT) 1992 received from the graphics acceleration module 1946. When performing graph operations, the effective address 1993 generated by the graphics processing engine is translated into an actual address by the MMU 1939.

[0202] In one embodiment, the same register set 1945 is copied for each graphics processing engine and / or graphics acceleration module 1946 and can be initialized by the hypervisor or operating system. Each of these copied registers can be included in the accelerator integration slice 1990. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0203] Table 1 - Registers for Supervisor Initialization

[0204]

[0205] Table 2 shows exemplary registers that can be initialized by the operating system.

[0206] Table 2 - Operating System Initialization Registers

[0207] 1 Process and thread identification 2 Valid Address (EA) Environment Save / Restore Pointer 3 Virtual Address (VA) accelerator utilization record pointer 4 Virtual address (VA) stores segment table pointers 5 mask of authority 6 Job descriptor

[0208] In one embodiment, each WD 1984 is specific to a particular graphics acceleration module 1946 and / or a particular graphics processing engine. It contains all the information required for the graphics processing engine to perform its work or to do so, or it may be a pointer to a memory location where the application has established a command queue for the work to be done.

[0209] Figure 20A and Figure 20B An exemplary graphics processor according to at least one embodiment herein is illustrated. In at least one embodiment, any exemplary graphics processor may be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuitry may be included in at least one embodiment, including additional graphics processor / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is used within a System-on-a-Chip (SoC).

[0210] Figure 20A An exemplary graphics processor 2010 of a SoC integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 20B An additional exemplary graphics processor 2040 of a SoC integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 20A The graphics processor 2010 is a low-power graphics processor core. In at least one embodiment, Figure 20B The graphics processor 2040 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 2010, 2040 may be... Figure 15 A variant of the 1510 graphics processor.

[0211] In at least one embodiment, the graphics processor 2010 includes a vertex processor 2005 and one or more fragment processors 2015A-2015N (e.g., 2015A, 2015B, 2015C, 2015D to 2015N-1 and 2015N). In at least one embodiment, the graphics processor 2010 may execute different shader programs via separate logic, such that the vertex processor 2005 is optimized to perform operations for the vertex shader program, while one or more fragment processors 2015A-2015N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 2005 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, the fragment processors 2015A-2015N use the primitive and vertex data generated by the vertex processor 2005 to generate framebuffers for display on a display device. In at least one embodiment, the fragment processors 2015A-2015N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0212] In at least one embodiment, the graphics processor 2010 additionally includes one or more MMUs 2020A-2020B, caches 2025A-2025B, and circuit interconnects 2030A-2030B. In at least one embodiment, one or more MMUs 2020A-2020B provide a virtual-to-physical address mapping for the graphics processor 2010, including for the vertex processor 2005 and / or fragment processors 2015A-2015N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 2025A-2025B. In at least one embodiment, one or more MMUs 2020A-2020B can be synchronized with other MMUs within the system, including with... Figure 15 One or more application processors 1505, graphics processors 1515, and / or video processors 1520 are associated with one or more MMUs, such that each processor 1505-1520 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2030A-2030B enable the graphics processor 2010 to be connected to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0213] In at least one embodiment, the graphics processor 2040 includes Figure 20A The graphics processor 2010 includes one or more MMUs 2020A-2020B, caches 2025A-2025B, and circuit interconnects 2030A-2030B. In at least one embodiment, the graphics processor 2040 includes one or more shader cores 2055A-2055N (e.g., 2055A, 2055B, 2055C, 2055D, 2055E, 2055F, to 2055N-1 and 2055N) that provide a unified shader core architecture, wherein a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, the graphics processor 2040 includes an inter-core task manager 2045 that acts as a thread dispatcher to assign execution threads to one or more shader cores 2055A-2055N and tile units 2058 to accelerate tile-based rendering operations, wherein rendering operations of a scene are subdivided in image space, for example, to take advantage of local spatial consistency within the scene or to optimize the use of internal caches.

[0214] Figure 21AA graphics core 2100 according to at least one embodiment is shown. In at least one embodiment, the graphics core 2100 may include... Figure 15 The graphics processor 1510 is located within it. In at least one embodiment, the graphics core 2100 may be... Figure 20B The graphics core 2100 uses a unified shader core 2055A-2055N. In at least one embodiment, the graphics core 2100 includes a shared instruction cache 2102, texture units 2118, and cache / shared memory 2120, which are common to execution resources within the graphics core 2100. In at least one embodiment, the graphics core 2100 may include multiple slices 2101A-2101N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 2100. Slices 2101A-2101N may include supporting logic, including a local instruction cache 2104A-2104N, a thread scheduler 2106A-2106N, a thread dispatcher 2108A-2108N, and a set of registers 2110A-2110N. In at least one embodiment, slices 2101A-2101N may include a set of additional function units (AFU) 2112A-2112N, floating-point units (FPU) 2114A-2114N, integer arithmetic logic units (ALU) 2116A-2116N, address calculation units (ACU) 2113A-2113N, double-precision floating-point units (DPFPU) 2115A-2115N, and matrix processing units (MPU) 2117A-2117N. In at least one embodiment, graphics core 2100 is referred to as a computing unit or arithmetic unit.

[0215] In one embodiment, the FPU 2114A-2114N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 2115A-2115N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 2116A-2116N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 2117A-2117N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 2117A-2117N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated Generalized Matrix-to-Matrix Multiplication (GEMM). In at least one embodiment, the AFU 2112A-2112N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0216] Figure 21BA general-purpose graphics processing unit (GPGPU) 2130 is illustrated in at least one embodiment. In at least one embodiment, the GPGPU 2130 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, the GPGPU 2130 can be configured to enable highly parallel computational operations to be performed by a GPU array. In at least one embodiment, the GPGPU 2130 can be directly linked to other instances of the GPGPU 2130 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, the GPGPU 2130 includes a host interface 2132 for connection to a host processor. In at least one embodiment, the host interface 2132 is a PCIe interface. In at least one embodiment, the host interface 2132 can be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 2130 receives commands from the host processor and uses a global scheduler 2134 to assign execution threads associated with those commands to a set of computational clusters 2136A-2136H. In at least one embodiment, computing clusters 2136A-2136H share cache memory 2138. In at least one embodiment, cache memory 2138 can be used as an advanced cache of cache memory within computing clusters 2136A-2136H.

[0217] In at least one embodiment, the GPGPU 2130 includes memory 2144A-2144B coupled to computing clusters 2136A-2136H via a set of memory controllers 2142A-2142B. In at least one embodiment, memory 2144A-2144B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0218] In at least one embodiment, computing clusters 2136A-2136H each include a set of graphics cores, such as Figure 21A The graphics core 2100 may include various types of integer and floating-point logic units, capable of performing computational operations at various precisions, including computations suitable for CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 2136A-2136H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0219] In at least one embodiment, multiple instances of GPGPU 2130 can be configured to operate as a computing cluster. The computing clusters 2136A-2136H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, the multiple instances of GPGPU 2130 communicate via host interface 2132. In at least one embodiment, GPGPU 2130 includes an I / O hub 2139 that couples GPGPU 2130 to GPU link 2140, enabling direct connection to other instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a dedicated GPU-to-GPU bridge, enabling communication and synchronization among the multiple instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, the multiple instances of GPGPU 2130 reside in a separate data processing system and communicate via a network device accessible via host interface 2132. In at least one embodiment, GPU link 2140 may be configured to connect to a host processor, supplementing or replacing host interface 2132. In at least one embodiment, GPGPU 2130 may be configured to execute CUDA programs.

[0220] Figure 22A A parallel processor 2200 according to at least one embodiment is shown. In at least one embodiment, various components of the parallel processor 2200 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or FPGAs.

[0221] In at least one embodiment, the parallel processor 2200 includes a parallel processing unit 2202. In at least one embodiment, the parallel processing unit 2202 includes an I / O unit 2204 that enables communication with other devices, including other instances of the parallel processing unit 2202. In at least one embodiment, the I / O unit 2204 can be directly connected to other devices. In at least one embodiment, the I / O unit 2204 is connected to other devices using a hub or switch interface (e.g., a memory hub 2205). In at least one embodiment, the connection between the memory hub 2205 and the I / O unit 2204 forms a communication link. In at least one embodiment, the I / O unit 2204 is connected to a host interface 2206 and a memory crossbar switch 2216, wherein the host interface 2206 receives commands for performing processing operations, and the memory crossbar switch 2216 receives commands for performing memory operations.

[0222] In at least one embodiment, when host interface 2206 receives a command buffer via I / O unit 2204, host interface 2206 can direct work operations to execute those commands to front end 2208. In at least one embodiment, front end 2208 is coupled to scheduler 2210, which is configured to assign commands or other work items to processing array 2212. In at least one embodiment, scheduler 2210 ensures that processing array 2212 is correctly configured and in an active state before assigning tasks to processing array 2212. In at least one embodiment, scheduler 2210 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2210 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, enabling fast preemption and environment switching of threads executing on processing array 2212. In at least one embodiment, host software can demonstrate workloads scheduled on processing array 2212 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed on the processing array 2212 by the scheduler 2210 logic within the microcontroller, which includes the scheduler 2210.

[0223] In at least one embodiment, the processing array 2212 may include up to "N" processing clusters (e.g., clusters 2214A, 2214B to 2214N). In at least one embodiment, each cluster 2214A-2214N of the processing array 2212 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2210 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2214A-2214N of the processing array 2212, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2210, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing array 2212. In at least one embodiment, different clusters 2214A-2214N of the processing array 2212 may be assigned to process different types of programs or to perform different types of computations.

[0224] In at least one embodiment, the processing array 2212 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 2212 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing array 2212 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0225] In at least one embodiment, the processing array 2212 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 2212 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 2212 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2202 may transfer data from system memory via I / O unit 2204 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2222) and then written back to system memory.

[0226] In at least one embodiment, when the parallel processing unit 2202 is used to perform graph processing, the scheduler 2210 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 2214A-2214N of the processing array 2212. In at least one embodiment, portions of the processing array 2212 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2214A-2214N may be stored in a buffer to allow intermediate data to be transferred between the clusters 2214A-2214N for further processing.

[0227] In at least one embodiment, the processing array 2212 may receive processing tasks to be executed via a scheduler 2210, which receives commands defining the processing tasks from the front end 2208. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2210 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2208. In at least one embodiment, the front end 2208 may be configured to ensure that the processing array 2212 is configured to be active before initiating a workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0228] In at least one embodiment, each of one or more instances of the parallel processing unit 2202 may be coupled to the parallel processor memory 2222. In at least one embodiment, the parallel processor memory 2222 may be accessed via a memory crossbar switch 2216, which may receive memory requests from the processing array 2212 and the I / O unit 2204. In at least one embodiment, the memory crossbar switch 2216 may be accessed via a memory interface 2218. In at least one embodiment, the memory interface 2218 may include a plurality of partition units (e.g., partition units 2220A, 2220B to 2220N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2222. In at least one embodiment, the plurality of partition units 2220A-2220N are configured to be equal to the number of memory units, such that the first partition unit 2220A has a corresponding first memory unit 2224A, the second partition unit 2220B has a corresponding memory unit 2224B, and the Nth partition unit 2220N has a corresponding Nth memory unit 2224N. In at least one embodiment, the number of partition units 2220A-2220N may not be equal to the number of memory devices.

[0229] In at least one embodiment, memory cells 2224A-2224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2224A-2224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 2224A-2224N, allowing partitioning cells 2220A-2220N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2222. In at least one embodiment, local instances of the parallel processor memory 2222 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0230] In at least one embodiment, any of the clusters 2214A-2214N of the processing array 2212 can process data to be written to any memory cell 2224A-2224N within the parallel processor memory 2222. In at least one embodiment, the memory crossbar switch 2216 can be configured to transfer the output of each cluster 2214A-2214N to any partition cell 2220A-2220N or another cluster 2214A-2214N, and the clusters 2214A-2214N can perform further processing operations on the output. In at least one embodiment, each cluster 2214A-2214N can communicate with the memory interface 2218 via the memory crossbar switch 2216 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 2216 has a connection to the memory interface 2218 for communication with the I / O unit 2204, and a connection to a local instance of the parallel processor memory 2222, thereby enabling processing units within different processing clusters 2214A-2214N to communicate with system memory or other memory not local to the parallel processing unit 2202. In at least one embodiment, the memory crossbar switch 2216 may use virtual channels to separate traffic flows between clusters 2214A-2214N and partition units 2220A-2220N.

[0231] In at least one embodiment, multiple instances of the parallel processing unit 2202 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2202 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2202 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 2202 or the parallel processor 2200 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0232] Figure 22B A processing cluster 2294 according to at least one embodiment is illustrated. In at least one embodiment, the processing cluster 2294 is included within a parallel processing unit. In at least one embodiment, the processing cluster 2294 is... Figure 22AAn instance of one of the processing clusters 2214A-2214N. In at least one embodiment, the processing cluster 2294 can be configured to execute a number of threads in parallel, wherein the term "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster 2294.

[0233] In at least one embodiment, the operation of the processing cluster 2294 can be controlled by a pipeline manager 2232 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2232... Figure 22A The scheduler 2210 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2234 and / or texture unit 2236. In at least one embodiment, the graphics multiprocessor 2234 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2294 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2294 may include one or more instances of the graphics multiprocessor 2234. In at least one embodiment, the graphics multiprocessor 2234 can process data, and the data crossover switch 2240 can be used to distribute the processed data to one of a number of possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2232 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossover switch 2240.

[0234] In at least one embodiment, each graphics multiprocessor 2234 within the processing cluster 2294 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units (LSUs), etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0235] In at least one embodiment, instructions sent to the processing cluster 2294 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes programs on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2234. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2234. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2234. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2234, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2234.

[0236] In at least one embodiment, the graphics multiprocessor 2234 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2234 may forgo the internal cache and use a cache memory within the processing cluster 2294 (e.g., L1 cache 2248). In at least one embodiment, each graphics multiprocessor 2234 may also access partition units (e.g., Figure 22A The L2 cache is located within partition units 2220A-2220N, which are shared among all processing clusters 2294 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2234 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2202 can be used as global memory. In at least one embodiment, the processing cluster 2294 includes multiple instances of the graphics multiprocessor 2234, which can share common instructions and data that can be stored in the L1 cache 2248.

[0237] In at least one embodiment, each processing cluster 2294 may include an MMU 2245 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2245 may reside in Figure 22AThe memory interface 2218 is located within the MMU 2245. In at least one embodiment, the MMU 2245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more information about tiles is discussed) and optionally to cache line indices. In at least one embodiment, the MMU 2245 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 2234, the L1 cache 2248, or the processing cluster 2294. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0238] In at least one embodiment, the processing cluster 2294 can be configured such that each graphics multiprocessor 2234 is coupled to a texture unit 2236 to perform texture mapping operations, which may involve determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2234, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2234 outputs a processed task to a data crossbar switch 2240 to provide the processed task to another processing cluster 2294 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 2216. In at least one embodiment, a pre-raster operation unit (preROP) 2242 is configured to receive data from the graphics multiprocessor 2234 and direct the data to a ROP unit, which may be associated with a partitioning unit (e.g., as described herein) Figure 22A The PreROP 2242 unit is located together with the partitioning units 2220A-2220N. In at least one embodiment, the PreROP 2242 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0239] Figure 22C A graphics multiprocessor 2296 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2296 is... Figure 22BThe graphics multiprocessor 2234 is included. In at least one embodiment, the graphics multiprocessor 2296 is coupled to the pipeline manager 2232 of the processing cluster 2294. In at least one embodiment, the graphics multiprocessor 2296 has an execution pipeline including, but not limited to, an instruction cache 2252, an instruction unit 2254, an address mapping unit 2256, a register file 2258, one or more GPGPU cores 2262, and one or more LSUs 2266. The GPGPU cores 2262 and LSUs 2266 are coupled to cache memory 2272 and shared memory 2270 via memory and cache interconnect 2268.

[0240] In at least one embodiment, instruction cache 2252 receives a stream of instructions to be executed from pipeline manager 2232. In at least one embodiment, instructions are cached in instruction cache 2252 and dispatched to instruction unit 2254 for execution. In one embodiment, instruction unit 2254 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread of the thread group to a different execution unit within GPGPU core 2262. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2256 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by LSU 2266.

[0241] In at least one embodiment, register file 2258 provides a set of registers for functional units of graphics multiprocessor 2296. In at least one embodiment, register file 2258 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 2296 (e.g., GPGPU core 2262, LSU 2266). In at least one embodiment, register file 2258 is partitioned among each functional unit, such that a dedicated portion of register file 2258 is allocated to each functional unit. In at least one embodiment, register file 2258 is partitioned among different thread groups being executed by graphics multiprocessor 2296.

[0242] In at least one embodiment, each of the GPGPU cores 2262 may include an FPU and / or an ALU for executing instructions of the graph multiprocessor 2296. The GPGPU cores 2262 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2208 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2296 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2262 may also include fixed-function or special-function logic.

[0243] In at least one embodiment, the GPGPU core 2262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2262 can physically execute SIMD4, SIMD8, and SIMD9 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0244] In at least one embodiment, the memory and cache interconnect 2268 is an interconnect network connecting each functional unit of the graphics multiprocessor 2296 to the register file 2258 and the shared memory 2270. In at least one embodiment, the memory and cache interconnect 2268 is a cross-switch interconnect that allows the LSU 2266 to perform load and store operations between the shared memory 2270 and the register file 2258. In at least one embodiment, the register file 2258 can operate at the same frequency as the GPGPU core 2262, resulting in very low latency for data transfer between the GPGPU core 2262 and the register file 2258. In at least one embodiment, the shared memory 2270 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 2296. In at least one embodiment, the cache memory 2272 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 2236. In at least one embodiment, the shared memory 2270 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in cache memory 2272, the thread executing on GPGPU core 2262 can also programmatically store data in shared memory.

[0245] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to the host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0246] Figure 23A graphics processor 2300 according to at least one embodiment is illustrated. In at least one embodiment, the graphics processor 2300 includes a ring interconnect 2302, a pipeline front end 2304, a media engine 2337, and graphics cores 2380A-2380N. In at least one embodiment, the ring interconnect 2302 couples the graphics processor 2300 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2300 is one of many processors integrated within a multi-core processing system.

[0247] In at least one embodiment, the graphics processor 2300 receives multiple batches of commands via a ring interconnect 2302. In at least one embodiment, the input commands are interpreted by a command stream converter 2303 in a pipeline front-end 2304. In at least one embodiment, the graphics processor 2300 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 2380A-2380N. In at least one embodiment, for 3D geometry processing commands, the command stream converter 2303 provides commands to the geometry pipeline 2336. In at least one embodiment, for at least some media processing commands, the command stream converter 2303 provides commands to a video front-end 2334, which is coupled to a media engine 2337. In at least one embodiment, the media engine 2337 includes a video quality engine (VQE) 2330 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 2333 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2336 and the media engine 2337 each generate an execution thread for the thread execution resources provided by at least one graphics core 2380A.

[0248] In at least one embodiment, the graphics processor 2300 includes scalable thread execution resources characterized by modular graphics cores 2380A-2380N (sometimes referred to as core slices), each modular core having multiple sub-cores 2350A-2350N, 2360A-2360N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2300 may have any number of graphics cores 2380A to 2380N. In at least one embodiment, the graphics processor 2300 includes a graphics core 2380A having at least a first sub-core 2350A and a second sub-core 2360A. In at least one embodiment, the graphics processor 2300 is a low-power processor having a single sub-core (e.g., 2350A). In at least one embodiment, the graphics processor 2300 includes multiple graphics cores 2380A-2380N, each graphics core including a set of first sub-cores 2350A-2350N and a set of second sub-cores 2360A-2360N. In at least one embodiment, each of the first sub-cores 2350A-2350N includes at least a first set of execution units (EUs) 2352A-2352N and media / texture samplers 2354A-2354N. In at least one embodiment, each of the second sub-cores 2360A-2360N includes at least a second set of execution units 2362A-2362N and samplers 2364A-2364N. In at least one embodiment, each sub-core 2350A-2350N and 2360A-2360N shares a set of shared resources 2370A-2370N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0249] Figure 24 A processor 2400 is illustrated according to at least one embodiment. In at least one embodiment, the processor 2400 may include, but is not limited to, logic circuitry for executing instructions. In at least one embodiment, the processor 2400 can execute instructions, including x86 instructions, ARM instructions, special-purpose instructions for ASICs, etc. In at least one embodiment, the processor 2410 may include registers for storing packaged data, such as the 64-bit wide MMX™ registers in an Intel microprocessor enabled by MMX technology in Santa Clara, California. In at least one embodiment, the MMX registers available in integer and floating-point forms can operate with packaged data elements accompanied by SIMD and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, the processor 2410 can execute instructions to accelerate CUAD programs.

[0250] In at least one embodiment, processor 2400 includes an ordered front end (“front end”) 2401 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 2401 may include several units. In at least one embodiment, instruction prefetcher 2426 fetches instructions from memory and provides the instructions to instruction decoder 2428, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2428 decodes the received instructions into one or more operations, so-called “micro-instructions” or “micro-operations” (also referred to as “micro-operations” or “micro-instructions”), for execution. In at least one embodiment, instruction decoder 2428 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform the operations. In at least one embodiment, trace cache 2430 may assemble the decoded micro-instructions into a program-ordered sequence or trace in micro-instruction queue 2434 for execution. In at least one embodiment, when trace cache 2430 encounters complex instructions, microcode ROM 2432 provides the micro-instructions required to complete the operation.

[0251] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 2428 may access the microcode ROM 2432 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 2428. In at least one embodiment, if multiple micro-instructions are required to complete an operation, the instructions may be stored in the microcode ROM 2432. In at least one embodiment, the trace cache 2430 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2432 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2432 has completed the micro-operation ordering of the instructions, the machine front end 2401 may resume fetching micro-operations from the trace cache 2430.

[0252] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2403 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. The out-of-order execution engine 2403 includes, but is not limited to, an allocator / register renamer 2440, a memory microinstruction queue 2442, an integer / floating-point microinstruction queue 2444, a memory scheduler 2446, a fast scheduler 2402, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2404, and a simple floating-point scheduler (“simple FP scheduler”) 2406. In at least one embodiment, the fast scheduler 2402, the slow / general-purpose floating-point scheduler 2404, and the simple floating-point scheduler 2406 are also collectively referred to as “microinstruction schedulers 2402, 2404, 2406”. The allocator / register renamer 2440 allocates the machine buffers and resources required for the sequential execution of each microinstruction. In at least one embodiment, the allocator / register renamer 2440 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2440 also assigns entries for each microinstruction in one of two microinstruction queues, memory microinstruction queue 2442 for memory operations and integer / floating-point microinstruction queue 2444 for non-memory operations, preceding the memory scheduler 2446 and microinstruction schedulers 2402, 2404, and 2406. In at least one embodiment, the microinstruction schedulers 2402, 2404, and 2406 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2402 of at least one embodiment can schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 2404 and the simple floating-point scheduler 2406 can schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 2402, 2404, and 2406 arbitrate the scheduling port to schedule microinstructions for execution.

[0253] In at least one embodiment, execution block 2411 includes, but is not limited to, integer register file / tribute network 2408, floating-point register file / tribute network (“FP register file / tribute network”) 2410, address generation units (“AGU”) 2412 and 2414, fast arithmetic logic units (“fast ALU”) 2416 and 2418, slow ALU 2420, floating-point ALU (“FP”) 2422, and floating-point movement unit (“FP movement”) 2424. In at least one embodiment, integer register file / tribute network 2408 and floating-point register file / bypass network 2410 are also referred to herein as “register files 2408, 2410”. In at least one embodiment, AGUS 2412 and 2414, fast ALU 2416 and 2418, slow ALU 2420, floating-point ALU 2422, and floating-point movement unit 2424 are also referred to herein as "execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424". In at least one embodiment, the execution block may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0254] In at least one embodiment, register files 2408, 2410 may be arranged between microinstruction schedulers 2402, 2404, 2406 and execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424. In at least one embodiment, integer register file / tribute network 2408 performs integer operations. In at least one embodiment, floating-point register file / tribute network 2410 performs floating-point operations. In at least one embodiment, each of register files 2408, 2410 may include, but is not limited to, a tribute network that can bypass or forward recently completed results not yet written to the register file to a new dependent object. In at least one embodiment, register files 2408, 2410 may communicate data with each other. In at least one embodiment, integer register file / tribute network 2408 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / branch network 2410 may include, but is not limited to, entries with a width of 128 bits, since floating-point instructions typically have operands with a width of 64 to 128 bits.

[0255] In at least one embodiment, execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424 can execute instructions. In at least one embodiment, register files 2408 and 2410 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2400 may include, but is not limited to, any number of execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424, and combinations thereof. In at least one embodiment, floating-point ALU 2422 and floating-point move unit 2424 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2422 may include, but is not limited to, a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to the fast ALUs 2416 and 2418. In at least one embodiment, the fast ALUs 2416 and 2418 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to the slow ALU 2420, because the slow ALU 2420 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by the ALUs 2412 and 2414. In at least one embodiment, the fast ALUs 2416, 2418, and 2420 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALUs 2416, 2418, and 2420 can be implemented to support various data bit sizes, including 16, 32, 128, 256, etc. In at least one embodiment, the floating-point ALU 2422 and the floating-point movement unit 2424 can be implemented to support a range of operands with various bit widths. In at least one embodiment, the floating-point ALU 2422 and the floating-point movement unit 2424 can operate on 128-bit wide packaged data operands in conjunction with SIMD and multimedia instructions.

[0256] In at least one embodiment, microinstruction schedulers 2402, 2404, and 2406 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 2400, processor 2400 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences used for text string comparison operations.

[0257] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction that identifies operands. In at least one embodiment, a register may be one that can be used externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0258] Figure 25 A processor 2500 according to at least one embodiment is illustrated. In at least one embodiment, the processor 2500 includes, but is not limited to, one or more processor cores (cores) 2502A-2502N, an integrated memory controller 2514, and an integrated graphics processor 2508. In at least one embodiment, the processor 2500 may include additional cores up to and including additional processor cores 2502N, indicated by dashed boxes. In at least one embodiment, each processor core 2502A-2502N includes one or more internal cache units 2504A-2504N. In at least one embodiment, each processor core may also access one or more units 2506 of a shared cache. In at least one embodiment, one or more processor cores 2502A-2502N are referred to as one or more computing units or arithmetic units.

[0259] In at least one embodiment, internal cache units 2504A-2504N and shared cache unit 2506 represent a cache memory hierarchy within processor 2500. In at least one embodiment, cache memory units 2504A-2504N may include at least one level of instruction and data within each processor core, and one or more levels of cache in a shared intermediate cache, such as L2, L3, L4, or other levels of cache, wherein the highest level of cache is classified as LLC before external memory. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2506 and 2504A-2504N.

[0260] In at least one embodiment, the processor 2500 may further include a group of one or more bus controller units 2516 and a system agent core 2510. In at least one embodiment, one or more bus controller units 2516 manage a group of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2510 provides management functions for various processor components. In at least one embodiment, the system agent core 2510 includes one or more integrated memory controllers 2514 to manage access to various external memory devices (not shown).

[0261] In at least one embodiment, one or more processor cores 2502A-2502N include support for multi-threaded concurrent processing. In at least one embodiment, system agent core 2510 includes components for coordinating and operating processor cores 2502A-2502N during multi-threaded processing. In at least one embodiment, system agent core 2510 may additionally include a power control unit (PCU) including logic and components for regulating one or more power states of processor cores 2502A-2502N and graphics processor 2508.

[0262] In at least one embodiment, processor 2500 further includes graphics processor 2508 to perform graphics processing operations. In at least one embodiment, graphics processor 2508 is coupled to a shared cache unit 2506 and a system proxy core 2510 including one or more integrated memory controllers 2514. In at least one embodiment, system proxy core 2510 further includes a display controller 2511 for driving graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2511 may also be a separate module coupled to graphics processor 2508 via at least one interconnect, or it may be integrated within graphics processor 2508.

[0263] In at least one embodiment, ring-based interconnect unit 2512 is used to couple internal components of processor 2500. In at least one embodiment, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, graphics processor 2508 is coupled to ring interconnect 2512 via I / O link 2513.

[0264] In at least one embodiment, I / O link 2513 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory module 2518 (e.g., eDRAM module). In at least one embodiment, each of processor cores 2502A-2502N and graphics processor 2508 uses embedded memory module 2518 as a shared LLC.

[0265] In at least one embodiment, processor cores 2502A-2502N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2502A-2502N are heterogeneous in terms of the ISA, with one or more processor cores 2502A-2502N executing a common instruction set, while one or more other processor cores 2502A-2502N execute a common instruction set or a subset of a different instruction set. In at least one embodiment, processor cores 2502A-2502N are heterogeneous in terms of microarchitecture, with one or more cores having relatively high power consumption coupled to one or more power cores having lower power consumption. In at least one embodiment, processor 2500 can be implemented on one or more chips or implemented as a SoC integrated circuit.

[0266] Figure 26 A graphics processing unit (GPU) core 2600 according to at least one embodiment described is illustrated. In at least one embodiment, the GPU core 2600 is included within a GPU core array. In at least one embodiment, the GPU core 2600 (sometimes referred to as a core slice) may be one or more GPU cores within a modular GPU. In at least one embodiment, the GPU core 2600 is an example of a GPU core slice, and the GPU described herein may include multiple GPU core slices based on target power and performance envelopes. In at least one embodiment, each GPU core 2600 may include a fixed-function block 2630, also referred to as a sub-slice, coupled to a plurality of sub-cores 2601A-2601F, which includes modules of general-purpose and fixed-function logic.

[0267] In at least one embodiment, the fixed-function block 2630 includes a geometry / fixed-function pipeline 2636, which, for example, may be shared by all sub-cores of the graphics processor 2600 in a lower-performance and / or lower-power graphics processor implementation. In at least one embodiment, the geometry / fixed-function pipeline 2636 includes a 3D fixed-function pipeline, a video front-end unit, a thread generator and a thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0268] In at least one embodiment, fixed function block 2630 further includes a graphics SoC interface 2637, a graphics microcontroller 2638, and a media pipeline 2639. The graphics SoC interface 2637 provides an interface between the graphics core 2600 and other processor cores in the SoC integrated circuit system. In at least one embodiment, the graphics microcontroller 2638 is a programmable subprocessor configurable to manage various functions of the graphics processor 2600, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 2639 includes logic that facilitates decoding, encoding, preprocessing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 2639 implements media operations via requests for computation or sampling logic within subcores 2601-2601F.

[0269] In at least one embodiment, the SoC interface 2637 enables the graphics core 2600 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2637 also enables communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enables the use and / or implementation of global memory atoms that can be shared between the graphics core 2600 and the CPU within the SoC. In at least one embodiment, the SoC interface 2637 also implements power management control for the graphics core 2600 and enables interfacing between the clock domain of the graphics core 2600 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2637 enables the receipt of command buffers from a command stream converter and a global thread dispatcher, configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, when a media operation is to be performed, commands and instructions can be dispatched to media pipeline 2639, or when a graph processing operation is to be performed, they can be assigned to geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 2636, geometry and fixed function pipeline 2614).

[0270] In at least one embodiment, the graphics microcontroller 2638 can be configured to perform various scheduling and management tasks on the graphics core 2600. In at least one embodiment, the graphics microcontroller 2638 can perform graph and / or computation workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 2602A-2602F, 2604A-2604F in the sub-cores 2601A-2601F. In at least one embodiment, host software executing on the CPU core of the SoC including the graphics core 2600 can submit a workload of one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload should be run next, submitting the workload to a command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, the graphics microcontroller 2638 may also facilitate a low-power or idle state of the graphics core 2600, thereby providing the graphics core 2600 with the ability to save and restore registers across low-power state transitions within the graphics core 2600, independent of the operating system and / or the graphics driver software on the system.

[0271] In at least one embodiment, the graphics core 2600 may have more or fewer subcores than the illustrated subcores 2601A-2601F, up to N modular subcores. For each group of N subcores, in at least one embodiment, the graphics core 2600 may further include shared functional logic 2610, shared and / or cache memory 2612, geometry / fixed-function pipeline 2614, and additional fixed-function logic 2616 to accelerate various graphics and computational processing operations. In at least one embodiment, the shared functional logic 2610 may include logic units (e.g., samplers, mathematical and / or inter-thread communication logic) that can be shared by each of the N subcores within the graphics core 2600. The shared and / or cache memory 2612 may be an LLC of the N subcores 2601A-2601F within the graphics core 2600, and may also be used as shared memory accessible by multiple subcores. In at least one embodiment, a geometry / fixed function pipeline 2614 may be included to replace the geometry / fixed function pipeline 2636 within the fixed function block 2630, and may include the same or similar logic units.

[0272] In at least one embodiment, the graphics core 2600 includes additional fixed-function logic 2616, which may include various fixed-function acceleration logics for use by the graphics core 2600. In at least one embodiment, the additional fixed-function logic 2616 includes additional geometry pipelines for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and in the full geometry pipeline and culling pipeline within the geometry / fixed-function pipelines 2616, 2636, it is an additional geometry pipeline that can be included in the additional fixed-function logic 2616. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of the application, each with a separate environment. In at least one embodiment, position-only shading can hide long culling runs of discarded triangles, thereby allowing shading to be completed earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed-function logic 2616 can execute the position shader in parallel with the main application and typically generates critical results faster than the full pipeline because the culling pipeline acquires and occludes the positional attributes of vertices without performing rasterization and rendering pixels to the framebuffer. In at least one embodiment, the culling pipeline can use the generated critical results to compute visibility information for all triangles, regardless of whether those triangles were culled. In at least one embodiment, the full pipeline (which may be referred to as the replay pipeline in this case) can consume visibility information to skip culled triangles and only occlude the visible triangles that are ultimately passed to the rasterization stage.

[0273] In at least one embodiment, the additional fixed-function logic 2616 may also include general target processing acceleration logic, such as fixed-function matrix multiplication logic, for implementing a decelerated CUAD program.

[0274] In at least one embodiment, each graphics subcore 2601A-2601F includes a set of execution resources that can be used to perform graph, media, and computational operations in response to requests from the graphics pipeline, media pipeline, or shader program. In at least one embodiment, the graphics subcore 2601A-2601F includes multiple EU arrays 2602A-2602F, 2604A-2604F, thread dispatch and inter-thread communication (TD / IC) logic 2603A-2603F, 3D (e.g., texture) samplers 2605A-2605F, media samplers 2606A-2606F, shader processors 2607A-2607F, and shared local memory (SLM) 2608A-2608F. Each of the EU arrays 2602A-2602F and 2604A-2604F contains multiple execution units, which are GUGPUs capable of servicing graphics, media, or computational operations, performing floating-point and integer / fixed-point logic operations, including graphics, media, or computational shader programs. In at least one embodiment, the TD / IC logic 2603A-2603F performs local thread dispatch and thread control operations for the execution units within the subcore and facilitates communication between threads executing on the execution units of the subcore. In at least one embodiment, the 3D samplers 2605A-2605F can read data associated with textures or other 3D graphics into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the sampling state and texture format configured and associated with a given texture. In at least one embodiment, the media samplers 2606A-2606F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics subcore 2601A-2601F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each subcore 2601A-2601F may utilize shared local memory 2608A-2608F within each subcore, enabling threads executing within a thread group to use a common pool of on-chip memory for execution.

[0275] Figure 27A parallel processing unit (“PPU”) 2700 according to at least one embodiment is illustrated. In at least one embodiment, the PPU 2700 is configured with machine-readable code that, if executed by the PPU 2700, causes the PPU 2700 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 2700 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multi-threading as a latency-hiding technique designed to process computer-readable instructions (also known as machine-readable instructions or simple instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of an instruction set configured to be executed by the PPU 2700. In at least one embodiment, the PPU 2700 is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data to generate two-dimensional (“2D”) image data for display on a display device, such as an LCD device. In at least one embodiment, the PPU 2700 is used to perform computations, such as linear algebra operations and machine learning operations. Figure 27 An example parallel processor is shown for illustrative purposes only and should be interpreted as a non-limiting example of a processor architecture implemented in at least one embodiment.

[0276] In at least one embodiment, one or more PPUs 2700 are configured to accelerate high-performance computing (“HPC”), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2700 are configured to accelerate CUDA programs. In at least one embodiment, the PPU 2700 includes, but is not limited to, I / O unit 2706, front-end unit 2710, scheduler unit 2712, job allocation unit 2714, hub 2716, crossbar switch (“Xbar”) 2720, one or more general-purpose processing clusters (“GPC”) 2718, and one or more partitioning units (“memory partitioning units”) 2722. In at least one embodiment, the PPU 2700 is connected to a host processor or other PPU 2700 via one or more high-speed GPU interconnects (“GPU interconnects”) 2708. In at least one embodiment, the PPU 2700 is connected to a host processor or other peripheral device via interconnect 2702. In one embodiment, the PPU 2700 is connected to local memory including one or more memory devices (“memory”) 2704. In at least one embodiment, the memory device 2704 includes, but is not limited to, one or more dynamic random access memory (“DRAM”) devices. In at least one embodiment, the one or more DRAM devices are configured and / or configurable as a high bandwidth memory (“HBM”) subsystem, and multiple DRAM dies are stacked within each device.

[0277] In at least one embodiment, the high-speed GPU interconnect 2708 may refer to a wire-based multi-channel communication link used by the system for scaling, and includes one or more PPUs 2700s (“CPUs”) coupled with one or more CPUs, supporting cache coherency between the PPUs 2700s and the CPUs, as well as CPU master control. In at least one embodiment, the high-speed GPU interconnect 2708 transmits data and / or commands to other units of the PPU 2700, such as one or more copy engines, video encoders, video decoders, power management units, and / or other components, via a hub 2716. Figure 27 Other components that may not be explicitly shown.

[0278] In at least one embodiment, the I / O unit 2706 is configured to access the host processor via the system bus 2702. Figure 27 (Not shown) Sending and receiving communications (e.g., commands, data). In at least one embodiment, I / O unit 2706 communicates directly with the host processor via system bus 2702 or via one or more intermediate devices (e.g., memory bridges). In at least one embodiment, I / O unit 2706 may communicate with one or more other processors (e.g., one or more PPUs 2700) via system bus 2702. In at least one embodiment, I / O unit 2706 implements a PCIe interface for communication via the PCIe bus. In at least one embodiment, I / O unit 2706 implements an interface for communication with external devices.

[0279] In at least one embodiment, I / O unit 2706 decodes packets received via system bus 2702. In at least one embodiment, at least some packets represent commands configured to cause PPU 2700 to perform various operations. In at least one embodiment, I / O unit 2706 sends the decoded commands to various other units of PPU 2700 as specified by the commands. In at least one embodiment, the commands are sent to front-end unit 2710 and / or to hub 2716 or other units of PPU 2700, such as one or more copy engines, video encoders, video decoders, power management units, etc. Figure 27 (Not explicitly shown in the text). In at least one embodiment, I / O unit 2706 is configured to route communication between various logical units of PPU 2700.

[0280] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPU 2700 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is a region in memory accessible (e.g., read / write) by both the host processor and the PPU 2700—the host interface unit can be configured to access a buffer in system memory connected to the system bus 2702 via memory requests transmitted through the system bus 2702 via the I / O unit 2706. In at least one embodiment, the host processor writes a command stream to the buffer and then sends a pointer indicating the start of the command stream to the PPU 2700, causing the front-end unit 2710 to receive pointers to one or more command streams and manage one or more command streams, read commands from the command streams, and forward the commands to the respective units of the PPU 2700.

[0281] In at least one embodiment, front-end unit 2710 is coupled to scheduler unit 2712, which configures various GPCs 2718 to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit 2712 is configured to track status information related to the various tasks managed by scheduler unit 2712, wherein the status information may indicate which GPC 2718 a task is assigned to, whether the task is active or inactive, the priority associated with the task, etc. In at least one embodiment, scheduler unit 2712 manages multiple tasks executed on one or more GPCs 2718.

[0282] In at least one embodiment, scheduler unit 2712 is coupled to job allocation unit 2714, which is configured to dispatch tasks for execution on GPC 2718. In at least one embodiment, job allocation unit 2714 tracks multiple scheduled tasks received from scheduler unit 2712 and manages a pool of pending tasks and an active task pool for each GPC 2718. In at least one embodiment, the pool of pending tasks includes multiple time slots (e.g., 32 time slots) containing tasks assigned to a particular GPC 2718; the active task pool may include multiple time slots (e.g., 4 time slots) for tasks actively processed by GPC 2718, such that as one of the GPCs 2718 completes its execution, that task is evicted from the active task pool of the GPC 2718, and one of other tasks is selected from the pool of pending tasks and scheduled for execution on the GPC 2718. In at least one embodiment, if an active task is idle on GPC 2718, for example while waiting for data dependencies to be resolved, the active task is evicted from GPC 2718 and returned to the pool of pending tasks, while another task in the pool of pending tasks is selected and scheduled to be executed on GPC 2718.

[0283] In at least one embodiment, the work allocation unit 2714 communicates with one or more GPCs 2718 via XBar 2720. In at least one embodiment, XBar 2720 is an interconnect network that couples a plurality of units of PPU 2700 to other units of PPU 2700, and can be configured to couple the work allocation unit 2714 to a specific GPC 2718. In at least one embodiment, other units of one or more PPUs 2700 can also be connected to XBar 2720 via hub 2716.

[0284] In at least one embodiment, tasks are managed by scheduler unit 2712 and assigned to one of GPCs 2718 by job allocation unit 2714. GPCs 2718 are configured to process tasks and produce results. In at least one embodiment, results may be consumed by other tasks in GPCs 2718, routed to different GPCs 2718 via XBar 2720, or stored in memory 2704. In at least one embodiment, results may be written to memory 2704 via partitioning unit 2722, which implements a memory interface for writing data to or reading data from memory 2704. In at least one embodiment, results may be transferred to another PPU 2700 or CPU via high-speed GPU interconnect 2708. In at least one embodiment, the PPU 2700 includes, but is not limited to, U partitioning units 2722, which is equal to the number of separate and distinct memory devices 2704 coupled to the PPU 2700.

[0285] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2700. In one embodiment, multiple computing applications are executed concurrently by the PPU 2700, and the PPU 2700 provides isolation, Quality of Service (“QoS”), and independent address spaces for the multiple computing applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 2700, and the driver core outputs the tasks to one or more streams processed by the PPU 2700. In at least one embodiment, each task includes one or more associated thread groups, which may be referred to as a warp. In at least one embodiment, a warp includes multiple associated threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a cooperating thread may refer to multiple threads, including instructions for performing tasks and exchanging data via shared memory.

[0286] Figure 28 A GPC 2800 according to at least one embodiment is illustrated. In at least one embodiment, the GPC 2800 is Figure 27The GPC 2718. In at least one embodiment, each GPC 2800 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2800 includes, but is not limited to, a pipeline manager 2802, a pre-raster operation unit (“PROP”) 2804, a raster engine 2808, a work assignment crossbar switch (“WDX”) 2816, a memory management unit (“MMU”) 2818, one or more data processing clusters (“DPC”) 2806, and any suitable combination of components.

[0287] In at least one embodiment, the operation of GPC 2800 is controlled by pipeline manager 2802. In at least one embodiment, pipeline manager 2802 manages the configuration of one or more DPCs 2806 to handle tasks assigned to GPC 2800. In at least one embodiment, pipeline manager 2802 configures at least one of one or more DPCs 2806 to implement at least a portion of the graphics rendering pipeline. In at least one embodiment, DPC 2806 is configured to execute vertex shader programs on programmable streaming multiprocessor (“SM”) 2814. In at least one embodiment, pipeline manager 2802 is configured to route packets received from the work allocation unit to appropriate logic units within GPC 2800, and in at least one embodiment, some packets may be routed to fixed-function hardware units in PROP 2804 and / or raster engine 2808, while other packets may be routed to DPC 2806 for processing by raw engine 2812 or SM 2814. In at least one embodiment, pipeline manager 2802 configures at least one of DPCs 2806 to implement a neural network model and / or computation pipeline. In at least one embodiment, pipeline manager 2802 configures at least one of DPCs 2806 to execute at least a portion of a CUDA program.

[0288] In at least one embodiment, the PROP unit 2804 is configured to route data generated by the raster engine 2808 and DPC 2806 to the raster operation (“ROP”) unit in the partition unit, for example, in conjunction with the above. Figure 27Memory partitioning unit 2722, etc., are described in more detail. In at least one embodiment, PROP unit 2804 is configured to perform optimizations for color blending, organize pixel data, perform address translation, etc. In at least one embodiment, raster engine 2808 includes, but is not limited to, multiple fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, raster engine 2808 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are transmitted to the coarse raster engine to generate coverage information of basic primitives (e.g., x, y coverage masks of tiles); the output of the coarse raster engine is transmitted to the culling engine, in which fragments associated with primitives that fail the z-test are culled, and transmitted to the clipping engine, in which fragments located outside the view frustum are clipped. In at least one embodiment, the cropped and culled fragments are passed to a fine raster engine to generate properties of the pixel fragments based on a planar equation generated by the settings engine. In at least one embodiment, the output of the raster engine 2808 includes fragments that will be processed by any suitable entity (e.g., by a fragment shader implemented within the DPC 2806).

[0289] In at least one embodiment, each DPC 2806 included in the GPC 2800 includes, but is not limited to, an M-pipeline controller (“MPC”) 2810; a primitive engine 2812; one or more SMs 2814; and any suitable combination thereof. In at least one embodiment, the MPC 2810 controls the operation of the DPC 2806, routing packets received from the pipeline manager 2802 to the appropriate units within the DPC 2806. In at least one embodiment, packets associated with vertices are routed to the primitive engine 2812, which is configured to retrieve vertex attributes associated with vertices from memory; conversely, packets associated with shader programs may be sent to the SM 2814.

[0290] In at least one embodiment, the SM 2814 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, the SM 2814 is multithreaded and configured to execute multiple threads (e.g., 32 threads) from a specific thread group concurrently, and implements a Single Instruction, Multiple Data (“SIMD”) architecture, wherein each thread in a group of threads (e.g., a thread bundle) is configured to process a different dataset based on the same instruction set. In at least one embodiment, all threads in the thread group execute the same instructions. In at least one embodiment, the SM 2814 implements a Single Instruction, Multiple Thread (“SIMT”) architecture, wherein each thread in a group of threads is configured to process a different dataset based on the same instruction set, but wherein individual threads in the thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each thread bundle, thereby achieving concurrency between the thread bundle and serial execution within the thread bundle when threads in the thread bundle diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby ensuring equal concurrency among all threads within and between thread bundles. In at least one embodiment, an execution state is maintained for each individual thread, and threads executing the same instructions can be converged and executed in parallel to improve efficiency. The following is in conjunction with... Figure 29 At least one embodiment of SM 2814 is described in more detail.

[0291] In at least one embodiment, the MMU 2818 is integrated with the GPC 2800 and memory partitioning unit (e.g., Figure 27 The MMU 2818 provides an interface between partition units 2722 and provides virtual address to physical address translation, memory protection, and memory request arbitration. In at least one embodiment, the MMU 2818 provides one or more translation back buffers (“TLBs”) for performing virtual address to physical address translation in memory.

[0292] Figure 29 A streaming multiprocessor (“SM”) 2900 according to at least one embodiment is shown. In at least one embodiment, the SM 2900 is Figure 28SM 2814. In at least one embodiment, SM 2900 includes, but is not limited to, instruction cache 2902; one or more scheduler units 2904; register file 2908; one or more processing cores (“cores”) 2910; one or more special function units (“SFUs”) 2912; one or more load / store units (“LSUs”) 2914; interconnect network 2916; shared memory / Level 1 (“L1”) cache 2918; and any suitable combination thereof. In at least one embodiment, the work allocation unit schedules tasks to execute on a general-purpose processing cluster (“GPC”) of parallel processing units (“PPUs”), and each task is assigned to a specific data processing cluster (“DPC”) within the GPC, and if the task is associated with a shader program, the task is assigned to one of the SMs 2900. In at least one embodiment, scheduler unit 2904 receives tasks from the work allocation unit and manages instruction scheduling for one or more thread blocks assigned to the SM 2900. In at least one embodiment, scheduler unit 2904 schedules thread blocks to execute as thread bundles of parallel threads, wherein each thread block is assigned at least one thread bundle. In at least one embodiment, each thread bundle executes a thread. In at least one embodiment, scheduler unit 2904 manages multiple different thread blocks, assigns thread bundles to different thread blocks, and then dispatches instructions from multiple different cooperative groups to various functional units (e.g., processing core 2910, SFU 2912, and LSU 2914) in each clock cycle. In at least one embodiment, SM 2900 includes one or more thread block clusters, wherein thread block clusters can provide local programming control with a larger granularity than a single thread block of a single streaming multiprocessor (SM). In at least one embodiment, thread block clusters (also referred to as “clusters”) enable multiple thread blocks running concurrently across streaming multiprocessors to synchronously and cooperatively acquire, exchange, or otherwise use data.

[0293] In at least one embodiment, a "cooperative group" can refer to a programming model used to organize groups of communicating threads, allowing developers to express the granularity at which threads are communicating, thereby enabling richer and more efficient parallel decompositions. In at least one embodiment, the cooperative startup API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, the API of a conventional programming model provides a single, simple construct for synchronizing cooperative threads: a barrier across all threads in a thread block (e.g., the `syncthreads()` function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than that of thread blocks and synchronize within the defined groups to achieve higher performance, design flexibility, and software reuse in the form of a set of group-wide functional interfaces. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at the sub-block and multi-block granularity and perform set operations, such as synchronizing threads within the cooperative group. In at least one embodiment, the sub-block granularity is as small as that of a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing library and utility functions to be safely synchronized in their local environment without having to make assumptions about convergence. In at least one embodiment, the cooperative group primitives enable new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across the entire thread block mesh.

[0294] In at least one embodiment, dispatch unit 2906 is configured to send instructions to one or more functional units, and scheduler unit 2904 includes, but is not limited to, two dispatch units 2906 that enable two different instructions from the same thread bundle to be dispatched in each clock cycle. In at least one embodiment, each scheduler unit 2904 includes a single dispatch unit 2906 or additional dispatch units 2906.

[0295] In at least one embodiment, each SM 2900 includes, but is not limited to, a register file 2908 that provides a set of registers for functional units of the SM 2900. In at least one embodiment, the register file 2908 is partitioned between each functional unit, thereby allocating a dedicated portion of the register file 2908 for each functional unit. In at least one embodiment, the register file 2908 is partitioned between different thread bundles executed by the SM 2900, and the register file 2908 provides temporary storage for operands connected to data paths of functional units. In at least one embodiment, each SM 2900 includes, but is not limited to, a plurality of L processing cores 2910. In at least one embodiment, the SM 2900 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 2910. In at least one embodiment, each processing core 2910 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, which includes, but is not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, the processing core 2910 includes, but is not limited to, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores and 8 tensor cores.

[0296] In at least one embodiment, the tensor core is configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in the processing core 2910. In at least one embodiment, the tensor core is configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs matrix multiplication and accumulation operations D = A×B + C, where A, B, C, and D are 4×4 matrices.

[0297] In at least one embodiment, matrix multiplication inputs A and B are 16-bit floating-point matrices, and accumulation matrices C and D are either 16-bit or 32-bit floating-point matrices. In at least one embodiment, the Tensor Core performs 32-bit floating-point accumulation on the 16-bit floating-point input data. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations to obtain a full-precision product, which is then accumulated with other intermediate multiplications using 32-bit floating-point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the Tensor Core is used to perform matrix operations on larger two-dimensional or higher-dimensional matrices composed of these smaller components. In at least one embodiment, an API (such as the CUDA-C++ API) exposes specialized matrix loading, matrix multiplication and accumulation, and matrix storage operations to efficiently utilize the Tensor Core from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the thread bundle level interface assumes a 16×16 matrix spanning all 32 thread bundle threads.

[0298] In at least one embodiment, each SM 2900 includes, but is not limited to, M SFUs 2912 that perform special functions (e.g., attribute evaluation, inverse square root, etc.). In at least one embodiment, the SFUs 2912 include, but are not limited to, tree traversal units configured to traverse hierarchical tree data structures. In at least one embodiment, the SFUs 2912 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture units are configured to load texture maps (e.g., a 2D array of texture pixels) from memory and sample the texture maps to produce sampled texture values ​​for use by a shader program executed by the SM 2900. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 2918. In at least one embodiment, the texture units use mip-maps (e.g., texture maps with different levels of detail) to implement texture operations (such as filtering operations). In at least one embodiment, each SM 2900 includes, but is not limited to, two texture units.

[0299] In at least one embodiment, each SM 2900 includes, but is not limited to, N LSUs 2914 that implement load and store operations between the shared memory / L1 cache 2918 and the register file 2908. In at least one embodiment, each SM 2900 includes, but is not limited to, an interconnect network 2916 that connects each functional unit to the register file 2908, and the LSUs 2914 that connect to both the register file 2908 and the shared memory / L1 cache 2918. In at least one embodiment, the interconnect network 2916 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 2908 and to connect the LSUs 2914 to memory locations in both the register file 2908 and the shared memory / L1 cache 2918.

[0300] In at least one embodiment, the shared memory / L1 cache 2918 is an array of on-chip memory that, in at least one embodiment, allows data storage and communication between the SM 2900 and the primitive engine, as well as between threads within the SM 2900. In at least one embodiment, the shared memory / L1 cache 2918 includes, but is not limited to, a storage capacity of 128KB and is located on the path from the SM 2900 to the partition unit. In at least one embodiment, the shared memory / L1 cache 2918 is used for cache reads and writes. In at least one embodiment, one or more of the shared memory / L1 cache 2918, the L2 cache, and the memory are backup storage.

[0301] In at least one embodiment, combining data caching and shared memory functionality into a single memory block provides improved performance for both types of memory access. In at least one embodiment, the capacity is used by programs that do not use shared memory or is used as a cache; for example, if shared memory is configured to use half its capacity, texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within the shared memory / L1 cache 2918 enables the shared memory / L1 cache 2918 to be used as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, a simpler configuration can be used compared to graphics processing when configured for general-purpose parallel computing. In at least one embodiment, a simpler programming model is created by bypassing fixed-function GPUs. In at least one embodiment, in a general-purpose parallel computing configuration, the work allocation unit directly allocates and distributes blocks of threads to the DPC. In at least one embodiment, threads within a block execute the same program, using unique thread IDs in computation to ensure each thread produces a unique result, using an SM 2900 to execute the program and perform computations, using shared memory / L1 cache 2918 for communication between threads, and using an LSU 2914 to read and write global memory via shared memory / L1 cache 2918 and memory partitioning units. In at least one embodiment, when configured for general-purpose parallel computing, the SM 2900 writes commands to the scheduler unit 2904 that can be used to start new work on the DPC. In at least one embodiment, the SM 2900 includes one or more distributed shared memories (or distributed shared memory), enabling direct SM-to-SM operations, such as loading, storing, and executing atomic operations across memory blocks shared by multiple SMs.

[0302] In at least one embodiment, the SM 2900 includes one or more asynchronous execution functions, including a Tensor Memory Accelerator (TMA) unit that can transfer data blocks between global memory and shared memory. In at least one embodiment, one or more processors use or access one or more TMAs to perform bidirectional copy operations, such as from global memory to shared memory and vice versa. In at least one embodiment, the SM 2900 includes one or more TMAs for asynchronous copying between thread blocks in a cluster. In at least one embodiment, the SM 2900 includes one or more asynchronous transaction barriers for performing atomic data moves and synchronization. In at least one embodiment, the SM 2900 includes a Tensor Core Transformer Engine that includes software for accelerating transformer model training and inference and one or more cores. In at least one embodiment, one or more processor cores executing one or more Tensor Core Transformer Engines manage FP8 and 16-bit computations and dynamically select between them by re-casting and scaling in each layer of one or more neural networks.

[0303] In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), PDA, digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-a-chip (“SoC”) along with one or more other devices (e.g., additional PPUs, memory, RISC CPU, MMU, digital-to-analog converter (“DAC”), etc.).

[0304] In at least one embodiment, the PPU may be included on a graphics card that includes one or more storage devices. The graphics card may be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU may be an integrated GPU (“iGPU”) included in the motherboard's chipset.

[0305] Software architecture for general-purpose computing

[0306] The following figures illustrate, but are not limited to, exemplary software constructions for implementing at least one embodiment.

[0307] Figure 30A software stack of a programming platform according to at least one embodiment is illustrated. In at least one embodiment, the programming platform is a platform for accelerating computational tasks by utilizing hardware on a computing system. In at least one embodiment, software developers can access the programming platform through libraries, compiler instructions, and / or extensions to programming languages. In at least one embodiment, the programming platform may be, but is not limited to, CUDA, Radeon Open Computing Platform (“ROCm”), OpenCL (OpenCL developed by Khronosgroup). TM ), SYCL or Intel One API.

[0308] In at least one embodiment, the software stack 3000 of the programming platform provides an execution environment for the application 3001. In at least one embodiment, the application 3001 may include any computer software capable of being launched on the software stack 3000. In at least one embodiment, the application 3001 may include, but is not limited to, artificial intelligence (“AI”) / machine learning (“ML”) applications, high-performance computing (“HPC”) applications, virtual desktop infrastructure (“VDI”) or data center workloads.

[0309] In at least one embodiment, application 3001 and software stack 3000 run on hardware 3007. In at least one embodiment, hardware 3007 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices supporting a programming platform. In at least one embodiment, such as using CUDA, software stack 3000 may be vendor-specific and compatible only with devices from a specific vendor. In at least one embodiment, such as using OpenCL, software stack 3000 may be used with devices from different vendors. In at least one embodiment, hardware 3007 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform computational tasks. In at least one embodiment, compared to the host within hardware 3007, which may include, but is not limited to, a CPU (but may also include computing devices) and its memory, devices within hardware 3007 may include, but are not limited to, GPUs, FPGAs, AI engines, or other computing devices (but may also include CPUs) and their memory.

[0310] In at least one embodiment, the software stack 3000 of the programming platform includes, but is not limited to, multiple libraries 3003, a runtime 3005, and a device kernel driver 3006. In at least one embodiment, each library in the library 3003 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, the library 3003 may include, but is not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the library 3003 includes functions optimized for execution on one or more types of devices. In at least one embodiment, the library 3003 may include, but is not limited to, functions for performing mathematical, deep learning, and / or other types of operations on the device. In at least one embodiment, the library 3003 is associated with a corresponding API 3002, which may include one or more APIs that expose functions implemented in the library 2903. In at least one embodiment, a processor (e.g., CPU, GPU) executes, calls, or otherwise uses one or more APIs to prioritize kernels. For example, a first kernel (e.g., a parent kernel) can launch a second kernel (e.g., a child kernel), and the second kernel can be used by the processor to launch an additional kernel (e.g., a grandchild kernel) independent of the first kernel. In at least one embodiment, the processor executes an API or calls an API from memory to support dynamic stream priorities (e.g., updating priorities when a stream is used to perform an operation). For example, when the processor executes the API, it allows a programmer to copy a stream priority from one stream to one or more other streams.

[0311] In at least one embodiment, the software stack 3000 includes an API for supporting dynamic stream prioritization (e.g., updating priority when a stream is used to perform an operation), which allows a programmer to set the priority of a stream at any time after its creation. In at least one embodiment, the software stack 3000 includes an API for supporting dynamic stream prioritization (e.g., updating priority when a stream is used to perform an operation), which allows a programmer to obtain the current priority of a stream, where priority is one of several attributes of the stream. In at least one embodiment, the software stack 3000 includes an API for supporting dynamic stream prioritization (e.g., updating priority when a stream is used to perform an operation), which allows a programmer to obtain the current priority of a stream as a single attribute. In at least one embodiment, the software stack 3000 includes an API for supporting dynamic stream prioritization (e.g., updating priority when a stream is used to perform an operation), which allows a programmer to start the kernel to perform operations on the stream at a set priority (which may be different from the stream priority). In at least one embodiment, the software stack 3000 includes an API that indicates whether an object (e.g., a thread synchronization object such as a barrier) is tracking whether all data movement operations of a set of threads operating on the GPU are complete and whether a specified state has been reached after a specified time period, wherein the specified state may be a state indicating that data has been moved and is ready for use, and is specified using an expected parity value as input to the API.

[0312] In at least one embodiment, the software stack 3000 includes one or more APIs for updating the kernel. In at least one embodiment, the processor executes the API or calls the API to be executed from memory to update existing APIs to support a contextless kernel. This allows programmers to add kernel nodes to the graph without a graphics context, enabling the graphics context to be dynamically associated with the kernel at runtime. In at least one embodiment, the software stack 3000 includes one or more APIs for allowing programmers to obtain kernel identifiers and graphics contexts as separate parameters from kernel nodes, thereby obtaining parameters from both the kernel and the contextless kernel. In at least one embodiment, the software stack 3000 includes one or more APIs for using parallel processors (such as one or more graphics processing units) to initiate a task graph (e.g., a task graph) and execute one or more task graphs (e.g., including one or more programs).

[0313] In at least one embodiment, the software stack 3000 includes one or more APIs for associating one or more instructions with one or more memory sorting operations (e.g., fence or memory bar operations). In at least one embodiment, instructions are associated with one or more domains such that memory sorting operations are performed in association with one or more specific domains without interfering with instructions in other domains. The software stack 3000 includes APIs for indicating that a thread has reached (e.g., at a thread synchronization barrier) or completed a work phase associated with an asynchronous data movement operation on the GPU. In at least one embodiment, the software stack 3000 includes one or more APIs for allowing a programmer to manually indicate an expected transaction count when a thread has completed a work phase; this count is used to update an object that tracks whether all data movement operations of a set of threads have completed.

[0314] In at least one embodiment, application 3001 is written as source code, which is compiled into executable code, as follows: Figures 35-37 This will be discussed in more detail. In at least one embodiment, the executable code of application 3001 may run at least partially on an execution environment provided by software stack 3000. In at least one embodiment, during the execution of application 3001, code that needs to run on the device (compared to the host) may be obtained. In this case, in at least one embodiment, runtime 3005 may be invoked to load and start the necessary code on the device. In at least one embodiment, runtime 3005 may include any technically feasible runtime system capable of supporting the execution of application 3001.

[0315] In at least one embodiment, runtime 3005 is implemented as one or more runtime libraries associated with a corresponding API (which is shown as API 3004). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, etc. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, freeing, and copying device memory, and for transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching functions on the device (sometimes referred to as "kernels" when the function is a global function that can be called from the host), and functions for setting attribute values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0316] In at least one embodiment, the runtime library and the corresponding API 3004 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs may expose a low-level set of functions for fine-grained control of the device, while another (or any number of) APIs may expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API can be built on top of the low-level APIs. In at least one embodiment, one or more runtime APIs may be language-specific APIs layered on top of language-independent runtime APIs.

[0317] In at least one embodiment, one or more processors disclosed in the "processing system" may execute, access, or otherwise use the software stack 3000. For example, an APU 1700, a CPU 1800, etc. Figures 20A-20B The exemplary graphics processor, general-purpose graphics processing unit (“GPGPU”) 2130, parallel processor 2200, processing cluster 2294, graphics multiprocessor 2234, graphics multiprocessor 2296, graphics processor 2300, processor 2400, processor 2500, parallel processing unit (“PPU”) 2700, GPC 2800 and / or streaming multiprocessor (“SM”) 2900 may execute, use, call or otherwise implement (e.g., by accessing memory) one or more APIs included in the software stack 3000.

[0318] In at least one embodiment, device kernel driver 3006 is configured to facilitate communication with the underlying device. In at least one embodiment, device kernel driver 3006 may provide APIs such as API 3004 and / or low-level functions upon which other software depends. In at least one embodiment, device kernel driver 3006 may be configured to compile intermediate representation (“IR”) code into binary code at runtime. In at least one embodiment, for CUDA, device kernel driver 3006 may compile non-hardware-specific parallel thread execution (“PTX”) IR code into binary code for a specific target device (cached compiled binary code), which is sometimes referred to as “final” code. In at least one embodiment, doing so allows the final code to run on the target device, which may not exist when the source code was initially compiled into PTX code. Alternatively, in at least one embodiment, the device source code may be compiled into binary code offline, without requiring device kernel driver 3006 to compile the IR code at runtime.

[0319] Figure 31 The illustration shows an embodiment according to at least one of the embodiments. Figure 30The software stack 3000 is a CUDA implementation. In at least one embodiment, the CUDA software stack 3100 on which an application 3101 can be launched includes a CUDA library 3103, a CUDA runtime 3105, a CUDA driver 3107, and a device kernel driver 3108. In at least one embodiment, the CUDA software stack 3100 executes on hardware 3109, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0320] In at least one embodiment, application 3101, CUDA runtime 3105, and device kernel driver 3108 can respectively perform functions similar to those of application 3001, runtime 3005, and device kernel driver 3006, in combination with the above. Figure 30 The CUDA driver 3107 is described in at least one embodiment. In at least one embodiment, the CUDA driver API 3107 includes a library (libcuda.so) implementing the CUDA driver API 3106. In at least one embodiment, similar to the CUDA runtime API 3104 implemented by the CUDA runtime library (cudart), the CUDA driver API 3106 may expose, but is not limited to, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 3106 differs from the CUDA runtime API 3104 in that the CUDA runtime API 3104 simplifies device code management by providing implicit initialization, context (similar to processes) management, and module (similar to dynamically loaded libraries) management. In contrast to the high-level CUDA runtime API 3104, in at least one embodiment, the CUDA driver API 3106 is a low-level API that provides finer-grained control over the device, particularly regarding context and module loading. In at least one embodiment, the CUDA driver API 3106 may expose functions for context management that are not exposed by the CUDA runtime API 3104. In at least one embodiment, the CUDA driver API 3106 is also language-independent and supports, in addition to the CUDA runtime API 3104, OpenCL, for example. Furthermore, in at least one embodiment, development libraries, including the CUDA runtime 3105, can be considered separate from the driver components, including the user-mode CUDA driver 3107 and the kernel-mode device driver 3108 (sometimes also referred to as the "display" driver).

[0321] In at least one embodiment, CUDA library 3103 may include, but is not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which parallel computing applications (e.g., application 3101) may utilize. In at least one embodiment, CUDA library 3103 may include mathematical libraries, such as the cuBLAS library, which is an implementation of basic linear algebra subroutines (“BLAS”) for performing linear algebra operations; the cuFFT library for computing the Fast Fourier Transform (“FFT”); and the cuRAND library for generating random numbers, etc. In at least one embodiment, CUDA library 3103 may include deep learning libraries, such as the cuDNN library for primitives of deep neural networks and the TensorRT platform for high-performance deep learning inference, etc.

[0322] Figure 32 The illustration shows an embodiment according to at least one of the embodiments. Figure 30 The software stack 3000 is a ROCm implementation. In at least one embodiment, the ROCm software stack 3200 on which the application 3201 can be launched includes a language runtime 3203, a system runtime 3205, a thunk 3207, and a ROCm kernel driver 3208. In at least one embodiment, the ROCm software stack 3200 executes on hardware 3209, which may include a ROCm-enabled GPU developed by AMD Inc. of Santa Clara, California.

[0323] In at least one embodiment, application 3201 can perform actions in conjunction with the above. Figure 30 The discussed application 3001 has similar functionality. Additionally, in at least one embodiment, the language runtime 3203 and system runtime 3205 can perform functions combined with the above. Figure 30The runtime 3005 discussed has similar functionality. In at least one embodiment, the language runtime 3203 and the system runtime 3205 differ in that the system runtime 3205 is a language-independent runtime that implements the ROCr System Runtime API 3204 and utilizes the Heterogeneous System Architecture (“HSA”) runtime API. In at least one embodiment, the HSA runtime API is a thin-user mode API that exposes interfaces for accessing and interacting with AMD GPUs, including functions for memory management, kernel execution control dispatched by the architecture, error handling, system and agent information, and runtime initialization and shutdown, etc. In at least one embodiment, compared to the system runtime 3205, the language runtime 3203 is an implementation of a language-specific runtime API 3202 layered on top of the ROCr System Runtime API 3204. In at least one embodiment, the language runtime API may include, but is not limited to, the Portable Heterogeneous Computing Interface (“HIP”) language runtime API, the Heterogeneous Computing Compiler (“HCC”) language runtime API, or the OpenCL API, etc. In particular, the HIP language is an extension of the C++ programming language, a functionally similar version with CUDA mechanisms, and in at least one embodiment, the HIP language runtime API includes elements combined with the above. Figure 31 The discussion focuses on functions similar to CUDA runtime API 3104, such as those used for memory management, execution control, device management, error handling, and synchronization.

[0324] In at least one embodiment, the thunk (ROCt) 3207 is an interface that can be used to interact with the underlying ROCm driver 3208. In at least one embodiment, the ROCm driver 3208 is a ROCk driver, which is a combination of an AMD GPU driver and an HSA core driver (amdkfd). In at least one embodiment, the AMD GPU driver is a device core driver for GPUs developed by AMD, which performs the above-described combination. Figure 30 The device kernel driver 3006 discussed has similar functionality. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to share system resources more efficiently via hardware features.

[0325] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 3200 above the language runtime 3203, and provide integration with the above. Figure 31 The discussed CUDA library 3103 has similar functionality. In at least one embodiment, various libraries may include, but are not limited to, mathematical, deep learning, and / or other libraries, such as the hipBLAS library which implements functions similar to CUDA cuBLAS, the rocFFT library which is similar to CUDA cuFFT for computing FFT, etc.

[0326] Figure 33 The illustration shows an embodiment according to at least one of the embodiments. Figure 30 The software stack 3000 is an OpenCL implementation. In at least one embodiment, the OpenCL software stack 3300 on which the application 3301 can be launched includes an OpenCL framework 3305, an OpenCL runtime 3306, and a driver 3307. In at least one embodiment, the OpenCL software stack 3300 executes on hardware 3109 that is not vendor-specific. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required for interoperability with hardware from such vendors.

[0327] In at least one embodiment, the application 3301, the OpenCL runtime 3306, the device kernel driver 3307, and the hardware 3308 can respectively execute the above-described combination. Figure 30 The application 3001, runtime 3005, device kernel driver 3006, and hardware 3007 discussed have similar functionality. In at least one embodiment, application 3301 also includes an OpenCL kernel 3302 with code that will be executed on the device.

[0328] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to that host. In at least one embodiment, the OpenCL framework provides a platform-level API and a runtime API, shown as Platform API 3303 and Runtime API 3305. In at least one embodiment, Runtime API 3305 uses a context to manage the execution of the kernel on the device. In at least one embodiment, each identified device can be associated with a respective context, which Runtime API 3305 can use to manage the device's command queue, program objects and kernel objects, shared memory objects, etc. In at least one embodiment, Platform API 3303 discloses functions that allow the device context to select and initialize devices, submit work to devices via command queues, and enable data transfers to and from devices, etc. Additionally, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, and image processing functions, etc.

[0329] In at least one embodiment, compiler 3304 is also included in the OpenCL framework 3305. In at least one embodiment, the source code can be compiled offline before executing the application or online during application execution. Unlike CUDA and ROCm, the OpenCL application in at least one embodiment can be compiled online by compiler 3304, which is included to represent any number of compilers that can be used to compile source code and / or IR code (e.g., Standard Portable Intermediate Representation (“SPIR-V”) code) into binary code. Alternatively, in at least one embodiment, the OpenCL application can be compiled offline before executing such an application.

[0330] Figure 34 Software supported by a programming platform according to at least one embodiment is illustrated. In at least one embodiment, the programming platform 3404 is configured to support various programming models 3403, middleware and / or libraries 3402, and frameworks 3401 that an application 3400 may depend on. In at least one embodiment, the application 3400 may be an AI / ML application implemented using, for example, a deep learning framework (e.g., MXNet, PyTorch, or TensorFlow), which may depend on libraries such as cuDNN, the NVIDIA Collective Communications Library (“NCCL”), and / or the NVIDIA Developer Data Loading Library (“DALI”) CUDA library to provide accelerated computation on the underlying hardware.

[0331] In at least one embodiment, the programming platform 3404 can be a combination of the above-described components. Figure 31 , Figure 32 and Figure 33 One of the described CUDA, ROCm, or OpenCL platforms. In at least one embodiment, the programming platform 3404 supports multiple programming models 3403, which are abstractions of the underlying computing system that allow for the expression of algorithms and data structures. In at least one embodiment, the programming model 3403 may expose features of the underlying hardware to improve performance. In at least one embodiment, the programming model 3403 may include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism (“C++AMP”), Open Multiprocessing (“OpenMP”), Open Accelerator (“OpenACC”), and / or Vulcan Compute.

[0332] In at least one embodiment, the library and / or middleware 3402 provides an abstract implementation of the programming model 3404. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, in addition to those available from the programming platform 3404, such middleware also includes software that provides services to applications. In at least one embodiment, the library and / or middleware 3402 may include, but is not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Additionally, in at least one embodiment, the library and / or middleware 3402 may include NCCL and ROCm communication collection library (“RCCL”) libraries, which provide communication routines for GPUs, the MIOpen library for deep learning acceleration, and / or intrinsic libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0333] In at least one embodiment, the application framework 3401 depends on libraries and / or middleware 3402. In at least one embodiment, each application framework 3401 is a software framework for implementing a standard structure of application software. Returning to the AI / ML example discussed above, in at least one embodiment, AI / ML applications can be implemented using frameworks such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or the MxNet deep learning framework.

[0334] Figure 35 Compilation code according to at least one embodiment is shown to be used in Figures 30-33 The program is executed on one of the programming platforms. In at least one embodiment, compiler 3501 receives source code 3500, which includes both host code and device code. In at least one embodiment, compiler 3501 is configured to convert source code 3500 into host executable code 3502 for execution on a host and device executable code 3503 for execution on a device. In at least one embodiment, source code 3500 may be compiled offline before executing the application or compiled online during application execution. In at least one embodiment, compiler 3501 includes or has access to one or more libraries to identify API call sequences to execute a single fused API, wherein the single fused API is a combination API of two or more APIs.

[0335] In at least one embodiment, source code 3500 may include code in any programming language supported by compiler 3501, such as C++, C, Fortran, etc. In at least one embodiment, source code 3500 may be included in a single-source file, which has a mixture of host code and device code, and indicates the location of the device code therein. In at least one embodiment, the single-source file may be a .cu file including CUDA code or a .hip.cpp file including HIP code. Alternatively, in at least one embodiment, source code 3500 may include multiple source code files instead of a single-source file, in which the host code and device code are separate.

[0336] In at least one embodiment, compiler 3501 is configured to compile source code 3500 into host executable code 3502 for execution on a host and device executable code 3503 for execution on a device. In at least one embodiment, compiler 3501 performs operations including resolving source code 3500 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 3500 comprises a single source file, compiler 3501 may separate device code and host code within such a single source file, compile the device code and host code into device executable code 3503 and host executable code 3502 respectively, and link the device executable code 3503 and host executable code 3502 together in a single file, as described below. Figure 36 To be discussed in more detail.

[0337] In at least one embodiment, the host executable code 3502 and the device executable code 3503 can be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, the host executable code 3502 may include native object code, while the device executable code 3503 may include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both the host executable code 3502 and the device executable code 3503 can include target binary code.

[0338] Figure 36 It is compiled code according to at least one embodiment to be used in Figures 30-33A more detailed illustration is provided on one of the programming platforms. In at least one embodiment, compiler 3601 is configured to receive source code 3600, compile source code 3600, and output executable file 3608. In at least one embodiment, source code 3600 is a single-source file, such as a .cu file, a .hip.cpp file, or a file of other formats, which includes both host code and device code. In at least one embodiment, compiler 3601 may be, but is not limited to, an NVIDIA CUDA compiler (“NVCC”) for compiling CUDA code in .cu files, or an HCC compiler for compiling HIP code in .hip.cpp files.

[0339] In at least one embodiment, compiler 3601 includes compiler front-end 3602, host compiler 3605, device compiler 3606, and linker 3609. In at least one embodiment, compiler front-end 3602 is configured to separate device code 3604 from host code 3603 in source code 3600. In at least one embodiment, device code 3604 is compiled by device compiler 3606 into device executable code 3608, which, as described, may include binary code or IR code. In at least one embodiment, host code 3603 is compiled separately by host compiler 3605 into host executable code 3607. In at least one embodiment, for NVCC, host compiler 3605 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 3606 may be, but is not limited to, a low-level virtual machine (“LLVM”) based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both the host compiler 3605 and the device compiler 3606 can be, but are not limited to, LLVM-based compilers that output target binary code.

[0340] In at least one embodiment, after compiling source code 3600 into host executable code 3607 and device executable code 3608, linker 3609 links the host and device executable codes 3607 and 3608 together in executable file 3610. In at least one embodiment, the native object code of the host and PTX or the binary code of the device can be linked together in an executable and linkable format (“ELF”) file, which is a container format for storing object code.

[0341] Figure 37The illustration shows the transformation of source code prior to compilation, according to at least one embodiment. In at least one embodiment, source code 3700 is passed via a transformation tool 3701, which transforms source code 3700 into transformed source code 3702. In at least one embodiment, a compiler 3703 is used to compile the transformed source code 3702 into host executable code 3704 and device executable code 3705, a process similar to that of compiler 3501 compiling source code 3500 into host executable code 3502 and device executable code 3503, as described above. Figure 35 The subject of discussion.

[0342] In at least one embodiment, the transformation performed by the transformation tool 3701 is used to port source code 3700 to perform in an environment different from where it was originally intended to run. In at least one embodiment, the transformation tool 3701 may include, but is not limited to, a HIP converter for “hipify” CUDA code for a CUDA platform into HIP code that can be compiled and executed on the ROCm platform. In at least one embodiment, the transformation of source code 3700 may include: parsing source code 3700 and converting calls to APIs provided by one programming model (e.g., CUDA) into corresponding calls to APIs provided by another programming model (e.g., HIP), as combined below. Figure 38A-39 This will be discussed in more detail. Returning to the example of porting CUDA code, in at least one embodiment, calls to the CUDA runtime API, CUDA driver API, and / or CUDA libraries can be translated into corresponding HIP API calls. In at least one embodiment, the automatic translation performed by the translation tool 3701 may sometimes be incomplete, requiring additional manual intervention to fully port the source code 3700.

[0343] Configure GPUs for general-purpose computing

[0344] The following figures illustrate, but are not limited to, exemplary architectures for compiling and executing computational source code according to at least one embodiment.

[0345] Figure 38AA system 3800 is shown, configured to compile and execute CUDA source code 3810 using different types of processing units according to at least one embodiment. In at least one embodiment, system 3800 includes, but is not limited to, CUDA source code 3810, CUDA compiler 3850, host executable code 3870(1), host executable code 3870(2), CUDA device executable code 3884, CPU 3890, CUDA-enabled GPU 3894, GPU 3892, CUDA to HIP conversion tool 3820, HIP source code 3830, HIP compiler driver 3840, HCC 3860, and HCC device executable code 3882.

[0346] In at least one embodiment, CUDA source code 3810 is a collection of human-readable code in the CUDA programming language. In at least one embodiment, CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language, which includes, but is not limited to, defining device code and mechanisms for distinguishing between device code and host code. In at least one embodiment, device code is source code that can be executed in parallel on a device after compilation. In at least one embodiment, the device may be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3890, GPU 3892, or another GPGPU. In at least one embodiment, host code is source code that can be executed on a host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as CPU 3890.

[0347] In at least one embodiment, the CUDA source code 3810 includes, but is not limited to, any number (including zero) of global functions 3812, any number (including zero) of device functions 3814, any number (including zero) of host functions 3816, and any number (including zero) of host / device functions 3818. In at least one embodiment, the global functions 3812, device functions 3814, host functions 3816, and host / device functions 3818 can be mixed in the CUDA source code 3810. In at least one embodiment, each global function 3812 is executable on a device and is callable from a host. Therefore, in at least one embodiment, one or more of the global functions 3812 can serve as entry points for a device. In at least one embodiment, each global function 3812 is a kernel. In at least one embodiment, and in a technique called dynamic parallelism, one or more global functions 3812 define a kernel that is executable on a device and is callable from such a device. In at least one embodiment, the kernel is executed in parallel N times (where N is any positive integer) by N different threads on the device during execution.

[0348] In at least one embodiment, each device function 3814 executes on a device and can only be called from such a device. In at least one embodiment, each host function 3816 executes on a host and can only be called from such a host. In at least one embodiment, each host / device function 3816 defines both a host version of a function that is executable on a host and can only be called from such a host, and a device version of a function that is executable on a device and can only be called from such a device.

[0349] In at least one embodiment, CUDA source code 3810 may also include, but is not limited to, any number of calls to any number of functions defined by CUDA runtime API 3802. In at least one embodiment, CUDA runtime API 3802 may include, but is not limited to, any number of functions executed on the host for allocating and releasing device memory, transferring data between host memory and device memory, managing a system with multiple devices, etc. In at least one embodiment, CUDA source code 3810 may also include, but is not limited to, any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, the CUDA API may be any API designed to be used by CUDA code. In at least one embodiment, the CUDA API includes, but is not limited to, CUDA runtime API 3802, CUDA driver APIs, APIs for any number of CUDA libraries, etc. In at least one e...

Claims

1. A processor, comprising: One or more circuits, said one or more circuits for executing a compiler to generate one or more executable programs that can be configured to be executed by one or more processor architectures of a plurality of different processor architectures.

2. The processor of claim 1, wherein each of the one or more executable programs comprises a set of one or more executable instructions and one or more comments.

3. The processor of claim 1, wherein the one or more executable programs are generated at least in part based on the one or more processor architectures of the plurality of different processor architectures.

4. The processor of claim 1, wherein the one or more executable programs are configurable to be executed by the one or more processor architectures of the plurality of different processor architectures based at least in part on one or more annotations generated together with the one or more executable programs.

5. The processor of claim 1, wherein the one or more executable programs are configured by further generating one or more comments, the one or more comments including information for configuring the one or more executable programs.

6. The processor according to claim 1, further comprising: A decompiler is executed to configure the one or more executable programs to be executed by the one or more processor architectures among the plurality of different processor architectures.

7. A system comprising: One or more processors, said one or more processors being used to execute a compiler to generate one or more executable programs that can be configured to be executed by one or more processor architectures of a plurality of different processor architectures.

8. The system of claim 7, wherein the one or more executable programs comprise a bundle of one or more executable instructions and one or more comments.

9. The system of claim 7, wherein the compiler is configured to generate the one or more executable programs based at least in part on the one or more processor architectures of the plurality of different processor architectures and one or more comments indicating information about one or more instructions of the one or more executable programs.

10. The system of claim 7, wherein the compiler is configured to generate the one or more executable programs by compiling one or more instructions and generating one or more annotations that can be used to configure the one or more executable programs.

11. The system of claim 7, wherein the one or more executable programs are decoded to generate one or more instructions and information for configuring the one or more executable programs.

12. The system of claim 7, wherein one or more other processors are configured to execute a decompiler to configure the one or more executable programs to be executed by the one or more processor architectures of the plurality of different processor architectures.

13. A method comprising: The compiler is executed to generate one or more executable programs that can be configured to be executed by one or more different processor architectures.

14. The method of claim 13, further comprising: Generate one or more annotations that can be used to configure the one or more executable programs.

15. The method of claim 13, further comprising: The one or more executable programs are bundled together with one or more annotations that can be used to configure the one or more executable programs.

16. The method of claim 13, wherein the compiler is configured to generate the one or more executable programs based at least in part on the one or more processor architectures of the plurality of different processor architectures and one or more comments indicating information about one or more instructions of the one or more executable programs.

17. The method of claim 13, wherein the one or more executable programs comprise a bundle of one or more executable instructions and one or more comments.

18. The method of claim 13, further comprising: Verify the behavior of the one or more executable programs.

19. The method of claim 13, further comprising: Execute a decompiler to configure the one or more executable programs to be executed by the one or more processor architectures among the plurality of different processor architectures.

20. The method of claim 13, further comprising: The one or more executable programs are executed by one or more processors of one or more processor architectures, which include the plurality of different processor architectures.

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