Urban community household charging pile harmonic suppression method

Abstract

The invention discloses an urban community household charging pile harmonic suppression method, which comprises the following steps: S1, collecting voltage and current data of a charging pile under different working conditions, analyzing harmonic generation characteristics, constructing a harmonic mathematical model, and determining typical harmonic frequency and amplitude range; s2, an FPGA real-time data processing architecture is designed according to the harmonic model, a high-speed data acquisition module is established, and real-time acquisition and accurate identification of harmonic signals are realized; s3, on the FPGA platform, based on the real-time harmonic spectrum data, deploying an adaptive harmonic suppression algorithm, dynamically filtering the target harmonic frequency, and reducing the harmonic content; and S4, according to suppression effect feedback, FPGA control parameters are optimized, energy consumption and cost of the device are reduced, and precise and efficient harmonic suppression performance and economical efficiency balance is achieved. The method can ensure that the current waveform of the charging pile meets the power grid standard, remarkably improves the harmonic suppression efficiency and the economical efficiency of the device, and reduces the energy consumption and the equipment maintenance cost.

Description

Technical Field

[0001] This invention relates to the field of power systems and electric vehicle charging infrastructure, and in particular to a method for harmonic mitigation of home charging piles in urban residential communities. Background Technology

[0002] With the increasing popularity of electric vehicles, the number of home charging stations in urban communities is gradually increasing, becoming an important part of modern urban power systems. However, during the charging process, charging stations are prone to generating various harmonic pollution due to the nonlinear characteristics of the power supply and load. Harmonic generation is particularly severe under high load conditions, which not only affects the operating efficiency of the charging stations themselves but also interferes with the power quality of the grid. Harmonics in the grid can lead to overheating of equipment, increased losses, and even damage to electrical equipment, affecting the stability and security of the power grid. Therefore, how to effectively suppress harmonics generated by charging stations has become an urgent problem to be solved in power system management.

[0003] Currently, some traditional harmonic suppression technologies have been applied to power systems, including the use of filters and harmonic compensation devices. However, these methods typically have certain limitations. Traditional filters usually rely on fixed parameters, making it difficult to cope with dynamic harmonics caused by changes in the charging pile load, resulting in limited suppression effectiveness. Furthermore, traditional harmonic mitigation devices often employ a single processing method, lacking flexibility and unable to adjust mitigation strategies in real time according to load changes. Therefore, existing technologies have failed to effectively solve the real-time and adaptability issues in harmonic mitigation for charging piles.

[0004] In recent years, with the rapid development of FPGA technology, FPGAs, with their high parallel computing power, real-time processing capabilities, and flexible programmability, have been increasingly applied to various real-time monitoring and processing tasks in power systems. FPGAs can acquire and process large amounts of data in real time, making their application in harmonic mitigation for charging piles extremely promising. Using FPGA technology, real-time monitoring and dynamic suppression of harmonics from charging piles can be achieved, and mitigation strategies can be automatically adjusted according to different load conditions to improve mitigation effectiveness. However, existing FPGA-based harmonic mitigation methods are mostly limited to signal acquisition and preliminary analysis, often employing fixed-parameter filtering or single processing methods, lacking the ability to adaptively adjust to different load conditions. Furthermore, the acquisition, spectrum analysis, and suppression stages are implemented separately, and the spectrum and control parameters lack linkage, resulting in insufficient real-time performance and accuracy of harmonic suppression. In addition, there is limited consideration for FPGA internal resource scheduling and energy efficiency optimization, leading to high power consumption and maintenance costs, making it difficult to balance mitigation performance and economy. Summary of the Invention

[0005] The purpose of this invention is to provide a method for harmonic mitigation of home charging piles in urban communities. This method not only enables real-time monitoring and suppression of harmonic signals generated during the operation of the charging piles, ensuring that the current waveform of the charging piles conforms to power grid standards, but also significantly improves the harmonic suppression efficiency and the economic efficiency of the device, reduces energy consumption and equipment maintenance costs, and effectively supports the stability and green development of the power grid.

[0006] The technical solution of the present invention to solve the above-mentioned technical problems is as follows:

[0007] This invention provides a method for harmonic mitigation of home charging piles in urban residential areas, the specific steps of which are as follows:

[0008] S1: Collect voltage and current data of charging piles under different operating conditions, analyze the characteristics of harmonic generation, construct a harmonic mathematical model, and determine the typical harmonic frequency and amplitude range.

[0009] S2: Based on the harmonic model, design an FPGA real-time data processing architecture, build a high-speed data acquisition module, and realize the real-time acquisition and accurate identification of harmonic signals;

[0010] S3: On the FPGA platform, based on real-time harmonic spectrum data, an adaptive harmonic suppression algorithm is deployed to dynamically filter out target harmonic frequencies and reduce harmonic content;

[0011] S4: Based on the feedback of the suppression effect, optimize the FPGA control parameters to reduce the device's energy consumption and cost, achieving a balance between accurate and efficient harmonic control performance and economy.

[0012] Optionally, in step S1, current and voltage data of the charging pile under different load conditions (such as no load, low load, high load, etc.) are collected to ensure the comprehensiveness and accuracy of the harmonic generation mechanism.

[0013] Alternatively, in step S2, the high-speed data acquisition module is used to acquire the current and voltage signals of the charging pile in real time at a frequency of at least 10kHz, and the parallel computing capabilities of the FPGA are used to quickly identify harmonic frequencies and process the data. This module can ensure accurate identification of harmonic signals even under dynamic load conditions.

[0014] Alternatively, in step S3, the adaptive harmonic suppression algorithm automatically adjusts the filtering parameters and the suppression strategy in real time by comparing real-time spectrum data with a preset harmonic standard. This algorithm can automatically optimize the processing strategy according to different operating conditions, thereby maximizing the suppression of harmonic pollution.

[0015] Optionally, in step S4, the optimization of FPGA control parameters includes filter parameter optimization, recalculating filter coefficients based on real-time harmonic amplitude and phase; FPGA resource scheduling optimization, reducing the operating frequency of the computing module to reduce power consumption when the harmonic content is below a threshold; and calling the optimization database to directly adopt the historically optimal parameter combination to shorten the response time when similar operating conditions occur. By dynamically adjusting the control strategy, the governance efficiency is improved and the operation and maintenance costs of the equipment are reduced.

[0016] Alternatively, in step S1, it is assumed that the acquired current and voltage signals are i(t) and v(t), respectively, where t represents time, and the signals are transmitted to the processing unit through the data acquisition module; then, the acquired time-domain signals are converted into frequency-domain signals through Fourier transform, and their spectrum is calculated:

[0017]

[0018] Here, I(f) and V(f) are the frequency domain representations of the current and voltage signals, respectively, where f is the frequency and j is the imaginary unit. The frequency domain signal obtained through Fourier transform can reveal the harmonic components in the signal; furthermore, the harmonic frequency f is identified. k (For example: 3rd harmonic 3f1, 5th harmonic 5f1, 7th harmonic 7f1, etc.) and their corresponding amplitude A k :

[0019]

[0020] Among them, A k is the amplitude of the kth harmonic, T is the sampling period, f1 is the fundamental frequency, and k is the order of the harmonic (e.g., the 3rd harmonic is k=3). By performing spectrum analysis on the current and voltage data collected under different load conditions, the main harmonic components and their amplitude ranges were determined.

[0021] Alternatively, in step S2, the acquired voltage and current signals are sent to an FPGA platform for spectrum analysis; on this platform, a Fast Fourier Transform (FFT) is used to perform frequency domain transformation on the signals to obtain the voltage and current spectra.

[0022]

[0023] Among them, f s is the sampling frequency, N is the number of sampling points, f is the frequency, j is the imaginary unit, and V(f) and I(f) are the spectral representations of the voltage and current signals, respectively.

[0024] Alternatively, in step S3, the basic idea of ​​the adaptive harmonic suppression algorithm is to adjust the filter coefficients h based on real-time spectrum data. mThis ensures that the filtered output signal y[n] can eliminate harmonic components as much as possible; specifically, for the suppression of the k-th harmonic, the filter's transfer function is optimized:

[0025] Among them, A k A1 is the amplitude of the kth harmonic, and f is the amplitude of the fundamental frequency. k Let f be the frequency of the kth harmonic, f be the frequency variable, and j be the imaginary unit; this transfer function describes the dynamic suppression process of the kth harmonic.

[0026] Then, this transfer function is used to generate a target harmonic frequency f. k filter coefficients h m The filter coefficients are then deployed on an FPGA platform. The FPGA calculates the filter coefficients for each time step through parallel computing and real-time adjustment, thereby dynamically adjusting the output current waveform.

[0027] For each sampling period, based on the real-time feedback spectrum data, the algorithm automatically adjusts the filter coefficients h. m To optimize the output signal y[n]:

[0028]

[0029] Where x[n] is the input signal, y[n] is the filtered output signal, and h m Here, h represents the filter coefficients, and M represents the filter length; by adjusting h... m It can accurately filter out harmonic components, especially suppressing high-order harmonics, making the output current waveform closer to the ideal state.

[0030] Alternatively, in step S4, the process of optimizing FPGA control parameters includes:

[0031] 1) Filter parameter optimization

[0032] Based on the latest harmonic amplitude and phase, the filter coefficients are recalculated to make the suppression of target harmonics more precise; the filter coefficient adjustment formula is:

[0033]

[0034] Where μ is the step size coefficient, which controls the update amplitude to prevent system instability;

[0035] 2) FPGA resource scheduling optimization

[0036] When the harmonic content is low and meets power grid standards, reduce the operating frequency f of the FFT calculation module and filter module. clk To reduce the dynamic power consumption of the FPGA; the power consumption can be approximated as:

[0037]

[0038] Among them, C L For the load capacitance, V dd f is the operating voltage. clk This is the system clock frequency; by reducing f clk It effectively reduces power consumption while ensuring real-time performance.

[0039] This invention enables high-frequency, continuous acquisition of voltage and current signals throughout the entire charging pile operation process, based on different load conditions. Combined with harmonic mathematical modeling under multiple operating conditions, it achieves precise characterization of different harmonic frequencies and amplitudes. Utilizing the high-speed parallel processing capabilities and adaptive harmonic suppression algorithms of FPGAs, signal acquisition, spectrum analysis, and harmonic identification are integrated on a single hardware platform, significantly improving the real-time performance and accuracy of data processing. The device automatically adjusts its suppression strategy when harmonic characteristics change, dynamically filtering out harmonic components of different orders, effectively reducing harmonic pollution to the power grid, ensuring the consistency of the output current waveform with power grid standards, guaranteeing the compatibility of the charging pile with the power grid, and enhancing the stability of the power system. Simultaneously, a feedback optimization mechanism is introduced to automatically optimize control parameters based on the harmonic suppression effect, reducing unnecessary computation and power consumption, and significantly improving the system's energy efficiency ratio while ensuring high suppression efficiency. This invention has significant advantages in improving power quality, extending equipment lifespan, and reducing power grid harmonic pollution, and provides technical support for the green development and intelligent operation of charging infrastructure. Attached Figure Description

[0040] Figure 1 The flowchart illustrates the harmonic mitigation method for household charging piles in urban residential areas provided by this invention. Detailed Implementation

[0041] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0042] This invention provides a method for harmonic mitigation of home charging piles in urban residential areas, with reference to... Figure 1 As shown, the method includes:

[0043] S1: Collect voltage and current data of charging piles under different operating conditions, analyze the characteristics of harmonic generation, construct a harmonic mathematical model, and determine the typical harmonic frequency and amplitude range.

[0044] Firstly, during the operation of the charging pile, voltage and current signals are collected under different operating conditions (multiple operating points) including no-load, low-load, medium-load, and full-load. The number of operating points is determined based on the rated power range of the charging pile and its sensitivity to harmonic characteristic changes. Typically, at least four typical operating points—no-load, low-load, medium-load, and full-load—are selected to ensure the comprehensiveness and accuracy of the harmonic generation mechanism modeling. For higher precision, power points can be further subdivided among these operating conditions, for example, data can be collected every 20% of the rated power, forming 5–6 operating points to ensure the accuracy and robustness of the model fitting. The sampling frequency is no less than 10kHz to ensure the capture of high-frequency harmonics. Assuming the collected current and voltage signals are i(t) and v(t), respectively, where t represents time, the signals are transmitted to the processing unit through the data acquisition module. Then, the collected time-domain signals are converted to frequency-domain signals using Fourier transform, and their spectrum is calculated.

[0045]

[0046] Here, I(f) and V(f) are the frequency domain representations of the current and voltage signals, respectively, where f is the frequency and j is the imaginary unit. The frequency domain signal obtained through Fourier transform can reveal the harmonic components in the signal; furthermore, the harmonic frequency f is identified. k (For example: 3rd harmonic 3f1, 5th harmonic 5f1, 7th harmonic 7f1, etc.) and their corresponding amplitude A k :

[0047]

[0048] Among them, A k is the amplitude of the kth harmonic, T is the sampling period, f1 is the fundamental frequency, and k is the order of the harmonic (e.g., the 3rd harmonic is k=3). By performing spectrum analysis on the current and voltage data collected under different load conditions, the main harmonic components and their amplitude ranges were determined.

[0049] To construct a mathematical model of harmonics in charging piles, considering the harmonic characteristics generated by charging piles under different loads, a simple model can be used to describe the variation law of harmonics:

[0050]

[0051] Where I1 is the fundamental amplitude, f1 is the fundamental frequency, and A k Let φ be the amplitude of the kth harmonic. k Let N be the phase of the kth harmonic, and N be the highest harmonic order considered.

[0052] By analyzing the voltage and current signals generated by charging piles under different operating conditions, the main harmonic frequencies (such as the 3rd, 5th, and 7th harmonics) were identified. Based on the harmonic frequency and amplitude data, a standard mathematical model of charging pile harmonics was constructed, providing a basis for subsequent harmonic suppression algorithms.

[0053] Finally, based on the harmonic frequencies and amplitude ranges obtained from the analysis, corresponding real-time harmonic mitigation strategies can be designed for charging piles to ensure that the current waveforms of charging piles under different load conditions comply with power grid standards and reduce harmonic pollution to the power grid.

[0054] S2: Based on the harmonic model, design an FPGA real-time data processing architecture, build a high-speed data acquisition module, and realize the real-time acquisition and accurate identification of harmonic signals;

[0055] Based on the spectrum data of the current and voltage signals obtained by Fourier transform in step S1, this step designs a real-time data processing architecture based on FPGA and builds a high-speed data acquisition module to realize real-time acquisition and accurate analysis of voltage and current signals during the operation of the charging pile.

[0056] First, in the data acquisition module, the voltage and current signals of the charging pile are sampled in real time at a frequency of not less than 10kHz using a high-speed analog-to-digital converter (ADC); the sampling period is set to T, and the resulting discrete signal sequence is as follows:

[0057] v[n]=v(t n ), i[n] = i(t) n (5)

[0058] Where n is the discrete-time index, t n = n·T represents the discrete sampling time; the acquired voltage and current signals are sent to the FPGA platform for spectrum analysis; on this platform, the Fast Fourier Transform (FFT) is used to perform frequency domain transformation on the signals to obtain the voltage and current spectra:

[0059]

[0060] Among them, f s is the sampling frequency, N is the number of sampling points, f is the frequency, j is the imaginary unit, and V(f) and I(f) are the spectral representations of the voltage and current signals, respectively.

[0061] By analyzing the spectral results V(f) and I(f), the main harmonic frequencies and their amplitudes in the signal are identified, especially the fundamental frequency f1 and higher harmonic frequencies (such as the 3rd harmonic 3f1, the 5th harmonic 5f1, etc.); assuming the amplitude A of the kth harmonic is... k It can be calculated using the following formula:

[0062]

[0063] Among them, A k f1 is the amplitude of the kth harmonic, f1 is the fundamental frequency, k is the order of the harmonic (e.g., the 3rd harmonic is k=3), and N is the number of sampling points.

[0064] Once the main harmonic frequencies and amplitudes are identified, the spectrum analysis module on the FPGA platform transmits this spectrum information to the real-time control module; the real-time control module then uses the identified harmonic frequencies f... k and amplitude A k A dynamic harmonic suppression strategy is employed; by adjusting the filter parameters, the target harmonic frequency is precisely suppressed; the filter's transfer function H(f) satisfies the following relationship:

[0065]

[0066] Where y[n] is the filtered output signal, x[n] is the input signal, and h m Here, h represents the filter coefficients, and M represents the filter length; by dynamically adjusting h... m It suppresses target harmonic frequency components in real time, reduces harmonic content, and ensures that the current waveform meets power grid standards.

[0067] Through the above process, the FPGA architecture can collect current and voltage signals in real time during the operation of the charging pile, perform spectrum analysis, quickly identify and accurately process harmonics, and ensure that the current waveform output by the charging pile meets the harmonic limit standards of the power grid. This real-time data processing architecture provides efficient data support for subsequent harmonic suppression algorithms and ensures the efficient and stable operation of the harmonic mitigation device under different load conditions.

[0068] S3: On the FPGA platform, based on real-time harmonic spectrum data, an adaptive harmonic suppression algorithm is deployed to dynamically filter out target harmonic frequencies and reduce harmonic content;

[0069] The core of step S3 is to utilize the parallel processing capability of the FPGA to deploy an adaptive harmonic suppression algorithm based on real-time spectrum data, thereby dynamically suppressing the harmonics generated in the charging pile.

[0070] First, using the voltage and current spectrum data V(f) and I(f) acquired in real time in step S2, the fundamental frequency f1 and its higher harmonic components (e.g., the 3rd harmonic 3f1, the 5th harmonic 5f1, etc.) are extracted on the FPGA platform; for each harmonic frequency f k According to amplitude A k and phase φ k Generate the transfer function of the harmonic filter.

[0071] To dynamically suppress target harmonics, an adaptive harmonic suppression algorithm is adopted. This algorithm dynamically adjusts the filter parameters based on real-time changes in spectrum data to ensure accurate suppression of harmonics generated under different load conditions. The goal of this algorithm is to minimize the harmonic content of the charging pile's output current so that the output current complies with the power grid's harmonic standards.

[0072] The basic idea of ​​the adaptive harmonic suppression algorithm is to adjust the filter coefficients h based on real-time spectrum data. m This ensures that the filtered output signal y[n] can eliminate harmonic components as much as possible; specifically, for the suppression of the k-th harmonic, the filter's transfer function is optimized:

[0073]

[0074] Among them, A k A1 is the amplitude of the kth harmonic, and f is the amplitude of the fundamental frequency. k Let f be the frequency of the k-th harmonic, f be the frequency variable, and j be the imaginary unit; this transfer function describes the dynamic suppression process of the k-th harmonic.

[0075] Then, this transfer function is used to generate a target harmonic frequency f. k filter coefficients h m The filter coefficients are then deployed on an FPGA platform. The FPGA calculates the filter coefficients for each time step through parallel computing and real-time adjustment, thereby dynamically adjusting the output current waveform.

[0076] For each sampling period, based on the real-time feedback spectrum data, the algorithm automatically adjusts the filter coefficients h. m To optimize the output signal y[n]:

[0077]

[0078] Where x[n] is the input signal, y[n] is the filtered output signal, and h m Here, h represents the filter coefficients, and M represents the filter length; by adjusting h... m It can accurately filter out harmonic components, especially suppressing high-order harmonics, making the output current waveform closer to the ideal state.

[0079] In this adaptive algorithm, the filter parameters are adjusted in real time according to the changes in the charging pile load, thereby ensuring that the target harmonic frequency can still be effectively suppressed when the load fluctuates or the operating conditions change. The real-time feedback mechanism makes the method highly adaptable and flexible, and can quickly respond to harmonic changes under different loads, ensuring the stability of the charging pile operation and the harmonic requirements of the power grid.

[0080] Through this process, the FPGA platform can accurately suppress various harmonics generated by charging piles and dynamically adjust the suppression strategy to ensure that the current waveform output by the charging piles meets the harmonic standards of the power grid, effectively reducing power grid pollution. At the same time, by dynamically optimizing the control parameters of the filter, the performance of the harmonic mitigation device is maximized.

[0081] S4: Based on the feedback of the suppression effect, optimize the FPGA control parameters to reduce the device's energy consumption and cost, achieving a balance between accurate and efficient harmonic control performance and economy.

[0082] The core of step S4 is to introduce a feedback optimization mechanism for harmonic suppression effect, dynamically optimize the control parameters in the FPGA platform, so that the harmonic mitigation device can reduce energy consumption and control the cost of hardware resources while maintaining high suppression efficiency.

[0083] First, after harmonic suppression is completed in step S3, the total harmonic distortion (THD) of the output current is monitored in real time as the core indicator for evaluating the harmonic mitigation effect; the THD calculation formula is:

[0084]

[0085] Where A1 is the fundamental amplitude, A k Let N be the amplitude of the k-th harmonic, and N be the highest harmonic number considered; when the real-time calculated THD is higher than the set threshold THD... max At this time, the system will trigger a parameter optimization process.

[0086] The optimization process includes two aspects:

[0087] 1. Filter parameter optimization

[0088] Based on the latest harmonic amplitude and phase, the filter coefficients are recalculated to make the suppression of target harmonics more precise; the filter coefficient adjustment formula is:

[0089]

[0090] Where μ is the step size coefficient, which controls the update amplitude to prevent system instability.

[0091] 2. FPGA resource scheduling optimization

[0092] When the harmonic content is low and meets power grid standards, reduce the operating frequency f of the FFT calculation module and filter module. clk To reduce the dynamic power consumption of the FPGA; the power consumption can be approximated as:

[0093]

[0094] Among them, C L For the load capacitance, V dd f is the operating voltage. clk This is the system clock frequency; by reducing f clk It effectively reduces power consumption while ensuring real-time performance.

[0095] In addition, the device continuously records the harmonic suppression effect and energy consumption data under different operating conditions to form an optimization database. When a similar operating condition is detected, the system can directly call the optimal parameter combination in the database, thereby reducing the amount of real-time calculation and speeding up the response.

[0096] Ultimately, through the above optimization strategies, the harmonic mitigation device can achieve low-energy operation while ensuring that the output current waveform meets the power grid harmonic standards (THD is lower than the set value), and reduce FPGA resource utilization and equipment maintenance costs, thus achieving a balance between precise mitigation and economic efficiency.

[0097] To verify the effectiveness of the method of the present invention, a simulation model of harmonic mitigation of household charging piles in urban communities was built using the MATLAB / Simulink platform. The simulation object was a single-phase household AC charging pile with a rated power of 7kW, an input voltage of 220V, a sampling frequency of 20kHz, and a maximum consideration of the 25th harmonic component.

[0098] 1. Operating Condition Settings

[0099] Operating condition 1: Low load (2kW), the main harmonics are the 3rd and 5th harmonics, and the THD is about 8.2%.

[0100] Operating condition 2: Medium load (4kW), the harmonic amplitude increases, mainly the 3rd, 5th and 7th harmonics, with a THD of about 12.6%.

[0101] Operating condition 3: Full load (7kW), high-order harmonics are significant, THD exceeds 18%.

[0102] 2. Simulation Result Data Table

[0103] Table 1 shows the suppression effect of the method of the present invention on the harmonics of the output current of the charging pile under different load power. As can be seen from the data in the table, the harmonic content increases significantly with the increase of load power. The method of the present invention can effectively reduce the total harmonic distortion (THD) to below 5% under all three operating conditions, meeting the power grid standard. At the same time, under medium and high load conditions, the FPGA clock frequency is reduced through the feedback optimization mechanism, achieving a power consumption reduction of 8%–15%.

[0104] Table 1 Harmonic suppression results under different load conditions

[0105]

[0106] Table 2 Comparison results of the method of the present invention and the traditional fixed filtering method

[0107]

[0108] Table 2 compares the method of this invention with the traditional fixed filter method. Under the same operating conditions, the THD suppression effect of the method of this invention is significantly better than that of the traditional method, with an average improvement of more than 30%. In addition, this invention can achieve energy efficiency management through a feedback optimization mechanism, while the traditional method does not have this function, demonstrating the comprehensive advantages of this invention in terms of suppression effect and energy efficiency optimization.

[0109] Simulation results demonstrate that the FPGA-based adaptive harmonic mitigation method proposed in this invention can effectively suppress harmonic pollution from charging piles under different load conditions, reducing THD from 8%–18% to below 5%, meeting the State Grid standard. Compared with traditional fixed filter methods, this invention exhibits more stable suppression performance under load fluctuations, with an average improvement exceeding 35%. Simultaneously, by dynamically reducing the FPGA clock frequency through a feedback optimization mechanism, an 8%–15% power consumption reduction is achieved, balancing energy efficiency and economy while ensuring effective harmonic mitigation. This verifies the significant advantages of this invention in improving power quality, reducing grid harmonic pollution, and promoting green energy conservation.

[0110] This invention proposes a harmonic mitigation device and optimization method for household charging piles in urban communities. By continuously acquiring voltage and current signals at high frequency throughout the entire charging pile operation process, and combining this with harmonic mathematical modeling under multiple operating conditions, it achieves accurate characterization of different harmonic frequencies and amplitudes. Utilizing the high-speed parallel processing capabilities of an FPGA, signal acquisition, spectrum analysis, and harmonic identification are integrated into a single hardware platform, significantly improving the real-time performance and accuracy of data processing. The device can automatically adjust its suppression strategy when harmonic characteristics change, dynamically filtering out harmonic components of different orders, effectively ensuring the consistency of the output current waveform with the power grid standard. Simultaneously, a feedback optimization mechanism is introduced to automatically optimize control parameters based on the harmonic suppression effect, reducing unnecessary computation and power consumption, and significantly improving the system's energy efficiency ratio while ensuring high suppression efficiency. This invention has significant advantages in improving power quality, extending equipment lifespan, and reducing grid harmonic pollution, and provides technical support for the green development and intelligent operation of charging infrastructure.

[0111] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for harmonic mitigation of home charging piles in urban residential communities, characterized in that, Includes the following steps: S1: Collect voltage and current data of charging piles under different operating conditions, analyze the characteristics of harmonic generation, construct a harmonic mathematical model, and determine the typical harmonic frequency and amplitude range. S2: Based on the harmonic model, design an FPGA real-time data processing architecture, build a high-speed data acquisition module, and realize the real-time acquisition and accurate identification of harmonic signals; S3: On the FPGA platform, based on real-time harmonic spectrum data, an adaptive harmonic suppression algorithm is deployed to dynamically filter out target harmonic frequencies and reduce harmonic content; S4: Based on the feedback of the suppression effect, optimize the FPGA control parameters to reduce the device's energy consumption and cost, achieving a balance between accurate and efficient harmonic control performance and economy.

2. The method for harmonic mitigation of household charging piles in urban residential areas according to claim 1, characterized in that, In step S1, the collected voltage and current data cover multiple operating points of the charging pile from no-load, low-load, medium-load to full-load states, ensuring the comprehensiveness and accuracy of the harmonic generation mechanism.

3. The method for harmonic mitigation of household charging piles in urban residential areas according to claim 1, characterized in that, In step S2, the high-speed data acquisition module acquires the voltage and current signals of the charging pile at a frequency of at least 10kHz and transmits the acquired data to the FPGA platform for real-time processing.

4. The method for harmonic mitigation of household charging piles in urban residential areas according to claim 1, characterized in that, In step S3, the adaptive harmonic suppression algorithm automatically adjusts the filtering parameters and the suppression strategy in real time by comparing real-time spectrum data with preset harmonic standards.

5. The harmonic method for household charging piles in urban residential areas according to claim 1, characterized in that, In step S4, the process of optimizing FPGA control parameters includes filter parameter optimization, which involves recalculating filter coefficients based on real-time harmonic amplitude and phase; FPGA resource scheduling optimization, which reduces the operating frequency of the computing module to reduce power consumption when the harmonic content is below a threshold; and calling the optimization database to directly adopt the historical optimal parameter combination to shorten the response time when similar operating conditions occur.

6. The harmonic method for household charging piles in urban residential areas according to claim 2, characterized in that, In step S1, it is assumed that the acquired current and voltage signals are i(t) and v(t), respectively, where t represents time. The signals are transmitted to the processing unit through the data acquisition module. Then, the acquired time-domain signals are converted into frequency-domain signals through Fourier transform, and their spectrum is calculated. Here, I(f) and V(f) are the frequency domain representations of the current and voltage signals, respectively, where f is the frequency and j is the imaginary unit. The frequency domain signal obtained through Fourier transform can reveal the harmonic components in the signal; furthermore, the harmonic frequency fk and its corresponding amplitude A are identified. k : Among them, A k is the amplitude of the kth harmonic, T is the sampling period, f1 is the fundamental frequency, and k is the harmonic order; by performing spectrum analysis on the current and voltage data collected under different load conditions, the main harmonic components and their amplitude ranges were determined.

7. The harmonic method for household charging piles in urban residential areas according to claim 3, characterized in that, In step S2, the acquired voltage and current signals are sent to the FPGA platform for spectrum analysis; on this platform, the Fast Fourier Transform (FFT) is used to perform frequency domain transformation on the signals to obtain the voltage and current spectra. Among them, f s is the sampling frequency, N is the number of sampling points, f is the frequency, j is the imaginary unit, and V(f) and I(f) are the spectral representations of the voltage and current signals, respectively.

8. The harmonic method for household charging piles in urban residential areas according to claim 4, characterized in that, In step S3, the basic idea of ​​the adaptive harmonic suppression algorithm is to adjust the filter coefficients h based on real-time spectrum data. m This ensures that the filtered output signal y[n] can eliminate harmonic components as much as possible; specifically, for the suppression of the k-th harmonic, the filter's transfer function is optimized: Among them, A k A1 is the amplitude of the kth harmonic, and f is the amplitude of the fundamental frequency. k Let f be the frequency of the kth harmonic, f be the frequency variable, and j be the imaginary unit; this transfer function describes the dynamic suppression process of the kth harmonic. Then, this transfer function is used to generate a target harmonic frequency f. k filter coefficients h m The filter coefficients are then deployed on an FPGA platform. The FPGA calculates the filter coefficients for each time step through parallel computing and real-time adjustment, thereby dynamically adjusting the output current waveform. For each sampling period, based on the real-time feedback spectrum data, the algorithm automatically adjusts the filter coefficients h. m To optimize the output signal y[n]: Where x[n] is the input signal, y[n] is the filtered output signal, and h m Here, h represents the filter coefficients, and M represents the filter length; by adjusting h... m It can accurately filter out harmonic components, especially suppressing high-order harmonics, making the output current waveform closer to the ideal state.

9. The harmonic method for household charging piles in urban residential areas according to claim 5, characterized in that, In step S4, the process of optimizing FPGA control parameters includes: 1) Filter parameter optimization Based on the latest harmonic amplitude and phase, the filter coefficients are recalculated to make the suppression of target harmonics more precise; the filter coefficient adjustment formula is: Where μ is the step size coefficient, which controls the update amplitude to prevent system instability; 2) FPGA resource scheduling optimization When the harmonic content is low and meets power grid standards, reduce the operating frequency f of the FFT calculation module and filter module. clk To reduce the dynamic power consumption of the FPGA; the power consumption can be approximated as: Among them, C L For the load capacitance, V dd f is the operating voltage. clk This is the system clock frequency; by reducing f clk It effectively reduces power consumption while ensuring real-time performance.

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