Continuous time linear equalizer, signal receiving circuit and chip

Abstract

The present disclosure relates to a continuous-time linear equalizer, a signal receiving circuit and a chip, the continuous-time linear equalizer comprising: a main current source; a first auxiliary current source; a second auxiliary current source; a receiver module coupled to the main current source, configured to receive a pair of differential input signals and output a pair of differential main output signals; a third auxiliary current source; a folded signal receiving module coupled to the third auxiliary current source, configured to receive the differential input signals and output a pair of differential auxiliary output signals; and an output load module coupled to the first auxiliary current source, the second auxiliary current source, the receiver module and the folded signal receiving module, configured to receive the differential main output signals and the differential auxiliary output signals, generate equalized differential signals according to the differential main output signals and the differential auxiliary output signals, and provide a pair of zero-poles for the equalized differential signals. The present disclosure realizes rail-to-rail input and high bandwidth application of the continuous-time linear equalizer, and can be controlled to be turned off to save power consumption.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a continuous time linear equalizer, a signal receiving circuit and a chip. BACKGROUND

[0002] A continuous time linear equalizer (CTLE) is an analog signal conditioning circuit widely used in high-speed serial links, mainly used to compensate for frequency-dependent losses caused by the channel. As the data rate increases to several Gbps (gigabits per second) or even higher, the signal will produce serious intersymbol interference in the transmission medium (such as PCB (Printed Circuit Board) traces, cables) due to skin effect and dielectric loss, resulting in the closing of the eye diagram at the receiving end. The continuous time linear equalizer works in the analog domain and is located at the front end of the receiver. By increasing the high-frequency component gain and suppressing the low-frequency gain, the high-frequency attenuation of the channel is offset, and the eye diagram is reopened.

[0003] For the continuous time linear equalizer, the priority of the high-frequency performance in the signal is much higher than the voltage swing, so the continuous time linear equalizer avoids rail-to-rail input. The continuous time linear equalizers used in related technologies are not designed for rail-to-rail input, which limits the application range of the continuous time linear equalizer in application scenarios. However, with the continuous development of integrated circuit technology, various application scenarios are constantly emerging, and potential requirements for continuous time linear equalizers that can realize rail-to-rail input have appeared.

[0004] In addition, as the signal transmission speed continues to increase, the signal receiving circuit (RX circuit) needs to consume a large current in order to meet sufficient bandwidth. In addition, the number of signal channels is increasing, which leads to the continuous increase of power consumption of the signal receiving circuit. Therefore, how to reduce the power consumption of the signal receiving circuit is also a problem that technicians in the field are constantly exploring. SUMMARY

[0005] Therefore, the present disclosure provides a continuous time linear equalizer, a signal receiving circuit and a chip to realize rail-to-rail input of the continuous time linear equalizer, enhance the compatibility and robustness of the continuous time linear equalizer, enable it to more flexibly receive data signals of different protocols or voltage standards, improve the tolerance of the signal receiving circuit to common-mode noise and power supply fluctuations, expand its more application scenarios, and on this basis, realize the signal receiving circuit to be turned on when in use and turned off when not in use, so as to reduce the overall power consumption of the signal receiving circuit during the working process of the chip.

[0006] According to an aspect of an embodiment of the present disclosure, a continuous time linear equalizer is provided, comprising:

[0007] a main current source;

[0008] a first sub current source;

[0009] a second sub current source;

[0010] a receiver module, coupled to the main current source, for receiving a pair of differential input signals and outputting a pair of differential main output signals when the main current source is powered;

[0011] a third sub current source;

[0012] a folded signal receiving module, coupled to the third sub current source, for receiving the differential input signals synchronously with the receiver module and outputting a pair of differential auxiliary output signals when the third sub current source is powered;

[0013] an output load module, coupled to the first sub current source, the second sub current source, the receiver module and the folded signal receiving module, for receiving the differential main output signals and the differential auxiliary output signals when the first sub current source and the second sub current source are powered, generating equalized differential signals according to the differential main output signals and the differential auxiliary output signals, and providing a pair of zero-pole for the equalized differential signals.

[0014] In a possible implementation, the output load module comprises:

[0015] a first output load sub-module, coupled to the first sub current source, the receiver module and the folded signal receiving module, for receiving a first differential signal in the differential main output signals and a first differential signal in the differential auxiliary output signals when the first sub current source is powered, generating a first differential signal in the equalized differential signals according to the first differential signal in the differential main output signals and the first differential signal in the differential auxiliary output signals, providing output load for a first differential signal main output terminal of the receiver module and a first differential signal auxiliary output terminal of the folded signal receiving module, and providing a pair of zero-pole for the first differential signal in the equalized differential signals;

[0016] a second output load sub-module coupled to the second auxiliary current source, the receiver module and the folded signal receiving module, configured to receive a second differential signal in the differential main output signal and a second differential signal in the differential auxiliary output signal under the power supply of the second auxiliary current source, and generate a second differential signal in the balanced differential signal according to the second differential signal in the differential main output signal and the second differential signal in the differential auxiliary output signal, the second output load sub-module providing an output load for a second differential signal main output end of the receiver module and a second differential signal auxiliary output end of the folded signal receiving module, and providing a pair of zero poles for the second differential signal in the balanced differential signal.

[0017] In a possible implementation, the receiver module comprises:

[0018] a first differential signal receiving transistor, a first end of the first differential signal receiving transistor being coupled to the main current source, a control end of the first differential signal receiving transistor being a first differential signal main receiving end of the receiver module to receive a first differential signal in the differential input signal, and a second end of the first differential signal receiving transistor being a first differential signal main output end of the receiver module to output a first differential signal in the differential main output signal;

[0019] a second differential signal receiving transistor, a first end of the second differential signal receiving transistor being coupled to the main current source, a control end of the second differential signal receiving transistor being a second differential signal main receiving end of the receiver module to receive a second differential signal in the differential input signal, and a second end of the second differential signal receiving transistor being a second differential signal main output end of the receiver module to output a second differential signal in the differential main output signal;

[0020] a first output common mode feedback resistor, a first end of the first output common mode feedback resistor being coupled to the second end of the first differential signal receiving transistor;

[0021] a second output common mode feedback resistor, a first end of the second output common mode feedback resistor being coupled to the second end of the second differential signal receiving transistor, and a second end of the second output common mode feedback resistor being coupled to a second end of the first output common mode feedback resistor;

[0022] a first receiver load transistor, a first end of the first receiver load transistor being grounded, a second end of the first receiver load transistor being coupled to the second end of the first differential signal receiving transistor, and a control end of the first receiver load transistor being coupled to the second end of the first output common mode feedback resistor and the second end of the second output common mode feedback resistor;

[0023] a second receiver load transistor, a first end of the second receiver load transistor being grounded, a second end of the second receiver load transistor being coupled to a second end of the second differential signal receiving transistor, and a control end of the second receiver load transistor being coupled to a second end of the first output common mode feedback resistor and a second end of the second output common mode feedback resistor.

[0024] In a possible implementation, the folded signal receiving module comprises:

[0025] a third differential signal receiving transistor, a first end of the third differential signal receiving transistor being coupled to the third auxiliary current source, a control end of the third differential signal receiving transistor being a first differential signal auxiliary receiving end of the folded signal receiving module, and a second end of the third differential signal receiving transistor being a first differential signal auxiliary output end of the folded signal receiving module to output a first belief signal in the differential auxiliary output signal;

[0026] a fourth differential signal receiving transistor, a first end of the fourth differential signal receiving transistor being coupled to the third auxiliary current source, a control end of the fourth differential signal receiving transistor being a second differential signal auxiliary receiving end of the folded signal receiving module, and a second end of the fourth differential signal receiving transistor being a second differential signal auxiliary output end of the folded signal receiving module to output a second belief signal in the differential auxiliary output signal.

[0027] In a possible implementation, the first output load sub-module comprises:

[0028] a first load resistor module, a first end of the first load resistor module being coupled to the first auxiliary current source and the first differential signal auxiliary output end;

[0029] a third load transistor, a first end of the third load transistor being grounded, a second end of the third load transistor being coupled to a second end of the first load resistor module and the first differential signal main output end;

[0030] a first compensation resistor, a first end of the first compensation resistor being coupled to the second end of the first load resistor module and the first differential signal main output end;

[0031] a first compensation capacitor module, a first end of the first compensation capacitor module being coupled to the control end of the third load transistor and a second end of the first compensation resistor, and a second end of the first compensation capacitor module being grounded;

[0032] the second output load sub-module comprises:

[0033] a second load resistor module, a first end of the second load resistor module being coupled to the second auxiliary current source and the second differential signal auxiliary output terminal;

[0034] a fourth load transistor, a first end of the fourth load transistor being grounded, a second end of the fourth load transistor being coupled to a second end of the second load resistor module and the second differential signal main output terminal;

[0035] a second compensation resistor, a first end of the second compensation resistor being coupled to the second end of the second load resistor module and the second differential signal main output terminal;

[0036] a second compensation capacitor module, a first end of the second compensation capacitor module being coupled to a control terminal of the fourth load transistor and a second end of the second compensation resistor, a second end of the second compensation capacitor module being grounded.

[0037] In a possible implementation, the first load resistor module comprises a first load transistor, a first end of the first load transistor being the first end of the first load resistor module, a second end of the first load transistor being the second end of the first load resistor module, a control terminal of the first load transistor receiving a clamping voltage, in operation, the first load transistor works in saturation region under the action of the clamping voltage.

[0038] the second load resistor module comprises a second load transistor, a first end of the second load transistor being the first end of the second load resistor module, a second end of the second load transistor being the second end of the second load resistor module, a control terminal of the second load transistor receiving the clamping voltage, in operation, the second load transistor works in saturation region under the action of the clamping voltage.

[0039] According to another aspect of the embodiments of the present disclosure, a signal receiving circuit is provided, comprising:

[0040] a continuous-time linear equalizer according to any one of the preceding items;

[0041] a bias clamping module, coupled to the main current source, the first auxiliary current source, the second auxiliary current source and the third auxiliary current source, for generating a bias voltage and controlling the currents of the main current source, the first auxiliary current source, the second auxiliary current source and the third auxiliary current source through the bias voltage;

[0042] a voltage gain amplification module, coupled to the continuous-time linear equalizer, configured to receive a first switch enable signal, a first inverted switch enable signal and the equalized differential signal, operate or shut down according to the first switch enable signal and the first inverted switch enable signal, and in the operating state, amplify the equalized differential signal to obtain an amplified differential signal;

[0043] a differential-to-single-ended output module, coupled to the voltage gain amplification module, configured to receive a second switch enable signal and the amplified differential signal, operate or shut down according to the second switch enable signal, and in the operating state, convert the amplified differential signal into a single-ended output signal and output the single-ended output signal;

[0044] a switch control module, coupled to the main current source, the first auxiliary current source, the second auxiliary current source and the voltage gain amplification module, configured to receive the first switch enable signal, generate the first inverted switch enable signal and a controlled source voltage according to the first switch enable signal, wherein the main current source, the first auxiliary current source and the second auxiliary current source operate under the action of the controlled source voltage;

[0045] a switch matching module, coupled to the bias clamping module, configured to generate a matching source voltage matched with the controlled source voltage, so that the bias clamping module generates the bias voltage based on the matching source voltage;

[0046] In the continuous-time linear equalizer, the semiconductor device in the bias clamping module, the semiconductor device in the switch control module and the semiconductor device in the switch matching module are semiconductor devices suitable for a first working voltage domain, the semiconductor device in the voltage gain amplification module is a semiconductor device suitable for a second working voltage domain and resistant to the first working voltage domain, and the semiconductor device in the differential-to-single-ended output module is a semiconductor device suitable for the second working voltage domain, wherein the first working voltage domain is higher than the second working voltage domain.

[0047] In a possible implementation, the bias clamping module includes:

[0048] a bias current source;

[0049] a bias clamping circuit resistance, a second end of the bias clamping circuit resistance being coupled to the bias current source;

[0050] a clamping transistor, a second end of the clamping transistor being coupled to a first end of the bias clamping circuit resistance, and a control end of the clamping transistor being coupled to a second end of the bias clamping circuit resistance;

[0051] a biasing transistor, a first end of the biasing transistor being connected to the matching source voltage, a second end of the biasing transistor being coupled to a first end of the clamping transistor, a control end of the biasing transistor being coupled to a second end of the clamping transistor, wherein the matching source voltage matches the controlled source voltage, the control end of the biasing transistor generates the bias voltage, and the control end of the clamping transistor generates a clamping voltage, wherein the control end of the biasing transistor is coupled to the main current source, the first auxiliary current source, and the second auxiliary current source, thereby forming a current mirror with the biasing transistor, the main current source, the first auxiliary current source, and the second auxiliary current source, such that a current flowing through the biasing transistor is copied into a current of the main current source, a current of the first auxiliary current source, and a current of the second auxiliary current source;

[0052] a first replica transistor, a first end of the first replica transistor being coupled to the first end of the biasing transistor, a control end of the first replica transistor being coupled to the control end of the biasing transistor, thereby forming a current mirror with the biasing transistor and the first replica transistor, such that a current flowing through the biasing transistor is copied into a current flowing through the first replica transistor;

[0053] a second replica transistor, a first end of the second replica transistor being coupled to a second end of the first replica transistor, a control end of the second replica transistor being coupled to the control end of the clamping transistor;

[0054] a reference transistor, a first end of the reference transistor being connected to ground, a second end of the reference transistor being coupled to a second end of the second replica transistor, a control end of the reference transistor being coupled to the second end of the reference transistor, the control end of the reference transistor being coupled to the third auxiliary current source, thereby forming a current mirror with the reference transistor and the third auxiliary current source, such that a current flowing through the reference transistor is copied into a current flowing through the third auxiliary current source.

[0055] In one possible implementation, the switch control module comprises:

[0056] a first switch circuit transistor, a first end of the first switch circuit transistor being coupled to the first operating voltage;

[0057] a second switch circuit transistor, a first end of the second switch circuit transistor being connected to ground, a control end of the second switch circuit transistor being coupled to a control end of the first switch circuit transistor and receiving the first switch enable signal, a second end of the second switch circuit transistor being coupled to a second end of the first switch circuit transistor, a junction of the second end of the second switch circuit transistor and the second end of the first switch circuit transistor generating the first inverted switch enable signal;

[0058] The third switching circuit transistor, wherein the first terminal of the third switching circuit transistor is coupled to the first operating voltage;

[0059] A fourth switching transistor, wherein the first terminal of the fourth switching transistor is grounded, the control terminal of the fourth switching transistor is coupled to the control terminal of the third switching transistor, and the control terminals of the fourth and third switching transistors are coupled to the second terminals of the first and second switching transistors, respectively. The second terminal of the fourth switching transistor is coupled to the second terminal of the third switching transistor, and the controlled source voltage is generated at the coupling point between the second terminals of the fourth and third switching transistors.

[0060] Wherein, the voltage domain of the first switch enable signal, the first inverting switch enable signal, and the controlled source voltage is the voltage domain of the first operating voltage.

[0061] In one possible implementation, the switch matching module includes:

[0062] A first matching transistor, wherein a first terminal of the first matching transistor is coupled to the first operating voltage, and a second terminal of the first matching transistor is coupled to the control terminal of the first matching transistor;

[0063] The second matching transistor has a first terminal grounded and a second terminal coupled to the control terminal of the first matching transistor.

[0064] A third matching transistor, wherein the first terminal of the third matching transistor is coupled to the first operating voltage, the control terminal of the third matching transistor is coupled to the second terminal of the second matching transistor, and the second terminal of the third matching transistor is coupled to the bias clamping module and generates the matching source voltage.

[0065] In one possible implementation, the voltage gain amplification module includes:

[0066] A first signal amplification and receiving transistor, the control terminal of which is coupled to the continuous-time linear equalizer to receive the positive phase signal in the equalized differential signal, and the first terminal of which is grounded.

[0067] a first amplification switch transistor, a control terminal of the first amplification switch transistor being coupled to the switch control module to receive the first inverting switch enable signal, a first terminal of the first amplification switch transistor being grounded, and a second terminal of the first amplification switch transistor being coupled to a control terminal of the first signal amplification receiving transistor;

[0068] a second signal amplification receiving transistor, a control terminal of the second signal amplification receiving transistor being coupled to the continuous time linear equalizer to receive an inverting signal in the equalized differential signal, and a first terminal of the second signal amplification receiving transistor being grounded;

[0069] a second amplification switch transistor, a control terminal of the second amplification switch transistor being coupled to the switch control module to receive the first inverting switch enable signal, a first terminal of the second amplification switch transistor being grounded, and a second terminal of the second amplification switch transistor being coupled to the control terminal of the second signal amplification receiving transistor;

[0070] a first amplification circuit transistor, a first terminal of the first amplification circuit transistor being coupled to the second operating voltage, and a second terminal of the first amplification circuit transistor being coupled to a second terminal of the first signal amplification receiving transistor;

[0071] a first amplification circuit common mode feedback resistor, a first terminal of the first amplification circuit common mode feedback resistor being coupled to the second terminal of the first amplification circuit transistor;

[0072] a second amplification circuit transistor, a first terminal of the second amplification circuit transistor being coupled to the second operating voltage, and a second terminal of the second amplification circuit transistor being coupled to a second terminal of the second signal amplification receiving transistor;

[0073] a second amplification circuit common mode feedback resistor, a first terminal of the second amplification circuit common mode feedback resistor being coupled to the second terminal of the second amplification circuit transistor, a second terminal of the second amplification circuit common mode feedback resistor being coupled to the second terminal of the second amplification circuit transistor, a control terminal of the first amplification circuit transistor, and a control terminal of the second amplification circuit transistor, the second terminal of the first amplification circuit transistor generating a positive signal in the amplified differential signal, and the second terminal of the second amplification circuit transistor generating an inverting signal in the amplified differential signal;

[0074] a third amplification switch transistor, a control terminal of the third amplification switch transistor receiving the first switch enable signal, a first terminal of the third amplification switch transistor being coupled to the second operating voltage, and a second terminal of the third amplification switch transistor being coupled to the second terminal of the first amplification circuit transistor.

[0075] In a possible implementation, the differential-to-single-ended output module comprises:

[0076] an inverter, an input terminal of the inverter receiving the second switch enable signal;

[0077] a first differential-to-single-ended receiving transistor, a control terminal of the first differential-to-single-ended receiving transistor being coupled to the voltage gain amplification module to receive a positive signal in the amplified differential signal, a first terminal of the first differential-to-single-ended receiving transistor being coupled to the second operating voltage;

[0078] a second differential-to-single-ended receiving transistor, a control terminal of the second differential-to-single-ended receiving transistor being coupled to the voltage gain amplification module to receive a negative signal in the amplified differential signal, a first terminal of the second differential-to-single-ended receiving transistor being coupled to the second operating voltage;

[0079] a first current copying transistor, a first terminal of the first current copying transistor being grounded, a second terminal and a control terminal of the first current copying transistor being coupled to a second terminal of the first differential-to-single-ended receiving transistor;

[0080] a second current copying transistor, a first terminal of the second current copying transistor being grounded, a control terminal of the second current copying transistor being coupled to a control terminal of the first current copying transistor, the first current copying transistor and the second current copying transistor constituting a current mirror, so that a current flowing through the first current copying transistor is copied into a current flowing through the second current copying transistor;

[0081] a first differential-to-single-ended switch transistor, a first terminal of the first differential-to-single-ended switch transistor being grounded, a second terminal of the first differential-to-single-ended switch transistor being coupled to a control terminal of the second current copying transistor, a control terminal of the first differential-to-single-ended switch transistor being coupled to an output terminal of the inverter;

[0082] a second differential-to-single-ended switch transistor, a first terminal of the second differential-to-single-ended switch transistor being coupled to a second terminal of the second differential-to-single-ended receiving transistor, a second terminal of the second differential-to-single-ended switch transistor being coupled to a second terminal of the second current copying transistor, the single-ended output signal being generated at the second terminal of the second differential-to-single-ended switch transistor, the single-ended output signal being output from an output terminal of the differential-to-single-ended output module, a control terminal of the second differential-to-single-ended switch transistor being coupled to the output terminal of the inverter.

[0083] According to another aspect of the embodiments of the present disclosure, a chip is provided, comprising the continuous-time linear equalizer as claimed in any one of the above.

[0084] From the above scheme, it can be seen that the continuous time linear equalizer, the signal receiving circuit and the chip of the present disclosure can realize all bias points in the receiver module by using one main current source. Only one main current source is needed to pour a current into the receiver module, and the receiver module can work. In the continuous time linear equalizer of the present disclosure, the differential auxiliary output signal of the folded signal receiving module is introduced into the differential main output signal of the receiver module by using the output load module coupled to the first auxiliary current source and the second auxiliary current source, so as to realize the rail-to-rail input of the continuous time linear equalizer. On the basis of realizing the rail-to-rail input of the continuous time linear equalizer, the output load module provides zero-pole for the generated equalized differential signal, so as to realize the high-bandwidth application of the continuous time linear equalizer, so that the continuous time linear equalizer can receive and process high-speed transmission signals.

[0085] The signal receiving circuit of the present disclosure is realized on the basis of the continuous time linear equalizer. In addition to the related effects of the continuous time linear equalizer, the signal receiving circuit also realizes the transition of signals from the circuit in the voltage domain of the first operating voltage to the circuit in the voltage domain of the second operating voltage. In addition, the signal receiving circuit also realizes the switching function, so as to turn on the signal receiving circuit when in use and turn off the signal receiving circuit when not in use to save power consumption, thereby helping to reduce the overall power consumption of the signal receiving circuit during the working process of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0086] Figure 1 is a structural block diagram of a continuous time linear equalizer according to an illustrative embodiment;

[0087] Figure 2 is a circuit structure schematic diagram of a continuous time linear equalizer according to an illustrative embodiment;

[0088] Figure 3 is an AC characteristic curve schematic diagram of the continuous time linear equalizer of the embodiment of the present disclosure;

[0089] Figure 4 is a structural block diagram of a signal receiving circuit according to an illustrative embodiment;

[0090] Figure 5 is a circuit structure schematic diagram of a signal receiving circuit according to an illustrative embodiment.

[0091] In the drawings, the component names represented by each reference numeral are as follows:

[0092] MS, main current source, SS1, first auxiliary current source, SS2, second auxiliary current source, 101, receiver module, SS3, third auxiliary current source, 102, folded signal receiving module, 103, output load module, 1031, first output load submodule, 1032, second output load submodule, T11, first differential signal receiving transistor, T12, second differential signal receiving transistor, R11, first output common mode feedback resistor, R12, second output common mode feedback resistor, T13, first receiver load transistor, T14, second receiver load transistor, T21, third differential signal receiving transistor, T22, fourth differential signal receiving transistor, T33, third load transistor, R31, first compensation resistor, CM31, first compensation capacitor module, T34, fourth load transistor, R32, second compensation resistor, CM32, second compensation capacitor module, T31, first load transistor, T32, second load transistor, BIASP2, clamping voltage, BIASP1, bias voltage, 100, continuous-time linear equalizer, 200, bias clamping module, 300, voltage gain amplification module, 400, differential to single-ended output module, 500, switch control module, 600, switch matching module, isource, bias current source, R41, bias clamping circuit resistor, T41, clamping transistor, T42, bias transistor, T43, first replica transistor, T44, second replica transistor, T45, reference transistor, T50, main current transistor, T51, first auxiliary current transistor, T52, second auxiliary current transistor, T53, third auxiliary current transistor, T61, first switch circuit transistor, T62, second switch circuit transistor, T63, third switch circuit transistor, T64, fourth switch circuit transistor, T71, first matching transistor, T72, second matching transistor, T73, third matching transistor, T81, first signal amplification receiving transistor, T82, first amplification switch transistor, T83, second signal amplification receiving transistor, T84, second amplification switch transistor, T85, first amplification circuit transistor, R81, first amplification circuit common mode feedback resistor, T86, second amplification circuit transistor, R82, second amplification circuit common mode feedback resistor, T87, third amplification switch transistor, INV, inverter, T91, first differential to single-ended receiving transistor, T92, second differential to single-ended receiving transistor, T93, first current replica transistor, T94, second current replica transistor, T95, first differential to single-ended switch transistor, T96, second differential to single-ended switch transistor, INP, positive signal in differential input signal, INN, negative signal in differential input signal, OUTP, first differential signal main output terminal, OUTN, second differential signal main output terminal, OUT, output terminal of differential to single-ended output module, EN, first switch enable signal, ENB, first inverted switch enable signal,EN LV, second switch enable signal, ENB LV, second inverted switch enable signal, VDDH, first operating voltage, VDD, second operating voltage. DETAILED DESCRIPTION

[0093] In order to make the objects, technical solutions and advantages of the present disclosure clearer, further detailed description will be made to the present disclosure with reference to the accompanying drawings and embodiments.

[0094] It should be noted that the terms "first", "second" and the like in the description and claims of the present disclosure and the above drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence.

[0095] The "coupling (or connection)" used in the description and claims of the present disclosure can refer to any direct or indirect connection means, for example, the first device is coupled (or connected) to the second device, which should be interpreted as that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or certain connection means.

[0096] Figure 1 is a structural block diagram of a continuous-time linear equalizer according to an exemplary embodiment, as shown in Figure 1As shown, in the illustrative embodiment, the continuous-time linear equalizer 100 comprises a main current source MS, a first auxiliary current source SS1, a second auxiliary current source SS2, a receiver module 101, a third auxiliary current source SS3, a folded signal receiving module 102, and an output load module 103. The receiver module 101 is coupled to the main current source MS and has a first differential signal main receiving end, a second differential signal main receiving end, a first differential signal main output end, and a second differential signal main output end, for receiving a pair of differential input signals through the first differential signal main receiving end and the second differential signal main receiving end and outputting a pair of differential main output signals at the first differential signal main output end and the second differential signal main output end under the power supply of the main current source MS. The folded signal receiving module 102 is coupled to the third auxiliary current source SS3 and has a first differential signal auxiliary receiving end, a second differential signal auxiliary receiving end, a first differential signal auxiliary output end, and a second differential signal auxiliary output end, for receiving the differential input signals through the first differential signal auxiliary receiving end and the second differential signal auxiliary receiving end synchronously with the receiver module 101 and outputting a pair of differential auxiliary output signals at the first differential signal auxiliary output end and the second differential signal auxiliary output end under the power supply of the third auxiliary current source SS3. The output load module 103 is coupled to the first auxiliary current source SS1, the second auxiliary current source SS2, the receiver module 101, and the folded signal receiving module 102, i.e., the output load module 103 is coupled to the first differential signal main output end and the first differential signal auxiliary output end of the receiver module 101 and the second differential signal main output end and the second differential signal auxiliary output end of the folded signal receiving module 102, for receiving the differential main output signals and the differential auxiliary output signals under the power supply of the first auxiliary current source SS1 and the second auxiliary current source SS2, generating an equalized differential signal according to the differential main output signals and the differential auxiliary output signals, and providing an output load for the receiver module 101 and the folded signal receiving module 102 and a pair of zero-poles for the equalized differential signal.

[0097] The continuous time linear equalizer 100 of the embodiment of the present disclosure works in the analog circuit part, and all bias points in the receiver module 101 can be realized by using one main current source MS. Only one current is needed to be poured into the receiver module 101 through the main current source MS, and the receiver module 101 can work. In the continuous time linear equalizer 100 of the embodiment of the present disclosure, the differential auxiliary output signal of the folded signal receiving module 102 is introduced into the differential main output signal of the receiver module 101 by using the output load module 103 coupled with the first auxiliary current source SS1 and the second auxiliary current source SS2, and the rail-to-rail input of the continuous time linear equalizer 100 is realized. On the basis of realizing the rail-to-rail input of the continuous time linear equalizer 100, the high bandwidth of the continuous time linear equalizer 100 of the embodiment of the present disclosure is realized by the zero-pole provided by the output load module 103 for the generated equalized differential signal, so that the continuous time linear equalizer 100 of the embodiment of the present disclosure can receive and process high-speed transmission signals.

[0098] From the perspective of the circuit structure, because the receiver module 101 and the folded signal receiving module 102 are connected to the output load module 103, and then the receiver module 101 and the folded signal receiving module 102 present a folding effect in the circuit structure, the folded signal receiving module 102 is named accordingly. In addition, because the folded signal receiving module 102 and the receiver module 101 receive the differential input signal synchronously, and the folded signal receiving module 102 provides the differential auxiliary output signal, the receiver module 101 is taken as the main module, and then the folded signal receiving module 102 can also be named as the auxiliary receiver module.

[0099] As Figure 1As shown, in the illustrative embodiment, the output load module 103 includes two corresponding output load modules corresponding to the positive-phase signal and the negative-phase signal in the differential signal, specifically, the output load module 103 includes a first output load submodule 1031 and a second output load submodule 1032. The first output load submodule 1031 is coupled to the first auxiliary current source SS1, the receiver module 101 and the folded signal receiving module 102, i.e., the first output load submodule 1031 is coupled to the first differential signal main output end of the receiver module 101 and the first differential signal auxiliary output end of the folded signal receiving module 102, for receiving the first-phase signal in the differential main output signal and the first-phase signal in the differential auxiliary output signal under the power supply of the first auxiliary current source SS1, generating the first-phase signal in the equalized differential signal according to the first-phase signal in the differential main output signal and the first-phase signal in the differential auxiliary output signal, the first output load submodule 1031 providing output load for the first differential signal main output end and the first differential signal auxiliary output end and providing a pair of zero poles for the first-phase signal in the equalized differential signal. The second output load submodule 1032 is coupled to the second auxiliary current source SS2, the receiver module 101 and the folded signal receiving module 102, i.e., the second output load submodule 1032 is coupled to the second differential signal main output end of the receiver module 101 and the second differential signal auxiliary output end of the folded signal receiving module 102, for receiving the second-phase signal in the differential main output signal and the second-phase signal in the differential auxiliary output signal under the power supply of the second auxiliary current source SS2, generating the second-phase signal in the equalized differential signal according to the second-phase signal in the differential main output signal and the second-phase signal in the differential auxiliary output signal, the second output load submodule 1032 providing output load for the second differential signal main output end and the second differential signal auxiliary output end and providing a pair of zero poles for the second-phase signal in the equalized differential signal.

[0100] The continuous-time linear equalizer 100 of the present disclosure is further described below in combination with a specific embodiment circuit structure.

[0101] Figure 2 is a circuit structure schematic diagram of a continuous-time linear equalizer according to an illustrative embodiment. As shown in the figure, Figure 2 and in combination with Figure 1As shown, in the illustrative embodiment, the receiver module 101 includes a first differential signal receiving transistor T11, a second differential signal receiving transistor T12, a first output common mode feedback resistor R11, a second output common mode feedback resistor R12, a first receiver load transistor T13, and a second receiver load transistor T14. The first end of the first differential signal receiving transistor T11 is coupled to the main current source MS, the control terminal of the first differential signal receiving transistor T11 serves as a first differential signal main receiving terminal of the receiver module 101 to receive a first belief signal (e.g., a positive belief signal INP in the differential input signal) in the differential input signal, and the second end of the first differential signal receiving transistor T11 is a first differential signal main output terminal OUTP of the receiver module 101 to output the first belief signal (e.g., a positive belief signal in the differential output signal) in the differential main output signal. The first end of the second differential signal receiving transistor T12 is coupled to the main current source MS, the control terminal of the second differential signal receiving transistor T12 serves as a second differential signal main receiving terminal to receive a second belief signal (e.g., a negative belief signal INN in the differential input signal) in the differential input signal, and the second end of the second differential signal receiving transistor T12 is a second differential signal main output terminal OUTN of the receiver module 101 to output the second belief signal (e.g., a negative belief signal in the differential output signal) in the differential main output signal. The first end of the first output common mode feedback resistor R11 is coupled to the second end of the first differential signal receiving transistor T11. The first end of the second output common mode feedback resistor R12 is coupled to the second end of the second differential signal receiving transistor T12, and the second end of the second output common mode feedback resistor R12 is coupled to the second end of the first output common mode feedback resistor R11. The first end of the first receiver load transistor T13 is grounded, the second end of the first receiver load transistor T13 is coupled to the second end of the first differential signal receiving transistor T11, and the control terminal of the first receiver load transistor T13 is coupled to the second end of the first output common mode feedback resistor R11 and the second end of the second output common mode feedback resistor R12. The first end of the second receiver load transistor T14 is grounded, the second end of the second receiver load transistor T14 is coupled to the second end of the second differential signal receiving transistor T12, and the control terminal of the second receiver load transistor T14 is coupled to the second end of the first output common mode feedback resistor R11 and the second end of the second output common mode feedback resistor R12.

[0102] In the illustrative embodiment, the first differential signal receiving transistor T11 and the second differential signal receiving transistor T12 can be PMOS (Positive Channel Metal Oxide Semiconductor), the first end of the first differential signal receiving transistor T11 and the first end of the second differential signal receiving transistor T12 can be the source of the PMOS, the second end of the first differential signal receiving transistor T11 and the second end of the second differential signal receiving transistor T12 can be the drain of the PMOS, and the control end of the first differential signal receiving transistor T11 and the control end of the second differential signal receiving transistor T12 can be the gate of the PMOS. In the illustrative embodiment, the first receiver load transistor T13 and the second receiver load transistor T14 can be NMOS (Negative Channel Metal Oxide Semiconductor), the first end of the first receiver load transistor T13 and the first end of the second receiver load transistor T14 can be the source of the NMOS, the second end of the first receiver load transistor T13 and the second end of the second receiver load transistor T14 can be the drain of the NMOS, and the control end of the first receiver load transistor T13 and the control end of the second receiver load transistor T14 can be the gate of the NMOS.

[0103] As shown in FIG. 1, the receiver module 101 includes a first differential signal receiving transistor T11 and a second differential signal receiving transistor T12, a first receiver load transistor T13 and a second receiver load transistor T14, a first output common mode feedback resistor R11 and a second output common mode feedback resistor R12, and a main current source MS. Figure 2 As shown in FIG. 1, the receiver module 101 includes a first differential signal receiving transistor T11 and a second differential signal receiving transistor T12, a first receiver load transistor T13 and a second receiver load transistor T14, a first output common mode feedback resistor R11 and a second output common mode feedback resistor R12, and a main current source MS.

[0104] As shown in FIG. 1, the receiver module 101 includes a first differential signal receiving transistor T11 and a second differential signal receiving transistor T12, a first receiver load transistor T13 and a second receiver load transistor T14, a first output common mode feedback resistor R11 and a second output common mode feedback resistor R12, and a main current source MS. Figure 2As shown, in the illustrative embodiment, the folded signal receiving module 102 includes a third differential signal receiving transistor T21 and a fourth differential signal receiving transistor T22. The first end of the third differential signal receiving transistor T21 is coupled to the third auxiliary current source SS3, the control end of the third differential signal receiving transistor T21 serves as a first differential signal auxiliary receiving end of the folded signal receiving module 102, for receiving a first belief signal in the differential input signal (e.g. the positive belief signal INP in the differential input signal), and the second end of the third differential signal receiving transistor T21 is a first differential signal auxiliary output end. The first end of the fourth differential signal receiving transistor T22 is coupled to the third auxiliary current source SS3, the control end of the fourth differential signal receiving transistor T22 serves as a second differential signal auxiliary receiving end of the folded signal receiving module 102, for receiving a second belief signal in the differential input signal (e.g. the negative belief signal INN in the differential input signal), and the second end of the fourth differential signal receiving transistor T22 is a second differential signal auxiliary output end.

[0105] In the illustrative embodiment, the third differential signal receiving transistor T21 and the fourth differential signal receiving transistor T22 can be NMOS, the first end of the third differential signal receiving transistor T21 and the first end of the fourth differential signal receiving transistor T22 can be the source of the NMOS, the second end of the third differential signal receiving transistor T21 and the second end of the fourth differential signal receiving transistor T22 can be the drain of the NMOS, and the control end of the third differential signal receiving transistor T21 and the control end of the fourth differential signal receiving transistor T22 can be the gate of the NMOS.

[0106] Because the voltage range of the signal input through the first differential signal receiving transistor T11 and the second differential signal receiving transistor T12 in the receiver module 101 is limited, in order to expand the overall range of the input signal voltage, the third differential signal receiving transistor T21 and the fourth differential signal receiving transistor T22 are introduced. As described above, in the self-biased comparator formed in the receiver module 101, there is no circuit connection point to introduce the folded cascode (the third differential signal receiving transistor T21 and the fourth differential signal receiving transistor T22 are cascode) structure for expanding the overall range of the input signal voltage. In the embodiment of the present disclosure, the cascode structure of the third differential signal receiving transistor T21 and the fourth differential signal receiving transistor T22 is introduced into the output load module 103, and in the output load module 103, the differential main output signal of the receiver module 101 and the differential auxiliary output signal of the folded signal receiving module 102 are combined to generate an equalized differential signal, thereby realizing the rail-to-rail input of the continuous-time linear equalizer 100.

[0107] In order to obtain a well-performing balanced differential signal, the output load module 103 of this embodiment is designed as follows: the first output load submodule 1031 and the second output load submodule 1032 are symmetrically designed to ensure the consistency of the positive and negative signals in the differential signal.

[0108] like Figure 2 As shown in the illustrative embodiment, the first output load submodule 1031 includes a first load resistor module, a third load transistor T33, a first compensation resistor R31, and a first compensation capacitor module CM31. The first terminal of the first load resistor module is coupled to a first auxiliary current source SS1 and a first differential signal auxiliary output terminal. The first terminal of the third load transistor T33 is grounded, and its second terminal is coupled to the second terminal of the first load resistor module and the first differential signal main output terminal OUTP. The first terminal of the first compensation resistor R31 is coupled to the second terminal of the first load resistor module and the first differential signal main output terminal OUTP. The first terminal of the first compensation capacitor module CM31 is coupled to the control terminal of the third load transistor T33 and the second terminal of the first compensation resistor R31, and its second terminal is grounded.

[0109] like Figure 2 As shown in the illustrative embodiment, the second output load submodule 1032 includes a second load resistor module, a fourth load transistor T34, a second compensation resistor R32, and a second compensation capacitor module CM32. The first terminal of the second load resistor module is coupled to the second auxiliary current source SS2 and the second differential signal auxiliary output terminal. The first terminal of the fourth load transistor T34 is grounded, and the second terminal of the fourth load transistor T34 is coupled to the second terminal of the second load resistor module and the second differential signal main output terminal OUTN. The first terminal of the second compensation resistor R32 is coupled to the second terminal of the second load resistor module and the second differential signal main output terminal OUTN. The first terminal of the second compensation capacitor module CM32 is coupled to the control terminal of the fourth load transistor T34 and the second terminal of the second compensation resistor R32, and the second terminal of the second compensation capacitor module CM32 is grounded.

[0110] As can be seen, corresponding to the circuit layout between ground and power supply in receiver module 101, which uses three-level devices to achieve the circuit layout between ground and power supply, output load module 103 also uses three-level devices to achieve the circuit layout between ground and power supply. For example, in the first output load submodule 1031, the circuit layout between ground and power supply is achieved through the third load transistor T33, the first load resistor module and the first auxiliary current source SS1.

[0111] In this way, the intermediate nodes can be generated in the output load module 103 to adjust the current of the output load module 103. For example, the intermediate nodes are generated in the first output load submodule 1031 to adjust the current of the first output load submodule 1031, and the current of the first output load submodule 1031 can be determined by the current flowing through the third differential signal receiving transistor T21 in the folded signal receiving module 102, thereby successfully introducing a transconductance (GM) component into the main path of the first output load submodule 1031, and the same is true for the second output load submodule 1032. The continuous-time linear equalizer 100 of the embodiment of the present disclosure successfully achieves the goal of rail-to-rail input on the basis of the traditional self-biased comparator form of the receiver module 101 through the cascode structure of the folded signal receiving module 102.

[0112] After achieving rail-to-rail input, in order to achieve the applicability of the continuous-time linear equalizer 100 of the embodiment of the present disclosure under high-bandwidth conditions, a pair of zero-pole is introduced into the continuous-time linear equalizer 100 of the embodiment of the present disclosure by accessing the RC circuit composed of the compensation resistance and the compensation capacitance module in the load transistor, thereby making the continuous-time linear equalizer 100 of the embodiment of the present disclosure have the AC (alternating current) characteristics required for high-speed signal processing. For example, in the first output load submodule 1031, the RC circuit composed of the first compensation resistance R31 and the first compensation capacitance module CM31 is accessed in the third load transistor T33, and correspondingly, in the second output load submodule 1032, the RC circuit composed of the second compensation resistance R32 and the second compensation capacitance module CM32 is accessed in the fourth load transistor T34, so that the zero-pole is introduced into the continuous-time linear equalizer 100 of the embodiment of the present disclosure.

[0113] In the illustrative embodiment, the first compensation capacitance module CM31 and the second compensation capacitance module CM32 can be implemented by MOS tubes, for example Figure 2 As shown in the figure, the first compensation capacitance module CM31 and the second compensation capacitance module CM32 can be NMOS, wherein the second end of the first compensation capacitance module CM31 and the second end of the second compensation capacitance module CM32 are the source and drain of the NMOS, that is, the source and drain of the NMOS are both grounded, and the first end of the first compensation capacitance module CM31 and the first end of the second compensation capacitance module CM32 are the gate of the NMOS.

[0114] As Figure 2As shown, in the illustrative embodiment, the first load resistance module includes a first load transistor T31, a first end of the first load transistor T31 is a first end of the first load resistance module, a second end of the first load transistor T31 is a second end of the first load resistance module, and a control end of the first load transistor T31 receives the clamping voltage BIASP2, and in operation, the first load transistor T31 works in the saturation region under the action of the clamping voltage BIASP2. In the illustrative embodiment, the second load resistance module includes a second load transistor T32, a first end of the second load transistor T32 is a first end of the second load resistance module, a second end of the second load transistor T32 is a second end of the second load resistance module, and a control end of the second load transistor T32 receives the clamping voltage BIASP2, and in operation, the second load transistor T32 works in the saturation region under the action of the clamping voltage BIASP2.

[0115] Figure 2 In the illustrative embodiment, the first load transistor T31 and the second load transistor T32 realize the function of resistance under the action of the clamping voltage BIASP2, and in addition, Figure 2 in other embodiments, the first load transistor T31 and the second load transistor T32 can also be replaced by resistors, i.e., the first load resistance module includes a first load resistor, a first end of the first load resistor is a first end of the first load resistance module, and a second end of the first load resistor is a second end of the first load resistance module, and the second load resistance module includes a second load resistor, a first end of the second load resistor is a first end of the second load resistance module, and a second end of the second load resistor is a second end of the second load resistance module.

[0116] Figure 3 is an AC characteristic curve diagram of the continuous-time linear equalizer of the embodiment of the present disclosure, as Figure 3 shown, the horizontal axis is the signal frequency (bandwidth), and the vertical axis is the AC gain (gain), and in the case of introducing rail-to-rail input, the introduction of zero-pole can gradually increase the AC gain of the continuous-time linear equalizer 100 of the embodiment of the present disclosure in the range from gradually increasing the signal frequency to reaching the required sufficiently high signal frequency, thereby ensuring that the continuous-time linear equalizer 100 of the embodiment of the present disclosure not only realizes rail-to-rail input but also can be applied to the processing of high-bandwidth signals.

[0117] On the basis of the continuous-time linear equalizer 100 of the embodiment of the present disclosure, the embodiment of the present disclosure further provides a signal receiving circuit, which realizes opening when in use and closing when not in use to save power consumption, and realizes the function of receiving a high-voltage domain differential signal from the outside to output a low-voltage domain single-ended output signal to the inside of the chip.

[0118] Figure 4This is a block diagram illustrating the structure of a signal receiving circuit according to an illustrative embodiment, such as... Figure 4As shown, in the illustrative embodiment, the signal receiving circuit includes a continuous-time linear equalizer 100, a bias clamping module 200, a voltage gain amplification module 300, a differential-to-single-ended output module 400, a switch control module 500, and a switch matching module 600. The continuous-time linear equalizer 100 is described above and will not be repeated here. The bias clamping module 200 is coupled to the main current source MS, the first auxiliary current source SS1, the second auxiliary current source SS2, and the third auxiliary current source SS3, and is configured to generate a bias voltage BIASP1 and control the currents of the main current source MS, the first auxiliary current source SS1, the second auxiliary current source SS2, and the third auxiliary current source SS3 by the bias voltage BIASP1. The voltage gain amplification module 300 is coupled to the continuous-time linear equalizer 100, and is configured to receive a first switch enable signal, a first inverted switch enable signal, and an equalized differential signal, operate or shut down according to the first switch enable signal and the first inverted switch enable signal, and in the operating state, amplify the equalized differential signal to obtain an amplified differential signal. The differential-to-single-ended output module 400 is coupled to the voltage gain amplification module 300, and is configured to receive a second switch enable signal and the amplified differential signal, operate or shut down according to the second switch enable signal, and in the operating state, convert the amplified differential signal into a single-ended output signal and output the single-ended output signal. The switch control module 500 is coupled to the main current source MS, the first auxiliary current source SS1, the second auxiliary current source SS2, and the voltage gain amplification module 300, and is configured to receive the first switch enable signal, generate the first inverted switch enable signal and a controlled source voltage according to the first switch enable signal, and operate the main current source MS, the first auxiliary current source SS1, and the second auxiliary current source SS2 under the action of the controlled source voltage. The switch matching module 600 is coupled to the bias clamping module 200, and is configured to generate a matching source voltage matched with the controlled source voltage, so that the bias clamping module 200 generates the bias voltage BIASP1 based on the matching source voltage. The semiconductor devices in the continuous-time linear equalizer 100, the semiconductor devices in the bias clamping module 200, the semiconductor devices in the switch control module 500, and the semiconductor devices in the switch matching module 600 are semiconductor devices suitable for the voltage domain of the first working voltage, the semiconductor devices in the voltage gain amplification module 300 are semiconductor devices suitable for the voltage domain of the second working voltage and capable of withstanding the voltage domain of the first working voltage, and the semiconductor devices in the differential-to-single-ended output module 400 are semiconductor devices suitable for the voltage domain of the second working voltage, where the voltage domain of the first working voltage is higher than the voltage domain of the second working voltage. In the illustrative embodiment, the first working voltage domain is 1.2V or 1.8V, and the related electronic elements can work at about 1.2V or about 1.8V, and the second working voltage domain is 0.75V or 0.85V, and the related electronic elements can work at about 0.75V or about 0.85V.It should be noted that the specific values of the voltage domains of the first operating voltage and the second operating voltage can vary depending on the application of different circuit nodes.

[0119] In an illustrative embodiment, the semiconductor device suitable for the voltage domain of the first operating voltage can be, for example, a semiconductor device used in an analog circuit. Since the analog circuit can be used in an input / output circuit, such a semiconductor device can also be referred to as an input / output device (IO device). The switching threshold of such a semiconductor device is relatively high, for example, about 1.2 V or about 1.8 V.

[0120] The semiconductor device suitable for the voltage domain of the second operating voltage can be, for example, a semiconductor device used in a digital circuit, which can also be referred to as a core device. The switching threshold of such a semiconductor device is relatively low, for example, about 0.75 V or about 0.85 V.

[0121] The semiconductor device suitable for the voltage domain of the second operating voltage and capable of withstanding the voltage of the voltage domain of the first operating voltage, for example, such a semiconductor device is prepared using the gate oxide layer of the semiconductor device suitable for the voltage domain of the first operating voltage, and the ion concentration of the doping in the substrate is different from that of the semiconductor device suitable for the voltage domain of the first operating voltage, so that the threshold voltage of such a semiconductor device is lower than that of the semiconductor device suitable for the voltage domain of the first operating voltage. Such a semiconductor device has a voltage withstand capability comparable to that of the semiconductor device suitable for the voltage domain of the first operating voltage, and a lower threshold voltage, for example, the threshold voltage of such a semiconductor device is, for example, about 0.75 V or about 0.85 V, and can withstand a voltage of about 1.2 V or about 1.8 V or even higher. In the context of a legacy circuit, there are often scenarios where signals need to be transmitted from one voltage domain to another. In such transmission circuits, the relevant semiconductor devices need to be underdriven to prevent overvoltage of the gate oxide layer or to reduce leakage that may occur, so such a semiconductor device can also be referred to as an underdrive device.

[0122] The signal receiving circuit of the embodiments of the present disclosure is applied in the scenario of signal conversion from the high voltage domain of the data transmission channel outside the chip to the low voltage domain of the digital circuit inside the chip. The semiconductor devices in the continuous time linear equalizer 100, the semiconductor devices in the bias clamping module 200, the semiconductor devices in the switch control module 500, and the semiconductor devices in the switch matching module 600 are suitable for the high voltage domain. The semiconductor devices in the voltage gain amplification module 300 are underdriven devices suitable for the low voltage domain and can withstand the high voltage domain. The semiconductor devices in the differential to single-ended output module 400 are suitable for the low voltage domain. Thus, the signal is transmitted step by step from the high voltage domain of the data transmission channel outside the chip to the low voltage domain of the digital circuit inside the chip.

[0123] Figure 5 is a circuit structure schematic diagram of the signal receiving circuit according to an illustrative embodiment, wherein the circuit part of the continuous time linear equalizer 100 is the same as that of the continuous time linear equalizer 100 shown in Figure 2 and will not be described herein again.

[0124] As shown in Figure 5 and in combination with Figure 4As shown, in the illustrative embodiment, the biasing clamping module 200 includes a biasing current source isource, a biasing clamping circuit resistor R41, a clamping transistor T41, a biasing transistor T42, a first replica transistor T43, a second replica transistor T44, and a reference transistor T45. The second end of the biasing clamping circuit resistor R41 is coupled to the biasing current source isource. The second end of the clamping transistor T41 is coupled to the first end of the biasing clamping circuit resistor R41, and the control end of the clamping transistor T41 is coupled to the second end of the biasing clamping circuit resistor R41. The first end of the biasing transistor T42 is connected to a matching source voltage, the second end of the biasing transistor T42 is coupled to the first end of the clamping transistor T41, and the control end of the biasing transistor T42 is coupled to the second end of the clamping transistor T41, wherein the matching source voltage is matched to a controlled source voltage, under the action of the biasing current source isource and the matching source voltage, the control end of the biasing transistor T42 generates a biasing voltage BIASP1, and the control end of the clamping transistor T41 generates a clamping voltage BIASP2, wherein the control end of the biasing transistor T42 is coupled to a main current source MS, a first auxiliary current source SS1, and a second auxiliary current source SS2, and in turn, the biasing transistor T42, the main current source MS, the first auxiliary current source SS1, and the second auxiliary current source SS2 form a current mirror, so that the current flowing through the biasing transistor T42 is copied into the current of the main current source MS, the current of the first auxiliary current source SS1, and the current of the second auxiliary current source SS2. The first end of the first replica transistor T43 is coupled to the first end of the biasing transistor T42, and the control end of the first replica transistor T43 is coupled to the control end of the biasing transistor T42, and the biasing transistor T42 and the first replica transistor T43 form a current mirror, so that the current flowing through the biasing transistor T42 is copied into the current flowing through the first replica transistor T43. The first end of the second replica transistor T44 is coupled to the second end of the first replica transistor T43, and the control end of the second replica transistor T44 is coupled to the control end of the clamping transistor T41. The first end of the reference transistor T45 is grounded, the second end of the reference transistor T45 is coupled to the second end of the second replica transistor T44, the control end of the reference transistor T45 is coupled to the second end of the reference transistor T45, and the control end of the reference transistor T45 is coupled to a third auxiliary current source SS3, and the reference transistor T45 and the third auxiliary current source SS3 form a current mirror, so that the current flowing through the reference transistor T45 is copied into the current flowing through the third auxiliary current source SS3.

[0125] In the illustrative embodiment, the clamping transistor T41, the bias transistor T42, the first replica transistor T43 and the second replica transistor T44 can be PMOS, the first end of the clamping transistor T41, the first end of the bias transistor T42, the first end of the first replica transistor T43 and the first end of the second replica transistor T44 can be the source of the PMOS, the second end of the clamping transistor T41, the second end of the bias transistor T42, the second end of the first replica transistor T43 and the second end of the second replica transistor T44 can be the drain of the PMOS, the control end of the clamping transistor T41, the control end of the bias transistor T42, the control end of the first replica transistor T43 and the control end of the second replica transistor T44 can be the gate of the PMOS, the reference transistor T45 can be NMOS, the first end of the reference transistor T45 can be the source of the NMOS, the second end of the reference transistor T45 can be the drain of the NMOS, and the control end of the reference transistor T45 can be the gate of the NMOS.

[0126] It can be seen that, in the bias clamping module 200, the clamping transistor T41 and the bias clamping circuit resistor R41 are used to lock the clamping voltage BIASP2. The bias transistor T42 and the first replica transistor T43 constitute a current mirror, wherein the bias transistor T42 is an input transistor in the current mirror, and the bias transistor T42 provides the bias voltage BIASP1 to the control end of the first replica transistor T43 as the input transistor, the first replica transistor T43 is an output transistor (or a mirror transistor) in the current mirror, and the first replica transistor T43 shares the same gate-source voltage as the bias transistor T42 as the output transistor, in the illustrative embodiment, the channel length-width ratio of the first replica transistor T43 and the bias transistor T42 is the same, and the current flowing through the bias transistor T42 is one-to-one replicated to the first replica transistor T43, i.e., the current flowing through the first replica transistor T43 is the same as the current flowing through the bias transistor T42. The current flowing through the first replica transistor T43 passes through the second replica transistor T44 and the reference transistor T45 in turn.

[0127] The reference transistor T45 and the third auxiliary current source SS3 constitute a current mirror. As Figure 5 and in combination Figure 4As shown, in the illustrative embodiment, the third auxiliary current source SS3 includes a third auxiliary current transistor T53, a first end of the third auxiliary current transistor T53 is grounded, a second end of the third auxiliary current transistor T53 is coupled to the folded signal receiving module 102, and a control end of the third auxiliary current transistor T53 is coupled to the control end of the reference transistor T45. In the illustrative embodiment, the third auxiliary current transistor T53 is an NMOS, the first end of the third auxiliary current transistor T53 is the source of the NMOS, the second end of the third auxiliary current transistor T53 is the drain of the NMOS, and the control end of the third auxiliary current transistor T53 is the gate of the NMOS. As can be seen, the reference transistor T45 and the third auxiliary current transistor T53 form a current mirror. In the illustrative embodiment, the channel length-width ratio of the third auxiliary current transistor T53 and the reference transistor T45 is the same, and thus the current flowing through the reference transistor T45 is copied to the third auxiliary current transistor T53 in a one-to-one manner, i.e., the current flowing through the third auxiliary current transistor T53 is the same as the current flowing through the reference transistor T45. Thus, the current flowing through the biasing transistor T42 is copied to the third auxiliary current source SS3 through the current mirror structure in the biasing clamping module 200.

[0128] The biasing transistor T42 and the main current source MS form a current mirror. As Figure 5 and in combination Figure 4 As shown, in the illustrative embodiment, the main current source MS includes a main current transistor T50, a first end of the main current transistor T50 is coupled to the switch control module 500 to receive the controlled source voltage, a second end of the main current transistor T50 is coupled to the receiver module 101, and a control end of the main current transistor T50 is coupled to the control end of the biasing transistor T42. In the illustrative embodiment, the main current transistor T50 is a PMOS, the first end of the main current transistor T50 is the source of the PMOS, the second end of the main current transistor T50 is the drain of the PMOS, and the control end of the main current transistor T50 is the gate of the PMOS. As can be seen, the biasing transistor T42 and the main current transistor T50 form a current mirror. In the illustrative embodiment, the channel length-width ratio of the main current transistor T50 and the biasing transistor T42 is the same, and thus the current flowing through the biasing transistor T42 is copied to the main current transistor T50 in a one-to-one manner, i.e., the current flowing through the main current transistor T50 is the same as the current flowing through the biasing transistor T42. Thus, the current flowing through the biasing transistor T42 is copied to the main current source MS through the current mirror formed by the biasing transistor T42 and the main current transistor T50.

[0129] The biasing transistor T42 and the first auxiliary current source SS1 form a current mirror. As Figure 5 and in combination Figure 4As shown, in the illustrative embodiment, the first sub-current source SS1 includes a first sub-current transistor T51, a first end of the first sub-current transistor T51 is coupled to the switch control module 500 to receive the controlled source voltage, a second end of the first sub-current transistor T51 is coupled to the first output load sub-module 1031, and a control end of the first sub-current transistor T51 is coupled to the control end of the biasing transistor T42. In the illustrative embodiment, the first sub-current transistor T51 is a PMOS, the first end of the first sub-current transistor T51 is the source of the PMOS, the second end of the first sub-current transistor T51 is the drain of the PMOS, and the control end of the first sub-current transistor T51 is the gate of the PMOS. As can be seen, the biasing transistor T42 and the first sub-current transistor T51 form a current mirror. In the illustrative embodiment, the channel length-width ratio of the first sub-current transistor T51 and the biasing transistor T42 is the same, and thus the current flowing through the biasing transistor T42 is copied to the first sub-current transistor T51 in a one-to-one ratio, i.e., the current flowing through the first sub-current transistor T51 is the same as the current flowing through the biasing transistor T42. Thus, the current mirror formed by the biasing transistor T42 and the first sub-current transistor T51 copies the current flowing through the biasing transistor T42 to the first sub-current source SS1.

[0130] The biasing transistor T42 and the second sub-current source SS2 form a current mirror. As Figure 5 and in combination Figure 4 As shown, in the illustrative embodiment, the second sub-current source SS2 includes a second sub-current transistor T52, a first end of the second sub-current transistor T52 is coupled to the switch control module 500 to receive the controlled source voltage, a second end of the second sub-current transistor T52 is coupled to the second output load sub-module 1032, and a control end of the second sub-current transistor T52 is coupled to the control end of the biasing transistor T42. In the illustrative embodiment, the second sub-current transistor T52 is a PMOS, the first end of the second sub-current transistor T52 is the source of the PMOS, the second end of the second sub-current transistor T52 is the drain of the PMOS, and the control end of the second sub-current transistor T52 is the gate of the PMOS. As can be seen, the biasing transistor T42 and the second sub-current transistor T52 form a current mirror. In the illustrative embodiment, the channel length-width ratio of the second sub-current transistor T52 and the biasing transistor T42 is the same, and thus the current flowing through the biasing transistor T42 is copied to the second sub-current transistor T52 in a one-to-one ratio, i.e., the current flowing through the second sub-current transistor T52 is the same as the current flowing through the biasing transistor T42. Thus, the current mirror formed by the biasing transistor T42 and the second sub-current transistor T52 copies the current flowing through the biasing transistor T42 to the second sub-current source SS2.

[0131] As can be seen from the above various embodiments, the signal receiving circuit of the embodiments of the present disclosure copies the current flowing through the bias transistor T42 to the main current source MS, the first auxiliary current source SS1, the second auxiliary current source SS2 and the third auxiliary current source SS3 through various current mirrors, thereby realizing the correlation control between the working currents of various parts in the continuous-time linear equalizer 100, and helping to realize the ideal rail-to-rail input of the continuous-time linear equalizer 100.

[0132] As Figure 5 and in combination Figure 4As shown, in the illustrative embodiment, the switch control module 500 includes a first switch circuit transistor T61, a second switch circuit transistor T62, a third switch circuit transistor T63, and a fourth switch circuit transistor T64. The first end of the first switch circuit transistor T61 is coupled to the first operating voltage VDDH. The first end of the second switch circuit transistor T62 is grounded, the control end of the second switch circuit transistor T62 is coupled to the control end of the first switch circuit transistor T61 and receives the first switch enable signal EN, the second end of the second switch circuit transistor T62 is coupled to the second end of the first switch circuit transistor T61, and the coupling between the second end of the second switch circuit transistor T62 and the second end of the first switch circuit transistor T61 generates the first inverted switch enable signal ENB; when the first switch enable signal EN is at a high level, the first switch circuit transistor T61 is cut off and the second switch circuit transistor T62 is turned on, and thus the first inverted switch enable signal ENB is at a low level; when the first switch enable signal EN is at a low level, the first switch circuit transistor T61 is turned on and the second switch circuit transistor T62 is cut off, and thus the first inverted switch enable signal ENB is at a high level. The first end of the third switch circuit transistor T63 is coupled to the first operating voltage VDDH. The first end of the fourth switch circuit transistor T64 is grounded, the control end of the fourth switch circuit transistor T64 is coupled to the control end of the third switch circuit transistor T63, and the control end of the fourth switch circuit transistor T64 and the control end of the third switch circuit transistor T63 are coupled to the second end of the first switch circuit transistor T61 and the second end of the second switch circuit transistor T62 to receive the first inverted switch enable signal ENB, the second end of the fourth switch circuit transistor T64 is coupled to the second end of the third switch circuit transistor T63, and the coupling between the second end of the fourth switch circuit transistor T64 and the second end of the third switch circuit transistor T63 generates the controlled source voltage; when the first inverted switch enable signal ENB is at a low level, the third switch circuit transistor T63 is turned on and the fourth switch circuit transistor T64 is cut off, and thus the controlled source voltage is at a high level; when the first inverted switch enable signal ENB is at a high level, the third switch circuit transistor T63 is cut off and the fourth switch circuit transistor T64 is turned on, and thus the controlled source voltage is at a low level. The voltage domains of the first switch enable signal EN, the first inverted switch enable signal ENB, and the controlled source voltage are the voltage domain of the first operating voltage VDDH.

[0133] In the illustrative embodiment, the first switch circuit transistor T61 and the third switch circuit transistor T63 can be PMOS, the first end of the first switch circuit transistor T61 and the first end of the third switch circuit transistor T63 can be the source of the PMOS, the second end of the first switch circuit transistor T61 and the second end of the third switch circuit transistor T63 can be the drain of the PMOS, and the control end of the first switch circuit transistor T61 and the control end of the third switch circuit transistor T63 can be the gate of the PMOS.

[0134] In the illustrative embodiment, the second switch circuit transistor T62 and the fourth switch circuit transistor T64 can be NMOS, the first end of the second switch circuit transistor T62 and the first end of the fourth switch circuit transistor T64 can be the source of the NMOS, the second end of the second switch circuit transistor T62 and the second end of the fourth switch circuit transistor T64 can be the drain of the NMOS, and the control end of the second switch circuit transistor T62 and the control end of the fourth switch circuit transistor T64 can be the gate of the NMOS.

[0135] In the switch control module 500, the first switch enable signal EN is an enable signal of the voltage domain where the first working voltage VDDH is located. When the first switch enable signal EN is at a high level, the generated controlled source voltage is close to the first working voltage VDDH, so that the main current source MS, the first auxiliary current source SS1 and the second auxiliary current source SS2 can be provided with a controlled source voltage with high enough voltage strength, so that the main current source MS, the first auxiliary current source SS1 and the second auxiliary current source SS2 can provide a large enough current. When the first switch enable signal EN is at a low high level, the first inverted switch enable signal ENB is at a high level, so that the third switch circuit transistor T63 is cut off and the fourth switch circuit transistor T64 is turned on, so that the controlled source voltage provided to the main current source MS, the first auxiliary current source SS1 and the second auxiliary current source SS2 is pulled down to the ground end level connected to the fourth switch circuit transistor T64, and then the main current source MS, the first auxiliary current source SS1 and the second auxiliary current source SS2 no longer generate current, so that the continuous-time linear equalizer 100 will not work, and based on this, when no input signal is received, the continuous-time linear equalizer 100 can be turned off by pulling down the first switch enable signal EN, thereby saving power consumption.

[0136] As Figure 5 and in combination Figure 4As shown, in the illustrative embodiment, the switch matching module 600 includes a first matching transistor T71, a second matching transistor T72, and a third matching transistor T73. The first end of the first matching transistor T71 is coupled to the first operating voltage VDDH, and the second end of the first matching transistor T71 is coupled to the control end of the first matching transistor T71. The first end of the second matching transistor T72 is grounded, and the second end of the second matching transistor T72 is coupled to the control end of the first matching transistor T71. The first end of the third matching transistor T73 is coupled to the first operating voltage VDDH, the control end of the third matching transistor T73 is coupled to the second end of the second matching transistor T72, and the second end of the third matching transistor T73 is coupled to the bias clamping module 200 and generates a matching source voltage.

[0137] In the illustrative embodiment, the first matching transistor T71 and the third matching transistor T73 can be PMOS, the first end of the first matching transistor T71 and the first end of the third matching transistor T73 can be the source of the PMOS, the second end of the first matching transistor T71 and the second end of the third matching transistor T73 can be the drain of the PMOS, and the control end of the first matching transistor T71 and the control end of the third matching transistor T73 can be the gate of the PMOS.

[0138] In the illustrative embodiment, the second matching transistor T72 can be NMOS, the first end of the second matching transistor T72 can be the source of the NMOS, the second end of the second matching transistor T72 can be the drain of the NMOS, and the control end of the second matching transistor T72 can be the gate of the NMOS.

[0139] In the embodiments of the present disclosure, the switch matching module 600 mainly matches the switch control module 500 in the implementation of the physical layout. The device size and connection relationship in the switch matching module 600 are the same as when the first switch enable signal EN in the switch control module 500 is high, and the switch matching module 600 and the switch control module 500 are equivalent, wherein the first matching transistor T71 corresponds to the first switch circuit transistor T61, the second matching transistor T72 corresponds to the second switch circuit transistor T62, and the third matching transistor T73 corresponds to the third switch circuit transistor T63. In this way, the matching source voltage generated by the switch matching module 600 is the same as the controlled source voltage generated by the switch control module 500, which ensures the matching of the continuous-time linear equalizer 100 and the bias clamping module 200 in the real physical circuit implementation.

[0140] As Figure 5 and in combination Figure 4As shown, in the illustrative embodiment, the voltage gain amplification module 300 includes a first signal amplification receiving transistor T81, a first amplification switch transistor T82, a second signal amplification receiving transistor T83, a second amplification switch transistor T84, a first amplification circuit transistor T85, a first amplification circuit common mode feedback resistor R81, a second amplification circuit transistor T86, a second amplification circuit common mode feedback resistor R82, and a third amplification switch transistor T87. The control terminal of the first signal amplification receiving transistor T81 is coupled to the continuous-time linear equalizer 100 to receive the positive-phase signal in the equalized differential signal, and the first terminal of the first signal amplification receiving transistor T81 is grounded. The control terminal of the first amplification switch transistor T82 is coupled to the switch control module 500 to receive the first inverted switch enable signal ENB, the first terminal of the first amplification switch transistor T82 is grounded, and the second terminal of the first amplification switch transistor T82 is coupled to the control terminal of the first signal amplification receiving transistor T81. The control terminal of the second signal amplification receiving transistor T83 is coupled to the continuous-time linear equalizer 100 to receive the negative-phase signal in the equalized differential signal, and the first terminal of the second signal amplification receiving transistor T83 is grounded. The control terminal of the second amplification switch transistor T84 is coupled to the switch control module 500 to receive the first inverted switch enable signal ENB, the first terminal of the second amplification switch transistor T84 is grounded, and the second terminal of the second amplification switch transistor T84 is coupled to the control terminal of the second signal amplification receiving transistor T83. The first terminal of the first amplification circuit transistor T85 is coupled to the second operating voltage VDD, and the second terminal of the first amplification circuit transistor T85 is coupled to the second terminal of the first signal amplification receiving transistor T81. The first terminal of the first amplification circuit common mode feedback resistor R81 is coupled to the second terminal of the first amplification circuit transistor T85. The first terminal of the second amplification circuit transistor T86 is coupled to the second operating voltage VDD, and the second terminal of the second amplification circuit transistor T86 is coupled to the second terminal of the second signal amplification receiving transistor T83. The first terminal of the second amplification circuit common mode feedback resistor R82 is coupled to the second terminal of the second amplification circuit transistor T86, the second terminal of the second amplification circuit common mode feedback resistor R82 is coupled to the second terminal of the second amplification circuit transistor T86, the control terminal of the first amplification circuit transistor T85, and the control terminal of the second amplification circuit transistor T86, the second terminal of the first amplification circuit transistor T85 generates the positive-phase signal in the amplified differential signal, and the second terminal of the second amplification circuit transistor T86 generates the negative-phase signal in the amplified differential signal. The control terminal of the third amplification switch transistor T87 receives the first switch enable signal EN, the first terminal of the third amplification switch transistor T87 is coupled to the second operating voltage VDD, and the second terminal of the third amplification switch transistor T87 is coupled to the second terminal of the first amplification circuit transistor T85.

[0141] In the illustrative embodiment, the first signal amplification receiving transistor T81, the first amplification switching transistor T82, the second signal amplification receiving transistor T83, and the second amplification switching transistor T84 can be NMOS transistors. The first terminal of the first signal amplification receiving transistor T81, the first terminal of the first amplification switching transistor T82, the first terminal of the second signal amplification receiving transistor T83, and the first terminal of the second amplification switching transistor T84 can be the source of the NMOS transistors. The second terminal of the first signal amplification receiving transistor T81, the second terminal of the first amplification switching transistor T82, the second terminal of the second signal amplification receiving transistor T83, and the second amplification switching transistor T84 can be the drain of the NMOS transistors. The control terminal of the first signal amplification receiving transistor T81, the control terminal of the first amplification switching transistor T82, the control terminal of the second signal amplification receiving transistor T83, and the control terminal of the second amplification switching transistor T84 can be the gate of the NMOS transistors.

[0142] In the illustrative embodiment, the first amplifier transistor T85, the second amplifier transistor T86, and the third amplifier switching transistor T87 can be PMOS transistors. The first terminal of the first amplifier transistor T85, the first terminal of the second amplifier transistor T86, and the first terminal of the third amplifier switching transistor T87 can be the source of the PMOS transistors. The second terminal of the first amplifier transistor T85, the second terminal of the second amplifier transistor T86, and the second terminal of the third amplifier switching transistor T87 can be the drain of the PMOS transistors. The control terminal of the first amplifier transistor T85, the control terminal of the second amplifier transistor T86, and the control terminal of the third amplifier switching transistor T87 can be the gate of the PMOS transistors.

[0143] When the first switch enable signal EN is high, the first inverting switch enable signal ENB is low, and the first amplifying switch transistor T82, the second amplifying switch transistor T84, and the third amplifying switch transistor T87 are all turned off. The equalized differential signal enters the voltage gain amplification module 300 and is amplified to obtain the amplified differential signal. When the first switch enable signal EN is low, the first inverting switch enable signal ENB is high, and the first amplifying switch transistor T82, the second amplifying switch transistor T84, and the third amplifying switch transistor T87 are all turned on. Consequently, the first signal amplification receiving transistor T81, the second signal amplification receiving transistor T83, the first amplification circuit transistor T85, and the second amplification circuit transistor T86 are all turned off, and the voltage gain amplification module 300 stops working.

[0144] Because the voltage gain amplification module 300 is connected to the second working voltage VDD, and works in the voltage domain of the second working voltage VDD, and the voltage domain of the second working voltage VDD is smaller than the voltage domain of the first working voltage VDDH, even if the received equalized differential signal is the voltage domain signal of the first working voltage VDDH, the voltage domain of the amplified differential signal obtained after passing through the voltage gain amplification module 300 is still the voltage domain of the second working voltage VDD, so the voltage gain amplification module 300 plays a role in changing (such as reducing) the voltage domain of the differential signal, and therefore, even if the amplitude of the equalized differential signal is too large (large swing signal), the amplitude of the amplified differential signal will be compressed to the amplitude of the voltage domain of the second working voltage VDD due to the limitation of the voltage domain of the second working voltage VDD, at this time the voltage gain amplification module 300 plays the role of a differential signal level shifter, and on the other hand, because of the amplification effect of the voltage gain amplification module 300 on the signal, in the case of a weak equalized differential signal (small swing signal), the amplitude of the amplified differential signal can also be amplified to the amplitude of the voltage domain of the second working voltage VDD. Therefore, whether the amplitude of the equalized differential signal is strong or weak, the voltage gain amplification module 300 can adjust the amplitude of the amplified differential signal to the corresponding amplitude of the voltage domain of the second working voltage VDD. At the same time, because the semiconductor devices in the voltage gain amplification module 300 are underdriven devices suitable for the voltage domain of the second working voltage VDD and can withstand the voltage domain of the first working voltage VDDH, even if the voltage of the equalized differential signal and the voltage of the first switch enable signal EN and the voltage of the first inverted switch enable signal ENB are higher than the voltage domain of the second working voltage VDD, the semiconductor devices in the voltage gain amplification module 300 will not be broken down. At the same time, because the voltage gain amplification module 300 is connected to the switch control module 500, it also realizes the synchronous opening and closing control of the voltage gain amplification module 300 and the continuous time linear equalizer 100, which helps to reduce the overall power consumption of the signal receiving circuit during the working process of the chip.

[0145] As Figure 5 and in combination ​As shown, in the illustrative embodiment, the differential-to-single-ended output module 400 includes an inverter INV, a first differential-to-single-ended receiving transistor T91, a second differential-to-single-ended receiving transistor T92, a first current copying transistor T93, a second current copying transistor T94, a first differential-to-single-ended switch transistor T95, and a second differential-to-single-ended switch transistor T96. The input of the inverter INV receives the second switch enable signal EN_LV, and generates the second inverted switch enable signal ENB_LV at the output of the inverter INV. The control terminal of the first differential-to-single-ended receiving transistor T91 is coupled to the voltage gain amplification module 300 to receive the positive signal in the amplified differential signal, and the first terminal of the first differential-to-single-ended receiving transistor T91 is coupled to the second operating voltage VDD. The control terminal of the second differential-to-single-ended receiving transistor T92 is coupled to the voltage gain amplification module 300 to receive the negative signal in the amplified differential signal, and the first terminal of the second differential-to-single-ended receiving transistor T92 is coupled to the second operating voltage VDD. The first terminal of the first current copying transistor T93 is grounded, and the second terminal and the control terminal of the first current copying transistor T93 are coupled to the second terminal of the first differential-to-single-ended receiving transistor T91. The first terminal of the second current copying transistor T94 is grounded, and the control terminal of the second current copying transistor T94 is coupled to the control terminal of the first current copying transistor T93. The first current copying transistor T93 and the second current copying transistor T94 form a current mirror, so that the current flowing through the first current copying transistor T93 is copied to the current flowing through the second current copying transistor T94. The first terminal of the first differential-to-single-ended switch transistor T95 is grounded, the second terminal of the first differential-to-single-ended switch transistor T95 is coupled to the control terminal of the second current copying transistor T94, and the control terminal of the first differential-to-single-ended switch transistor T95 is coupled to the output of the inverter INV to receive the second inverted switch enable signal ENB_LV. When the second switch enable signal EN_LV is high, the second inverted switch enable signal ENB_LV is low, and the first differential-to-single-ended switch transistor T95 is off. When the second switch enable signal EN_LV is low, the second inverted switch enable signal ENB_LV is high, and the first differential-to-single-ended switch transistor T95 is on.The first end of the second differential-to-single-ended switching transistor T96 is coupled to the second end of the second differential-to-single-ended receiving transistor T92, the second end of the second differential-to-single-ended switching transistor T96 is coupled to the second end of the second current copying transistor T94, a single-ended output signal is generated at the second end of the second differential-to-single-ended switching transistor T96, the single-ended output signal is output from the output end OUT of the differential-to-single-ended output module 400, and the control end of the second differential-to-single-ended switching transistor T96 is coupled to the output end of the inverter INV to receive the second inverted switching enable signal ENB_LV, when the second switching enable signal EN_LV is at a high level, the second inverted switching enable signal ENB_LV is at a low level, and the second differential-to-single-ended switching transistor T96 is turned on, when the second switching enable signal EN_LV is at a low level, the second inverted switching enable signal ENB_LV is at a high level, and the second differential-to-single-ended switching transistor T96 is turned off.

[0146] In an illustrative embodiment, the first differential-to-single-ended receiving transistor T91, the second differential-to-single-ended receiving transistor T92, and the second differential-to-single-ended switching transistor T96 can be PMOS, the first end of the first differential-to-single-ended receiving transistor T91, the first end of the second differential-to-single-ended receiving transistor T92, and the first end of the second differential-to-single-ended switching transistor T96 can be the source of the PMOS, the second end of the first differential-to-single-ended receiving transistor T91, the second end of the second differential-to-single-ended receiving transistor T92, and the second end of the second differential-to-single-ended switching transistor T96 can be the drain of the PMOS, and the control end of the first differential-to-single-ended receiving transistor T91, the control end of the second differential-to-single-ended receiving transistor T92, and the control end of the second differential-to-single-ended switching transistor T96 can be the gate of the PMOS.

[0147] In an illustrative embodiment, the first current copying transistor T93, the second current copying transistor T94, and the first differential-to-single-ended switching transistor T95 can be NMOS, the first end of the first current copying transistor T93, the first end of the second current copying transistor T94, and the first end of the first differential-to-single-ended switching transistor T95 can be the source of the NMOS, the second end of the first current copying transistor T93, the second end of the second current copying transistor T94, and the second end of the first differential-to-single-ended switching transistor T95 can be the drain of the NMOS, and the control end of the first current copying transistor T93, the control end of the second current copying transistor T94, and the control end of the first differential-to-single-ended switching transistor T95 can be the gate of the NMOS.

[0148] Since the first current replication transistor T93 and the second current replication transistor T94 form a current mirror, the current flowing through the first current replication transistor T93 is replicated as the current flowing through the second current replication transistor T94. Therefore, when the second switch enable signal EN_LV is high and the second inverting switch enable signal ENB_LV is low, the first differential-to-single-ended switch transistor T95 is turned off and the second differential-to-single-ended switch transistor T96 is turned on. Thus, the current representing the positive phase signal and the current representing the inverting phase signal in the differential signal are combined to form a single-ended output signal, which is output from the output terminal of the differential-to-single-ended output module 400. Conversely, when the second switch enable signal EN_LV is low and the second inverting switch enable signal ENB_LV is high, the first differential-to-single-ended switch transistor T95 is turned on and the second differential-to-single-ended switch transistor T96 is turned off, thereby turning off the differential-to-single-ended output module 400.

[0149] In this embodiment, the second switch enable signal EN_LV and the first switch enable signal EN change synchronously, that is, they are synchronously pulled high or low to achieve overall switching control of the signal receiving circuit. The voltage domain of the second switch enable signal EN_LV is the same as the voltage domain of the second operating voltage VDD, so the voltage of the second switch enable signal EN_LV is lower than the voltage of the first switch enable signal EN.

[0150] like ​ As shown in the illustrative embodiment, the inverter INV can be a conventional inverter INV circuit, which can be composed of a PMOS and an NMOS. The gates of the PMOS and NMOS are coupled together to form the input terminal of the inverter INV, and the drains of the PMOS and NMOS are coupled together to form the output terminal of the inverter INV. Since it is in the voltage domain of the second operating voltage VDD, the source of the PMOS is coupled to the second operating voltage VDD, and the source of the NMOS is grounded.

[0151] The signal receiving circuit of this embodiment operates in the analog circuit section and is implemented based on the continuous-time linear equalizer 100. In addition to having the related effects of the continuous-time linear equalizer 100, it also realizes the transition of the signal from the circuit in the voltage domain of the first operating voltage VDDH to the circuit in the voltage domain of the second operating voltage VDD. At the same time, it also realizes the switching function of the signal receiving circuit, thereby turning on the signal receiving circuit when in use and turning off the signal receiving circuit when not in use to save power consumption, thereby helping to reduce the overall power consumption of the signal receiving circuit during chip operation.

[0152] In the illustrative embodiment, at least one of the continuous-time linear equalizer 100 and the various components of the signal receiving circuit according to the present disclosure can be implemented in a combination of hardware, firmware, software (i.e., program), depending on the design.

[0153] In hardware form, at least one of the continuous-time linear equalizer 100 and the various components of the signal receiving circuit according to the present disclosure can be implemented in logic circuitry on an integrated circuit. For example, the functions of at least one of the continuous-time linear equalizer 100 and the various components of the signal receiving circuit according to the present disclosure can be implemented in various logic blocks, modules, and circuits of one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), or other processing units. The functions of at least one of the continuous-time linear equalizer 100 and the various components of the signal receiving circuit according to the present disclosure can be implemented in hardware circuitry, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages (e.g., Verilog HDL or VHDL) or other suitable programming languages.

[0154] In software or firmware form, the functions of at least one of the various components of the continuous-time linear equalizer 100 and the signal receiving circuit according to the embodiments of the present disclosure can be implemented as programming codes. For example, at least one of the various components of the continuous-time linear equalizer 100 and the signal receiving circuit according to the embodiments of the present disclosure can be implemented by using general programming languages (such as C, C++, or assembly language) or other suitable programming languages. The programming codes can be recorded, stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, a semiconductor memory and / or a storage device. An electronic device (such as a CPU, a hardware controller, a microcontroller, a hardware processor, or a microprocessor) can read and execute the programming codes from the non-transitory machine-readable storage medium, thereby implementing the functions of at least one of the various components of the continuous-time linear equalizer 100 and the signal receiving circuit according to the embodiments of the present disclosure.

[0155] In illustrative embodiments, the continuous-time linear equalizer 100 and the signal receiving circuit according to the embodiments of the present disclosure are applicable to a SoC chip, etc., where the SoC chip can be any one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), a NPU (Neural network Processing Unit), a DPU (Deep learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Unit).

[0156] In illustrative embodiments, a chip is also provided, which includes the continuous-time linear equalizer according to any one of the embodiments above.

[0157] In illustrative embodiments, a chip is also provided, which includes the signal receiving circuit according to any one of the embodiments above.

[0158] The above merely provides preferred embodiments of the present disclosure, and is not used to limit the present disclosure. Any modification, equivalent replacement, improvement, and the like made within the spirit and principle of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A continuous-time linear equalizer, characterized in that, include: Main current source; The first secondary current source; Secondary current source; The receiver module is coupled to the main current source and is used to receive a pair of differential input signals and output a pair of differential main output signals when powered by the main current source. The third auxiliary current source; A foldable signal receiving module, coupled to the third auxiliary current source, is used to receive the differential input signal synchronously with the receiver module when the third auxiliary current source is powered, and to output a pair of differential auxiliary output signals. The output load module is coupled to the first secondary current source, the second secondary current source, the receiver module and the foldable signal receiving module. When powered by the first secondary current source and the second secondary current source, it receives the differential main output signal and the differential auxiliary output signal, generates an equalized differential signal based on the differential main output signal and the differential auxiliary output signal, and provides a pair of zeros and poles for the equalized differential signal. The foldable signal receiving module includes: The third differential signal receiving transistor has a first terminal coupled to the third auxiliary current source, a control terminal of the third differential signal receiving transistor that is the first differential signal auxiliary receiving terminal of the folded signal receiving module, and a second terminal of the third differential signal receiving transistor that is the first differential signal auxiliary output terminal of the folded signal receiving module to output the first phase signal in the differential auxiliary output signal. The fourth differential signal receiving transistor has its first terminal coupled to the third auxiliary current source. The control terminal of the fourth differential signal receiving transistor is the second differential signal auxiliary receiving terminal of the folded signal receiving module, and the second terminal of the fourth differential signal receiving transistor is the second differential signal auxiliary output terminal of the folded signal receiving module to output the second phase signal in the differential auxiliary output signal. The output load module includes: The first output load submodule, coupled to the first auxiliary current source, the receiver module, and the folded signal receiving module, is used to receive the first phase signal in the differential main output signal and the first phase signal in the differential auxiliary output signal when powered by the first auxiliary current source, and to generate the first phase signal in the equalized differential signal based on the first phase signal in the differential main output signal and the first phase signal in the differential auxiliary output signal. The first output load submodule provides an output load to the first differential main output terminal of the receiver module and the first differential auxiliary output terminal of the folded signal receiving module, and provides a pair of zeros and poles for the first phase signal in the equalized differential signal. The second output load submodule, coupled to the second auxiliary current source, the receiver module, and the folded signal receiving module, is used to receive the second phase signal in the differential main output signal and the second phase signal in the differential auxiliary output signal when powered by the second auxiliary current source. It generates the second phase signal in the equalized differential signal based on the second phase signal in the differential main output signal and the second phase signal in the differential auxiliary output signal. The second output load submodule provides an output load to the second differential main output terminal of the receiver module and the second differential auxiliary output terminal of the folded signal receiving module, and provides a pair of zeros and poles for the second phase signal in the equalized differential signal.

2. The continuous-time linear equalizer according to claim 1, characterized in that, The receiver module includes: The first differential signal receiving transistor has a first terminal coupled to the main current source. The control terminal of the first differential signal receiving transistor is the first differential signal main receiving terminal of the receiver module to receive the first phase signal in the differential input signal. The second terminal of the first differential signal receiving transistor is the first differential signal main output terminal of the receiver module to output the first phase signal in the differential main output signal. The second differential signal receiving transistor has a first terminal coupled to the main current source, a control terminal of the second differential signal receiving transistor as the second differential signal main receiving terminal of the receiver module to receive the second phase signal in the differential input signal, and a second terminal of the second differential signal receiving transistor as the second differential signal main output terminal of the receiver module to output the second phase signal in the differential main output signal. The first output common-mode feedback resistor has its first terminal coupled to the second terminal of the first differential signal receiving transistor. The second output common-mode feedback resistor has a first terminal coupled to the second terminal of the second differential signal receiving transistor, and a second terminal coupled to the second terminal of the first output common-mode feedback resistor. A first receiver load transistor, the first terminal of the first receiver load transistor is grounded, the second terminal of the first receiver load transistor is coupled to the second terminal of the first differential signal receiving transistor, and the control terminal of the first receiver load transistor is coupled to the second terminal of the first output common-mode feedback resistor and the second terminal of the second output common-mode feedback resistor. The second receiver load transistor has a first terminal grounded, a second terminal coupled to the second terminal of the second differential signal receiving transistor, and a control terminal coupled to the second terminal of the first output common-mode feedback resistor and the second terminal of the second output common-mode feedback resistor.

3. The continuous-time linear equalizer according to claim 1, characterized in that: The first output load submodule includes: The first load resistor module has a first terminal coupled to the first auxiliary current source and the first differential signal auxiliary output terminal. The third load transistor has a first terminal grounded and a second terminal coupled to the second terminal of the first load resistor module and the first differential signal main output terminal. The first compensation resistor has its first end coupled to the second end of the first load resistor module and the first differential signal main output terminal. A first compensation capacitor module, wherein a first terminal of the first compensation capacitor module is coupled to the control terminal of the third load transistor and the second terminal of the first compensation resistor, and the second terminal of the first compensation capacitor module is grounded. The second output load submodule includes: The second load resistor module has a first terminal coupled to the second auxiliary current source and the second differential signal auxiliary output terminal. The fourth load transistor has a first terminal grounded and a second terminal coupled to the second terminal of the second load resistor module and the second differential signal main output terminal. The second compensation resistor has its first end coupled to the second end of the second load resistor module and the second differential signal main output terminal. The second compensation capacitor module has its first terminal coupled to the control terminal of the fourth load transistor and the second terminal of the second compensation resistor, and its second terminal grounded.

4. The continuous-time linear equalizer according to claim 3, characterized in that: The first load resistor module includes a first load transistor. The first terminal of the first load transistor is the first terminal of the first load resistor module, and the second terminal of the first load transistor is the second terminal of the first load resistor module. The control terminal of the first load transistor receives a clamping voltage. During operation, the first load transistor operates in the saturation region under the action of the clamping voltage. The second load resistor module includes a second load transistor. The first terminal of the second load transistor is the first terminal of the second load resistor module, and the second terminal of the second load transistor is the second terminal of the second load resistor module. The control terminal of the second load transistor receives the clamping voltage. During operation, the second load transistor operates in the saturation region under the action of the clamping voltage.

5. A signal receiving circuit, characterized in that, include: The continuous-time linear equalizer as described in any one of claims 1 to 4; A bias clamping module, coupled to the main current source, the first secondary current source, the second secondary current source and the third secondary current source, is used to generate a bias voltage and control the current of the main current source, the first secondary current source, the second secondary current source and the third secondary current source through the bias voltage; A voltage gain amplification module, coupled to the continuous-time linear equalizer, is used to receive a first switch enable signal, a first inverting switch enable signal, and the equalized differential signal. It operates or shuts down according to the first switch enable signal and the first inverting switch enable signal, and amplifies the equalized differential signal in the operating state to obtain an amplified differential signal. A differential-to-single-ended output module is coupled to the voltage gain amplifier module. It is used to receive a second switch enable signal and the amplified differential signal, and to operate or turn off according to the second switch enable signal. In the operating state, it converts the amplified differential signal into a single-ended output signal and outputs the single-ended output signal. A switch control module, coupled to the main current source, the first auxiliary current source, the second auxiliary current source and the voltage gain amplification module, is used to receive the first switch enable signal, and generate the first inverting switch enable signal and the controlled source voltage according to the first switch enable signal, wherein the main current source, the first auxiliary current source and the second auxiliary current source operate under the action of the controlled source voltage; A switch matching module, coupled to the bias clamping module, is used to generate a matching source voltage that matches the controlled source voltage, so that the bias clamping module generates the bias voltage based on the matching source voltage; Wherein, the semiconductor devices in the continuous-time linear equalizer, the semiconductor devices in the bias clamping module, the semiconductor devices in the switch control module, and the semiconductor devices in the switch matching module are semiconductor devices suitable for the voltage domain of the first operating voltage; the semiconductor devices in the voltage gain amplification module are semiconductor devices suitable for the voltage domain of the second operating voltage and can withstand voltages higher than those in the voltage domain of the first operating voltage; and the semiconductor devices in the differential-to-single-ended output module are semiconductor devices suitable for the voltage domain of the second operating voltage. The voltage domain of the first operating voltage is higher than that of the second operating voltage.

6. The signal receiving circuit according to claim 5, characterized in that, The bias clamping module includes: Bias current source; A bias clamping circuit resistor, the second end of which is coupled to the bias current source; A clamping transistor, wherein the second terminal of the clamping transistor is coupled to the first terminal of the bias clamping circuit resistor, and the control terminal of the clamping transistor is coupled to the second terminal of the bias clamping circuit resistor; A bias transistor is provided, wherein a first terminal of the bias transistor is connected to the matching source voltage, a second terminal of the bias transistor is coupled to the first terminal of the clamping transistor, and a control terminal of the bias transistor is coupled to the second terminal of the clamping transistor. The matching source voltage is matched with the controlled source voltage. The control terminal of the bias transistor generates the bias voltage, and the control terminal of the clamping transistor generates the clamping voltage. The control terminal of the bias transistor is coupled to the main current source, the first secondary current source, and the second secondary current source. The bias transistor, the main current source, the first secondary current source, and the second secondary current source form a current mirror, such that the current flowing through the bias transistor is replicated as the current of the main current source, the current of the first secondary current source, and the current of the second secondary current source. A first replicating transistor, the first terminal of which is coupled to the first terminal of the bias transistor, and the control terminal of which is coupled to the control terminal of the bias transistor, form a current mirror by the bias transistor and the first replicating transistor, such that the current flowing through the bias transistor is replicated as the current flowing through the first replicating transistor. The second replica transistor has a first terminal coupled to the second terminal of the first replica transistor, and a control terminal coupled to the control terminal of the clamping transistor. A reference transistor has a first terminal grounded, a second terminal coupled to the second terminal of the second replica transistor, a control terminal coupled to the second terminal of the reference transistor, and a control terminal coupled to the third auxiliary current source. The reference transistor and the third auxiliary current source form a current mirror, such that the current flowing through the reference transistor is replicated as the current flowing through the third auxiliary current source.

7. The signal receiving circuit according to claim 5, characterized in that, The switch control module includes: A first switching circuit transistor, wherein the first terminal of the first switching circuit transistor is coupled to the first operating voltage; The second switching transistor has a first terminal grounded, a control terminal coupled to the control terminal of the first switching transistor and receiving the first switch enable signal, and a second terminal coupled to the second terminal of the first switching transistor. The first inverting switch enable signal is generated at the coupling point between the second terminal of the second switching transistor and the second terminal of the first switching transistor. The third switching circuit transistor, wherein the first terminal of the third switching circuit transistor is coupled to the first operating voltage; A fourth switching transistor, wherein the first terminal of the fourth switching transistor is grounded, the control terminal of the fourth switching transistor is coupled to the control terminal of the third switching transistor, and the control terminals of the fourth and third switching transistors are coupled to the second terminals of the first and second switching transistors, respectively. The second terminal of the fourth switching transistor is coupled to the second terminal of the third switching transistor, and the controlled source voltage is generated at the coupling point between the second terminals of the fourth and third switching transistors. Wherein, the voltage domain of the first switch enable signal, the first inverting switch enable signal, and the controlled source voltage is the voltage domain of the first operating voltage.

8. The signal receiving circuit according to claim 5, characterized in that, The switch matching module includes: A first matching transistor, wherein a first terminal of the first matching transistor is coupled to the first operating voltage, and a second terminal of the first matching transistor is coupled to the control terminal of the first matching transistor; The second matching transistor has a first terminal grounded and a second terminal coupled to the control terminal of the first matching transistor. A third matching transistor, wherein the first terminal of the third matching transistor is coupled to the first operating voltage, the control terminal of the third matching transistor is coupled to the second terminal of the second matching transistor, and the second terminal of the third matching transistor is coupled to the bias clamping module and generates the matching source voltage.

9. The signal receiving circuit according to claim 5, characterized in that, The voltage gain amplification module includes: A first signal amplification and receiving transistor, the control terminal of which is coupled to the continuous-time linear equalizer to receive the positive phase signal in the equalized differential signal, and the first terminal of which is grounded. A first amplifying switching transistor, the control terminal of which is coupled to the switch control module to receive the first inverting switch enable signal, the first terminal of which is grounded, and the second terminal of which is coupled to the control terminal of the first signal amplifying receiving transistor. The second signal amplification and receiving transistor has its control terminal coupled to the continuous-time linear equalizer to receive the inverted signal in the equalized differential signal, and its first terminal is grounded. The second amplifying switching transistor has its control terminal coupled to the switch control module to receive the first inverting switch enable signal. The first terminal of the second amplifying switching transistor is grounded, and the second terminal of the second amplifying switching transistor is coupled to the control terminal of the second signal amplifying and receiving transistor. A first amplifier transistor, wherein a first terminal of the first amplifier transistor is coupled to the second operating voltage, and a second terminal of the first amplifier transistor is coupled to the second terminal of the first signal amplification and receiving transistor. The first common-mode feedback resistor of the first amplifier circuit is coupled to the second terminal of the transistor of the first amplifier circuit. The second amplifier transistor has a first terminal coupled to the second operating voltage and a second terminal coupled to the second signal amplification and receiving transistor. The second amplifier circuit common-mode feedback resistor has a first terminal coupled to the second terminal of the second amplifier circuit transistor. The second terminal of the second amplifier circuit common-mode feedback resistor is coupled to the second terminal of the second amplifier circuit transistor, the control terminal of the first amplifier circuit transistor, and the control terminal of the second amplifier circuit transistor. The second terminal of the first amplifier circuit transistor generates the positive phase signal in the amplified differential signal, and the second terminal of the second amplifier circuit transistor generates the inverted phase signal in the amplified differential signal. The third amplifying switching transistor has a control terminal that receives the first switching enable signal, a first terminal of the third amplifying switching transistor that is coupled to the second operating voltage, and a second terminal of the third amplifying switching transistor that is coupled to the second terminal of the first amplifying circuit transistor.

10. The signal receiving circuit according to claim 5, characterized in that, The differential-to-single-ended output module includes: An inverter, the input of which receives the second switch enable signal; The first differential-to-single-ended receiving transistor has its control terminal coupled to the voltage gain amplification module to receive the positive phase signal in the amplified differential signal, and its first terminal is coupled to the second operating voltage. The second differential-to-single-ended receiving transistor has its control terminal coupled to the voltage gain amplification module to receive the inverted signal in the amplified differential signal, and its first terminal is coupled to the second operating voltage. A first current replicating transistor, the first terminal of the first current replicating transistor is grounded, and the second terminal of the first current replicating transistor and the control terminal are coupled to the second terminal of the first differential to single-ended receiving transistor. The second current replicating transistor has a first terminal grounded and a control terminal coupled to the control terminal of the first current replicating transistor. The first current replicating transistor and the second current replicating transistor form a current mirror, such that the current flowing through the first current replicating transistor is replicated into the current flowing through the second current replicating transistor. The first differential-to-single-ended switching transistor has a first terminal grounded, a second terminal coupled to the control terminal of the second current replica transistor, and the control terminal coupled to the output terminal of the inverter. The second differential-to-single-ended switching transistor has a first terminal coupled to the second terminal of the second differential-to-single-ended receiving transistor, and a second terminal coupled to the second terminal of the second current replicating transistor. The single-ended output signal is generated at the second terminal of the second differential-to-single-ended switching transistor and is output from the output terminal of the differential-to-single-ended output module. The control terminal of the second differential-to-single-ended switching transistor is coupled to the output terminal of the inverter.

11. A chip, characterized in that, Including the continuous-time linear equalizer as described in any one of claims 1 to 4.

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