3D SiP package structure

Abstract

The application discloses a 3D SiP packaging structure, which comprises a substrate, a component packaging assembly, a first chip, a second chip and a packaging shell; the component packaging assembly is arranged on the substrate and electrically connected with the substrate; the first chip is vertically stacked on the top of the component packaging assembly and electrically connected with the substrate through a lead; the second chip is flip-chip arranged above the first chip and electrically connected with the first chip; the packaging shell is arranged on the substrate, and the component packaging assembly, the first chip and the second chip are packaged in the packaging shell. The application relates to the technical field of semiconductor packaging and can solve the problems of large packaging structure size and large application limitation in space-limited equipment in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, and particularly relates to a 3D SiP (SIP is Single In-line Package, which is a single in-line integrated circuit packaging technology) packaging structure. BACKGROUND

[0002] In a conventional packaging structure, components are horizontally placed on a substrate and connected to the substrate by wire bonding, which occupies a large horizontal space of the substrate, resulting in a large size of the entire packaging structure. For small, high-integration space-limited devices, the application of the large-size packaging structure of the prior art has great limitations. Therefore, it is necessary to provide a 3D SiP packaging structure to solve the problems of large size of the packaging structure and great application limitations in space-limited devices in the prior art. SUMMARY

[0003] The purpose of the present application is to provide a 3D SiP packaging structure to solve the problems of large size of the packaging structure and great application limitations in space-limited devices in the prior art.

[0004] The present application is implemented as follows:

[0005] A 3D SiP packaging structure includes a substrate, a component packaging assembly, a first chip, a second chip, and a packaging shell. The component packaging assembly is arranged on the substrate and electrically connected to the substrate. The first chip is vertically stacked on the top of the component packaging assembly and electrically connected to the substrate by a lead. The second chip is flip-chip arranged above the first chip, and the second chip is electrically connected to the first chip. The packaging shell is arranged on the substrate, and the component packaging assembly, the first chip, and the second chip are packaged in the packaging shell.

[0006] The component packaging assembly includes components and a packaging body. One or more components are packaged into a whole by the packaging body, and the bottom surface of the components is exposed to the bottom surface of the packaging body and electrically connected to the substrate. The first chip is stacked on the top surface of the packaging body.

[0007] The packaging body is an epoxy resin packaging body.

[0008] The components are one or more of a capacitor, a resistor, and an inductor.

[0009] The second chip is electrically connected to the first chip by a micro-bump.

[0010] The first chip is provided with a through-silicon via, and the second chip is electrically connected to the first chip through the through-silicon via.

[0011] The second chip is provided with one or more.

[0012] Compared with the prior art, the present application has the following beneficial effects:

[0013] 1、The present application adopts a vertical stacking manner to arrange the substrate, the component packaging assembly, the first chip and the second chip, and the second chip is arranged on the first chip in a flip-chip manner, which can greatly reduce the occupation of horizontal space and height space, save substrate space, make the entire packaging structure smaller, and is especially suitable for application in space-limited devices such as smart phones and wearable devices.

[0014] 2、The present application adopts a through silicon via and / or micro-bump manner to realize vertical electrical connection between the first chip and the second chip, which shortens the signal transmission distance and is beneficial to improve signal integrity and communication speed.

[0015] 3、The present application packages multiple components into one whole through the packaging body, and integrates the component packaging assembly, the first chip and the second chip together through the packaging shell, which can combine various types of chips manufactured by different processes together to form a multi-chip / heterogeneous integration, optimize the function of the packaging structure, and reduce the cost of the packaging structure. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a sectional view of the 3D SiP packaging structure of the present application.

[0017] In the figure, the substrate 1, the first chip 2, the through silicon via 21, the second chip 3, the micro-bump 31, the packaging shell 4, the component 5, the packaging body 6, and the lead 7. DETAILED DESCRIPTION

[0018] The present application will be further described below in combination with the drawings and specific embodiments.

[0019] Please refer to the accompanying Figure 1 A 3D SiP packaging structure, comprising a substrate 1, a component packaging assembly, a first chip 2, a second chip 3 and a packaging shell 4; the component packaging assembly is arranged on the substrate 1 and electrically connected with the substrate 1, the first chip 2 is vertically stacked on the top of the component packaging assembly and electrically connected with the substrate 1 through the lead 7; the second chip 3 is arranged on the top of the first chip 2 in a flip-chip manner, and the second chip 3 is electrically connected with the first chip 2; the packaging shell 4 is arranged on the substrate 1, and the component packaging assembly, the first chip 2 and the second chip 3 are packaged in the packaging shell 4.

[0020] The substrate 1, the component package assembly, the first chip 2 and the second chip 3 are arranged in a vertical stacked manner, which can greatly reduce the occupation of horizontal space, thereby reducing the size of the package structure. Meanwhile, the second chip 3 is arranged above the first chip 2 in a flip manner, which can shorten the interconnection path of the first chip 2 and the second chip 3, thereby reducing the thickness of the package structure, so as to better meet the miniaturization and integration requirements of the package structure and improve the application adaptability of the package structure in space-limited equipment.

[0021] The first chip 2 and the second chip 3 can be logic chips, memories, analog circuits, passive elements or sensors, and the second chip 3 can also be a conversion board. Different types of chips are integrated into one package structure through the package shell 4, forming a multi-chip / heterogeneous integration, realizing high integration, miniaturization and high performance of the package structure.

[0022] The substrate 1 can also be a conversion board made of silicon, glass, organic material, etc. A wiring layer is arranged on the substrate 1 for electrical connection with the component package assembly and the lead 7, so as to realize vertical stacking and 3D SiP packaging.

[0023] The component package assembly comprises components 5 and a package body 6. One or more components 5 are packaged into one whole through the package body 6, and the bottom surface of the component 5 is exposed to the bottom surface of the package body 6 and is electrically connected with the substrate 1. The first chip 2 is arranged on the top surface of the package body 6 in a stacked manner.

[0024] Preferably, the component 5 can be mounted on the substrate 1 in a patch type and is electrically connected with the substrate 1. The number and type of the component 5 can be adaptively selected according to actual use requirements. The component 5 is packaged in the package body 6, and the package body 6 is used to protect the internal component 5, so as to avoid the influence of the external environment on the sensitive component.

[0025] The package body 6 is an epoxy resin package body.

[0026] The materials of the package body 6 and the package shell 4 can be adaptively selected according to actual packaging requirements.

[0027] The component 5 can be a small-size patch component, such as a capacitor, a resistor, an inductor, etc. One or more small-size patch components can be selected according to actual application requirements and functional requirements, which is convenient for electrical connection with the substrate 1.

[0028] The second chip 3 is electrically connected with the first chip 2 in a micro bump 31 manner.

[0029] The micro bump technology can realize accurate connection between the first chip 2 and the second chip 3, and between the first chip 2 and the conversion board (the second chip 3).

[0030] The first chip 2 is provided with a through silicon via (TSV) 21, and the second chip 3 is electrically connected with the first chip 2 through the through silicon via 21.

[0031] The TSV technology is a vertical electrical connection hole created on a silicon wafer or a chip, and the TSV replaces a traditional long lead, so that direct and high-speed vertical communication between the first chip 2 and the second chip 3 is realized through the through silicon via 21, and the TSV has the characteristics of high bandwidth and low delay.

[0032] The second chip 3 is provided with one or more, and the number of the second chip 3 can be adaptively configured according to actual application requirements and functional requirements, and the connection mode of the second chip 3 with the first chip 2 can also be adaptively selected according to actual requirements, such as a micro bump 31 or a through silicon via 21. Similarly, the second chip 3 can also be electrically connected with the substrate 1 in a mode of a lead 7 according to actual electrical connection requirements.

[0033] The above is only a preferred embodiment of the present application, and is not used to limit the protection scope of the present application, so any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A 3D SiP packaging structure, characterized in that: The device includes a substrate (1), a component packaging assembly, a first chip (2), a second chip (3), and a packaging shell (4). The component packaging assembly is arranged on the substrate (1) and electrically connected to the substrate (1). The first chip (2) is vertically stacked on top of the component packaging assembly and electrically connected to the substrate (1) through a lead (7). The second chip (3) is flip-chip arranged above the first chip (2) and electrically connected to the first chip (2). The packaging shell (4) is disposed on the substrate (1), and the component packaging assembly, the first chip (2), and the second chip (3) are packaged in the packaging shell (4). The component packaging assembly includes components (5) and a package (6); one or more components (5) are packaged into a whole by the package (6), and the bottom surface of the components (5) is exposed on the bottom surface of the package (6) and electrically connected to the substrate (1), and the first chip (2) is stacked on the top surface of the package (6).

2. The 3D SiP packaging structure according to claim 1, characterized in that: The encapsulation body (6) is an epoxy resin encapsulation body.

3. The 3D SiP packaging structure according to claim 1, characterized in that: The aforementioned component (5) is one or more of capacitors, resistors, and inductors.

4. The 3D SiP packaging structure according to claim 1, characterized in that: The second chip (3) is electrically connected to the first chip (2) via microbumps (31).

5. The 3D SiP packaging structure according to claim 1, characterized in that: The first chip (2) is provided with a through-silicon via (21), and the second chip (3) is electrically connected to the first chip (2) through the through-silicon via (21).

6. The 3D SiP packaging structure according to any one of claims 1, 4, and 5, characterized in that: The second chip (3) has one or more.

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