INGAALP-OR INGAALAS-BASED FAST SWITCHING Mu-LED FOR HIGH SPEED DATA COMMUNICATION

Abstract

The invention relates to an LED comprising a semiconductor layer stack having a first layer of a first doping type, a second layer of a second doping type, and an active region arranged between the first layer and the second layer. The semiconductor layer stack includes a bottom surface and a top surface and mesa structured side surfaces connecting the top surface and the bottom surface, and includes a central region having a lateral dimension less than half a lateral dimension of the semiconductor layer stack. Further, the semiconductor layer stack includes a material including at least one of phosphide and arsenide, and a current path from the first layer through the active region to the second layer is limited to the central region.

Description

[0001] This application claims priority to German patent application DE 10 2023 115 113.4, filed on June 8, 2023, the disclosure of which is incorporated herein by reference in its entirety.

[0002] The present invention relates to µ-LEDs used as devices for optical data communication and methods for manufacturing such µ-LEDs.

[0003] background

[0004] The modern internet relies on large data centers. However, the high power consumption of these large data centers poses a challenge to operating them using only sustainable energy sources. Much of the electricity is not consumed for computing but for short-distance (<<10m) data transmission: CPU to GPU, server to server, rack to rack.

[0005] Using µ-LEDs for optical and data communication offers several advantages. Besides their small size (which provides easier interconnection with fiber optics), vertical or horizontal optoelectronic components offer improved scalability and can be easily implemented in large quantities within existing designs. In this context, µ-LEDs refer to optoelectronic components with a diameter or more generally a dimension of less than 50 µm, and particularly less than 20 µm. In some specific applications, the diameter of µ-LEDs can range from 1 µm to 10 µm.

[0006] µ-LEDs require very low current compared to conventional LEDs with their larger size, resulting in lower overall power consumption and thus reducing the amount of heat generated during operation. This again not only saves power—particularly beneficial for short- and mid-range interconnects—but also simplifies the requirements for heat transfer layers, enabling the dense application of such optoelectronic components. However, in addition to requiring high quantum efficiency to provide sufficient light, data communication also requires high switchability or, more broadly, large amplitude modulation depth at high frequencies. Current optical data communication ranges from hundreds of megahertz to several gigahertz, for example, in the range between 10 GHz and 50 GHz.

[0007] Therefore, current µ-LEDs must be switched on and off within this frequency range, or at least modulated within their respective emission amplitudes. Considering that the light pulses themselves require a certain length to be detected at the receiver, such high frequencies necessitate radiative recombination lifetimes in the tens of picoseconds and shorter. Radiative recombination lifetime is the time required for a minority of charge carriers to recombine under radiation after the current flowing through the µ-LED is interrupted. Therefore, radiative recombination lifetime directly affects the fall time of the light pulses emitted by the µ-LED.

[0008] Various measures have been proposed to reduce the rise and fall times during pulsed or amplitude-modulated transmission, as current µ-LEDs are limited in this respect, resulting in switching times of only a few hundred megahertz and rise and fall times of 100 ps or more.

[0009] As an example, background doping can be performed on the quantum barriers of individual optoelectronic components to increase charge carrier density. While this is suitable in some cases, it requires precise control during the epitaxial growth of the quantum barrier. As an alternative, nonradiative defect centers can be provided within the active region to increase nonradiative recombination, which competes with radiative recombination of charge carriers. However, these induction measures face reliability issues and are difficult to control during device fabrication due to dopant or defect center diffusion and other characteristics.

[0010] Therefore, the object of the present invention is to provide an optoelectronic device that can be used for optical data communication with reduced energy consumption, while maintaining or even increasing the data transmission rate to be achieved or reducing the switching time required for this purpose. Summary of the Invention

[0011] This objective, along with other objectives, is addressed by the subject matter of the independent claims. Features and other aspects of the proposed principles are outlined in the dependent claims.

[0012] The inventors have recognized that for optoelectronic devices such as µ-LEDs based on gallium arsenide (GaAs) or indium aluminum gallium arsenide (InAlGaAs) material systems, increasing the current density through the optoelectronic device increases the carrier concentration in the radiative recombination region. This leads to a higher recombination rate and, consequently, a higher switching speed to be achieved using the optoelectronic device. The current density is thus particularly increased for a given current and size optoelectronic device by reducing the area through which current flows in the active region of the optoelectronic device.

[0013] In one aspect of the proposed principle, optoelectronic devices such as µ-LEDs include a stack of semiconductor layers. The semiconductor layer stack includes a first layer having a first doping type and a second layer having a second doping type. The first doping type may, for example, include n-type doping, while the second doping type may include corresponding p-type doping. In this respect, the first and second layers may each include multiple sublayers comprising different doping concentrations and doping distributions. For example, the doped sublayer opposite the active region may include a higher doping concentration suitable for the current distribution across the entire region of each doped layer.

[0014] An active region is arranged between the first and second layers. In some aspects, the active region may include a simple pn junction. In other aspects, the active region may include a quantum well layer. As an alternative, the active region may include a multi-quantum-well structure having multiple alternating barrier layers and quantum well layers.

[0015] Based on the proposed principle, materials used for semiconductor layer stacking include gallium arsenide (GaAs) or aluminum gallium arsenide (InAlGaAs). The combination of these materials is suitable for emitting light in the red and infrared portions of the emission spectrum. In this regard, aluminum gallium arsenide (InAlGaAs) within the layer stack... x Ga 1-x The aluminum (Al) content of the As layer can vary with parameter x and can range from 0% to 70%. In some aspects, the Al content varies with color and can reach up to 80% in the outer layer, where the Al content decreases along the direction of the active region. For longer wavelengths, i.e., in the infrared spectrum, the Al content can be 30% or lower. In some aspects, the active region may have no Al content or less than 10% in some other aspects, and the active region may include InAlGaAs in which the In content ranges from 0% to 50%. In this respect, the active region may include multiple quantum wells, with a barrier layer having an Al content greater than 10% and a quantum well layer having an Al content less than 10%.

[0016] The semiconductor layer stack includes a top surface and a bottom surface opposite the top surface, as well as mesa-structured side surfaces connecting the top and bottom surfaces. The mesa-structured side surfaces extend from the first layer to the second layer. The side surfaces can be tilted at different angles. In some aspects, the side surfaces extend along specific crystal orientations, particularly in directions that generate only a few natural nonradiative recombination centers. In other aspects, the tilt of the side surfaces can be varied. In particular, the tilt of the side surfaces closer to the active region can be smaller than the tilt of the side surfaces further away, particularly on one of the first and second layers, respectively.

[0017] The semiconductor layer stack also includes a central region having a lateral dimension less than half the lateral dimension of the semiconductor layer stack. Specifically, the semiconductor layer includes a central region extending between a top surface and a bottom surface, and spaced from the side surfaces at least one-quarter of the distance between two opposing side surfaces. The term central region can be specifically understood as an area extending around the centroid of the semiconductor layer stack and spaced from the side surfaces at least one-quarter of the distance between two opposing side surfaces, thus including a lateral dimension less than three-quarters or less than half the lateral dimension of the semiconductor layer stack, wherein the lateral dimension extends in the lateral direction between opposing side surfaces. Less than half the lateral dimension can specifically mean that the area of ​​the central region is less than one-ninth of the area of ​​the semiconductor layer stack.

[0018] Based on the proposed principle, the current path from the first layer through the active region to the second layer is confined to the central region. This can be achieved through several measures proposed in the following aspects. Different aspects allow, for example, optimization of the active region size for high current density / switching speed, while maintaining corresponding dimensions of the semiconductor layer stack to remove heat generated within the optoelectronic device during operation. Improved thermal management can thus have a positive impact on the reliability and lifespan of the optoelectronic device.

[0019] In some aspects, the semiconductor layer stack includes partially oxidized Al. x Ga 1-x As layer, this part of the oxidized Al x Ga 1-x The As layer is disposed between the first layer and the active region and / or between the second layer and the active region. The parameter x is therefore particularly greater than 0.5, and particularly greater than 0.9, and particularly greater than 0.97. Partially oxidized Al x Ga 1-x The oxide portion of the As layer extends from the side surface to the central region, while the Al layer... x Ga 1-x The central region of the As layer remains largely unoxidized. Partially oxidized Al... x Ga 1-x The As layer can, for example, include a thickness in the range of 5 nm to 20 nm and / or optionally be doped. This is achieved by means of partially oxidized Al. x Ga 1-x The oxide portion of the As layer creates a current limit on the current applied to the first and second layers because the oxide region has an insulating effect, and therefore the current only flows through the unoxidized central region, into and through the adjacent active region. While this results in a smaller emission area in the active region, on the other hand, it leads to a higher carrier concentration in the radiative recombination region, resulting in a higher recombination rate and thus improving the switching speed of optoelectronic devices.

[0020] Al x Ga 1-x Oxidation of the As layer can be performed, for example, in a wet furnace after mesa structuring of the semiconductor layer stack. Therefore, the depth of oxidation can be specifically adjusted by, for example, the duration of the oxidation step performed in the wet furnace. Partially oxidized Al x Ga 1-x The As layer can be placed on the first layer, the second layer, or in the barrier / active region of a stack of semiconductor layers.

[0021] In some respects, the active region includes a hybrid region outside the central region, particularly a quantum well hybrid region, which has a larger bandgap than the active region within the central region. By means of the hybrid region in the active region, a current limit is created for the current applied to the first and second layers, because the hybrid region, with its larger bandgap compared to the central region, has more or less an insulating effect or at least a current-guiding effect, and therefore the current flows primarily through the active region via the central region. While this results in a smaller emission area for the active region, on the other hand, it leads to a higher carrier concentration in the radiative recombination region, resulting in a higher recombination rate and therefore a higher switching speed for the optoelectronic device.

[0022] Quantum well mixing can simultaneously lead to an increase in the amount of defects (dangling bonds / nonradiative recombination centers) along the side surfaces of the active region, thereby affecting the likelihood of nonradiative recombination in the active region. In particular, in this way, the diffusion length / mean free path of charge carriers is confined to the central region of the active region, where radiative recombination luminescence can occur, resulting in a shortened charge carrier lifetime.

[0023] The term "carrier lifetime" should specifically be understood as the time *t* until the charge carriers in the active region recombine under light emission or non-radiatively. A high charge carrier lifetime is associated with a high turn-off time for optoelectronic devices, and therefore with a potentially shorter switching time, because the high-lifetime charge carriers in the active region may fully recombine under light emission after the point when the optoelectronic device has been disconnected from its power supply. This "afterglow" does not allow for fast switching frequencies, e.g., in the GHz range. However, by means of quantum well mixing of the active region in the region outside the central region, the charge carrier lifetime can be shortened, resulting in a high turn-off time for the optoelectronic device.

[0024] In some aspects, the active region, and particularly the semiconductor layer stack, includes an ion-implanted region outside the central region, which has a lower conductivity than the active region within the central region, and particularly the semiconductor layer stack within the central region. Ion implantation can be performed, particularly by bombarding the side surfaces of the semiconductor layer stack with ions, thereby creating an ion-implanted region outside the central region. Therefore, the type and amount of ions implanted into the semiconductor layer stack outside the central region can be selected such that the ion-implanted region outside the central region has either lower conductivity or higher insulation properties than within the central region. Furthermore, or alternatively, due to ion implantation, the active region outside the central region can include a larger band gap than within the active region.

[0025] By utilizing an ion-implanted region outside the central region, a current limit is created for the current applied to the first and second layers. This is because the ion-implanted region, with its larger bandgap and / or poorer conductivity compared to the central region, has more or less an insulating or at least current-guiding effect, and therefore the current flows primarily through the central region to the active region. While this results in a smaller emission area for the active region, it also leads to a higher carrier concentration in the radiative recombination region, resulting in a higher recombination rate and thus a higher switching speed for the optoelectronic device.

[0026] As described for quantum well mixing, ion implantation can simultaneously increase the amount of defects (dangling bonds / nonradiative recombination centers) along the side surfaces of the active region, thereby affecting the likelihood of nonradiative recombination in the active region. Specifically, in this way, the diffusion length / mean free path of charge carriers is confined to the central region of the active region, where radiative recombination luminescence can occur, resulting in a shortened charge carrier lifetime. Therefore, by ion implantation into the active region outside the central region, the carrier lifetime can be shortened, leading to a high off-time for optoelectronic devices.

[0027] In some respects, the first and / or second layers are confined to the central region. The first and / or second layers can be selectively grown on the active region such that they are confined to the central region. By doing so, current confinement is created to the first and second layers, as they are confined to the central region, resulting in a current-guiding effect, and thus the current flows primarily through the central region to the active region. While this leads to a smaller emission area in the active region, on the other hand, it results in a higher carrier concentration in the radiative recombination region, leading to a higher recombination rate and therefore a higher switching speed for the optoelectronic device.

[0028] Several other aspects involve semiconductor layer stacking. In some aspects, the semiconductor layer stack includes a first cladding layer and a second cladding layer—specifically, an undoped first cladding layer and a second cladding layer. The cladding layer is positioned directly adjacent to the active region and may comprise, for example, undoped aluminum gallium arsenide. The cladding layer is typically used to prevent undesirable diffusion of dopants from the doped first and second layers into the active region. The thickness of the cladding layer can range from a few nm to tens of nm.

[0029] In some aspects, the active region may include a quantum well layer having a density of 1e16 1 / cm 3 Up to 1e18 1 / cm 3 Additional doping levels fall within a range between these levels. Increased doping levels increase the charge carrier density within the quantum well layer, thereby shortening the carrier lifetime. Combined with other measures, this can further shorten the overall radiation lifetime.

[0030] In some other aspects, the active region comprises a multi-quantum-well structure with multiple alternating barrier layers and quantum well layers. The barrier layers have a higher Al content than adjacent quantum well layers. In this respect, at least two barrier layers may comprise 1e16 1 / cm². 3 Up to 1e18 1 / cm 3 Doping levels within a certain range. Similar to previous implementations, the charge carrier density in the barrier layer increases, thereby shortening the radiation lifetime.

[0031] On the other hand, the active region can include multiple quantum dots, particularly GaAs / AlGaAs quantum dots. Due to the faster recombination of quantum dots, inserting quantum dots into the active region instead of quantum wells can also improve the overall switching speed. Similar to previous implementations, this aspect can be combined with the realization of non-radiative recombination centers.

[0032] In this respect, optoelectronic devices can be implemented as vertical or horizontal optoelectronic devices. In a horizontal optoelectronic device, the device includes respective highly doped or otherwise conductive contact regions on the same side of the layer stack, preferably opposite the main emitting surface of the device. A vertical optoelectronic device includes corresponding highly doped or otherwise conductive contact regions on two opposite sides, wherein one of the contact regions may also include the main emitting surface. The principles presented later in various embodiments are not limited to vertical or horizontal optoelectronic devices, but can be implemented in both.

[0033] In some aspects, the optoelectronic device further includes at least one regenerated layer covering the side surface and / or optionally a passivation layer disposed on the exposed surface of the regenerated layer and / or the exposed surface of the semiconductor layer stack. The at least one regenerated layer can be, for example, a structure of alternating layers with different doping types, such as a pnp or npn structure covering the side surface of the semiconductor layer stack. This implementation can be particularly suitable for current limiting within the semiconductor layer stack, even without any of the aspects described above, when the lateral dimensions of the semiconductor layer stack are reduced to a minimum, thereby reducing the emission area of ​​the active region. Simultaneously, this results in a higher carrier concentration in the radiative recombination region, leading to a higher recombination rate and consequently improving the switching speed of the optoelectronic device. Therefore, at least one regenerated layer and / or passivation layer acts as a current-limiting structure for guiding current through the active region and protecting the side surface from other undesirable influences.

[0034] In some aspects, the optoelectronic device further includes a first contact element disposed on a first layer and / or a second contact element disposed on a second layer. The first and / or second contact elements are specifically used to provide power current to the optoelectronic device. The first and / or second contact elements may be, for example, transparent conductive oxides (TCOs) used to allow light generated in the active region to be emitted from the optoelectronic device, and / or, when viewed from the bottom surface, the first and second contact elements may include a structure in which the central region of the first and / or second layers remains without the first contact element and is particularly formed in a ring shape. However, it is also conceivable that the first and / or second contact elements completely cover the respective underlying semiconductor layers.

[0035] According to at least one aspect, the central region of the active region comprises a lateral dimension smaller than the diffusion length of the material system of the active region. In this way, the charge carrier lifetime can be further shortened, and the desired switching time of the optoelectronic device can be achieved.

[0036] According to at least one aspect, the optoelectronic device is configured to have an on-time and / or off-time in the range of 0.5 ns to 10 ns, particularly as low as 0.1 ns. With such switching times, fast switching frequencies, for example, in the GHz range, can be achieved.

[0037] According to another aspect of the invention, the optoelectronic device according to at least one of the above aspects can be used as an apparatus for short-range communication, particularly less than 10 m, for optical data communication. The optoelectronic device according to at least one of the above aspects can be particularly used for data transmission in large data centers, etc., to transmit data over short distances (<<10 m), such as from CPU to GPU, server to server, and / or rack to rack.

[0038] Other aspects relate to methods for manufacturing optoelectronic devices. This method provides a semiconductor layer stack having a first layer and a second layer. The first layer includes a first doping type, and the second layer includes a second doping type. An active region is disposed between the first and second layers. The semiconductor layer stack thus includes a material comprising at least one of phosphides and arsenides, and is, for example, based on a GaAs / AlGaAs material combination.

[0039] In a further step, a mesa etching process is performed to form a side surface that connects the top and bottom surfaces of the semiconductor layer stack and exposes a portion of the active region on its circumferential perimeter. In a top view, the perimeter may have a shape such as circular, rectangular, or polygonal, like a hexagon.

[0040] The semiconductor layer stack is then processed in such a way that a central region is formed, having a lateral dimension less than half that of the semiconductor layer stack, and such that the current path from the first layer through the active region to the second layer is confined to this central region. Thus, the semiconductor layer stack is processed to achieve current confinement of the current applied to the first and second layers, limiting it to at least the central region of the active region. This can be achieved through several measures proposed in the following aspects. These different aspects allow, for example, optimization of the active region size for high current density / switching speed, while maintaining a corresponding size of the semiconductor layer stack to remove heat generated within it during operation of the optoelectronic device. Improved thermal management can thus have a positive impact on the reliability and lifespan of the optoelectronic device.

[0041] In some aspects, the steps of providing semiconductor layer stacking include depositing Al x Ga 1-x As layer, Al x Ga 1-x The As layer is positioned between the first layer and the active region and / or between the second layer and the active region. The parameter x is therefore particularly greater than 0.5, and particularly greater than 0.9, and particularly greater than 0.97. x Ga 1-x The As layer may include, for example, a thickness in the range of 5 nm to 20 nm and / or optionally be doped with the same range as the first and second doped layers in the layer stack. Suitable doping concentrations are known to those skilled in the art.

[0042] In some aspects, the steps of processing semiconductor layer stacking include Al x Ga 1-x The As layer undergoes partial oxidation, resulting in partially oxidized Al. x Ga 1-x The oxidized portion of the As layer extends from the side surface to the central region, with the central portion remaining substantially unoxidized. Therefore, the semiconductor layer stack comprises partially oxidized Al. x Ga 1-x As layer, this part of the oxidized Al x Ga 1-x The As layer is disposed between the first layer and the active region and / or between the second layer and the active region. Partially oxidized Al x Ga 1-x The oxide portion of the As layer extends from the side surface to the central region, while the Al layer... x Ga 1-x The central region of the As layer remains largely unoxidized. This is achieved through the partial oxidation of Al. x Ga 1-xThe oxide portion of the As layer creates a current limit on the current applied to the first and second layers because the oxide region has an insulating effect, and therefore the current only flows through the unoxidized central region, into and through the adjacent active region. While this results in a smaller emission area of ​​the active region, on the other hand, it leads to a higher carrier concentration in the radiative recombination region, resulting in a higher recombination rate and therefore a higher switching speed for optoelectronic devices.

[0043] Al x Ga 1-x Oxidation of the As layer can be performed, for example, in a wet furnace after mesa structuring of the semiconductor layer stack. Therefore, the depth of oxidation can be specifically adjusted by, for example, the duration of the oxidation step performed in the wet furnace. Partially oxidized Al x Ga 1-x The As layer can be arranged on the first layer, the second layer, or both of the semiconductor layers in the barrier / active region.

[0044] In some aspects, the steps of processing the semiconductor layer stack include: implanting ions into the semiconductor layer stack at least outside the active region and particularly outside the central region, forming an ion-implanted region outside the central region, which has a lower conductivity and / or a larger band gap than the active region inside the central region and particularly outside the semiconductor layer stack inside the central region. Ion implantation can be performed by bombarding the side surfaces with ions followed by, for example, annealing, such that the semiconductor layer stack at least outside the active region and particularly outside the central region forms an ion-implanted region outside the central region, which has a lower conductivity and / or a larger band gap than the active region inside the central region and particularly outside the semiconductor layer stack inside the central region. The ion-implanted region outside the central region creates a current limit on the current applied to the first and second layers because the ion-implanted region has an insulating effect, and therefore the current flows only through the active region to the central region. While this results in a smaller emission area for the active region, on the other hand, it results in a higher carrier concentration in the radiative recombination region, leading to a higher recombination rate and therefore a higher switching speed for the optoelectronic device.

[0045] In some aspects, the steps of processing semiconductor layer stacking include: mixing the active regions outside the central region (particularly quantum well mixing) to form a region of the active region with a larger bandgap than the active region inside the central region. By means of the mixed region outside the central region, a current limit is created on the current applied to the first and second layers, because the mixed region has an insulating effect, and therefore the current flows only through the active region via the central region. While this results in a smaller emission area of ​​the active region, on the other hand, it results in a higher carrier concentration in the radiative recombination region, leading to a higher recombination rate and therefore a higher switching speed for the optoelectronic device. Therefore, the mixing of the active regions can be performed by any known process known in the art.

[0046] In some aspects, the steps of providing or processing a semiconductor layer stack include: structuring and / or selectively growing a first and / or second layer such that the first and / or second layers are confined to a central region. Specifically, selectively growing the first and / or second layers on an active region includes providing a hard mask, such as SiO2 or Si3N4, on an active region adjacent to the central region, and growing the first and / or second layers on the active region within the central region. The confinement of the first and / or second layers results in current limitation on the current applied to the first and second layers, as the current flows only through the active region to the central region. While this results in a smaller emission area of ​​the active region, on the other hand, it results in a higher carrier concentration in the radiative recombination region, leading to a higher recombination rate and therefore a higher switching speed for the optoelectronic device. Therefore, structuring and / or growing the first and / or second layers can be performed by any known process known in the art.

[0047] In some aspects, the method further includes the step of regenerating at least one regenerated layer on a side surface and / or optionally growing a passivation layer on the exposed surface of the regenerated layer and / or the exposed surface of the semiconductor layer stack.

[0048] In some aspects, the method further includes the steps of providing a first contact element on a first layer and / or providing a bottom contact element on a second layer. The first contact element and / or the second contact element can thus be formed according to the aspects described above for optoelectronic devices.

[0049] In some aspects, the steps of providing a semiconductor layer stack include: providing a first cladding layer and a second cladding layer directly adjacent to the active region, particularly undoped first and second cladding layers. In this regard, the semiconductor layer stack includes, in some aspects, a first cladding layer and a second cladding layer directly adjacent to the active region, particularly undoped first and second cladding layers. These layers prevent the diffusion of dopants but can also serve as charge carrier blocking structures.

[0050] The optoelectronic devices presented in this paper, such as µ-LEDs, are suitable for a variety of applications requiring high switching or current modulation frequencies. In some respects, optoelectronic devices based on the proposed principles are used for optical data communication, particularly for short- and medium-range optical data communication at modulation frequencies greater than 1 GHz and especially greater than 10 GHz. Attached Figure Description

[0051] Referring to the various embodiments and examples described in detail with reference to the accompanying drawings, other aspects and embodiments based on the proposed principles will become apparent, in conjunction with the accompanying drawings:

[0052] Figures 1A to 1D The steps of a method for manufacturing optoelectronic devices based on some aspects of the proposed principles are shown;

[0053] Figures 2A to 2D The steps of a method for manufacturing an optoelectronic device according to some aspects of the proposed principles are shown;

[0054] Figure 3a to Figure 3D The steps of a method for manufacturing an optoelectronic device according to some aspects of the proposed principles are shown;

[0055] Figures 4A to 4D The steps of a method for manufacturing an optoelectronic device according to some aspects of the proposed principles are shown; and

[0056] Figures 5A to 5D The steps of a method for manufacturing an optoelectronic device according to some aspects of the proposed principles are shown. Detailed Implementation

[0057] The following embodiments and examples disclose various aspects and combinations thereof based on the proposed principles. The embodiments and examples are not always drawn to scale. Similarly, different elements may be shown enlarged or reduced in size to emphasize various aspects. It goes without saying that the aspects of the embodiments and examples shown in the figures can be combined with each other without contradiction to the principles of the invention. Some aspects show regular structures or forms. It should be noted that in practice, minor differences and deviations from the ideal form may occur; however, this does not contradict the concept of the invention.

[0058] Furthermore, the various figures and aspects are not necessarily shown at the correct size, and the proportions between the elements need not be substantially accurate. Some aspects are highlighted by showing them enlarged. However, terms such as "above," "over," "below," "under," "larger," and "smaller" correctly denote the elements in the figures. Therefore, such relationships between elements can be inferred from the figures.

[0059] Figures 1A to 1D The steps of a method for fabricating optoelectronic devices, particularly µ-LEDs 1, based on the proposed principles are illustrated. These steps are performed in a similar manner in all the corresponding embodiments shown herein. However, certain variations and deviations from the illustrated steps can be achieved without departing from the overall scope. Furthermore, although only vertical optoelectronic devices are shown herein, it will be appreciated that the proposed principles are not limited to such devices. Instead, the respective contact regions can be arranged on the same side, with vias passing through the active region and connecting to the desired doped layer.

[0060] Figure 1A The epitaxial deposition of the semiconductor layer stack 2 on a corresponding growth substrate 11 is shown. The growth substrate 11 includes an n-doped gallium arsenide layer that serves as a wafer substrate, on which subsequent layers are epitaxially deposited. Furthermore, the n-doped gallium arsenide substrate may include multiple buffer layers to make its surface smooth and flat, for example, to provide a substantially defect-free surface.

[0061] In subsequent steps, an n-type doped aluminum gallium arsenide layer 3 is epitaxially deposited as a first semiconductor layer on the surface of the growth substrate. The first layer 3 may include a doping distribution and / or varying doping concentrations based on desired requirements. For example, the doping concentration closer to the growth substrate 11 may be greater than the doping concentration further away to improve carrier injection into the aluminum gallium arsenide layer 3. Furthermore, the aluminum content of the first layer 3 may vary, and a corresponding distribution may be included across the thickness of the first layer 3. In this regard, the first layer 3 may include one or more sublayers in which the aforementioned variations in dopant and Al content concentration and distribution are implemented.

[0062] At the top of the first layer 3, the first Al is arranged. x Ga 1-x Layer 12, where parameter x is greater than 0.5, and particularly greater than 0.9, and particularly greater than 0.97. First Al x Ga 1-x As layer 12 may specifically include such that the first Al x Ga 1-x As layer 12 can be easily oxidized due to its high Al content.

[0063] First Al x Ga 1-x An undoped aluminum gallium arsenide (AGa) first cladding layer 14 is deposited on top of the As layer 12. The aluminum content of this layer can be similar to that of the first layer 3, but can also be varied to improve the transport and diffusion of charge carriers into the active region 5 epitaxially deposited on top of the first cladding layer 14. The thickness of the first cladding layer 14 is in the range of 10 nm to 50 nm. The purpose of the first cladding layer 14 is to prevent dopants from escaping from the first layer 3 and the first Al layer 12, respectively. x Ga 1-x As layer 12 diffuses into active region 5.

[0064] The active region 5 is deposited on the first cladding layer 14 and, in this embodiment, includes a pn junction or a multiple quantum well structure. The multiple quantum well structure, for example, includes multiple barrier layers and quantum well layers, with the aluminum content of the barrier layers slightly greater than that of the individual quantum well layers. Therefore, a varying bandgap is provided in the semiconductor material of the active region 5, trapping charge carriers between the "valleys" of the bandgap.

[0065] The active region 5 is covered by another aluminum gallium arsenide cladding layer 15, which is similar to the first cladding layer 14.

[0066] On top of the second covering layer 15, a second Al is arranged. x Ga 1-x As layer 13, where parameter x is greater than 0.5, and particularly greater than 0.9, and particularly greater than 0.97. Second Al x Ga 1-x As layer 13 may specifically include Al content, such that the second Al x Ga 1-x As layer 13 can be easily oxidized.

[0067] In the second Al x Ga 1-x A p-doped layer 4 is deposited on top of the As layer 13 as a second semiconductor layer. Similar to the n-type doped layer 3, the doping concentration and doping distribution of the p-type doped aluminum gallium arsenide layer 4 can be varied.

[0068] In this regard, both layers 3 and 4 may include not only aluminum gallium arsenide sublayers, but also one or more gallium arsenide sublayers or aluminum gallium arsenide sublayers with different aluminum contents. The purpose of these sublayers is to distribute the injected charge carriers throughout the entire region of the semiconductor layer stack 2 and to provide a continuous and uniform diffusion toward the active region.

[0069] The top surface of the second layer 4 is covered by a highly doped gallium arsenide contact layer 16. The contact layer 16 not only provides a connection to a conductive metal or a transparent conductive oxide, but also serves as the main emission surface during the later operation of the device 1.

[0070] First Al x Ga 1-x As layer 12 and second Al x Ga 1-x As layer 13 is, for example, a very thin layer containing aluminum gallium arsenide with a high aluminum content, introduced between the first layer 3 and the second layer 4 and the corresponding cladding layers 14 and 15, or more generally, between the first layer 3 and the second layer 4 and the active region 5. x Ga 1-x The aluminum content of the As layer includes a very high aluminum content, where parameter x is greater than 0.9 and particularly greater than 0.97.

[0071] The next step of the proposed method is... Figure 1B As shown in the figure, a mask layer material (not shown) is deposited on the p-type doped gallium arsenide contact layer 16, and then the mask layer material (not shown) is structured to form the central portion of the hard mask layer.

[0072] In the top view, the central portion forms a circular, rectangular, or any other polygonal structure such as a hexagon. Then, one or more mesa etching steps are performed to provide side surfaces 2c that expose the active region 5 and the facets of the first layer 3 and the second layer 4, respectively. The result of the mesa etching process is... Figure 1B As shown, this can be achieved through several subsequent mesa etching steps. In the two-step process, after the first etching step, the side surfaces 2c of the semiconductor layer stack 2, and particularly the active region 5, can also be cleaned and annealed to remove any plasma damage from the side surfaces 2c.

[0073] For example, in the first mesa etching step, a plasma etching process or any similar suitable method is used to remove the contact layer 16, the p-type doped aluminum gallium arsenide layer 4, the cladding layers 14 and 15, and the first Al x Ga 1-x As layer 12 and second Al x Ga 1-x The material of As layer 13 and active region 5. The exposed surfaces are cleaned and annealed using NH3 or other suitable gases. Cleaning reduces damage and nonradiative recombination centers after the mesa etching process, resulting in a more clearly defined side surface 2c with preferably only a small number of nonradiative recombination centers and therefore a well-defined surface condition.

[0074] To increase the charge carrier density within the active region 5, then as Figure 1C The process shown applies to semiconductor layer stack 2. Therefore, the semiconductor layer stack is exposed to an oxygen-containing atmosphere (indicated by the two arrows), initiating the first Al... x Ga 1-x As layer 12 and second Al x Ga 1-x Oxidation of aluminum within layer 13. Due to the oxygen-containing atmosphere and the high Al content of layers 12 and 13, portions of layers 12 and 13 starting from side surface 2c are oxidized, resulting in thin oxidized portions of layers 12 and 13 extending to the central region 10 of the semiconductor layer stack 2.

[0075] Oxidation leads to the first Al x Ga 1-x As layer 12 and second Al x Ga 1-x The conductivity of As layer 13 is confined to some of its smaller central portions, similar to the apertures used for charge carriers, such as... Figure 1D As shown. Therefore, the charge density within the active region 5 in the central region is significantly increased by the resulting porous structure, while simultaneously, for example, a certain amount of non-radiative recombination centers can be formed below and above the active region 5 and around its circumference. In this way, the rise and fall times of the optoelectronic device can be reduced by changing the charge carrier density within the active region.

[0076] In order to obtain such Figure 1D The illustrated optoelectronic device removes the growth substrate 11 and provides top contact elements 7a and bottom contact elements 7b on the top surface 2a and bottom surface 2b of the semiconductor layer stack 2, and passivates the side surfaces by means of a passivation layer 8. In the illustrated embodiment, the bottom contact element 7a is exemplaryly arranged on the bottom surface 2a, and the bottom contact element 7a includes an annular shape so that the central region 10 of the semiconductor layer stack 2 is not covered.

[0077] The method based on the proposed principle follows the latter approach, but can be combined with other measures to increase charge density or bandgap structure to provide faster radiative recombination.

[0078] Figures 2A to 2D The corresponding implementation is shown. Figure 2A and Figure 2B The steps of providing the semiconductor layer stack 2 and structuring the semiconductor layer stack 2 as shown are thus related to Figure 1A and Figure 1B The illustrated implementation is related, but does not provide a first Al. x Ga 1-x As layer and second Al x Ga 1-x As layer. To increase the charge carrier density within the active region 5, then as Figure 2C The semiconductor layer stack shown is 2.

[0079] To increase the charge carrier density within the active region 5, a structured mask 9 is provided on the semiconductor layer stack 2 to perform quantum well mixing of the active region 5 in the region between the side surface 2c and the central region 10 (indicated by the vertical arrow). Thus, the mixed region 17 of the active region 5 produces a band gap with a larger band gap than the active region within the central region 10 where quantum well mixing is not performed.

[0080] The mixing results in a higher bandgap in the active region 5 outside the central region 10. Consequently, the charge density within the active region 5 inside the central region is significantly increased through the resulting porous structure, while simultaneously, a certain amount of nonradiative recombination centers are formed below and above the active region 5, as well as around its circumference. In this way, the rise and fall times of the optoelectronic device can be reduced by altering the charge carrier density within the active region and increasing the amount of nonradiative recombination centers in the mixing region 17.

[0081] In order to obtain such Figure 2DThe illustrated optoelectronic device removes the growth substrate 11, and top contact elements 7a and bottom contact elements 7b are disposed on the top surface 2a and bottom surface 2b of the semiconductor layer stack 2, and the side surface 2c is passivated by means of a passivation layer 8. In the illustrated embodiment, the bottom contact element 7a is exemplary disposed on the bottom surface 2a, and the bottom contact element 7a includes an annular shape so that the central region 10 of the semiconductor layer stack 2 is not covered.

[0082] Figures 3A to 3D Another embodiment is shown where the current is limited to the central region of the optoelectronic device 1. Figure 3A and Figure 3B The steps of providing the semiconductor layer stack 2 and structuring the semiconductor layer stack 2 as shown are thus related to Figure 2A and Figure 2B The illustrated implementation differs in that it provides an active region with a simple pn junction instead of a quantum well or multiple quantum well layers. However, this is to be understood as exemplary, and other implementations may also be employed as follows: Figure 2A and Figure 2B The same method is shown. To increase the charge carrier density within the active region 5, then as shown... Figure 3C The semiconductor layer stack shown is 2.

[0083] To increase the charge carrier density within the active region 5, a structured mask 9 is provided on the semiconductor layer stack 2 to perform ion bombardment (indicated by arrows) on the side surface 2c of the semiconductor layer stack 2 in the region between the side surface 2c and the central region 10. As a result, the ion-implanted region 18 of the semiconductor layer stack 2 produces a conductivity that is semi-insulating and particularly poor compared to the semiconductor layer stack 2 within the central region 10. Furthermore, ion bombardment can cause the active region outside the central region 10 to have a larger band gap than the active region 5 within the central region 10.

[0084] Ion bombardment results in a difference in conductivity between the layers adjacent to the active region 5 and a higher bandgap in the active region 5 outside the central region 10. Consequently, the charge density within the active region 5 in the central region is significantly increased through the resulting porous structure, while simultaneously a certain amount of nonradiative recombination centers are formed below and above the active region 5, as well as around its circumference. In this way, the rise and fall times of the optoelectronic device can be reduced by altering the charge carrier density within the active region and increasing the amount of nonradiative recombination centers in the mixing region 17.

[0085] In order to obtain such Figure 3DThe illustrated optoelectronic device removes the growth substrate 11 and provides a top contact element 7a and a bottom contact element 7b on the top surface 2a and bottom surface 2b of the semiconductor layer stack 2. In the illustrated embodiment, the bottom contact element 7a is exemplary disposed on the bottom surface 2a and includes an annular shape so that the central region 10 of the semiconductor layer stack 2 is not covered.

[0086] Figures 4A to 4D Another embodiment is shown where the current is limited to the central region of the optoelectronic device 1. Figures 4A to 4C The steps of providing the semiconductor layer stack 2 and structuring the semiconductor layer stack 2 as shown are thus related to Figure 3A and Figure 3B The illustrated embodiment differs in that the structured mask 9 is used to selectively deposit the second layer 4 and the contact layer 16 only in the central region 10 of the semiconductor layer stack 2 on the active region 5. In this embodiment, this step can be understood as a step to increase the charge carrier density within the active region 5. Then as... Figure 4C The semiconductor layer stack 2 is structured into a mesa to obtain the side surface 2c of the semiconductor layer stack 2.

[0087] Selective growth results in current being fed into the active region 5 only in the central region 10. Therefore, the charge density within the active region 5 inside the central region is significantly increased by the resulting porous structure. In this way, the rise and fall times of the optoelectronic device can be reduced by altering the charge carrier density within the active region 5.

[0088] In order to obtain such Figure 4D The illustrated optoelectronic device removes the growth substrate 11, and top contact elements 7a and bottom contact elements 7b are disposed on the top surface 2a and bottom surface 2b of the semiconductor layer stack 2, and the side surface 2c is passivated by means of a passivation layer 8. In the illustrated embodiment, the bottom contact element 7a is exemplary disposed on the bottom surface 2a, and the bottom contact element 7a includes an annular shape so that the central region 10 of the semiconductor layer stack 2 is not covered.

[0089] Figures 5A to 5D Another embodiment is shown where the current is limited to the central region of the optoelectronic device 1. Figure 5A and Figure 5B The steps of providing the semiconductor layer stack 2 and structuring the semiconductor layer stack 2 as shown are thus related to Figure 3A and Figure 3B The embodiment shown differs from the one described above in that, by using a structured mask 9 for mesa structuring, the smaller semiconductor layer stack 2 is pixelated with a smaller lateral dimension compared to the embodiment described above.

[0090] In this way, compared to a larger layer stack 2 with a larger lateral dimension and assuming the same current is applied to the active region 5, the charge carrier density within the active region 5 can be increased. To further improve the efficiency of the optoelectronic device, a regrown layer 6 is disposed along the side surface 2c of the semiconductor layer stack 2. The regrown layer 6 can be, for example, a structure of alternating layers with different doping types, such as a pnp or npn structure covering the side surface 2c of the semiconductor layer stack 2. This implementation, combined with any of the aspects described above, can also be particularly suitable for current confinement within the semiconductor layer stack 2. This results in a higher carrier concentration in the radiative recombination region, leading to a higher recombination rate and therefore a higher switching speed of the optoelectronic device 1. Thus, the regrown layer 6 acts as a current-confining structure for guiding current through the active region 5 and protecting the side surface 2c from undesirable influences.

[0091] In order to obtain such Figure 5D The illustrated optoelectronic device removes the growth substrate 11 and provides a top contact element 7a and a bottom contact element 7b on the top surface 2a and bottom surface 2b of the semiconductor layer stack 2. In the illustrated embodiment, the bottom contact element 7a is exemplary disposed on the bottom surface 2a and includes an annular shape so that the central region 10 of the semiconductor layer stack 2 is not covered.

[0092] List of reference numerals

[0093] 1. Optoelectronic device, µ-LED

[0094] 2-layer stack

[0095] 2a Top Surface

[0096] 2b bottom surface

[0097] 2c side surface

[0098] 3 floors

[0099] 4 floors

[0100] 5 active areas

[0101] 6 Regeneration Layer

[0102] 7a Contact Element

[0103] 7b Contact Element

[0104] 8 passivation layers

[0105] 9 masks

[0106] 10 Central Districts

[0107] 11 Growth substrate

[0108] 12Alx Ga 1-x As layer

[0109] 13Al x Ga 1-x As layer

[0110] 14 coating layers

[0111] 15 coating layers

[0112] 16 contact layers

[0113] 17 Mixed Zone

[0114] 18. Injection area.

Claims

1. A µ-LED (1), comprising: A semiconductor layer stack (2) having a first layer (3) of a first doping type, a second layer (4) of a second doping type, and an active region (5) disposed between the first layer (3) and the second layer (4); The semiconductor layer stack (2) includes a bottom surface (2a) and a top surface (2b) and a mesa-structured side surface (2c) connecting the top surface (2b) and the bottom surface (2a). The semiconductor layer stack (2) includes a central region (10), which has a lateral dimension that is less than half or three-quarters of the lateral dimension of the semiconductor layer stack (2). Wherein, the semiconductor layer stack (2) comprises a material containing at least one of phosphide and arsenide; and The current path from the first layer (3) through the active region (5) to the second layer (4) is restricted to the central region (10).

2. The µ-LED according to claim 1, wherein, The semiconductor layer stack (2) includes partially oxidized Al x Ga 1-x As layers (12, 13), the partially oxidized Al x Ga 1-x Layers As (12, 13) are arranged between the first layer (3) and the active region (5) and / or between the second layer (4) and the active region (5). Wherein, the parameter x is greater than 0.5, and in particular greater than 0.9, and in particular greater than 0.

97. Among them, the partially oxidized Al x Ga 1-x The oxidized portion of the As layer (12, 13) extends from the side surface (2c) to the central region (10), and the Al x Ga 1-x The central region (10) of the As layers (12, 13) remains substantially unoxidized, and Optionally, the partially oxidized Al x Ga 1-x The As layers (12, 13) include thicknesses ranging from 5 nm to 20 nm; and / or Optionally, the partially oxidized Al x Ga 1-x The As layers (12, 13) are doped.

3. The µ-LED according to claim 1 or 2, wherein, The active region (5) includes a hybrid region (17) outside the central region (10), particularly including a quantum well hybrid region (17) having a larger band gap than the active region (5) within the central region (10).

4. The µ-LED according to any one of claims 1 to 3, wherein, The active region (5), particularly the semiconductor layer stack (2), includes an ion implantation region (18) outside the central region (10), the ion implantation region (18) having a lower conductivity and / or a larger band gap than the active region (5) within the central region (10) and particularly than the semiconductor layer stack (2) within the central region (10).

5. The µ-LED according to any one of claims 1 to 4, wherein, The first layer (3) and / or the second layer (4) are confined to the central area (10).

6. The µ-LED according to any one of claims 1 to 5, wherein, The semiconductor layer stack (2) includes a first cladding layer (14) and a second cladding layer (14, 15) directly adjacent to the active region (5), and specifically includes an undoped first cladding layer (14) and an undoped second cladding layer (15).

7. The µ-LED according to any one of claims 1 to 6, wherein, The active region (5) includes at least one of the following: - At least one quantum well layer, said at least one quantum well layer comprising 1e16 1 / cm 3 With 1e18 2 / cm 3 Doping levels within the range between; - At least two barrier layers, said at least two barrier layers surrounding at least one quantum well layer, said at least two barrier layers comprising 1e16 1 / cm 3 With 1e18 1 / cm 3 Doping levels within the range between; - Multiple quantum dots.

8. The µ-LED according to any one of claims 1 to 7 further comprises at least one regenerated layer (6) covering the side surface (2c), and / or optionally includes a passivation layer (8) disposed on the exposed surface of the regenerated layer (6) and / or the exposed surface of the semiconductor layer stack (2).

9. The µ-LED according to any one of claims 1 to 8 further comprises a first contact element (7a) disposed on the first layer (3) and / or a second contact element (7b) disposed on the second layer (4).

10. The µ-LED according to claim 9, wherein, When viewed on the bottom surface (2a), the central area of ​​the first layer (3) remains without the first contact element (7a), which in particular includes an annular form.

11. The µ-LED according to any one of the preceding claims, wherein, The central region (10) of the active region (5) includes a lateral dimension smaller than the diffusion length of the material system of the active region (5).

12. The µ-LED according to any one of the preceding claims, wherein, The µ-LED (1) is configured to have an on-time and / or off-time in the range of 0.1 ns to 10 ns.

13. The µ-LED (1) according to any one of the preceding claims is used as an apparatus for optical data communication, particularly as an apparatus for short-range communication of less than 10 m.

14. A method for manufacturing µ-LEDs (1), comprising the following steps: A semiconductor layer stack (2) is provided, the semiconductor layer stack (2) having a first layer (3) of a first doping type, a second layer (4) of a second doping type and an active region (5) disposed between the first layer (3) and the second layer (4), wherein the semiconductor layer stack (2) comprises a material containing at least one of phosphide and arsenide; The semiconductor layer stack (2) is structured such that the semiconductor layer stack (2) includes a side surface (2c) connecting the top surface and bottom surface (2a, 2b) of the semiconductor layer stack (2). The semiconductor layer stack (2) is processed to form a central region (10) having a lateral dimension less than half the lateral dimension of the semiconductor layer stack (2) and such that the current path from the first layer (3) through the active region (5) to the second layer (4) is restricted to the central region (10).

15. The method according to claim 14, wherein, The steps of providing the semiconductor layer stack (2) include: - Deposited Al x Ga 1-x As layer (12, 13), the Al x Ga 1-x Layers As (12, 13) are arranged between the first layer (3) and the active region (5) and / or between the second layer (13) and the active region (5), wherein parameter x is greater than 0.5, and particularly greater than 0.9, and particularly greater than 0.97; and wherein - Optionally, the Al x Ga 1-x The As layers (12, 13) include thicknesses ranging from 5 nm to 20 nm; and / or wherein - Optionally, the Al x Ga 1-x The As layers (12, 13) are doped.

16. The method according to claim 15, wherein, The step of processing the semiconductor layer stack (2) includes: For the Al x Ga 1-x The As layers (12, 13) undergo partial oxidation, resulting in partially oxidized Al. x Ga 1-x The oxidized portion of the As layer (12, 13) extends from the side surface (2c) to the central region (10), and makes the Al x Ga 1-x The portion of the As layer (12, 13) within the central region (10) remains substantially unoxidized.

17. The method according to any one of claims 14 to 16, wherein, The step of processing the semiconductor layer stack (2) includes: Ions are implanted into the semiconductor layer stack (2) outside at least the active region (5) and particularly the central region (10) to form an ion implantation region (18) outside the central region (5), the ion implantation region (18) having a poorer conductivity and / or a larger band gap than the active region (5) within the central region (10) and particularly the semiconductor layer stack (2) within the central region (10).

18. The method according to any one of claims 14 to 17, wherein, The step of processing the semiconductor layer stack (2) includes: The active region (5) outside the central region (10) is mixed, particularly the quantum well is mixed, to form a mixed region (17) of the active region (5) having a larger band gap than the active region (5) inside the central region (10).

19. The method according to any one of claims 14 to 18, wherein, The step of processing the semiconductor layer stack (2) includes: The first layer (3) and / or the second layer (4) are structured such that the first layer (3) and / or the second layer (4) are confined to the central region (10).

20. The method according to any one of claims 14 to 19, further comprising the steps of regrowing at least one regrowing layer (6) on the side surface (2c) and / or optionally growing a passivation layer (8) on the exposed surface of the regrowing layer (6) and / or on the exposed surface of the semiconductor layer stack (2).

21. The method according to any one of claims 14 to 20, further comprising the steps of providing a first contact element (7a) on the first layer (3) and / or providing a second contact element (7b) on the second layer (4).

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