PCIe interrupt verification method and device, hardware simulation equipment and medium

Abstract

The embodiment of the invention discloses a PCIe interrupt verification method and device, hardware simulation equipment and a medium, and relates to the field of chip verification. The method is executed by a hardware simulation device, the hardware simulation device runs a to-be-tested design and an interrupt processing engine, the to-be-tested design is an RTL code of a PCIe controller, and the method comprises the following steps: generating an interrupt signal triggered by a PCIe interrupt trigger event through the to-be-tested design; determining an interrupt processing mode of the interrupt signal through an interrupt processing engine; and performing interrupt processing on the interrupt signal according to the interrupt processing mode through an interrupt processing engine to obtain an interrupt processing result which is used for determining a verification result of the to-be-tested design. By adopting the PCIe interrupt verification method provided by the invention, the resource bottleneck caused by a host and a Speed Bridge in related technologies is eliminated, the verification efficiency and the test throughput are improved, and the feasibility of large-scale pressure test is realized.

Description

Technical Field

[0001] This application relates to the field of chip verification, and in particular to a PCIe interrupt verification method, apparatus, hardware simulation device and medium. Background Technology

[0002] PCIe interrupt verification is used to ensure that the PCIe interrupt mechanism between PCIe devices (such as graphics cards, SSDs, network cards, etc.) and the host system operates reliably. For example, in an Emulation (hardware emulation) environment, errors that trigger PCIe interrupts can be artificially injected into the RTL code of the PCIe controller to check whether the RTL code of the PCIe controller can meet expectations in the process of interrupt signal generation, transmission, and response.

[0003] In related technologies, a hardware emulator typically runs the RTL code of the PCIe controller, and a dedicated hardware adapter (such as a Speed ​​Bridge) is used to establish communication connections between the hardware emulator and the PCIe device, as well as between the hardware emulator and the host system. For example, when a PCIe interrupt trigger event occurs, the PCIe device sends a trigger command to the hardware emulator via the Speed ​​Bridge. The hardware emulator generates an interrupt signal based on the trigger command and sends the interrupt signal to the host system via the Speed ​​Bridge. The host system processes the interrupt signal according to its interrupt signal handling logic and then sends an ACK response back to the hardware emulator via the Speed ​​Bridge.

[0004] However, for hardware emulators, the aforementioned process relies on external devices such as the Speed ​​Bridge and the host system, resulting in significant communication latency and reducing the efficiency of PCIe interrupt verification. Furthermore, the Speed ​​Bridge and the host system may create an interaction bottleneck, limiting test throughput and the feasibility of large-scale interrupt stress testing. Summary of the Invention

[0005] This application provides a PCIe interrupt verification method, apparatus, hardware simulation device, and medium. The technical solution is as follows: On one hand, embodiments of this application provide a PCIe interrupt verification method, which is executed by a hardware emulation device. The hardware emulation device runs a design under test (DUT) and an interrupt handling engine. The DUT is the RTL code of a PCIe controller. The method includes: The design under test generates an interrupt signal triggered by a PCIe interrupt event. The interrupt handling engine determines the interrupt handling method for the interrupt signal. The interrupt signal is processed by the interrupt processing engine according to the interrupt processing method to obtain the interrupt processing result, which is used to determine the verification result of the design under test.

[0006] On the other hand, embodiments of this application provide a PCIe interrupt verification device, which is applied to a hardware emulation device, and the device includes: The design under test (DUT) is used to generate an interrupt signal triggered by a PCIe interrupt event. The DUT is the RTL code of the PCIe controller. An interrupt handling engine is used to determine the interrupt handling method for the interrupt signal; The interrupt handling engine is also used to perform interrupt processing on the interrupt signal according to the interrupt processing method to obtain an interrupt processing result, which is used to determine the verification result of the design under test.

[0007] On the other hand, embodiments of this application provide a hardware simulation device, which includes a processor and a memory. The memory stores at least one computer instruction, which is loaded and executed by the processor to implement the method described above.

[0008] On the other hand, embodiments of this application provide a computer-readable storage medium storing at least one computer instruction, which is loaded and executed by a processor to implement the method described above.

[0009] On the other hand, embodiments of this application provide a computer program product including computer instructions stored in a computer-readable storage medium. A processor of a hardware emulation device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the hardware emulation device to perform the methods provided in the various optional implementations of the above aspects.

[0010] In this embodiment, the hardware simulation device runs the design under test (RTL code of the PCIe controller) and an interrupt handling engine. Since the interrupt handling engine replaces the host system's interrupt signal processing logic in related technologies, when the design under test generates an interrupt signal triggered by a PCIe interrupt event, the hardware simulation device does not need to request the interrupt handling method from the host system. Instead, it can directly determine the interrupt handling method through the interrupt handling engine running on the hardware simulation device, and process the interrupt signal according to the interrupt handling method to obtain the interrupt handling result. The verification result of the design under test can then be determined through the interrupt handling result. The PCIe interrupt verification method provided in this application forms a closed loop in the hardware simulation environment, avoiding requests for interrupt handling from the host system and the SpeedBridge hardware device required for interaction with the host system and physical PCIe devices. Therefore, it eliminates the resource and performance bottlenecks caused by the host system and SpeedBridge, improves verification efficiency and test throughput, and realizes the feasibility of large-scale stress testing. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of PCIe interrupt verification in related technologies; Figure 2 This is a flowchart of a PCIe interrupt verification method provided in an exemplary embodiment of this application; Figure 3 This is a schematic diagram of the various software modules running in a hardware simulation device provided in an exemplary embodiment of this application; Figure 4 This is a schematic diagram of a PCIe interrupt verification method provided in an exemplary embodiment of this application; Figure 5 This is a schematic diagram of an interrupt handling engine provided in an exemplary embodiment of this application; Figure 6 This is a structural block diagram of a PCIe interrupt verification device provided in an exemplary embodiment of this application; Figure 7 This is a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of this application. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0014] First, the terms used in the embodiments of this application will be introduced.

[0015] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard. Its core function is to enable data exchange between the CPU and peripherals (such as graphics cards, SSDs, and high-speed network cards). It has replaced traditional PCI and AGP buses as the mainstream expansion interface for modern computers. PCIe has the following characteristics: Layered architecture: The physical layer uses differential signal transmission (such as 8B / 10B or 128B / 130B encoding), the data link layer ensures reliability through the Ack / Nak mechanism, and the transaction layer handles end-to-end data routing; High bandwidth and scalability: Bandwidth is doubled through aggregation channels (x1 to x32); Key functions: Supports active power management, Quality of Service (QoS), hot-plugging, and Advanced Error Reporting (AER), significantly improving system reliability and flexibility. PCIe has become the core interconnect standard for high-speed devices such as graphics cards, SSDs, and network cards, and is widely used in servers, embedded systems, and consumer electronics.

[0016] Hardware emulation is a chip verification technology based on a dedicated hardware platform (such as an FPGA array or a custom processor). It achieves a speedup of thousands of times higher than traditional software emulation (speeds up to 500kHz–5MHz, while software emulation is typically only 1–100Hz) by compiling and mapping the RTL code of the design under test (DUT) onto physical hardware for parallel execution. It can handle ultra-large-scale SoC designs with over 1 billion gates. Its core value lies in supporting full chip-level deep debugging (such as full signal visibility, dynamic probe insertion, and billions of cycle waveform tracing) and multi-scenario verification (such as operating system startup, power consumption analysis, virtual peripheral testing, and post-silicon verification reproduction). It is particularly suitable for pre-tape-out hardware-software co-verification and complex system-level error localization. Chip-level system simulation on an emulator features large logic scale, fast simulation speed, and strong debugging capabilities, which can greatly shorten the chip verification iteration cycle.

[0017] MSI / MSIX Memory Write Interrupts: MSI stands for Message Signaled Interrupts, and MSIX stands for Message Signaled Interrupts Extended. MSI / MSIX memory write interrupts are modern interrupt mechanisms in PCIe based on memory writes. MSI triggers an interrupt by sending a specific formatted Transaction Layer Message (TLP) to a specified memory address, without requiring a dedicated interrupt line. MSIX, as an extension, supports more independent interrupt vectors and allows dynamic configuration of the MSI / MSIX preset table. It achieves efficient interrupt routing through memory write operations, significantly improving the processing efficiency of concurrent interrupts from multiple devices.

[0018] Level interrupt: This is an interrupt method based on hardware level signals (such as the traditional PCIe INTx). The device requests an interrupt by continuously pulling the signal low or holding it high (such as INTA#~INTD# signals). The interrupt source needs to be confirmed by software polling, and the interrupt signal needs to be actively cleared after processing to avoid repeated triggering. This method is suitable for early low-speed devices.

[0019] Pulse interrupt: A mechanism that triggers an interrupt through a short signal pulse. It does not require a continuous level. The interrupt request ends automatically with the pulse signal. The hardware can respond quickly through edge detection, reducing the resource occupation on the signal line. It is often used in scenarios with high real-time requirements.

[0020] Register Transfer Level (RTL) code is the core code written in hardware description languages ​​(such as Verilog and VHDL) in digital circuit design. It describes the data transfer, storage, and operation processes between registers and combinational logic in a digital system, transforming abstract functional requirements into concrete logical behaviors that can be implemented in hardware. The quality of RTL code directly determines the functional correctness, performance indicators, and hardware resource utilization of a chip or FPGA, and is a key carrier for digital hardware from concept to reality.

[0021] In related technologies, PCIe interrupt verification in an emulation environment primarily employs a SpeedBridge speed adapter paired with a real PCIe device. A dedicated hardware adapter (such as Cadence SpeedBridge) connects the hardware emulator to the physical PCIe device. The physical PCIe device runs an operating system, while the hardware emulator internally runs the RTL design of the PCIe controller. The SpeedBridge connects the two for communication. Simultaneously, communication between the hardware emulator and the host system also requires a SpeedBridge connection.

[0022] See Figure 1 , Figure 1 This is a schematic diagram of PCIe interrupt verification in related technologies.

[0023] like Figure 1 As shown, when a PCIe interrupt trigger event occurs, the physical PCIe device 101 sends a PCIe interrupt trigger command to the hardware emulator 104 via SpeedBridge 103. The hardware emulator 104 generates an interrupt signal based on the trigger command and sends the interrupt signal to the host system 103 via SpeedBridge 103. The host system 102 determines the processing logic for the interrupt signal through the running management software (such as a driver simulation program), performs interrupt processing on the interrupt signal, and sends an ACK response back to the hardware emulator 104 via SpeedBridge 103 again.

[0024] However, adopting such Figure 1 The related technologies shown require external SpeedBridge physical hardware devices and host devices, and these technologies have at least the following disadvantages.

[0025] (1) SpeedBridge dependency restrictions.

[0026] The related technologies heavily rely on SpeedBridge physical hardware cards to bridge interrupt signals. SpeedBridge is expensive, resource-limited, complex to configure, and prone to becoming a bottleneck. At the same time, SpeedBridge physical hardware has hardware connection stability issues. Interrupt loss caused by unstable physical connection transmission can be mistakenly attributed to RTL design problems in the hardware emulator. SpeedBridge physical hardware lacks good localization methods, making it difficult to trace the root cause of problems.

[0027] (2) Host interaction restrictions.

[0028] In related technologies, interrupt signals need to be transmitted to the management software (such as a driver emulator) running on the host system via SpeedBridge, processed, and then returned as an ACK response via SpeedBridge. This loop introduces significant communication latency and processing delays caused by software processing, making it difficult to precisely control timing and affecting the localization of hardware problems.

[0029] (3) The flexibility and efficiency of verification are limited.

[0030] In related technologies, for mixed interrupt sources (such as MSI / MSIX memory write, level interrupt signals, and pulse interrupt signals), the verification scheme needs to start the complex upper-layer PCIe driver protocol stack running on the host system, and the scheduling of the upper-layer PCIe driver protocol stack and its handler is quite difficult; at the same time, the host interaction bottleneck limits the feasibility of test throughput and large-scale interrupt stress testing.

[0031] Based on this, this application provides a PCIe interrupt verification method that eliminates the dependence on SpeedBridge physical hardware and host devices, and directly implements closed-loop PCIe interrupt verification within the hardware emulation device. This application can reduce communication latency, improve verification efficiency and test throughput, and realize the feasibility of large-scale stress testing.

[0032] See Figure 2 , Figure 2 This is a flowchart of a PCIe interrupt verification method provided in an exemplary embodiment of this application. The method includes the following steps.

[0033] Step 201: Generate an interrupt signal triggered by a PCIe interrupt trigger event using the design under test.

[0034] In some embodiments, the method is executed by a hardware emulation device. A hardware emulation device, also known as a hardware simulator, is a verification device based on a programmable logic device or a dedicated hardware architecture. It is used to perform functional verification of a PCIe controller by mapping the logical behavior of the device under test (DUT) to physical hardware.

[0035] Optionally, hardware emulation devices may include FPGA array emulators, ASIC accelerated emulators, or hybrid architecture emulators, without limitation.

[0036] In some embodiments, the hardware emulation device runs a design-to-test (DT) and interrupt handling engine.

[0037] The design under test is the RTL code of the PCIe controller.

[0038] Optionally, the PCIe controller is a native PCIe controller, which is integrated into the chip architecture and directly connected to the core system components (such as the CPU and memory controller) via an internal high-speed bus, rather than a PCIe controller implemented through a third-party bridge chip.

[0039] The interrupt handling engine is used to simulate the host device's logic for handling interrupt signals.

[0040] In some embodiments, a PCIe interrupt trigger event is an event used to trigger the generation of an interrupt signal by the design under test.

[0041] Optionally, the PCIe interrupt trigger event can be a normal function event or an abnormal alarm event.

[0042] For illustrative purposes only, normal functional events can include events such as PCIe device completing data reception, register configuration update (Configuration Write), and DMA transfer completion.

[0043] For example only, abnormal alarm events can include data link layer errors, transaction layer protocol errors, out-of-bounds address access, and repeated triggering.

[0044] It should be noted that the above PCIe interrupt triggering events are merely examples. Those skilled in the art can determine the specific event type of the PCIe interrupt triggering event according to the actual needs of PCIe interrupt verification. This application does not impose any restrictions on this.

[0045] Regarding the specific method of generating an interrupt signal triggered by a PCIe interrupt trigger event through the design under test, in one possible scenario, the hardware emulation device can receive an injection command for injecting a PCIe interrupt trigger event, convert the injection command into an executable injection command for the hardware emulation device, and trigger the design under test to generate an interrupt signal triggered by a PCIe interrupt trigger event based on the executable injection command.

[0046] Regarding the specific method for generating an interrupt signal triggered by a PCIe interrupt event from the design under test (DUT), in another possible scenario, the hardware emulation device can also receive test stimuli and send them to the DUT. The test stimuli are used to incentivize the DUT to generate the interrupt signal for the PCIe interrupt event.

[0047] Optionally, the interrupt signal generated by the design under test can have a variety of possible interrupt signal types.

[0048] For illustrative purposes only, interrupt signal types include the MSI / MSIX memory write interrupt type. The MSI / MSIX memory write interrupt type triggers an interrupt by sending a Transaction Layer Message (TLP) of a specific format to a specified memory address. As an extension, MSIX supports more independent interrupt vectors and allows dynamic configuration of the MSI / MSIX preset table, enabling efficient interrupt routing through memory write operations and significantly improving the handling efficiency of concurrent interrupts from multiple devices.

[0049] For illustrative purposes only, interrupt signal types include level interrupt types. Level interrupt types are interrupt methods based on hardware level signals (such as PCIe traditional INTx and Level interrupt). An interrupt is requested by continuously pulling the signal low or holding it high (such as INTA~INTD signals). The interrupt source needs to be confirmed by software polling, and the interrupt signal must be actively cleared after processing to avoid repeated triggering. This type is suitable for early, low-speed devices.

[0050] For illustrative purposes only, interrupt signal types include pulse interrupts. Pulse interrupts are mechanisms that trigger interrupts through a short signal pulse (such as Plus interrupts). They do not require a continuous level, and the interrupt request ends automatically with the pulse signal. The hardware can respond quickly through edge detection, reducing resource consumption on signal lines. They are often used in scenarios with high real-time requirements.

[0051] In addition, those skilled in the art can determine the interrupt signal type according to actual needs. The interrupt signal type includes any possible mixed interrupt sources, without limitation.

[0052] In some embodiments, the design under test sends the generated interrupt signal to the interrupt handling engine.

[0053] Optionally, the design under test can send an interrupt signal to the interrupt handling engine via the PCIe Hardware Core.

[0054] Step 202: Determine the interrupt handling method for the interrupt signal through the interrupt handling engine.

[0055] In some embodiments, the interrupt handling engine stores processing logic for interrupt signals. Upon receiving an interrupt signal sent by the design under test, the interrupt handling engine determines the interrupt handling method for the interrupt signal based on the stored processing logic for interrupt signals.

[0056] In one possible scenario, the interrupt handling engine stores the correspondence between interrupt index numbers (INT Index) and interrupt handling methods (interrupt handler). The interrupt handling engine can determine the interrupt index number of an interrupt signal and determine the interrupt handling method corresponding to that interrupt index number as the interrupt handling method for that interrupt signal.

[0057] For illustrative purposes only, interrupt handling methods corresponding to interrupt index number 0 are exception alarm handling, interrupt handling methods corresponding to interrupt index number 1 are error recovery handling, and so on. The interrupt handling methods corresponding to the above interrupt index numbers are only examples; those skilled in the art can set the interrupt handling methods corresponding to the interrupt index numbers according to actual needs, and there are no restrictions on this.

[0058] In one possible implementation, an interrupt handling configuration file can be preloaded into the interrupt handling engine running on the hardware emulation device, so that the interrupt handling engine can pre-store the processing logic for interrupt signals (e.g., storing the correspondence between interrupt index numbers and interrupt handling methods).

[0059] Step 203: The interrupt signal is processed by the interrupt processing engine according to the interrupt processing method to obtain the interrupt processing result. The interrupt processing result is used to determine the verification result of the design under test.

[0060] In some embodiments, after determining the interrupt triggering method corresponding to the interrupt signal, the interrupt handling engine performs interrupt handling on the interrupt signal according to the interrupt handling method to obtain the interrupt handling result.

[0061] Optionally, the interrupt handling result includes the interrupt index number and an identifier indicating whether the interrupt handling is complete.

[0062] For example, in the interrupt handling report, if the interrupt handling results for each interrupt signal meet expectations, the verification result of the design under test is determined to be successful. If, in the interrupt handling report, the interrupt handling result for at least one interrupt signal does not meet expectations, the verification result of the design under test is determined to be unsuccessful.

[0063] In summary, the hardware simulation device runs the design under test (the RTL code of the PCIe controller) and an interrupt handling engine. Since the interrupt handling engine replaces the host system's interrupt signal processing logic in related technologies, when the design under test generates an interrupt signal triggered by a PCIe interrupt event, the hardware simulation device does not need to request the interrupt handling method from the host system. Instead, it can directly determine the interrupt handling method through the interrupt handling engine running on the hardware simulation device, and then process the interrupt signal according to the interrupt handling method to obtain the interrupt handling result. The verification result of the design under test can then be determined from the interrupt handling result. The PCIe interrupt verification method provided in this application forms a closed loop in the hardware simulation environment, avoiding requests for interrupt handling from the host system and the SpeedBridge hardware device required for interaction with the host system and physical PCIe devices. Therefore, it eliminates the resource and performance bottlenecks caused by the host system and SpeedBridge, improves verification efficiency and test throughput, and realizes the feasibility of large-scale stress testing.

[0064] See Figure 3 , Figure 3 This is a schematic diagram of the various software modules running in a hardware simulation device provided in an exemplary embodiment of this application.

[0065] In some embodiments, the software modules running on the hardware emulation device 300 include an interrupt process engine 303 and a design under test (DUT) PCIe Subsystem 306. The DUT 306 is the RTL code of the PCIe controller.

[0066] Optionally, the software modules running on the hardware emulation device 300 may also include a command conversion module 301 (Linux adapter), a configuration engine 302, an error injection engine 304, and a PCIe protocol core 305.

[0067] Command conversion module 301 converts received commands into executable commands that can be executed by the hardware emulation device. As an example only, when an error injection command is received, command conversion module 301 converts the error injection command into an executable error injection command for the error injection engine. This error injection command is used to inject a PCIe interrupt trigger event. As an example only, when a reset command is received, command conversion module 301 converts the reset command into an executable reset command that can be executed by the hardware emulation device. This reset command is used to perform a reset operation on the hardware emulation device.

[0068] Configuration engine 302 is used to configure the PCIe protocol core running in the hardware emulation device. For example, configuration engine 302 can be used to establish a PCIe link between PCIe protocol core 305 and the design under test (DUT) 306 based on a PCIe configuration file. For example, configuration engine 302 can also be used to perform BIOS configuration based on a BIOS configuration file. The BIOS configuration is used to identify the DUT and configure initialization parameters for it. For example, the BIOS configuration file also includes an MSI / MSIX preset table. Configuration engine 302 can also be used to configure the MSI / MSIX preset table for the DUT based on the BIOS configuration file. The MSI / MSIX preset table in the DUT is consistent with the MSI / MSIX preset table configured by the interrupt signal identification module corresponding to the MSI / MSIX memory write interrupt type, and the MSI / MSIX preset table stores the correspondence between write addresses and interrupt index numbers.

[0069] Interrupt handling engine 303 is used to determine the interrupt handling method for an interrupt signal, and to perform interrupt handling on the interrupt signal according to the interrupt handling method to obtain the interrupt handling result. In some embodiments, interrupt handling engine 303 is used to identify an interrupt signal, perform interrupt handling on the interrupt signal, and clear the processed interrupt signal. For the specific structure of interrupt handling engine 303, please refer to the embodiments and related descriptions below, and it will not be repeated here.

[0070] Error injection engine 304 is used to execute executable error injection commands to generate trigger commands for PCIe interrupt trigger events. For example, command conversion module 301 converts error injection commands into executable error injection commands for error injection engine 304 and sends them to error injection engine 304. Error injection engine 304 executes the executable error injection commands received from command conversion module 301 to obtain the trigger commands for PCIe interrupt trigger events.

[0071] The PCIe protocol core 305 is used to convert received data into messages conforming to the PCIe protocol and to achieve data interaction with the design under test 306 via the PCIe link. For example, the PCIe protocol core 305 can convert the trigger command sent by the error injection engine 304 into a test stimulus conforming to the PCIe protocol and send the test stimulus to the design under test 306 via the PCIe link. In some embodiments, the PCIe protocol core 305 can realize data interaction between the interrupt handling engine 303 and the design under test 306. For example, the PCIe protocol core 305 can send the interrupt signal generated by the design under test 306 to the interrupt handling engine 303. As another example, the PCIe protocol core 305 can send the interrupt handling method returned by the interrupt handling engine 303 to the design under test 306.

[0072] The design under test (DUT) 306 is used to generate an interrupt signal triggered by a PCIe interrupt event. For example, upon receiving a test stimulus from the PCIe protocol core, the DUT 306 generates an interrupt signal based on the test stimulus and sends the interrupt signal to the interrupt handling engine through the PCIe protocol core.

[0073] It should be noted that the above embodiments only illustrate the general architecture of the various software modules running on the hardware emulation device. The system may also include more or fewer components, or combine certain components; this embodiment does not limit this. For example, the hardware emulation device may also run a PIPE Wrapper module and a dynamic delay control module. The PCIe protocol core 305 can send interrupt signals to the design under test 306 through the PIPE Wrapper module (PCI Express PHY Interface Wrapper) and the dynamic delay control module. The hardware emulation device can also be called a hardware emulation environment.

[0074] See Figure 4 , Figure 4 This is a schematic diagram of a PCIe interrupt verification method provided in an exemplary embodiment of this application. The method includes the following steps.

[0075] Step S1: Obtain the configuration file.

[0076] In some embodiments, the configuration files include a BIOS configuration file (BIOS Firmware), a PCIe configuration file (PCIe Firmware), and an interrupt handling configuration file (interrupt handler Firmware).

[0077] The BIOS configuration file is used to simulate the motherboard's BIOS logic (Basic Input / Output System). This BIOS logic handles low-level hardware input / output interactions, such as power-on self-test (POST), hard drive read / write control, and display output. Optionally, the hardware emulation device can execute BIOS configuration based on the BIOS configuration file. The BIOS configuration is used to identify the design under test (DUT) and configure initialization parameters for it. For example, through the BIOS configuration file, the hardware emulation device can execute the BIOS_SETUP instruction to enumerate and initialize the design under test.

[0078] In some embodiments, the BIOS configuration file also includes an MSI / MSIX preset table. The MSI / MSIX preset table is used to store the correspondence between write addresses and interrupt index numbers. The hardware emulation device can write the MSI / MSIX preset table for the design under test based on the MSI / MSIX preset table in the BIOS configuration file through the configuration engine. The MSI / MSIX preset table in the design under test is consistent with the MSI / MSIX preset table configured by the interrupt signal identification module corresponding to the MSI / MSIX memory write interrupt type.

[0079] The PCIe configuration file is used to establish the PCIe link between the PCIe protocol core and the design under test. For example, based on the PCIe configuration file, hardware emulation devices can configure the link parameters of the PCIe link through a configuration engine.

[0080] The interrupt handling configuration file is used to indicate how to handle interrupt signals.

[0081] In some embodiments, the interrupt handling configuration file may include the correspondence between the interrupt index number (INTIndex) of the interrupt signal and the interrupt handling method (interrupt handler).

[0082] Step S2: Perform a reset operation on the hardware simulation system.

[0083] It should be noted that step S2 is optional. By performing a reset operation on the software modules in the hardware simulation system through step S2, a clean operating environment can be provided for subsequent PCIe interrupt verification of the design under test, ensuring the accuracy of the verification results. In actual execution, the hardware simulation system may also skip step S2 and directly execute other subsequent steps.

[0084] In some embodiments, the hardware emulation device performs a reset operation based on a reset command.

[0085] like Figure 4 In the process, the command conversion module (Linux adapter) in the hardware emulation device converts the received reset command into an executable Reset command (or executable reset command) that can be executed by the hardware emulation device. The hardware emulation device executes the executable Reset command to achieve a system-wide reset.

[0086] Optionally, a full system reset includes resetting the interrupt handling engine, configuration engine, and error injection engine, as well as resetting the design under test.

[0087] Step S3: PCIe link established.

[0088] In some embodiments, the hardware emulation system establishes a PCIe link based on a PCIe configuration file.

[0089] Optionally, the hardware simulation system can load and execute the PCIe configuration file during the restart and link establishment process.

[0090] Optionally, the hardware emulation system uses Python tools to convert the PCIe configuration file into an executable PCIe bin file that the hardware emulation system can run, and then executes the executable PCIe bin file to establish and check the PCIe link. For example, based on the PCIe configuration file, the hardware emulation device can configure the link parameters of the PCIe link through a configuration engine.

[0091] BIOS configuration is executed after a successful PCIe connection is detected.

[0092] Step S4, BIOS configuration.

[0093] In some embodiments, once the PCIe link is established, the hardware emulation device performs BIOS configuration through a configuration engine based on the BIOS configuration file.

[0094] The BIOS configuration is used to identify the design under test and to configure initialization parameters for the design under test.

[0095] like Figure 4 In the process, the hardware simulation system uses Python tools to convert the BIOS configuration file into an executable BIOS bin file that the hardware simulation system can execute. By executing the executable BIOS bin file and the executable BIOS_SETUP instruction, the system can perform enumeration and initialization configuration of the design under test.

[0096] Step S5: Inject PCIe interrupt trigger event and generate test stimulus.

[0097] In some embodiments, the hardware emulation device uses a command conversion module (Linux adapter) to convert injection commands into executable injection commands for the injection engine.

[0098] Among them, the error injection command is used to inject PCIe interrupt trigger events.

[0099] In some embodiments, the hardware emulation device executes executable injection commands through an injection engine to generate a trigger command for a PCIe interrupt trigger event, and sends the trigger command for the PCIe interrupt trigger event to the PCIe protocol core.

[0100] In some embodiments, the hardware emulation device converts trigger commands into test stimuli that conform to the PCIe protocol through the PCIe protocol core.

[0101] In some embodiments, the hardware emulation device sends test stimuli to the design under test (DUT) via the PCIe link between the PCIe protocol core and the DUT.

[0102] Step S6: The design under test generates an interrupt signal.

[0103] In some embodiments, the design under test generates an interrupt signal for a PCIe interrupt trigger event based on test stimuli sent by the PCIe protocol core.

[0104] In some embodiments, the design under test (DUT) sends an interrupt signal to the interrupt handling engine via the PCIe protocol core.

[0105] Step S7: The interrupt handling engine performs interrupt processing on the interrupt signal and obtains the interrupt processing result.

[0106] In some embodiments, the hardware emulation device preloads an interrupt handling configuration file into the interrupt handling engine. This interrupt handling configuration file indicates how interrupt signals are handled.

[0107] As an example only, the interrupt handling configuration file may include the mapping between the interrupt signal's interrupt index (INT index) and the interrupt handler. The hardware emulation device pre-loads the interrupt handling configuration file into the interrupt handling engine using pythontools, and the interrupt handling engine stores the mapping between the interrupt index and the interrupt handling mode.

[0108] It should be noted that the interrupt handling configuration file can implement non-hard-coded interrupt handling logic. Through the interrupt handling configuration file, users can flexibly define, load, and modify the processing flow and behavior of each interrupt signal in different simulation test scenarios, greatly enhancing the coverage and flexibility of the verification scenarios.

[0109] For details on the specific structure of the interrupt handling engine and more information on interrupt handling, please refer to the embodiments below, which will not be elaborated here.

[0110] In some embodiments, the interrupt handling engine can summarize the interrupt handling results corresponding to one or more interrupt signals sent by the design under test into an interrupt handling report, and return the interrupt handling report to the user interface through the command translation module (Linux adapter).

[0111] Step S8: Process the incentive distribution.

[0112] In some embodiments, the hardware emulation device sends interrupt handling methods (handlers) to the PCIe protocol core through an interrupt handling engine. For example... Figure 4 In the process, the hardware simulation device sends the interrupt handling method to the configuration engine through the interrupt handling engine, and then sends the interrupt handling method to the PCIe protocol core through the configuration engine.

[0113] In some embodiments, the hardware emulation device converts the interrupt handling method into a processing stimulus that conforms to the PCIe protocol through the PCIe protocol core, and sends the processing stimulus to the design under test.

[0114] In some embodiments, when the design under test receives a processing stimulus, the hardware simulation device sends a processing completion message of the interrupt signal to the interrupt handling engine through the design under test. The processing completion message indicates that the interrupt processing of the interrupt signal has been completed.

[0115] For example, when the design under test (DUT) receives a processing stimulus, the DUT sends an interrupt signal processing completion message to the PCIe protocol core, and then the PCIe protocol core sends the interrupt signal processing completion message to the interrupt handling engine.

[0116] In this embodiment, by loading the BIOS configuration file, the enumeration and initialization configuration of the design under test can be realized; by loading the PCIe configuration file, the PCIe link between the PCIe protocol core and the design under test can be established; by loading the interrupt handling configuration file, the interrupt handling method for interrupt signals can be preloaded in the interrupt handling engine, thereby realizing the simulation of the BIOS configuration, PCIe link establishment and interrupt signal handling logic of the host system, and getting rid of the dependence on external devices of the host system.

[0117] The following section describes the specific structure of the interrupt handling engine.

[0118] In some embodiments, the interrupt handling engine includes an interrupt signal recognition module and an interrupt signal processing module.

[0119] The interrupt signal identification module is used to determine the interrupt index number of the interrupt signal, and the interrupt signal processing module is used to determine the interrupt processing method corresponding to the interrupt index number of the interrupt signal, and to process the interrupt signal according to the interrupt processing method to obtain the interrupt processing result.

[0120] In some embodiments, the interrupt handling engine further includes an interrupt signal buffer module.

[0121] Optionally, the hardware simulation device writes the interrupt signal information into the interrupt signal buffer module through the interrupt signal identification module.

[0122] As an example only, the interrupt signal identification module can write the interrupt processing sequence composed of the interrupt signal information of each interrupt signal into the interrupt signal buffer module.

[0123] The interrupt signal information includes the interrupt index number and the processing status. When the interrupt signal information is written to the interrupt signal buffer module, the processing status of the interrupt signal is unprocessed.

[0124] Optionally, the hardware simulation device can read the interrupt signal information from the interrupt signal buffer module through the interrupt signal processing module.

[0125] Optionally, if the processing status in the interrupt signal information is unprocessed, the hardware simulation device determines the interrupt processing method corresponding to the interrupt index number through the interrupt signal processing module.

[0126] See Figure 5 , Figure 5 This is a schematic diagram of an interrupt handling engine provided in an exemplary embodiment of this application.

[0127] like Figure 5 As shown, the interrupt handling engine 500 includes an interrupt signal identification module 510, an interrupt signal buffer module 520, and an interrupt signal processing module 530.

[0128] In some embodiments, the hardware simulation device determines the interrupt index number of the interrupt signal through the interrupt signal identification module 510.

[0129] In one possible scenario, the interrupt handling engine includes different interrupt signal identification modules corresponding to different interrupt signal types.

[0130] For illustrative purposes only, when the interrupt signal type is MSI / MSIX memory write interrupt, the interrupt signal identification module corresponding to the interrupt signal type is the MSI / MSIX interrupt signal identification module.

[0131] As an example only, when the interrupt signal type is INTA / B / C / D interrupt type within the level interrupt type, the interrupt signal identification module corresponding to the interrupt signal type is the INTA / B / C / D interrupt signal identification module.

[0132] As an example only, in the case of a Level interrupt interrupt, the interrupt signal identification module corresponding to the interrupt signal type is the Level interrupt interrupt signal identification module.

[0133] As an example only, when the interrupt signal type is pulse interrupt, the interrupt signal identification module corresponding to the interrupt signal type is the Plus interrupt interrupt signal identification module.

[0134] In some embodiments, the hardware simulation device determines the interrupt signal type of the interrupt signal and sends the interrupt signal to the interrupt signal identification module corresponding to the interrupt signal type.

[0135] Optionally, upon receiving an interrupt signal generated by the design under test, the PCIe protocol core can determine the interrupt signal type and, based on that type, send the interrupt signal to the corresponding interrupt signal identification module. For example, if the PCIe protocol core determines the interrupt signal type to be a pulse interrupt, it will send the interrupt signal to the Plus interrupt identification module; if the PCIe protocol core determines the interrupt signal type to be an INTA / B / C / D interrupt type within the level interrupt types, it will send the interrupt signal to the INTA / B / C / D interrupt signal identification module.

[0136] Regarding the specific method by which the hardware simulation device determines the interrupt index number of the interrupt signal through the interrupt signal identification module, in some embodiments, the hardware simulation device determines the index number range corresponding to the interrupt signal type through the interrupt signal identification module corresponding to the interrupt signal type.

[0137] Different interrupt signal types correspond to different index number ranges.

[0138] For illustrative purposes only, the index number range for the MSI / MSIX memory write interrupt type is 0~31, the index number range for the INTA / B / C / D interrupt type in the level interrupt type is 32~35, the index number range for the Levelinterrupt interrupt type in the level interrupt type is 36~78, and the index number range for the pulse interrupt type is 79~100.

[0139] It should be noted that the above correspondence between interrupt signal types and index number ranges is only an example. Those skilled in the art can make any possible settings according to actual needs. For example, the index number ranges corresponding to different interrupt signal types can be continuous or discontinuous, and this application does not impose any restrictions on this.

[0140] In some embodiments, the interrupt signal identification module determines the interrupt index number of the interrupt signal from the index number range corresponding to the interrupt signal type. Optionally, when the interrupt signal type is an MSI / MSIX memory write interrupt type, the hardware simulation device determines the write address of the memory write operation corresponding to the interrupt signal through the interrupt signal identification module corresponding to the interrupt signal type (i.e., the MSI / MSIX interrupt signal identification module); and determines the interrupt index number of the interrupt signal from the index number range corresponding to the interrupt signal type according to the correspondence between the write address and the interrupt index number stored in the MSI / MSIX preset table.

[0141] For illustrative purposes only, the index range for the MSI / MSIX memory write interrupt type is 0~31. The MSI / MSIX preset table stores interrupt index number 0 corresponding to write address 0x0000_7F00. The PCIe interrupt trigger event associated with interrupt index number 0 is the completion of a PCIe device DMA transfer. When the MSI / MSIX interrupt signal identification module detects an MSI message sent to write address 0x0000_7F00, the MSI / MSIX interrupt signal identification module determines that the write address belongs to an address in the MSI / MSIX preset table, and determines the interrupt index number of the interrupt signal to be 0 from the index range 0~31 according to the correspondence between write address 0x0000_7F00 and index number 0 stored in the MSI / MSIX preset table.

[0142] For illustrative purposes only, the index range for the MSI / MSIX memory write interrupt type is 0~31. The MSI / MSIX default table stores interrupt index number 1 corresponding to write address 0x0000_7F04. The PCIe interrupt trigger event associated with interrupt index number 1 is a link anomaly alarm. When the MSI / MSIX interrupt signal identification module detects an MSI message sent to write address 0x0000_7F04, the MSI / MSIX interrupt signal identification module determines that the write address belongs to an address in the MSI / MSIX default table, and determines the interrupt index number of the interrupt signal to be 1 from the index range 0~31, according to the correspondence between write address 0x0000_7F04 and index number 1 stored in the MSI / MSIX default table.

[0143] In one possible implementation, the MSI / MSIX interrupt signal identification module stores an MSI / MSIX preset table.

[0144] In some embodiments, the design under test also stores an MSI / MSIX preset table, and the MSI / MSIX preset table in the design under test is consistent with the MSI / MSIX preset table in the MSI / MSIX interrupt signal identification module.

[0145] Optionally, the BIOS configuration file also includes an MSI / MSIX preset table. The hardware emulation device can pre-write the MSI / MSIX preset table to the design under test based on the BIOS configuration file through the configuration engine.

[0146] The MSI / MSIX Preset Table is used to store the correspondence between write addresses and interrupt index numbers.

[0147] By pre-configuring the MSI / MSIX preset table in the MSI / MSIX interrupt signal recognition module, the module can store the correspondence between write addresses and interrupt index numbers. This allows it to determine the corresponding interrupt index number from the MSI / MSIX preset table based on the detected write address when an interrupt signal of the MSI / MSIX memory write interrupt type is received.

[0148] Optionally, when the interrupt signal type is a level interrupt or a pulse interrupt, the hardware simulation device determines the transmission pin number of the interrupt signal through the interrupt signal identification module corresponding to the interrupt signal type; and determines the interrupt index number of the interrupt signal from the index number range corresponding to the interrupt signal type according to the correspondence between the transmission pin number and the interrupt index number.

[0149] As an example only, when the interrupt signal type is INTA / B / C / D interrupt type in the level interrupt type, the hardware simulation device uses the INTA / B / C / D interrupt signal identification module to determine the transmission pin number of the interrupt signal (such as transmission pin number a), and determines the interrupt index number corresponding to the transmission pin number (such as transmission pin number a corresponding to index number 32) from the index number range 32~35 corresponding to the INTA / B / C / D interrupt signal type.

[0150] As an example only, when the interrupt signal type is the Level interrupt type, the hardware simulation device uses the Level interrupt signal identification module to determine the transmission pin number of the interrupt signal (e.g., transmission pin number f), and determines the interrupt index number corresponding to the transmission pin number (e.g., transmission pin number f corresponds to index number 37) from the index number range 36~78 corresponding to the Level interrupt signal type.

[0151] As an example only, when the interrupt signal type is pulse interrupt, the hardware simulation device uses the Plusinterrupt interrupt signal identification module to determine the transmission pin number of the interrupt signal (e.g., transmission pin number z), and determines the interrupt index number corresponding to the transmission pin number (e.g., transmission pin number z corresponds to index number 100) from the index number range 79~100 corresponding to the Plus interrupt interrupt signal type.

[0152] Among them, the hardware simulation device can pre-store the correspondence between different transmission pin numbers and different index numbers.

[0153] In some embodiments, the hardware simulation device uses a different interrupt signal identification module corresponding to different interrupt signal types to determine the interrupt signal information of different interrupt signals of different interrupt signal types.

[0154] The interrupt signal information obtained by different interrupt signal identification modules adopts the same format.

[0155] Optionally, the interrupt signal information includes the interrupt index number and the processing status. When the interrupt signal information is written to the interrupt signal buffer module, the interrupt signal's processing status is set to unprocessed.

[0156] Optionally, the interrupt signal information may also include the interrupt signal type.

[0157] For example, the MSI / MSIX interrupt signal identification module, INTA / B / C / D interrupt signal identification module, Levelinterrupt interrupt signal identification module, and Plus interrupt interrupt signal identification module all use the same format (interrupt index number, processing status) to determine the interrupt signal information of different interrupt signals of different interrupt signal types, and write the interrupt signal information of each interrupt signal into the interrupt signal buffer module.

[0158] As an example only, the MSI / MSIX interrupt signal identification module writes the interrupt signal information of interrupt signal A (interrupt index number 0, processing status flag=1) into the interrupt signal buffer module, and the INTA / B / C / D interrupt signal identification module writes the interrupt signal information of interrupt signal B (interrupt index number 32, processing status flag=1) into the interrupt signal buffer module. Here, processing status flag=1 indicates that the interrupt signal is in an unprocessed state.

[0159] Optionally, the hardware simulation device can read the interrupt signal information from the interrupt signal buffer module through the interrupt signal processing module.

[0160] Optionally, if the processing status in the interrupt signal information is unprocessed, the hardware simulation device determines the interrupt processing method corresponding to the interrupt index number through the interrupt signal processing module.

[0161] As an example only, when the interrupt signal processing module 530 reads the interrupt signal information of interrupt signal A from the interrupt signal buffer module 520 as (interrupt index number 0, processing status flag=1), since the processing status flag=1 indicates that the processing status of the interrupt signal is unprocessed, the interrupt signal processing module 530 determines the interrupt processing method corresponding to interrupt index number 0 and uses the determined interrupt processing method to process interrupt signal A.

[0162] The correspondence between the interrupt index number (INT Index) and the interrupt handling method stored in the interrupt signal processing module 530 can be achieved by preloading the interrupt handling configuration file.

[0163] In some embodiments, when interruption processing is performed on the interrupt signal, the interrupt signal processing module modifies the processing status of the interrupt signal in the interrupt signal buffer module to the processed status.

[0164] As an example only, when the interrupt signal processing module 530 processes interrupt signal A, the interrupt signal processing module 530 modifies the processing status of interrupt signal A in the interrupt signal buffer module 520 to a processed state. For example, the processing status flag=0 indicates that the interrupt signal processing status is processed.

[0165] Regarding the specific timing for changing the processing status of the interrupt signal in the interrupt signal buffer module to the processed state, in one possible scenario, the interrupt signal processing module can change the processing status of the interrupt signal in the interrupt signal buffer module to the processed state once the interrupt index number is determined.

[0166] As an example only, when the interrupt signal processing module 530 determines that the interrupt handling method handler0 corresponds to the interrupt index number 0, the interrupt signal processing module 530 modifies the processing status of interrupt signal A in the interrupt signal buffer module 520 to the processed status (that is, changes the flag of interrupt signal A from 1 to 0).

[0167] Regarding the specific timing for changing the processing status of the interrupt signal in the interrupt signal buffer module to the processed state, in another possible scenario, when the interrupt signal processing module receives a message indicating that the interrupt signal processing is complete from the design under test, the interrupt signal processing module changes the processing status of the interrupt signal in the interrupt signal buffer module to the processed state.

[0168] The completion message indicates that the interrupt signal has been processed.

[0169] As an example only, when the interrupt signal processing module 530 receives the interrupt signal A processing completion message sent by the design under test, the interrupt signal processing module 530 modifies the processing status of interrupt signal A in the interrupt signal buffer module 520 to the processed status (that is, changes the flag of interrupt signal A from 1 to 0).

[0170] In this embodiment, the interrupt handling engine includes different interrupt signal identification modules corresponding to different interrupt signal types. Since different interrupt signal identification modules use the same format to determine the interrupt signal information of the interrupt signal and write the interrupt signal information into the interrupt signal cache module, this embodiment realizes the unified identification, storage, sorting, scheduling and processing of mixed interrupt signals of different interrupt signal types. This avoids the need to call the complex upper-layer PCIe driver protocol stack in the host system in related technologies, significantly accelerates the verification cycle of PCIe interrupt verification, and improves verification efficiency.

[0171] In some embodiments, the interrupt signal processing module further includes a processing state machine, wherein the processing state machine is used to characterize the working state of the interrupt signal processing module.

[0172] For example, Figure 5 The interrupt signal processing module 530 includes a Finite State Machine (FSM).

[0173] In some embodiments, when the interrupt signal processing status in the interrupt signal information is unprocessed, the hardware simulation device changes the working status of the interrupt signal processing module from idle to busy by processing the state machine.

[0174] As an example only, if the interrupt signal processing module 530 reads that the processing status of interrupt signal A is unprocessed (flag=1), the processing state machine will change the working state of the interrupt signal processing module from idle state (IDLE) to busy state (PROCESS).

[0175] In some embodiments, after determining the interrupt handling method corresponding to the interrupt index number through the interrupt signal processing module, the hardware simulation device can change the working state from the busy state to the waiting state by processing the state machine.

[0176] As an example only, after the interrupt signal processing module 530 determines the interrupt handling mode handler0 corresponding to the interrupt index number 0 of interrupt signal A, the hardware simulation device can change the working state of the interrupt signal processing module from the busy state (PROCESS) to the waiting state (WAIT) by processing the state machine.

[0177] In some embodiments, when the interrupt signal processing status in the interrupt signal information is "processed", the working state of the interrupt signal processing module is changed from the waiting state to the idle state by the processing state machine.

[0178] Optionally, if the processing state machine reads from the interrupt signal buffer module that the processing state of interrupt signal A is processed (flag=0), the hardware simulation device changes the working state of the interrupt signal processing module from the waiting state (WAIT) to the idle state (IDLE) through the processing state machine.

[0179] Optionally, when the interrupt signal processing module 530 receives a message indicating that the design under test has completed processing of interrupt signal A, the hardware simulation device changes the working state of the interrupt signal processing module from the waiting state (WAIT) to the idle state (IDLE) through the processing state machine.

[0180] In this embodiment, a state processor is used to realize real-time monitoring of the working status of the interrupt signal processing module.

[0181] In some embodiments, the interrupt signal processing module 530 further includes an interrupt processing interface.

[0182] Optionally, after processing the interrupt signal according to the interrupt handling method corresponding to the interrupt index number and obtaining the interrupt handling result, the interrupt signal processing module can also send the interrupt handling result to other modules by calling the interrupt handling interface.

[0183] For example, the interrupt signal handling module can send the interrupt handling method (handler) to the configuration engine by calling the interrupt handling interface. Subsequently, the configuration engine sends the interrupt handling method to the PCIe protocol core, which converts the interrupt handling method into a processing stimulus conforming to the PCIe protocol and sends the processing stimulus to the design under test (DUT). Based on the processing stimulus, the DUT generates an interrupt signal processing completion message and returns the processing completion message to the interrupt handling engine through the PCIe protocol core to indicate that the interrupt signal processing has been completed.

[0184] The PCIe terminal verification method provided in the above embodiments has at least the following beneficial effects.

[0185] (1) Closed loop inside the hardware simulation equipment.

[0186] The PCIe interrupt verification method provided in the above embodiments completes the generation, identification, buffering, processing and response (through register operations) of interrupt signals within the hardware simulation device, without any interaction with external physical hosts or SpeedBridge. This avoids the processing delays and software interference introduced by external physical hosts or SpeedBridge hardware at the architectural level.

[0187] (2) Unified processing of mixed interrupt signal types.

[0188] It also natively supports and uniformly manages the capture, description, and program-driven response of several major interrupt mechanisms in the PCIe protocol (MSI-X TLP, INTA, level signals, pulse signals). This avoids the need to call the complex upper-layer PCIe driver protocol stack in the host system, as required by related technologies, significantly accelerating the verification cycle of PCIe interrupt verification and improving verification efficiency.

[0189] (3) Programmability of interrupt handling configuration files.

[0190] The interrupt handling configuration file contains non-hard-coded interrupt handling logic. Through this configuration file, users can flexibly define, load, and modify the processing flow and behavior of each interrupt signal in different simulation test scenarios, greatly enhancing the coverage and flexibility of the verification scenarios.

[0191] (4) High performance and high controllability.

[0192] By eliminating the huge resource overhead and performance limitations of SpeedBridge and host devices, the simulation speed of test cases involving dense interrupts (such as stress tests and interrupt storms) is increased by several orders of magnitude; precise control of the interrupt process can be achieved by monitoring the interrupt handling sequence and the execution process of the interrupt signal processing module in the environment.

[0193] See Figure 6 , Figure 6 This is a structural block diagram of a PCIe interrupt verification apparatus provided in an exemplary embodiment of this application. The apparatus is applied to a hardware emulation device that runs a design under test (DUT) and an interrupt handling engine. The DUT is the RTL code of a PCIe controller. The apparatus includes: The generation unit 601 is used to generate an interrupt signal triggered by a PCIe interrupt triggering event based on the design under test. The determining unit 602 is used to determine the interrupt handling method for the interrupt signal through the interrupt handling engine; The processing unit 603 is used to process the interrupt signal according to the interrupt processing method through the interrupt processing engine to obtain the interrupt processing result, and the interrupt processing result is used to determine the verification result of the design under test.

[0194] Optionally, the interrupt handling engine includes an interrupt signal identification module and an interrupt signal processing module, and the determination unit 602 is used for: The interrupt index number of the interrupt signal is determined by the interrupt signal identification module. The interrupt signal processing module determines the interrupt handling method corresponding to the interrupt index number. The interrupt signal processing module stores the correspondence between the interrupt index number and the interrupt handling method.

[0195] Optionally, the interrupt handling engine further includes an interrupt signal buffer module and a determination unit 602, used for: The interrupt signal identification module writes the interrupt signal information of the interrupt signal into the interrupt signal buffer module. The interrupt signal information includes the interrupt index number and the processing status. When the interrupt signal information is written into the interrupt signal buffer module, the processing status of the interrupt signal is unprocessed.

[0196] Optionally, the determining unit 602 is used for: The interrupt signal information is read from the interrupt signal buffer module through the interrupt signal processing module. If the processing status in the interrupt signal information is unprocessed, the interrupt processing module determines the interrupt processing method corresponding to the interrupt index number.

[0197] Optionally, the determining unit 602 is used for: When the interrupt signal is interrupted, the interrupt signal processing module modifies the processing status of the interrupt signal in the interrupt signal buffer module to the processed status.

[0198] Optionally, the determining unit 602 is used for: When the interrupt signal processing module determines the interrupt processing method corresponding to the interrupt index number, the interrupt signal processing module modifies the processing status of the interrupt signal in the interrupt signal buffer module to the processed status, or; Upon receiving a processing completion message for the interrupt signal sent by the design under test, the interrupt signal processing module modifies the processing status of the interrupt signal in the interrupt signal buffer module to the processed status. The processing completion message indicates that the interrupt processing of the interrupt signal has been completed.

[0199] Optionally, the interrupt signal processing module further includes a processing state machine, which is used to characterize the working state of the interrupt signal processing module. The device further includes a working state determination unit, used for: If the processing state of the interrupt signal in the interrupt signal information is unprocessed, the working state is changed from idle state to busy state through the processing state machine; After the interrupt signal processing module determines the interrupt handling method corresponding to the interrupt index number, the working state determination unit is used for: The working state is changed from a busy state to a waiting state through the processing state machine; If the processing state of the interrupt signal in the interrupt signal information is a processed state, the working state is changed from a waiting state to an idle state by the processing state machine.

[0200] Optionally, the interrupt handling engine includes a different interrupt signal identification module corresponding to different interrupt signal types, and a determination unit 602, used for: Determine the interrupt signal type of the interrupt signal; The interrupt signal is sent to the interrupt signal identification module corresponding to the interrupt signal type.

[0201] Optionally, the determining unit 602 is used for: The interrupt signal identification module corresponding to the interrupt signal type determines the index number range corresponding to the interrupt signal type, wherein different interrupt signal types correspond to different index number ranges; The interrupt index number of the interrupt signal is determined from the index number range corresponding to the interrupt signal type.

[0202] Optionally, the interrupt signal information obtained by different interrupt signal identification modules can be in the same format.

[0203] Optionally, the determining unit 602 is used for: When the interrupt signal type is MSI / MSIX memory write interrupt type, the write address of the memory write operation corresponding to the interrupt signal is determined by the interrupt signal identification module corresponding to the interrupt signal type. The interrupt index number of the interrupt signal is determined from the index number range corresponding to the interrupt signal type, according to the correspondence between the write address and the interrupt index number stored in the MSI / MSIX preset table.

[0204] Optionally, the determining unit 602 is used for: When the interrupt signal type is a level interrupt type or a pulse interrupt type, the transmission pin number of the interrupt signal is determined by the interrupt signal identification module corresponding to the interrupt signal type. The interrupt index number of the interrupt signal is determined from the index number range corresponding to the interrupt signal type, according to the correspondence between the transmission pin number and the interrupt index number.

[0205] Optionally, the hardware emulation device also runs a command conversion module, an error injection engine, and a PCIe protocol core. The device further includes an error injection unit for: The command conversion module converts the error injection command into an executable error injection command of the error injection engine, and the error injection command is used to inject the PCIe interrupt trigger event. The executable injection command is executed through the injection engine to generate the trigger command for the PCIe interrupt trigger event; Through the core of the PCIe protocol, the trigger command is converted into a test stimulus that conforms to the PCIe protocol; The test stimulus is sent to the design under test via the PCIe link between the PCIe protocol core and the design under test.

[0206] Optionally, the hardware simulation device also runs a configuration engine, and the device further includes a configuration unit for: Based on the reset command, a reset operation is performed on the hardware simulation device; The PCIe link is established based on the PCIe configuration file; Once the PCIe link is established, BIOS configuration is performed through the configuration engine based on the BIOS configuration file. The BIOS configuration is used to identify the design under test and to configure initialization parameters for the design under test.

[0207] Optionally, the BIOS configuration file also includes an MSI / MSIX preset table, and the configuration unit is used for: Based on the BIOS configuration file, the configuration engine configures the MSI / MSIX preset table for the interrupt signal identification module corresponding to the MSI / MSIX memory write interrupt type. The MSI / MSIX preset table is used to store the correspondence between write address and interrupt index number.

[0208] Optionally, the configuration unit is further configured to: An interrupt handling configuration file is loaded into the interrupt handling engine. The interrupt handling configuration file is used to indicate the interrupt handling method for the interrupt signal.

[0209] Optionally, the device further includes a processing stimulus distribution unit. After the interrupt signal is processed by the interrupt processing engine according to the interrupt processing method to obtain the interrupt processing result, the processing stimulus distribution unit is used to: The interrupt handling engine sends the interrupt handling method to the PCIe protocol core. Through the core of the PCIe protocol, the interrupt handling method is converted into a processing stimulus that conforms to the PCIe protocol, and the processing stimulus is sent to the design under test; The design under test sends a processing completion message for the interrupt signal to the interrupt handling engine, the processing completion message indicating that the interrupt signal has been processed.

[0210] See Figure 7 , Figure 7 This is a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of this application. This electronic device can be implemented as the hardware emulation device in the above embodiments. Specifically, the electronic device may include: at least one processor 71, at least one memory 72, a power supply 73, a communication interface 74, an input / output interface 75, and a communication bus 76. The memory 72 stores a computer program 722, which is loaded and executed by the processor 71 to implement the relevant steps in the PCIe interrupt verification method disclosed in any of the foregoing embodiments.

[0211] In this embodiment, the power supply 73 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 74 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 75 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0212] Furthermore, the memory 72, as a carrier for resource storage, can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored on it can include an operating system 721, computer programs 722, and data 723, etc. The data 723 can include various types of data. The storage method can be temporary storage or permanent storage.

[0213] The operating system 721 is used to manage and control the various hardware devices on the electronic device and the computer program 722, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the PCIe interrupt verification method executed by the electronic device (hardware emulation device) as disclosed in any of the foregoing embodiments, the computer program 722 may further include a computer program capable of performing other specific tasks.

[0214] This application also provides a computer-readable storage medium storing at least one computer instruction, which is loaded and executed by a processor to implement the method described in the above embodiments. Optionally, the computer-readable storage medium may include ROM, RAM, solid-state drives (SSDs), or optical discs, etc. The RAM may include resistive random access memory (ReRAM) and dynamic random access memory (DRAM).

[0215] This application also provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the methods provided in the various optional implementations of the above aspects.

[0216] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A PCIe interrupt validation method, characterized in that, The method is executed by a hardware simulation device, the hardware simulation device runs a design under test and an interrupt processing engine, the design under test is an RTL code of a PCIe controller, and the method comprises the following steps of: generating, by the design under test, an interrupt signal triggered by a PCIe interrupt trigger event; determining, by the interrupt processing engine, an interrupt processing mode of the interrupt signal; processing, by the interrupt processing engine, the interrupt signal according to the interrupt processing mode to obtain an interrupt processing result, the interrupt processing result being used to determine a verification result of the design under test.

2. The method of claim 1, wherein, The interrupt processing engine comprises an interrupt signal identification module and an interrupt signal processing module, and the step of determining, by the interrupt processing engine, the interrupt processing mode of the interrupt signal comprises the following steps of: determining, by the interrupt signal identification module, an interrupt index number of the interrupt signal; determining, by the interrupt signal processing module, the interrupt processing mode corresponding to the interrupt index number, the interrupt signal processing module storing a corresponding relationship between interrupt index numbers and interrupt processing modes.

3. The method of claim 2, wherein, The interrupt processing engine further comprises an interrupt signal cache module, and the method further comprises the following steps of: writing, by the interrupt signal identification module, interrupt signal information of the interrupt signal into the interrupt signal cache module, the interrupt signal information comprising the interrupt index number and a processing state, wherein the processing state of the interrupt signal is an unprocessed state when the interrupt signal information is written into the interrupt signal cache module.

4. The method of claim 3, wherein, The step of determining, by the interrupt signal processing module, the interrupt processing mode corresponding to the interrupt index number comprises the following steps of: reading, by the interrupt signal processing module, the interrupt signal information of the interrupt signal from the interrupt signal cache module; in a case where the processing state in the interrupt signal information is an unprocessed state, determining, by the interrupt signal processing module, the interrupt processing mode corresponding to the interrupt index number.

5. The method of claim 3, wherein, The method further comprises the following steps of: in a case of interrupt processing of the interrupt signal, modifying, by the interrupt signal processing module, the processing state of the interrupt signal in the interrupt signal cache module to a processed state.

6. The method of claim 5, wherein, The step of modifying, by the interrupt signal processing module, the processing state of the interrupt signal in the interrupt signal cache module to the processed state in the case of interrupt processing of the interrupt signal comprises the following steps of: in a case where the interrupt signal processing module determines the interrupt processing mode corresponding to the interrupt index number, modifying, by the interrupt signal processing module, the processing state of the interrupt signal in the interrupt signal cache module to the processed state, or in a case where a processing completion message of the interrupt signal sent by the design under test is received, modifying, by the interrupt signal processing module, the processing state of the interrupt signal in the interrupt signal cache module to the processed state, the processing completion message representing that the interrupt processing of the interrupt signal is completed.

7. The method of claim 3, wherein, The interrupt signal processing module further comprises a processing state machine configured to represent a working state of the interrupt signal processing module, and the method further comprises: in a case where the processing state of the interrupt signal in the interrupt signal information is an unprocessed state, modifying, by the processing state machine, the working state from an idle state to a busy state; after determining, by the interrupt signal processing module, the interrupt index number corresponding to the interrupt processing mode, the method further comprises: modifying, by the processing state machine, the working state from the busy state to a waiting state; in a case where the processing state of the interrupt signal in the interrupt signal information is a processed state, modifying, by the processing state machine, the working state from the waiting state to the idle state.

8. The method of claim 2, wherein, The interrupt processing engine comprises different interrupt signal identification modules corresponding to different interrupt signal types, and the method further comprises: determining an interrupt signal type of the interrupt signal; sending the interrupt signal to the interrupt signal identification module corresponding to the interrupt signal type.

9. The method of claim 8, wherein, The determination of the interrupt index number of the interrupt signal by the interrupt signal identification module comprises: determining, by the interrupt signal identification module corresponding to the interrupt signal type, an index number interval corresponding to the interrupt signal type, wherein different interrupt signal types correspond to different index number intervals; determining the interrupt index number of the interrupt signal from the index number interval corresponding to the interrupt signal type.

10. The method of claim 8, wherein, The method further comprises: the interrupt signal information determined by different interrupt signal identification modules adopts a same format.

11. The method of claim 9, wherein, The determination of the interrupt index number of the interrupt signal from the index number interval corresponding to the interrupt signal type comprises: in a case where the interrupt signal type is an MSI / MSIX memory write interrupt type, determining, by the interrupt signal identification module corresponding to the interrupt signal type, a write address of a memory write operation corresponding to the interrupt signal; determining the interrupt index number of the interrupt signal from the index number interval corresponding to the interrupt signal type according to a correspondence between the write address and the interrupt index number stored in an MSI / MSIX preset table.

12. The method of claim 9, wherein, The determination of the interrupt index number of the interrupt signal from the index number interval corresponding to the interrupt signal type comprises: in a case where the interrupt signal type is a level interrupt type or a pulse interrupt type, determining, by the interrupt signal identification module corresponding to the interrupt signal type, a transmission pin number of the interrupt signal; determining the interrupt index number of the interrupt signal from the index number interval corresponding to the interrupt signal type according to a correspondence between the transmission pin number and the interrupt index number.

13. The method according to any one of claims 1 to 12, characterized in that, The hardware simulation device further runs a command conversion module, an error injection engine, and a PCIe protocol core, and the method further comprises: converting, by the command conversion module, an error injection command into an executable error injection command of the error injection engine, the error injection command being used to inject the PCIe interrupt trigger event; The error injection engine executes the executable error injection command to generate a trigger command of the PCIe interrupt trigger event; The PCIe protocol core converts the trigger command into a test stimulus conforming to the PCIe protocol; The PCIe protocol core converts the trigger command into a test stimulus conforming to the PCIe protocol; 14. The method of claim 13, wherein, The hardware simulation device further runs a configuration engine, and the method further includes: Based on a reset command, performing a reset operation on the hardware simulation device; Based on a PCIe configuration file, establishing the PCIe link; In a case where the PCIe link is established, based on a BIOS configuration file, performing BIOS configuration by the configuration engine, the BIOS configuration being used to identify the design under test and configure initialization parameters for the design under test.

15. The method of claim 14, wherein, The BIOS configuration file further includes an MSI / MSIX preset table, and the method further includes: Based on the BIOS configuration file, configuring the MSI / MSIX preset table for the design under test by the configuration engine, the MSI / MSIX preset table in the design under test being consistent with the MSI / MSIX preset table configured by an interrupt signal identification module corresponding to an MSI / MSIX memory write interrupt type, and the MSI / MSIX preset table being used to store a corresponding relationship between a write address and an interrupt index number.

16. The method of any one of claims 1 to 12, wherein, The method further includes: Loading an interrupt processing configuration file in the interrupt processing engine, the interrupt processing configuration file being used to indicate the interrupt processing mode of the interrupt signal.

17. The method of any one of claims 1 to 12, wherein, After the interrupt processing engine processes the interrupt signal according to the interrupt processing mode to obtain an interrupt processing result, the method further includes: The interrupt processing engine sends the interrupt processing mode to a PCIe protocol core; The PCIe protocol core converts the interrupt processing mode into a processing stimulus conforming to the PCIe protocol and sends the processing stimulus to the design under test; The design under test sends a processing completion message of the interrupt signal to the interrupt processing engine, the processing completion message indicating that the interrupt processing of the interrupt signal is completed.

18. A PCIe interrupt validation apparatus, comprising: The device is applied to a hardware simulation device, the hardware simulation device running a design under test and an interrupt processing engine, the design under test being an RTL code of a PCIe controller, and the device includes: A generation unit generates an interrupt signal triggered by a PCIe interrupt trigger event through the design under test; A determination unit determines an interrupt processing mode of the interrupt signal through the interrupt processing engine; A processing unit processes the interrupt signal according to the interrupt processing mode through the interrupt processing engine to obtain an interrupt processing result, the interrupt processing result being used to determine a verification result of the design under test.

19. A hardware emulation apparatus, comprising: The hardware emulation device comprises a processor and a memory; the memory stores at least one computer instruction, the at least one computer instruction is used for being executed by the processor to realize the PCIe interrupt verification method as any one of claims 1 to 17.

20. A computer-readable storage medium, characterized in that, The computer readable storage medium stores at least one computer instruction, the computer instruction is loaded and executed by the processor to realize the PCIe interrupt verification method as any one of claims 1 to 17.

21. A computer program product, characterised in that, The computer program product comprises computer instructions stored in a computer readable storage medium; the processor of the hardware emulation device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the hardware emulation device executes the PCIe interrupt verification method as any one of claims 1 to 17.

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