Satellite in-satellite CameraLink interface and WiFi (Wireless Fidelity) interface conversion device and method

Abstract

The invention provides a device and a method for converting a CameraLink interface and a WiFi (Wireless Fidelity) interface in a satellite, belongs to the technical field of wireless communication, and aims to solve the problems of insufficient transmission rate, high power consumption of communication equipment, large size and opaque protocol conversion in the existing satellite wireless communication technology. The device comprises a core controller, a wired module, a wireless module, a power supply module, a DDR (Double Data Rate) module, a clock module, a Flash module, a JTAG (Joint Test Action Group) module, a USB-UART (Universal Asynchronous Receiver / Transmitter) interface, an M.2 interface and an SD (Secure Digital) card, and the method comprises the following steps of: sending wired data to a PL end after level conversion and isolation, transmitting the wired data to the wireless module through a PCIe (Peripheral Component Interconnect Express) interface after protocol analysis and format unification, and sending the wired data in a wireless mode; and a receiving end executes an inverse process and recovers to an original wired signal, thereby realizing transparent transmission.

Description

Technical Field

[0001] This invention relates to a satellite-based CameraLink interface and WiFi7 interface conversion device and method, belonging to the field of wireless communication technology. Background Technology

[0002] With the rapid development of aerospace technology, satellite systems are placing higher demands on the flexibility, reliability, and lightweight nature of data transmission. Traditional satellite internal wiring methods suffer from complex cable layouts, maintenance difficulties, heavy weight, and poor flexibility. Wireless transmission technology, with its advantages of requiring no physical connection, high flexibility, and easy expansion, is gradually becoming an important supplement to satellite internal data transmission. Furthermore, in some satellite applications, the payload compartment and platform compartment need to be physically separated. This physical separation means that the high-speed camera payload cannot be connected via traditional cables, and the risk of cable entanglement and signal interference severely restricts system reliability. Therefore, this paper proposes a satellite internal CameraLink interface to WiFi7 interface conversion device and method, providing core technical support for split-type data transmission and stable control.

[0003] Although domestic and international research has attempted to introduce wireless communication technologies into satellites, such as ZigBee, Bluetooth, UWB, and LiFi, several problems remain: 1. Insufficient transmission rate: Low-speed wireless technologies like ZigBee and Bluetooth cannot meet the transmission requirements of high-speed data buses (such as CameraLink). 2. Power consumption and size limitations: Onboard equipment has strict limitations on power consumption and size. Existing wireless solutions are often high in power consumption and large in size, making it difficult to meet onboard requirements. 3. Lack of transparency in protocol conversion: Existing conversion schemes cannot guarantee the transparency of data transmission. Their conversion process is usually related to the format and protocol of the data payload, lacking a transparent transmission mechanism. Summary of the Invention

[0004] To address the problems of insufficient transmission rate, high power consumption, large size, and opaque protocol conversion in existing satellite wireless communication technologies, this invention proposes a satellite-based CameraLink interface to WiFi7 interface conversion device and method.

[0005] The technical solution adopted by the present invention to solve the above problems is: a satellite-to-satellite CameraLink interface and WiFi7 interface conversion device, comprising: The core controller integrates PS and PL terminals to support CameraLink protocol processing for wired interface circuits and drive wireless interfaces. The wired module is bidirectionally connected to the core controller via the AXI-Stream bus. The wired module includes one CameraLink interface, supports Base mode, and has a speed of 1Gbps, which is used to receive wired data to be transmitted. The wireless module connects bidirectionally to the wired module, providing a stable high-speed connection of over 1.2Gbps for the CameraLink interface in complex wireless environments. The power module supports 28V±3V input, with a total power consumption of ≤15W. It features multi-level power management and isolation design to supply power to various modules in the conversion device.

[0006] Furthermore, the core controller is bidirectionally connected to the DDR module, clock module, Flash module, JTAG module, USB-UART interface, M.2 interface, and SD card; The DDR module is used to provide temporary data storage space for the core controller and to process cached data; The clock module is responsible for generating precise frequency signals and determining the operating timing of all components in the conversion device; The Flash module is used to firmware. The JTAG module is used for debugging, logic analysis, controller configuration, and Flash programming. The USB-UART interface is used to connect terminal devices to output debugging information and run commands; The wireless module communicates with the core controller via PCIe through the M.2 interface; SD cards are used to store bootloaders, kernel images, and root file systems.

[0007] Furthermore, the receiving circuitry of the CameraLink interface includes: The receiver protocol chip is used to convert 4 channels of video data into 28 channels of parallel data, and to achieve serial-to-parallel data alignment based on the high and low levels of the input clock. The receiver-side command signal conversion chip supports low-voltage TTL / CMOS input levels and converts low-voltage TTL / CMOS input levels into 350mV low-voltage differential output signals for the conversion of four control signals. A receiver level conversion chip is used for level conversion between asynchronous serial communication signals SerTF and SerTC; Digital isolation chips are used to achieve digital isolation of circuits; An isolation power supply chip is used to provide isolated power to the receiving circuit. The connector conforms to the CameraLink standard and is compatible with the Base mode interface requirements of the CameraLink interface.

[0008] Furthermore, the transmission circuitry of the CameraLink interface includes: The transmitting protocol chip is used to convert parallel data to serial data and is compatible with the Base mode signal transmission of the CameraLink interface. The transmitting end command signal conversion chip is used to control the level conversion and transmission of signals; The transmitter serial communication signal level conversion chip is used to convert the levels of asynchronous serial communication signals SerTFG and SerTC. The transmitter level conversion chip is a 16-channel chip used to convert the 1.8V signal from the PL terminal of the core control module into the 3.3V signal required by the transmitter protocol chip.

[0009] Furthermore, the wireless module adopts the Socket 1 Key-E interface form, is compatible with the ZU4EV's PCIe hard core, and uses a PCIe 3.0×1 channel to provide 8GT / s transmission capability.

[0010] Furthermore, the firmware and software of the core controller adopt a layered architecture, including: The driver layer is used to manage underlying hardware resources, including CameraLink interface drivers, PCIe drivers, and DDR module drivers. The protocol conversion layer, at the transmitting end, is used to parse CameraLink protocol frames and convert them into a unified internal data format suitable for wireless transmission. At the receiving end, it performs the reverse operation. The protocol conversion layer includes a protocol parsing module, a unified encapsulation module, and a data buffering and scheduling module. The network transport layer receives unified data frames from the protocol conversion layer, encapsulates them, and sends them to the receiving end of the wireless module through the Linux network protocol stack. It also receives data from the SD card, decapsulates the received data, and passes it to the protocol conversion layer.

[0011] Furthermore, the protocol parsing module is used to identify and parse the raw data stream of the CameraLink interface; The unified encapsulation module is used to encapsulate the parsed data stream into a custom intermediate frame structure; The data buffering and scheduling module is used to manage data streams from interfaces with different rates, and to perform buffering and priority scheduling.

[0012] A method for converting a satellite's onboard CameraLink interface to a WiFi 7 interface, comprising: Step 1: During data transmission, the CameraLink interface receives the wired data to be transmitted, performs level conversion, electrical isolation, and protocol parsing on the wired data, converting it into parallel data. The CameraLink interface transmits the parsed wired data to the core controller via the AXI-Stream bus. In the core controller, the parsed data is uniformly encapsulated into a custom intermediate frame format, and the encapsulated data is transmitted to the wireless module via the M.2 interface. The wireless module then transmits the encapsulated data wirelessly. Step 2: During the data reception process, the wireless module receives the wired data to be transmitted and transmits it back to the core controller through the M.2 interface. The core controller decapsulates the wired data to be transmitted, restores the original data structure and instructions, and transmits the encapsulated data to the CameraLink interface through the AXI-Stream bus. The CameraLink interface converts the parallel data into a serial signal that conforms to the CameraLink standard and outputs it through the CameraLink interface.

[0013] Furthermore, the encapsulation of the parsed data specifically includes: adding identification information to the parsed data and converting it into an inner frame structure suitable for wireless transparent transmission, wherein the identification information includes, but is not limited to, source ID, timestamp, and type field.

[0014] The beneficial effects of this invention are: 1. High-speed wireless transmission: This invention uses WiFi 7 technology and supports CameraLink base mode to meet the needs of high-definition image and high-speed data stream transmission; 2. Low power consumption and small size: The power consumption of the adapter device of this invention is ≤15W, and its size and weight are strictly controlled within the requirements of spaceborne applications; 3. Transparent transmission: This invention requires no modification to the data during the conversion process, ensuring signal integrity and consistency; Attached Figure Description Figure 1 A schematic diagram of the hardware structure of a satellite-in-satellite CameraLink interface to WiFi7 interface conversion device; Figure 2 This is a schematic diagram of the CameraLink interface receiver circuit. Figure 3 Schematic diagram of the CameraLink interface transmission circuit; Figure 4 This is a schematic diagram of the wireless module interface circuit. Figure 5 This is a schematic diagram of the firmware for the core controller.

[0015] Figure 6 This is a flowchart illustrating a method for converting a satellite's internal CameraLink interface to a WiFi 7 interface. Detailed Implementation Specific implementation method one: as follows Figure 1 As shown, the hardware structure of the satellite-to-cameraLink interface and WiFi7 interface conversion device described in this embodiment includes: The system includes a core controller, wired module, wireless module, power module, DDR module, clock module, Flash module, JTAG module, USB-UART interface, M.2 interface, and SD card. Wired data communication with the core controller is achieved through the CameraLink interface circuit. The core controller is a Xilinx ZYNQ UltraScale+ MPSoC (model ZU4EV), integrating a PS and PL side. The PS side uses an ARM Cortex-A53 processor, while the PL side uses programmable logic, supporting CameraLink protocol processing and wireless module drivers. The wired module uses one CameraLink interface, supports Base mode, and has a speed of 1Gbps. The wireless module uses an Intel BE200 WiFi 7 module, leveraging the frequency division multiplexing advantage of its Multi-Link Operation (MLO) and Dynamic Frequency Selection (DFS) function to achieve intelligent anti-interference and link redundancy in the 2.4 / 5 / 6GHz frequency bands, ensuring a stable high-speed connection of over 1.2Gbps for CameraLink even in complex wireless environments. The power module supports 28V±3V input, with a total power consumption of ≤15W. It features multi-level power management and isolation design, and the overall structural dimensions of the conversion device are ≤150mm×150mm×70mm, with a weight of ≤1kg, meeting the requirements for miniaturization in space.

[0016] The M.2 interface circuitry provides the hardware foundation for wireless module development and the PCIe 3.0 protocol. DDR provides the core controller with a large-capacity, high-bandwidth temporary data storage space for processing cached data. The clock module is responsible for generating precise frequency signals to ensure that all modules requiring precise timing, such as the core controller and DDR, can operate synchronously and stably. The USB-UART module is used to connect to a computer terminal to output debugging information and run commands. The wireless module communicates with the core controller via the M.2 interface using PCIe. The SD card serves as the system boot medium, storing the bootloader, kernel image, and root file system. JTAG is the main interface for debugging, logic analysis, controller configuration, and Flash programming. Flash memory is used for program embedding. DC-DC power isolation provides electrical isolation between input and output power supplies, preventing interference, surges, or ground loops from affecting the stable operation of the core system, improving system reliability and anti-interference capabilities. The power module is responsible for powering all modules on the board, converting the 28V input voltage to the various voltage levels required by the core controller and peripheral devices. The reset circuit provides a reset function for the terminal.

[0017] like Figure 2 As shown, the CameraLink receiver interface circuit design utilizes a protocol chip to perform serial-to-parallel conversion of image signals. The chosen protocol chip is the DS90CR288A, which can convert 4 channels of video data into 28 channels of parallel data. It can use the high and low levels of the input clock as a standard for serial-to-parallel data alignment, with each LVDS data channel transmitting 28 bits of data at a rate of 595 Mbps. Using an 85 MHz clock, the data throughput is 2.38 Gbit / s. Its package also occupies relatively little physical space. Additionally, the command signals CC1, CC2, CC3, and CC4 use the DS90LV047A chip, which supports low-voltage TTL / CMOS input levels and converts them into low-voltage (350mV) differential output signals, supporting the conversion of 4 control signals. The DS90LV019 chip is used for level conversion of asynchronous serial communication signals SerTFG and SerTC. The SI8660BB is used for digital isolation, and the B0505ST8 provides the isolation power supply. The connector selected is the SDR connector commonly used by CameraLink. One SDR connector is required to meet CameraLink's base mode requirements.

[0018] like Figure 3As shown, the design of the CameraLink transmitter is similar to that of the receiver. The protocol chip is the DS90CR287, and the command signal is level-converted using the DS90LV048A chip. The asynchronous serial communication signals SerTFG and SerTC are level-converted using the DS90LV019 chip. However, due to the limitations of PL-side I / O resources, since the aforementioned chips have a 3.3V input level, they can only be connected to the FPGA's HRIO interface. The FPGA in this design already has a significant amount of HRIO space occupied, while the HPIO (High Performance Input / Output) interface resources are plentiful. Therefore, a level-conversion chip is needed to convert the 1.8V signal from the HP port to a 3.3V signal compatible with the protocol chip. The 16-channel SN74AVCH16T245GR level-conversion chip is chosen to save PCB layout resources.

[0019] like Figure 4 As shown, the onboard wired / wireless interface conversion terminal adopts WiFi 7 wireless transmission technology based on IEEE 802.11 be, and selects a 2230 specification M.2 interface wireless module. This module achieves device miniaturization through a compact M.2 interface (formerly NGFF, Next Generation Form Factor), meeting the stringent requirements of the spaceborne environment for size and mass payload. The selected wireless module adopts the Socket 1 Key-E interface form factor, and according to the pin specifications defined in the PCI Express M.2 Specification standard, it can be directly adapted to the ZU4EV's PCIe hard core. This interface solution combines low latency and high bandwidth, providing 8GT / s transmission capability through a PCIe 3.0 × 1 lane, meeting the physical layer requirements of WiFi 7's theoretical speed of up to 30Gbps. The Key-E structure enhances adaptability to vibration environments, and the plug-and-play feature significantly reduces the startup latency of the onboard system, providing a reliable wireless solution for this design.

[0020] To utilize the ZU4EV's PCIe hard core, this implementation connects the PCIe communication pins to the BANK224.

[0021] like Figure 5 As shown, in order to clearly define functions and improve maintainability and scalability, this implementation adopts a layered design for the firmware and embedded software system of the core controller, which is divided into three layers from bottom to top: driver layer, protocol conversion layer, and network transmission layer.

[0022] This includes the underlying communication protocols, data transmission and reception, interrupt handling, and DMA control for interfaces such as eraLink. It also adapts and optimizes for the PL-side peripheral IP of Zynq MP. The wireless interface driver manages the PCIe hard core, responsible for high-speed data exchange and control command transmission with the mounted wireless module, relying on the Linux kernel's native PCIe driver framework. Finally, the DDR controller driver optimizes DDR memory access on the PS side, ensuring the efficiency and stability of the high-speed data buffer.

[0023] The protocol conversion layer is responsible for receiving raw data from the driver layer, parsing the unique frame structures of different wired buses, and converting them into a unified internal data format suitable for wireless transmission; it performs the reverse operation at the receiving end. This enables the aggregation, synchronization, and format standardization of multi-source data. The protocol conversion layer includes a protocol parsing module, responsible for identifying and parsing the CameraLink's raw data stream; a unified encapsulation module, responsible for encapsulating the parsed payload data, timestamp, priority, and checksum information into a custom intermediate frame structure; and a data buffering and scheduling module, which manages data streams from different rate interfaces, performing buffering and priority scheduling to prevent data congestion or loss.

[0024] The network transport layer is responsible for handling IP-based data packet transmission. It receives unified data frames from the protocol conversion layer, encapsulates them, and sends them to the wireless receiver via the Linux network protocol stack. It also receives data from the wireless network card, decapsulates it, and passes it to the protocol conversion layer. Furthermore, it manages and optimizes the wireless link. The Linux network protocol stack provides support for network protocols such as TCP / IP and UDP. It integrates the Intel iwlwifi driver to support the BE200 wireless module and configures its advanced features. It integrates wpa_supplicant and hostapd for wireless connection establishment, authentication, encryption, and parameter configuration.

[0025] To achieve efficient collaboration of the aforementioned layered functions, the system employs a clear functional division in its hardware and software co-design. The underlying data acquisition logic is deployed on the PL side, implementing the CameraLink physical interface and its corresponding controller to capture raw data from the physical link. Data output from each interface is uniformly converted into a standard stream format via the AXI4-Stream interface adapter and efficiently transferred to the DDR memory on the PS side via the AXI FPD interface using DMA.

[0026] Building upon this foundation, the Linux system running on the PS terminal handles the core functions of data parsing and protocol conversion. This Linux system is built on PetaLinux. The protocol conversion layer, comprised of kernel modules or user-space processes, encapsulates the data and connects it to the Linux network protocol stack via PF_PACKET sockets. Subsequently, controlled by the iwlwifi driver, the data is passed to the BE200 wireless network card for 802.11be protocol processing via the PCIe interface, and finally transmitted at high speed to the target receiver via the antenna.

[0027] On the receiving path, the BE200 network card captures the wireless signal and completes physical / MAC layer processing before transmitting the data to the iwlwifi driver via PCIe, and then into the protocol stack. The unified frame unpacking module is responsible for parsing the custom header and restoring the original CameraLink data structure. Depending on the type and bandwidth requirements, the restored data is sent to the PL controller via the AXILite interface for control command communication, or returned to the PL end via the AXI4-Stream interface for high-speed data output, thus achieving a complete data loop.

[0028] Specific Implementation Method Two: In this implementation, the system hardware layer deploys one CameraLink data interface. This key hardware unit, after completing physical layer signal conditioning and electrical isolation through precision circuitry, connects to the central controller. The controller's internal firmware adopts a modular design. The transceiver logic driver module parses the CameraLink bus protocol frame structure in real time; the data buffer pool dynamically balances burst traffic; the processing engine performs protocol conversion and data encapsulation; the aggregation module integrates signals into an AXI bus-compatible format; the DDR memory serves as a high-speed buffer pool to temporarily store pre-processed data, supporting burst writes and sequential reads; the PCIe firmware module achieves zero-copy transmission through the DMA channel; the interrupt control unit responds to millisecond-level event triggers; and the triple redundancy module ensures reliability in the satellite environment through a triple verification mechanism.

[0029] At the software layer, a customized PCIe driver establishes the connection between hardware acceleration and the host system, while the wireless communication driver is deeply optimized for the multi-link operation characteristics of WiFi 7, supporting dynamic aggregation of three bands (2.4 / 5 / 6GHz) and 320MHz channel bonding. Firmware and software collaboration is achieved through the AXI-Stream bus, a pipeline-based transmission mechanism that enables lossless conversion of CameraLink data streams into high-speed WiFi 7 wireless data streams. The system features a specially designed reverse path control logic, allowing the wireless module to directly write to DDR memory via the PCIe interface, and after protocol reverse conversion, output to the wired bus, forming a bidirectional real-time communication closed loop.

[0030] like Figure 6As shown, the steps of the satellite-to-satellite CameraLink interface and WiFi7 interface conversion method described in this embodiment include: S1: Parse and send wired data; The CameraLink interface receives wired data to be transmitted, performs level conversion, electrical isolation, and protocol parsing on the wired data, converts it into parallel data, and transmits the parsed wired data to the core controller via the AXI-Stream bus. In the core controller, the parsed data is uniformly encapsulated into a custom intermediate frame format, and the encapsulated data is transmitted to the wireless module via the M.2 interface. The wireless module then transmits the encapsulated data wirelessly. During the data encapsulation process, the wired data stream mentioned above is read from DDR to complete a unified frame packing operation. That is, while retaining the original payload data, identification information such as source ID, timestamp, and type field is added to construct an internal frame structure suitable for wireless transparent transmission.

[0031] S2: Perform data recovery on the parsed data to achieve transparent transmission; The wireless module receives wired data to be transmitted and transmits it back to the core controller via the M.2 interface. Within the core controller, the wired data to be transmitted is decapsulated to restore the original data structure and instructions. The decapsulated data is then transmitted to the CameraLink interface via the AXI-Stream bus. The CameraLink interface converts the parallel data into a serial signal conforming to the CameraLink standard and outputs it through the CameraLink interface, thus achieving transparent transmission.

[0032] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A satellite intra- satellite CameraLink interface and WiFi7 interface conversion device, characterized in that, It comprises: a core controller integrated with a PS end and a PL end, used for supporting CameraLink protocol processing of a wired interface circuit and driving of a wireless interface; a wired module bidirectionally connected with the core controller through an AXI-Stream bus, the wired module comprising a CameraLink interface, supporting a Base mode and having a rate of 1 Gbps, and used for receiving wired data to be transmitted; a wireless module bidirectionally connected with the wired module, used for providing a stable high-speed connection of more than 1.2 Gbps for the CameraLink interface in a complex wireless environment; a power module supporting 28V±3V input, having a power consumption of less than or equal to 15W, and having multi-stage power management and isolation design, used for supplying power to each module in the conversion device.

2. The satellite intra- satellite CameraLink interface and WiFi 7 interface conversion device according to claim 1, characterized in that, The core controller is also bidirectionally connected with a DDR module, a clock module, a Flash module, a JTAG module, a USB-UART interface, an M.2 interface and an SD card; the DDR module is used for providing temporary data storage space for the core controller, and used for processing cache data; the clock module is responsible for generating an accurate frequency signal and determining the working timing of all components in the conversion device; the Flash module is used for solidifying programs; the JTAG module is used for debugging, logic analysis, controller configuration and Flash programming; the USB-UART interface is used for connecting terminal equipment to output debugging information and run command lines; the wireless module communicates with the core controller through the M.2 interface by PCIe; the SD card is used for storing a boot program, a kernel image and a root file system.

3. The satellite intra- satellite CameraLink interface and WiFi 7 interface conversion device according to claim 1, characterized in that, The receiving circuit of the CameraLink interface comprises: a receiving end protocol chip, used for converting 4-way video data into 28-way parallel data, and realizing serial-to-parallel data alignment according to the high and low levels of an input clock; a receiving end instruction signal conversion chip, supporting low-voltage TTL / CMOS input level, converting the low-voltage TTL / CMOS input level into a 350mV low-voltage differential output signal, and converting 4-way control signals; a receiving level conversion chip, used for level conversion of asynchronous serial communication signals SerTF and SerTC; a digital isolation chip, used for realizing circuit digital isolation; an isolated power supply chip, used for providing an isolated power supply for the receiving circuit; a connector, conforming to the CameraLink standard and adapting to the interface requirement of the Base mode of the CameraLink interface.

4. The satellite intra- satellite CameraLink interface and WiFi 7 interface conversion device according to claim 1, characterized in that, The transmitting circuit of the CameraLink interface comprises: a transmitting end protocol chip, used for realizing parallel-to-serial data conversion and adapting to the Base mode signal transmission of the CameraLink interface; a transmitting end instruction signal conversion chip, used for level conversion and transmission of control signals; a transmitting end serial communication signal level conversion chip, used for level conversion of asynchronous serial communication signals SerTFG and SerTC; The sending end level conversion chip is a 16-channel chip, which is used for converting 1.8V signals on the PL end of the core control module into 3.3V signals required by the sending end protocol chip.

5. The satellite intra-vehicle CameraLink interface and WiFi 7 interface conversion device according to claim 1, characterized in that, The wireless module adopts a Socket 1 Key-E interface form, adapts to a PCIe hard core of a ZU4EV, and adopts a PCIe3.0x1 channel to provide 8GT / s transmission capacity.

6. The satellite intra- satellite CameraLink interface and WiFi 7 interface conversion device according to claim 1, characterized in that, The firmware and software of the core controller adopt a layered architecture, including: a driving layer, which is used for managing underlying hardware resources, including a CameraLink interface driver, a PCIe driver and a DDR module driver; a protocol conversion layer, which is used for analyzing CameraLink protocol frames and converting them into unified internal data formats suitable for wireless transmission at the sending end, and performing reverse operations at the receiving end; the protocol conversion layer includes a protocol analysis module, a unified packaging module and a data buffering and scheduling module; a network transmission layer, which receives unified data frames from the protocol conversion layer, encapsulates the unified data frames, sends the encapsulated data frames to the receiving end of the wireless module through a Linux network protocol stack, and receives data from an SD card, decapsulates the received data and transmits the decapsulated data to the protocol conversion layer.

7. The satellite intra- satellite CameraLink interface and WiFi 7 interface conversion device of claim 6, wherein, The protocol analysis module is used for identifying and analyzing the original data stream of the CameraLink interface; the unified packaging module is used for packaging the analyzed data stream into a self-defined intermediate frame structure; and the data buffering and scheduling module is used for managing data streams of different rate interfaces, buffering and priority scheduling.

8. A satellite intra-satellite CameraLink interface and WiFi7 interface conversion method applied to the satellite intra-satellite CameraLink interface and WiFi7 interface conversion device of any one of claims 1-7, characterized in that, The method comprises the following steps: Step 1: in the data sending process, receiving wired data to be transmitted through a CameraLink interface, performing level conversion, electrical isolation and protocol analysis on the wired data, converting the wired data into parallel data, transmitting the analyzed wired data to the core controller through an AXI-Stream bus, uniformly packaging the analyzed data into a self-defined intermediate frame format in the core controller, and transmitting the packaged data to the wireless module through an M.2 interface and sending the packaged data wirelessly through the wireless module; Step 2: in the data receiving process, receiving wired data to be transmitted through the wireless module, transmitting the received wired data to be transmitted back to the core controller through the M.2 interface, unpackaging the wired data to be transmitted in the core controller to restore the original data structure and instructions, transmitting the encapsulated data to the CameraLink interface through the AXI-Stream bus, converting the parallel data into serial signals conforming to the CameraLink standard through the CameraLink interface, and outputting the serial signals through the CameraLink interface.

9. The method according to claim 8, wherein, The packaging of the analyzed data specifically comprises: adding identification information to the analyzed data, and converting the analyzed data into an internal frame structure suitable for wireless transparent transmission, wherein the identification information includes but is not limited to a source ID, a timestamp and a type field.

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