Frequency adjustment method and device, electronic equipment and storage medium

Abstract

The invention discloses a frequency adjustment method and device, electronic equipment, a storage medium and a computer program product, and belongs to the technical field of computers.The method comprises the steps that the frequency upper limit value of a double data rate synchronous dynamic random access memory DDR of the electronic equipment is determined based on operation parameters of a processor of the electronic equipment; and when the working frequency of the DDR is higher than the frequency upper limit value, lowering the working frequency of the DDR, and enabling the adjusted working frequency of the DDR to be lower than or equal to the frequency upper limit value.

Description

Technical Field

[0001] This application belongs to the field of computer technology, and specifically relates to a frequency adjustment method, device, electronic device, storage medium, and computer program product. Background Technology

[0002] Double Data Rate Synchronous Dynamic Random-Access Memory (DDR SDRAM) is a core component of electronic devices, often abbreviated as DDR. In related technologies, to meet the bandwidth requirements of core components (such as the Central Processing Unit (CPU)), DDR frequencies are always kept at high levels.

[0003] This results in significantly higher power consumption for electronic devices. Summary of the Invention

[0004] The purpose of this application is to provide a frequency adjustment method, apparatus, electronic device, storage medium, and computer program product that can reduce the power consumption of electronic devices without affecting their performance.

[0005] In a first aspect, embodiments of this application provide a frequency adjustment method, which includes: determining the upper limit of the frequency of the DDR of the electronic device based on the operating parameters of the processor of the electronic device; and lowering the operating frequency of the DDR when the operating frequency of the DDR is higher than the upper limit of the frequency, such that the adjusted operating frequency of the DDR is lower than or equal to the upper limit of the frequency.

[0006] Secondly, embodiments of this application provide a frequency adjustment device, which includes a determining module and an adjusting module. The determining module is used to determine the upper limit of the DDR frequency of the electronic device based on the operating parameters of the processor of the electronic device. The adjusting module is used to lower the operating frequency of the DDR when the operating frequency of the DDR is higher than the upper limit determined by the determining module, such that the adjusted operating frequency of the DDR is lower than or equal to the upper limit.

[0007] Thirdly, embodiments of this application provide an electronic device including a processor and a memory, wherein the memory stores programs or instructions executable on the processor, and the programs or instructions, when executed by the processor, implement the steps of the method described in the first aspect.

[0008] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the first aspect.

[0009] Fifthly, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the method as described in the first aspect.

[0010] In a sixth aspect, embodiments of this application provide a computer program / program product stored in a storage medium, which is executed by at least one processor to implement the method as described in the first aspect.

[0011] In this embodiment, the upper frequency limit of the DDR (DDR memory) of the electronic device is determined based on the operating parameters of the processor. If the DDR's operating frequency is higher than the upper frequency limit, the DDR's operating frequency is lowered, and the adjusted DDR operating frequency is lower than or equal to the upper frequency limit. In this solution, since an upper frequency limit for the DDR of the electronic device can be determined based on the processor's operating parameters, and then the DDR's operating frequency is controlled to not exceed this upper frequency limit, the DDR's operating frequency is matched with the processor's operating requirements, avoiding the DDR from constantly operating at a high frequency. This reduces the power consumption of the electronic device without affecting its performance. Attached Figure Description

[0012] Figure 1 This is a flowchart of a frequency adjustment method provided in some embodiments of this application;

[0013] Figure 2 This is a flowchart of a frequency adjustment method provided in some embodiments of this application;

[0014] Figure 3 This is a flowchart of a frequency adjustment method provided in some embodiments of this application;

[0015] Figure 4 This is a flowchart of a frequency adjustment method provided in some embodiments of this application;

[0016] Figure 5 This is a flowchart of a frequency adjustment method provided in some embodiments of this application;

[0017] Figure 6 These are schematic diagrams of the frequency adjustment device provided in some embodiments of this application;

[0018] Figure 7 These are schematic diagrams of the hardware structure of electronic devices provided in some embodiments of this application;

[0019] Figure 8 These are schematic diagrams of the hardware structure of electronic devices provided in some embodiments of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0021] The terms "first," "second," etc., used in this application's specification are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects. For example, a first object can be one or more, where "more" means at least two. Furthermore, in the specification, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0022] The terms "at least one" and "at least one of" in this application's specification refer to any one, any two, or a combination of two or more of the included objects. For example, "at least one of a, b, and c" can mean "a", "b", "c", "a and b", "a and c", "b and c", and "a, b, and c", where a, b, and c can be single or multiple, and multiple means at least two. Similarly, "at least two" means two or more, and its meaning is similar to "at least one". The identifiers in this application are text, symbols, images, etc., used to indicate information, and can use controls or other containers as carriers for displaying information, including but not limited to text identifiers, symbol identifiers, and image identifiers.

[0023] The terminology used in the implementation section of this application is only for explaining specific embodiments of this application and is not intended to limit this application. The terminology involved in the embodiments of this application is explained below.

[0024] 1. CPU, the core processing unit of a computer, is responsible for coordinating and scheduling all core computing tasks of the device, including logical judgment, data processing, instruction execution, and the coordinated management of various hardware modules. Its architecture is designed to balance complex single-threaded tasks and multi-tasking parallel processing capabilities. Whether it is daily system operation and software startup, or complex office calculations and program compilation, all rely on the core computing support of the CPU, which is the core hub for the stable operation of the device.

[0025] 2. Graphics Processing Unit (GPU): A processor specifically designed for processing graphics and image data. It possesses a large number of computing cores and excels in high-concurrency floating-point operations and parallel data processing. It not only handles core graphics tasks such as image rendering, video decoding, and game screen generation, but also leverages its parallel computing advantages in scenarios such as artificial intelligence training, scientific computing, and deep learning, significantly improving data processing efficiency. It is a crucial hardware module that balances graphics display and high-performance computing.

[0026] 3. The Image Signal Processor (ISP) is a dedicated processor for processing data acquired by image sensors. It is a crucial component connecting the camera sensor to the final image output. It performs a series of processing operations on the raw image data acquired by the sensor, including noise reduction, white balance correction, exposure adjustment, high-dynamic-range (HDR) image synthesis, and sharpening optimization. It also assists in achieving functions such as autofocus and electronic image stabilization, ultimately transforming the original blurry data into clear, color-accurate images or videos. It is widely used in devices such as mobile phones, cameras, and surveillance cameras.

[0027] 4. The Neural Network Processing Unit (NPU) is a dedicated processor designed specifically for running Artificial Intelligence (AI) algorithms. Its core advantage lies in efficiently handling matrix operations within neural networks. It can accelerate the inference and part of the training process of AI models, quickly completing tasks such as facial recognition, speech recognition, image semantic segmentation, and intelligent recommendation on terminal devices, while supporting the computational needs of large-scale AI models in the cloud. Compared to CPUs and GPUs, NPUs consume less power and are faster when processing AI tasks, making them one of the core hardware drivers for the development of smart devices.

[0028] 5. DDR, a high-speed memory, serves as a device's "temporary data warehouse." Its core characteristic is the ability to transmit data on both the rising and falling edges of the clock signal, doubling the bandwidth compared to traditional memory. This provides high-speed data read / write support for processors such as CPUs, GPUs, and NPUs. Instructions and temporary data required by the processor are stored in DDR. Its capacity and frequency directly affect the smoothness of multitasking and the processor's computational efficiency. It is commonly found in computer RAM modules and mobile phone RAM.

[0029] DDR frequency, or DDR operating frequency, is a core indicator for measuring the data transfer speed of DDR memory. The unit is usually megahertz (MHz). Essentially, it represents the oscillation frequency of the memory clock signal. DDR's "double data rate" characteristic allows it to complete one data transfer on each of the rising and falling edges of the clock signal. Therefore, the actual data transfer frequency (effective frequency) is usually twice its core clock frequency. A higher DDR frequency means faster data exchange between the memory and processors such as the CPU and GPU per unit time, providing the processor with the necessary instructions and temporary data more efficiently, effectively reducing the processor's data waiting time. Conversely, a low frequency can become a bottleneck for device operation, affecting the smoothness of multitasking and loading large games.

[0030] With memory bus width and number of channels remaining constant, a higher DDR frequency results in a higher effective frequency and ultimately greater memory bandwidth. Greater bandwidth means that processors (CPU, GPU, NPU, etc.) can read or write data from memory faster, reducing data waiting time and thus improving the smoothness of device operation in scenarios such as multitasking, large-scale games, and high-definition video rendering. Conversely, if the frequency is too low, even with a large memory capacity, insufficient bandwidth may become a bottleneck for system performance.

[0031] The frequency adjustment method provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0032] The frequency adjustment method provided in this application can be applied to scenarios where the operating frequency of the DDR in an electronic device is adjusted.

[0033] As the complexity of mobile terminal applications and user experience requirements continue to increase, System-on-Chip (SoC) integrates multi-level heterogeneous computing units (multi-core CPUs, GPUs, NPUs, etc.), high-bandwidth storage subsystems, and complex memory control logic on a single chip. To ensure responsiveness and graphics rendering throughput, modern mobile platforms typically use DDR interfaces that support multiple memory frequency levels, with the CPU, GPU, and other subsystems jointly determining the memory frequency level through an internal "voting" or QoS mechanism within the SoC. In related technologies, when a single or partial computing domain makes a short-term high-bandwidth request, the system tends to increase the DDR frequency to a high level to meet the worst-case scenario. This conservative strategy based on the worst-case scenario can lead to memory "oversupply" in many common low- to medium-load scenarios, resulting in a significant increase in energy consumption with limited performance gains. Classic research on Dynamic Voltage and Frequency Scaling (DVFS) indicates that dynamic frequency limiting based on bandwidth utilization can bring considerable energy savings with minimal performance loss.

[0034] Existing frequency control at the kernel level largely relies on static mapping or simple threshold / delay strategies, and different domains (CPU, GPU, memory) are mostly managed by independent algorithm modules (governors), lacking cross-domain coordination and global optimization considerations. Recent system-level research (such as system-level collaborative scaling (SysScale) and coarse-grained model-based dynamic voltage and frequency scaling (CGM-DVFS)) has proposed the necessity and feasibility of cross-domain collaborative DVFS: by jointly considering the performance status of CPU / GPU, load prediction, memory controller configuration, and DVFS conversion overhead, energy efficiency can be significantly improved and the additional system-level overhead (such as voltage steady-state, controller timeout, and timing adjustments) caused by rapid frequency increases in a single domain can be avoided. These works also emphasize the switching costs and timing consistency issues—frequency switching is not "zero-cost," and overly frequent or inconsistent switching can erode energy-saving benefits and may cause performance jitter.

[0035] In actual measurement studies of mobile terminals, it has been demonstrated that there is an adjustable trade-off between memory frequency and user-perceived performance and overall power consumption: in most user scenarios, moderately reducing the DDR frequency can achieve a significant reduction in power consumption with a small or negligible increase in latency. This conclusion provides an engineering feasibility basis for dynamic frequency limiting based on runtime conditions. However, implementing such a mechanism requires solving several key technical challenges: first, how to accurately and with low overhead measure and predict short-term and medium-term memory bandwidth requirements (including asynchronous bursts and graphics pipeline latency); second, how to design a fair and controllable voting / arbitration strategy at the kernel (or driver) level so that short-term peak requests from a single subsystem do not leverage up the global DDR level; and third, how to safely coordinate frequency adjustment with memory controller registers and power management subsystems to avoid data errors or performance anomalies caused by timing mismatches.

[0036] To address the issues of excessively high DDR frequencies, performance redundancy, and high power consumption caused by the current CPU / GPU voting mechanism, a dynamic frequency limiting method with real-time awareness, cross-domain coordination, and cost awareness at the kernel and SoC runtime levels is urgently needed. This method should reduce memory oversupply and optimize overall system energy efficiency while ensuring user experience and the integrity of critical timings.

[0037] In existing mobile SoC power management systems, dynamic voltage and frequency regulation of DDR memory has become an important means of reducing the power consumption of the memory subsystem. However, although existing solutions perform well in responding to performance demands and improving data throughput, they still generally suffer from the problem of "DDR frequency over-supply," that is, maintaining high-frequency operation even under non-peak loads, resulting in significantly higher storage power consumption and making it difficult to achieve optimal system-level energy efficiency. The root cause is that current frequency regulation mechanisms are mostly based on single-dimensional performance indicators, static mapping logic, or hysteresis control strategies, lacking cross-domain coordination and timing correlation modeling.

[0038] Mainstream memory dynamic voltage and frequency adjustment schemes often determine frequency levels by monitoring metrics such as DDR controller or memory bus bandwidth utilization and request queue length. However, these metrics exhibit significant time delays and short-term fluctuations. Bandwidth statistics are typically based on a sliding time window, and the sampling period and averaging process cause DDR frequency adjustments to lag behind actual computational load changes. After a momentary drop in CPU or GPU load, DDR continues to operate at a high frequency, resulting in wasted energy. Simultaneously, when graphics rendering frame switching or cache miss peaks occur, sudden high bandwidth requests are mistakenly interpreted by the system as sustained high load, triggering a high-frequency adjustment. However, the actual demand duration is extremely short, and the frequency drop-off delay leads to redundant energy consumption. Bandwidth monitoring is usually sampled locally by a single controller, failing to accurately reflect the true collaborative needs of the CPU and GPU, resulting in overly protective frequency increases.

[0039] In mobile SoC architectures, computing units such as CPUs and GPUs collectively determine the upper limit of DDR frequency through a voting mechanism. When any subsystem makes a high-performance request, the system boosts DDR to a higher level to avoid performance bottlenecks. This design ensures performance integrity in extreme scenarios but introduces significant energy efficiency issues. In existing DDR voting strategies, the DDR frequency is determined by the highest voter. Even if only a single core or rendering unit enters a high-load state, the system still boosts DDR to a globally high level, while other modules remain in a low-activity state, resulting in over-supply. Simultaneously, most platforms implement down-hysteresis to avoid stability issues caused by frequent frequency switching, causing the DDR frequency to remain at a high level for an extended period after the load ends. As the primary consumers of DDR bandwidth, CPUs and GPUs exhibit significantly different sensitivities to DDR bandwidth. CPU load changes are often more frequent and on shorter timescales, while GPU frame rendering has strong periodicity and burstiness. The lack of a unified and coordinated voting mechanism makes it impossible to accurately assess the actual bandwidth usage ratio of both, thus over-amplifying the impact of high-frequency voting.

[0040] Modern SoC power consumption control is achieved collaboratively by multiple subsystems, including the CPU Frequency and Voltage Scaling Framework (CPUfreq), GPU governor, Device Frequency Dynamic Scaling Framework (Devfreq), peripherals managing DDR / NPU / ISP, and user-space policies of the Power Hardware Abstraction Layer (PowerHAL). However, insufficient information exchange between modules leads to problems. The GPU governor predicts performance requirements based on frame rate (FPS) or frame time, but this information fails to reach the DDR control layer, resulting in DDR still using outdated load sampling results. The CPU governor tends to maintain high-frequency operation to ensure computing performance, but Devfreq cannot perceive the CPU status in real time. Therefore, it independently decides the DDR level based on local bandwidth monitoring, ultimately leading to a decrease in overall energy efficiency.

[0041] To address the aforementioned issues, it's evident that existing DDR frequency control generally lacks global correlation modeling of the system's operational state, particularly failing to utilize the real-time frequency states of peripherals such as the CPU and GPU as effective constraints. In fact, CPU and GPU frequency changes are highly correlated with their internal load and task scheduling states, reflecting the immediate bandwidth demands of the computing domain. Therefore, if a joint assessment of the real-time frequency and load characteristics of the CPU and GPU can be introduced into the DDR frequency control strategy, and a reasonable dynamic upper limit for the DDR frequency can be set based on this—i.e., dynamic DDR frequency limiting—it's possible to suppress energy consumption degradation caused by excessive supply without sacrificing performance as much as possible. This dynamic constraint, using the frequencies of peripherals, especially the CPU and GPU, as the "upper bound of demand," actively suppresses DDR frequency increases when CPU / GPU frequencies are low, thus avoiding bandwidth redundancy; under high load conditions, as peripheral frequencies rise synchronously, the DDR frequency upper limit is relaxed to meet performance demands. Through this collaborative mechanism of "cross-domain awareness + amplitude limiting," a power optimization method with real-time performance, low latency, and scalability is provided. The system can achieve real-time matching between bandwidth supply and computing demands, achieving the goal of significantly reducing power consumption while maintaining frame rate and smooth interaction.

[0042] The frequency adjustment method provided in this application can determine an upper frequency limit for the DDR of an electronic device based on the operating parameters of the processor, and then control the DDR's operating frequency to not exceed this upper frequency limit. This achieves a match between the DDR's operating frequency and the processor's operating requirements, preventing the DDR from constantly operating at a high frequency. Thus, it reduces the power consumption of the electronic device without affecting its performance.

[0043] The frequency adjustment method provided in this application is executed by a frequency adjustment device, which can be an electronic device, or a functional module or entity within an electronic device. This application does not limit the specific implementation of this method. The following will use an electronic device as an example to illustrate the frequency adjustment method provided in this application.

[0044] This application provides a frequency adjustment method. Figure 1 A flowchart of a frequency adjustment method provided in an embodiment of this application is shown. Figure 1 As shown, the frequency adjustment method provided in this application embodiment may include the following steps 201 and 202.

[0045] Step 201: Based on the operating parameters of the processor of the electronic device, determine the upper limit of the DDR frequency of the electronic device.

[0046] In some embodiments of this application, the processor may include at least one of the following: CPU, GPU, ISP, NPU, etc. The specific processor can be determined according to actual usage requirements, and this application does not limit this.

[0047] In some embodiments of this application, the operating parameters of the processor may include at least one of the following: processor frequency, processor load, etc. The specific parameters can be determined according to actual usage requirements, and this application does not limit this.

[0048] In some embodiments of this application, the aforementioned processor operating parameters can be understood as the bandwidth utilization characteristics of the electronic device during operation, i.e., bandwidth utilization rate. It is understood that since higher frequencies and loads result in higher bandwidth requirements, processor operating parameters can be used to characterize bandwidth utilization rate.

[0049] In some embodiments of this application, the aforementioned upper frequency limit of DDR can be understood as an upper frequency limit set for the operating frequency of DDR. It is understood that when the operating frequency of DDR is higher than this upper frequency limit, the electronic device will lower the operating frequency of DDR to ensure that the operating frequency of DDR does not exceed the upper frequency limit.

[0050] It is understandable that when the DDR operating frequency is lower than or equal to the above-mentioned frequency upper limit, the DDR operating frequency can meet the processor's DDR frequency requirements.

[0051] In some embodiments of this application, the electronic device can collect the operating parameters of the processor and then determine the upper limit of the DDR frequency of the electronic device based on the operating parameters of the processor.

[0052] In some embodiments of this application, the electronic device can collect the processor's operating parameters at preset time intervals, and then determine the upper limit of the DDR frequency of the electronic device based on the newly collected processor operating parameters. It can be understood that each time the electronic device determines the upper limit of the DDR frequency, it updates the upper limit of the DDR frequency, and then the electronic device can control the operating frequency of the DDR based on the latest updated upper limit of the DDR frequency.

[0053] In some embodiments of this application, the electronic device can input the processor's operating parameters into a prediction model to obtain the upper limit of DDR frequency output by the prediction model corresponding to the processor's operating parameters.

[0054] Step 202: When the operating frequency of DDR is higher than the upper frequency limit, the electronic device lowers the operating frequency of DDR.

[0055] In the embodiments of this application, the adjusted DDR operating frequency is lower than or equal to the upper frequency limit.

[0056] It is understandable that electronic devices can adjust the operating frequency of DDR to the upper limit of the frequency range, or they can adjust the operating frequency of DDR to a value lower than the upper limit of the frequency range.

[0057] In some embodiments of this application, the electronic device can register a frequency monitoring module and a frequency control interface, and bind the frequency monitoring module to the frequency control interface. Then, when the frequency monitoring module detects that the operating frequency of the DDR is higher than the upper frequency limit, the electronic device can send a frequency adjustment command to the DDR through the frequency control interface to lower the operating frequency of the DDR. The adjusted operating frequency of the DDR is lower than or equal to the upper frequency limit.

[0058] In some embodiments of this application, the frequency monitoring module described above is used to monitor the operating frequency of the DDR.

[0059] In some embodiments of this application, the frequency control interface described above is used to control the operating frequency of the DDR, and can also be understood as being used to adjust the operating frequency of the DDR.

[0060] In some embodiments of this application, the frequency control interface described above can be a DDR DVFS interface.

[0061] In some embodiments of this application, when the electronic device detects that it is in a high-load, high-power scenario, it can register a frequency monitoring module and a frequency control interface, and bind the frequency monitoring module to the frequency control interface.

[0062] In some embodiments of this application, the electronic device can clear the registered frequency monitoring module and frequency control interface when exiting a high-load, high-power scenario.

[0063] In the frequency adjustment method provided in this application embodiment, since an upper frequency limit for the DDR of the electronic device can be determined based on the operating parameters of the processor, and then the operating frequency of the DDR is controlled not to exceed this upper frequency limit, the operating frequency of the DDR is matched with the operating requirements of the processor, avoiding the DDR from always operating at a high frequency. This reduces the power consumption of the electronic device without affecting its performance.

[0064] In some embodiments of this application, after step 201 described above, the frequency adjustment method provided in this application further includes steps 301 and 302 as described below.

[0065] Step 301: The electronic device determines the processor's load change information based on the processor's operating parameters.

[0066] It is understandable that after the electronic device determines the upper limit of frequency, it can adjust the upper limit of frequency in real time based on the processor's real-time load change information, and control the operating frequency of DDR based on the adjusted upper limit of frequency.

[0067] It should be noted that the processor operating parameters used to determine processor load change information are collected at different times than the processor operating parameters used to determine the upper frequency limit of DDR.

[0068] Step 302: The electronic device adjusts the upper limit of frequency based on the processor's load change information.

[0069] In some embodiments of this application, the above-mentioned load change information is used to characterize the changes in the processor's load within a preset time period.

[0070] For example, the above load change information can be used to characterize any of the following:

[0071] The processor load fluctuates within a certain range over a preset duration;

[0072] The processor load increases within a preset time period, for example, it increases continuously;

[0073] The processor load decreases within a preset time period, for example, a continuous decrease.

[0074] In some embodiments of this application, step 302 can be implemented by step 302a or step 302b as described below.

[0075] Step 302a: When an increase in processor load is detected, the electronic device increases the upper limit of frequency.

[0076] In some embodiments of this application, if an increase in processor load is detected within a preset time period, the electronic device can increase the upper limit of frequency.

[0077] In some embodiments, when a continuous increase in processor load is detected, the electronic device may increase the upper limit of frequency by a preset value.

[0078] For example, assuming the preset value is 400, when the current upper limit of DDR frequency is 2400MHz, electronic devices can adjust the upper limit of DDR frequency to 2800MHz by setting it to 400MHz.

[0079] In some embodiments, when an increase in processor load is detected, such as a sustained increase, the electronic device can obtain the current operating parameters of the processor and then adjust the upper limit of the DDR frequency based on the current operating parameters of the processor.

[0080] It is understandable that electronic devices can redetermine the upper limit of DDR frequency based on the newly acquired current operating parameters of the processor.

[0081] For example, assuming the upper limit of DDR frequency is 2400MHz, if an electronic device determines the upper limit of DDR frequency to be 2600MHz based on the current operating parameters of the processor, the electronic device can adjust the upper limit of DDR frequency to 2600MHz, that is, increase the upper limit of DDR frequency.

[0082] In some embodiments of this application, when an increase in processor load is detected, such as a continuous increase, the electronic device can first increase the upper limit of DDR frequency according to a preset value, and then, based on the current operating parameters of the processor, determine the upper limit of frequency corresponding to the current operating parameters of the processor, and then adjust the upper limit of DDR frequency again.

[0083] It is understandable that when the processor load is detected to be increasing, such as continuously increasing, the electronic device can first adjust the upper limit of the DDR frequency as soon as possible according to the preset value, that is, first roughly control the operating frequency of the DDR, and then, based on the current operating parameters of the processor, determine the upper limit of the frequency that precisely corresponds to the current operating parameters of the processor, and then precisely control the operating frequency of the DDR.

[0084] Thus, as the processor load increases, for example, and continues to increase, electronic devices will actively relax the upper frequency limit of DDR, thereby allowing the bandwidth of DDR to be fully released to ensure overall performance output.

[0085] Step 302b: When a decrease in processor load is detected, the electronic device lowers the upper frequency limit.

[0086] In some embodiments of this application, if a decrease in processor load is detected within a preset time period, the electronic device can lower the upper limit of frequency.

[0087] In some embodiments, when a decrease in processor load is detected, such as a continuous decrease, the electronic device may lower the upper frequency limit by a preset value.

[0088] For example, assuming the preset value is 600, when the current upper limit of DDR frequency is 2400MHz, electronic devices can adjust the upper limit of DDR frequency to 1800MHz by setting it to 600MHz.

[0089] In some embodiments, when a decrease in processor load is detected, such as a sustained decrease, the electronic device can obtain the current operating parameters of the processor and then adjust the upper limit of the DDR frequency based on the current operating parameters of the processor.

[0090] It is understandable that electronic devices can redetermine the upper limit of DDR frequency based on the newly acquired current operating parameters of the processor.

[0091] For example, assuming the upper limit of DDR frequency is 2400MHz, if the electronic device determines the upper limit of DDR frequency to be 2300MHz based on the current operating parameters of the processor, the electronic device can adjust the upper limit of DDR frequency to 2300MHz, that is, lower the upper limit of DDR frequency.

[0092] In some embodiments of this application, when a decrease in processor load is detected, such as a continuous decrease, the electronic device can first lower the upper limit of DDR frequency according to a preset value, and then, based on the current operating parameters of the processor, determine the upper limit of frequency corresponding to the current operating parameters of the processor, and then adjust the upper limit of DDR frequency again.

[0093] It is understandable that when the processor load is detected to be increasing, such as continuously increasing, the electronic device can first adjust the upper limit of the DDR frequency as soon as possible according to the preset value, that is, first roughly control the operating frequency of the DDR, and then, based on the current operating parameters of the processor, determine the upper limit of the frequency that precisely corresponds to the current operating parameters of the processor, and then precisely control the operating frequency of the DDR.

[0094] Thus, as the processor load decreases, for example, when it continues to decrease, the electronic device will actively tighten the upper frequency limit of DDR, thereby saving power while ensuring overall performance output.

[0095] In some embodiments of this application, the processor's operating parameters include N processor operating parameters, where N is an integer greater than 1; combined with Figure 1 ,like Figure 2 As shown, step 201 can be implemented through steps 401 and 402 as described below.

[0096] Step 401: The electronic device determines the N frequency values ​​corresponding to the operating parameters of the N processors.

[0097] In some embodiments of this application, the electronic device can input the operating parameters of N processors into the prediction model to obtain the frequency value corresponding to the operating parameters of each processor output by the prediction model. Then, the electronic device can determine the maximum frequency value among the output frequency values ​​as the upper limit of DDR frequency.

[0098] In some embodiments of this application, when determining the upper limit of the DDR frequency of an electronic device based on the operating parameters of a single processor, the electronic device inputs the operating parameters of the single processor into a prediction model, and after obtaining the frequency value corresponding to the operating parameters of the processor output by the prediction model, the electronic device can determine the frequency value as the upper limit of the frequency.

[0099] In some embodiments of this application, the electronic device can input the operating parameters of N processors and the first information corresponding to each of the N processors into the prediction model to obtain the N frequency values ​​corresponding to the operating parameters of the N processors output by the prediction model.

[0100] In some embodiments of this application, the aforementioned first information may include at least one of the following: processor scheduling information, frame rate stability, memory bandwidth utilization, temperature, and power limit. The specific information can be determined based on actual usage requirements, and this application does not limit this aspect.

[0101] For example, the processor scheduling information mentioned above may include at least one of the following: maximum frequency limit, minimum frequency limit, core online status, run queue depth, and real-time task identifier. The specific details can be determined according to actual usage requirements, and this application embodiment does not limit this.

[0102] In some embodiments of this application, the electronic device can collect the operating parameters of at least one processor and the operating frequency of the DDR corresponding to the operating parameters of at least one processor. Then, based on the collected operating parameters of at least one processor and the operating frequency of the DDR corresponding to the operating parameters of at least one processor, the initial model is trained to obtain the above-mentioned prediction model, so that the prediction model can calculate and output the frequency value corresponding to the operating parameters of the processor based on the real-time operating parameters of the input processor.

[0103] In some embodiments of this application, the electronic device can collect the operating parameters of at least one processor and the operating frequency of DDR corresponding to the operating parameters of at least one processor in different scenarios.

[0104] In some embodiments of this application, the electronic device may also collect first information corresponding to at least one processor, and then train the above-mentioned initial model based on the collected operating parameters of at least one processor, the operating frequency of DDR corresponding to the operating parameters of at least one processor, and the first information corresponding to at least one processor.

[0105] In some embodiments of this application, when the electronic device detects that it is in a preset scenario, it can collect the operating parameters of at least one processor and the operating frequency of the DDR corresponding to the operating parameters of at least one processor. Then, based on the collected operating parameters of at least one processor and the operating frequency of the DDR corresponding to the operating parameters of at least one processor, it can train an initial model to obtain a prediction model.

[0106] For example, the preset scenarios described above can be high-load, high-power scenarios. For instance, preset scenarios may include any of the following: gaming scenarios, live video streaming scenarios, short video playback scenarios, etc.

[0107] It is understandable that electronic devices tend to be under high load and high power consumption scenarios.

[0108] Step 402: The electronic device determines the maximum frequency value among the N frequency values ​​as the upper frequency limit.

[0109] In some embodiments of this application, the electronic device can compare N frequency values ​​and then determine the maximum frequency value among the N frequency values ​​as the upper frequency limit.

[0110] In some embodiments of this application, the above-mentioned N frequency values ​​can be understood as the calculated voting values ​​of N processors. Determining the maximum frequency value among the N frequency values ​​as the upper limit of frequency can be understood as a comprehensive decision based on the calculated voting values ​​of N processors, which is a decision rule.

[0111] In some embodiments of this application, the electronic device may also determine the frequency upper limit using other decision rules. For example, the average of N frequency values ​​may be used to determine the frequency upper limit. The specific determination can be made based on actual usage requirements, and this application does not limit this.

[0112] In some embodiments of this application, the prediction model may be configured with decision rules. The electronic device inputs the operating parameters of N processors into the prediction model. After the prediction model calculates the N frequency values ​​corresponding to the operating parameters of the N processors, it can directly output the maximum frequency value among the N frequency values. Then, the electronic device can determine the maximum frequency value as the upper limit of the frequency, that is, directly output the upper limit of the frequency.

[0113] In this way, because electronic devices can determine the frequency value corresponding to each processor's operating parameters—that is, determine the DDR frequency requirement for each processor—and then set the maximum frequency value as the upper limit of DDR frequency, a precise correspondence between the upper limit of DDR frequency and the operating state of each processor can be achieved, avoiding DDR from always operating at a high frequency. This reduces the power consumption of electronic devices without affecting their performance.

[0114] In some embodiments of this application, the electronic device can collect the operating parameters of at least one processor and the operating frequency of the DDR corresponding to the operating parameters of the at least one processor. Then, based on the collected operating parameters of the at least one processor and the operating frequency of the DDR corresponding to the operating parameters of the at least one processor, a correlation relationship is constructed between the operating parameters of the processor and the upper frequency limit of the DDR operating frequency. Subsequently, the electronic device can determine the upper frequency limit corresponding to the operating parameters of the processor from the above correlation relationship based on the operating parameters of the processor.

[0115] In some embodiments of this application, the specific form of the above-mentioned association relationship may include any of the following: lookup table, graph, etc. The specific form can be determined according to actual usage requirements, and this application does not limit this aspect.

[0116] In some embodiments of this application, after determining the upper frequency limit, if the electronic device raises or lowers the upper frequency limit more than or equal to a fourth preset threshold number of times within a preset time period, the electronic device can dynamically correct the prediction model based on the second information. This allows the prediction model to more accurately output the upper frequency limit corresponding to the processor's operating parameters.

[0117] For example, the second information may include at least one of the following: the processor's operating parameters within a preset time period, the actual operating frequency of the DDR within a preset time period, the adjustment record of the frequency value corresponding to the processor's operating parameters within a preset time period, the performance feedback information of the electronic device, power consumption change information, etc.

[0118] In some embodiments of this application, the electronic device can continuously monitor the performance feedback and power consumption changes of the electronic device through a feedback and adaptive adjustment module, and dynamically correct the prediction model based on the monitoring results.

[0119] It is understandable that through this continuous closed-loop optimization approach, electronic devices can automatically adjust their decision-making strategies under different load scenarios, thereby achieving adaptive optimization and long-term evolution of the frequency upper limit, and ultimately achieving a dynamic balance between low power consumption and high performance.

[0120] In some embodiments of this application, combined with Figure 1 ,like Figure 3 As shown, step 201 above can be specifically implemented through step 501 below.

[0121] Step 501: When the electronic device is not under high load, the electronic device determines the upper limit of frequency based on the operating parameters of the processor of the electronic device.

[0122] In some embodiments of this application, the electronic device can determine whether it is in a high-load state. Then, when the electronic device is not in a high-load state, the electronic device can determine the upper limit of the frequency based on the operating parameters of the processor of the electronic device. Then, when the operating frequency of the DDR is higher than the upper limit of the frequency, the electronic device lowers the operating frequency of the DDR. That is, when the electronic device is not in a high-load state, the electronic device can enable a dynamic frequency limiting strategy.

[0123] In some embodiments of this application, if a first condition is met, the electronic device can determine that it is not under high load.

[0124] In some embodiments of this application, the first condition described above includes at least one of the following:

[0125] The processor load rate of the electronic device is lower than the second preset threshold;

[0126] The processor frequency of the electronic device is lower than the third preset threshold;

[0127] The load rate of the processor in the electronic device decreases within a preset time period, for example, continuously;

[0128] The frequency of the processor in the electronic device decreases over a preset period of time, for example, continuously.

[0129] The workload scenarios corresponding to the applications running on electronic devices are not considered high-load scenarios.

[0130] In some embodiments of this application, the load scenario corresponding to the application can be understood as: the current load scenario of the application, or the usage scenario of the application.

[0131] In some embodiments of this application, the load scenarios corresponding to the application can be divided into low-load scenarios, medium-load scenarios, and high-load scenarios.

[0132] For example, the low-load scenarios corresponding to the application may include any of the following: text chatting based on an instant messaging application; sending text messages based on an SMS application; browsing news based on a news application, etc.

[0133] For example, the medium-load scenarios corresponding to the application may include any of the following: making video calls based on an instant messaging application, watching videos based on a video application, playing music based on a music player application, navigating based on a navigation application, etc.

[0134] For example, the high-load scenarios corresponding to the application may include any of the following: playing games based on a game application, live streaming based on a short video application, recording video using a camera application, etc.

[0135] In some embodiments of this application, the electronic device does not limit the operating frequency of DDR when the electronic device is under high load.

[0136] It's understandable that when electronic devices are under high load, they employ a native DDR frequency modulation strategy, which means removing the limitations on DDR frequency. This allows the DDR bandwidth to be fully utilized, ensuring overall performance output.

[0137] In some embodiments of this application, the electronic device can determine whether it is in a high-load state when it detects that the electronic device is in a high-load, high-power scenario, i.e., the aforementioned preset scenario.

[0138] In some embodiments of this application, combined with Figure 1 ,like Figure 4 As shown, step 202 above can be specifically implemented through step 202a below.

[0139] Step 202a: When the operating frequency of DDR is higher than the upper frequency limit and the difference between the operating frequency of DDR and the upper frequency limit is greater than the first preset threshold, the electronic device gradually lowers the operating frequency of DDR according to the preset step value.

[0140] It is understandable that when the operating frequency of DDR is significantly higher than the upper limit, electronic devices can adopt a gradual reduction strategy to smoothly lower the operating frequency level of DDR.

[0141] For example, if the DDR is currently running at 3200MHz and the upper limit of the DDR frequency is 2400MHz, the electronic device can adjust the DDR operating frequency to 2800MHz and 2400MHz in preset steps of 400MHz.

[0142] In some embodiments of this application, during actual operation, the electronic device can also combine the processor's operating history and trend information to smoothly adjust the DDR's operating frequency.

[0143] Thus, when the operating frequency of DDR is significantly higher than the upper frequency limit, electronic devices can adopt a gradual down-adjustment strategy to smoothly reduce the operating frequency level of DDR, thereby avoiding sudden performance drops or system jitter in electronic devices.

[0144] In some embodiments of this application, when the electronic device is detected to be under high load and high power consumption, the electronic device can initiate a DDR dynamic frequency adjustment process to reduce power consumption by dynamically limiting the maximum frequency of the DDR. For example... Figure 5 As shown, the frequency adjustment method provided in this application embodiment may include the following steps S1 to S8.

[0145] S1. When the electronic device is detected to be in a high-load, high-power scenario, the electronic device registers a frequency monitoring module and binds the frequency monitoring module to the frequency control interface.

[0146] Understandably, in the early stages of system operation, the algorithm first initializes the monitoring environment, registers frequency monitoring modules for processors such as CPU and GPU, and completes the binding with the DDR DVFS frequency control interface, laying the foundation for subsequent management and control.

[0147] S2. The electronic device acquires the operating parameters of at least one processor and the operating frequency of the DDR corresponding to the operating parameters of at least one processor through the data acquisition module. Then, based on the acquired operating parameters of at least one processor and the operating frequency of the DDR corresponding to the operating parameters of at least one processor, the initial model is trained to obtain the prediction model.

[0148] It is understandable that electronic devices can be analyzed based on collected data to determine their overall operational characteristics. By analyzing data collected under different scenarios and task types, the algorithm can identify the sensitivity of DDR frequency changes to system performance and power consumption, thus providing data support for subsequent modeling.

[0149] S3. The electronic device determines whether it is currently under high load.

[0150] If yes, execute S4; if no, execute S5.

[0151] It is understandable that when the system is identified as being under high load, such as when the CPU or GPU load is rising or continuously rising and requires high performance support, or when there is a clear performance bottleneck or frame dropping, the DDR frequency should not be limited, the dynamic frequency limiting strategy is not enabled, and the process proceeds to S4; if the system is under low load, i.e. when the CPU and GPU loads are low, the process proceeds to step S5.

[0152] S4. Electronic devices execute native DDR frequency modulation strategies.

[0153] It is understandable that electronic devices actively relax or remove the upper limit frequency limit of DDR and implement the native DDR frequency adjustment strategy (relax the frequency limit) to fully release the storage bandwidth and ensure overall performance output.

[0154] S5. The electronic device inputs the operating parameters of N processors into the prediction model to obtain N frequency values ​​corresponding to the operating parameters of the N processors output by the prediction model; and determines the maximum frequency value among the N frequency values ​​as the upper frequency limit.

[0155] It is understandable that electronic devices can calculate the DDR frequency requirements for different processors (such as ISP / NPU, GPU, CPU) separately, and then make a comprehensive decision based on the calculated voting values ​​of each processor to obtain the precise correspondence between the upper limit frequency of DDR and the operating state of each processor under the current load and power consumption conditions.

[0156] S6. The electronic device adjusts the upper limit of frequency based on the processor's load change information.

[0157] S7. If the frequency monitoring module detects that the DDR operating frequency is higher than the upper frequency limit, the electronic device can lower the DDR operating frequency through the frequency control interface.

[0158] It is understandable that the adjusted DDR operating frequency is lower than or equal to the upper frequency limit.

[0159] S8. The electronic device continuously monitors the system's performance feedback and power consumption changes through the feedback and adaptive adjustment module, and dynamically corrects the prediction model based on the monitoring results.

[0160] This is understandable; the model can be iteratively trained to avoid stability issues caused by frequent fluctuations.

[0161] It should be noted that the execution order of S7 and S8 is not limited in the embodiments of this application.

[0162] It should be noted that the relevant descriptions of steps S1 to S8 can be found in the above embodiments, and will not be repeated here.

[0163] In the embodiments of this application, in order to solve the problem of oversupply in the current DDR frequency control and the resulting defects of high overall energy consumption and low energy efficiency, this application proposes a frequency adjustment method. This method takes the real-time operating frequency and load status of the processor as the core control basis, and combines the bandwidth utilization characteristics of the system operation to dynamically limit and adaptively adjust the DDR frequency, so as to match the DDR bandwidth supply with the computing demand, thereby effectively reducing the overall power consumption and improving the system energy efficiency ratio without significantly affecting the performance. (1) Innovatively, a DDR dynamic frequency limiting idea based on peripheral frequency awareness is proposed to realize cross-layer collaborative control between the computing domain and the storage domain. In related technologies, the DDR dynamic frequency control mechanism generally only relies on the bandwidth utilization rate or the memory controller queue depth as the frequency adjustment basis, which cannot accurately reflect the real-time performance demand of the system. Starting from the operating characteristics of SoC, this application takes the real-time frequency and load status of the processor (e.g., CPU and GPU) as an important input parameter for DDR regulation for the first time, and builds a cross-domain information path, so that the DDR operating frequency is no longer decided independently by a single controller, but dynamically related to the operating state of the CPU / GPU. When both the CPU and GPU are in a low-frequency or light-load state, this application actively sets an upper limit on the DDR frequency to prevent unnecessary increases; when either computing domain enters a high-frequency operation phase, the DDR frequency limit is automatically relaxed to ensure performance, thereby realizing an "on-demand" memory frequency control mechanism. It breaks through the domain adjustment limitations of traditional DVFS, extending power management from single-domain closed-loop control to cross-domain collaborative optimization. (2) Innovatively designing a dynamic limiting algorithm based on "frequency ratio mapping" to realize an adaptive mapping relationship between DDR frequency and CPU / GPU frequency. In order to achieve fine control of DDR frequency, this application proposes a modeling method of "frequency ratio mapping", that is, by calculating the proportion of the processor's working frequency (relative to their respective maximum frequencies) to establish a dynamic adjustment curve of DDR frequency (i.e. the above-mentioned correlation relationship). When the processor frequency is low, the upper limit of DDR frequency is compressed linearly or non-linearly according to the ratio to reduce energy waste; when the processor frequency rises rapidly or both are in the high-frequency range, the upper limit of DDR frequency moves up accordingly to ensure that the data path bandwidth does not become a performance bottleneck. Through this proportional mapping relationship, DDR can achieve "soft coupling" control that is dynamically bound to the processor frequency, and can adapt to different chip platforms, different memory specifications and different application scenarios, thus possessing universality and scalability. (3) An intelligent decision-making mechanism that integrates multiple sources of indicators is proposed to improve the real-time performance and stability of frequency limiting judgment. This application not only relies on the real-time frequency information of the processor, but also comprehensively considers multi-dimensional system indicators, including task queue length, frame rate stability, memory bandwidth utilization, temperature and power limit, etc., so as to construct a multi-dimensional perception frequency limiting decision model (i.e. the above prediction model).The model forms a comprehensive "system load intensity" by weighting different indicators, thereby determining the triggering condition and release threshold of DDR frequency limiting, avoiding the frequent frequency jitter or instability caused by fluctuations in a single indicator in traditional schemes. At the same time, in order to cope with the voltage steady-state overhead and control delay caused by frequency switching, this application introduces a dynamic hysteresis window to achieve smooth timing control of frequency limiting action, thereby maximizing power consumption benefits while ensuring system stability. (4) This application introduces the working state of peripherals such as processor frequency as a dynamic constraint factor for DDR frequency control, forming a cross-domain collaborative, real-time sensing, and low-overhead DDR dynamic frequency limiting control mechanism, taking into account real-time performance, stability and energy efficiency. It can automatically adjust the upper limit frequency of DDR according to the system operating state, effectively avoiding the oversupply problem caused by single indicator decision in traditional DDR control, and realizing dynamic power consumption optimization and stable performance output. It can significantly reduce the working frequency of DDR without affecting the frame rate and interaction smoothness, thereby effectively reducing system power consumption.

[0164] It should be noted that the above-described method embodiments, or the various possible implementations of the method embodiments, can be executed individually, or, provided there are no contradictions, they can be combined with each other. The specific implementation can be determined according to actual usage requirements, and this application embodiment does not impose any restrictions on this.

[0165] It should be noted that the frequency adjustment method provided in this application embodiment can be executed by a frequency adjustment device. This application embodiment uses a frequency adjustment device executing the frequency adjustment method as an example to illustrate the frequency adjustment device provided in this application embodiment.

[0166] Figure 6 A schematic diagram of a possible structure of the frequency adjustment device involved in an embodiment of this application is shown. For example... Figure 6 As shown, the frequency adjustment device 70 may include a determination module 71 and an adjustment module 72.

[0167] Among them, the determining module 71 is used to determine the upper limit of the DDR frequency of the electronic device based on the operating parameters of the processor of the electronic device;

[0168] The adjustment module 72 is used to lower the operating frequency of the DDR when the operating frequency of the DDR is higher than the upper frequency limit determined by the determination module 71. The adjusted operating frequency of the DDR is lower than or equal to the upper frequency limit.

[0169] In the frequency adjustment device provided in this application embodiment, since an upper limit value for the DDR frequency of the electronic device can be determined based on the operating parameters of the processor, and then the operating frequency of the DDR is controlled not to exceed the upper limit value, the operating frequency of the DDR is matched with the operating requirements of the processor, avoiding the DDR from always operating at a high frequency. Thus, the power consumption of the electronic device is reduced without affecting its performance.

[0170] In one possible implementation, the determining module 71 is further configured to, after determining the upper limit of the DDR frequency of the electronic device based on the operating parameters of the processor of the electronic device, determine the load change information of the processor based on the operating parameters of the processor; and adjust the upper limit of the frequency based on the load change information of the processor.

[0171] In one possible implementation, the adjustment module 72 is specifically used to: increase the upper limit of frequency when an increase in processor load is detected; or decrease the upper limit of frequency when a decrease in processor load is detected.

[0172] In one possible implementation, the processor's operating parameters include N processor operating parameters, where N is an integer greater than 1; the aforementioned determining module 71 is specifically used to determine the N frequency values ​​corresponding to the N processor operating parameters respectively; and to determine the maximum frequency value among the N frequency values ​​as the upper frequency limit.

[0173] In one possible implementation, the adjustment module 72 is specifically used to gradually reduce the operating frequency of the DDR according to a preset step value when the operating frequency of the DDR is higher than the upper frequency limit and the difference between the operating frequency of the DDR and the upper frequency limit is greater than a first preset threshold.

[0174] In one possible implementation, the aforementioned determining module 71 is specifically used to determine the upper limit of frequency based on the operating parameters of the processor of the electronic device when the electronic device is not under high load.

[0175] The frequency adjustment device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the device.

[0176] The frequency adjustment device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system used.

[0177] The frequency adjustment device provided in this application embodiment can realize the various processes implemented in the above method embodiment, and will not be described again here to avoid repetition.

[0178] Optionally, such as Figure 7 As shown, this application embodiment also provides an electronic device 90, including a processor 91 and a memory 92. The memory 92 stores a program or instructions that can run on the processor 91. When the program or instructions are executed by the processor 91, they implement the various steps of the above method embodiments and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0179] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0180] Figure 8 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0181] The electronic device 100 includes, but is not limited to, components such as: radio frequency unit 101, network module 102, audio output unit 103, input unit 104, sensor 105, display unit 106, user input unit 107, interface unit 108, memory 109, and processor 110.

[0182] Those skilled in the art will understand that the electronic device 100 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 110 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 8 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0183] The processor 110 is used to determine the upper limit of the DDR frequency of the electronic device based on the operating parameters of the processor of the electronic device; and when the operating frequency of the DDR is higher than the upper limit, the operating frequency of the DDR is reduced so that the adjusted operating frequency of the DDR is lower than or equal to the upper limit.

[0184] In the electronic device provided in this application embodiment, since an upper frequency limit for the DDR of the electronic device can be determined based on the operating parameters of the processor, and then the operating frequency of the DDR can be controlled to not exceed this upper frequency limit, the operating frequency of the DDR is matched with the operating requirements of the processor, avoiding the DDR from always operating at a high frequency. This reduces the power consumption of the electronic device without affecting its performance.

[0185] In some embodiments of this application, the processor 110 is further configured to, after determining the upper limit of the DDR frequency of the electronic device based on the operating parameters of the processor of the electronic device, determine the load change information of the processor based on the operating parameters of the processor; and adjust the upper limit of the frequency based on the load change information of the processor.

[0186] In some embodiments of this application, the processor 110 described above is specifically used for:

[0187] If an increase in processor load is detected, increase the upper frequency limit; or,

[0188] If a decrease in processor load is detected, lower the upper frequency limit.

[0189] In some embodiments of this application, the processor's operating parameters include N processor operating parameters, where N is an integer greater than 1; the processor 110 is specifically used to determine N frequency values ​​corresponding to the operating parameters of the N processors respectively; and to determine the maximum frequency value among the N frequency values ​​as the upper frequency limit value.

[0190] In some embodiments of this application, the processor 110 is specifically used to gradually reduce the operating frequency of the DDR according to a preset step value when the operating frequency of the DDR is higher than the upper frequency limit and the difference between the operating frequency of the DDR and the upper frequency limit is greater than a first preset threshold.

[0191] In some embodiments of this application, the processor 110 is specifically used to determine the upper limit of frequency based on the operating parameters of the processor of the electronic device when the electronic device is not under high load.

[0192] The electronic device provided in this application embodiment can implement the various processes implemented in the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0193] For details on the beneficial effects of the various implementation methods in this embodiment, please refer to the beneficial effects of the corresponding implementation methods in the above method embodiments. To avoid repetition, these will not be repeated here.

[0194] It should be understood that, in this embodiment, the input unit 104 may include a graphics processing unit (GPU) 1041 and a microphone 1042. The GPU 1041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 106 may include a display panel 1061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 107 includes at least one of a touch panel 1071 and other input devices 1072. The touch panel 1071 is also called a touch screen. The touch panel 1071 may include a touch detection device and a touch controller. Other input devices 1072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.

[0195] The memory 109 can be used to store software programs and various data. The memory 109 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 109 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 109 in the embodiments of this application includes, but is not limited to, these and any other suitable types of memory.

[0196] Processor 110 may include one or more processing units; optionally, processor 110 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 110.

[0197] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0198] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0199] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0200] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0201] This application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the various processes of the above method embodiments and achieve the same technical effects. To avoid repetition, it will not be described again here.

[0202] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0203] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0204] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A frequency adjustment method, characterized in that, Performed by an electronic device, the method includes: Based on the operating parameters of the processor of the electronic device, the upper frequency limit of the Double Data Rate Synchronous Dynamic Random Access Memory (DDR) of the electronic device is determined. If the operating frequency of the DDR is higher than the upper frequency limit, the operating frequency of the DDR is lowered, and the adjusted operating frequency of the DDR is lower than or equal to the upper frequency limit.

2. The method according to claim 1, characterized in that, After determining the upper limit of the DDR frequency of the electronic device based on the operating parameters of the processor of the electronic device, the method further includes: Based on the processor's operating parameters, determine the processor's load change information; The upper limit of frequency is adjusted based on the processor's load change information.

3. The method according to claim 2, characterized in that, Adjusting the upper frequency limit based on the processor's load change information includes: If an increase in processor load is detected, the upper frequency limit is increased; or, If a decrease in the processor's load is detected, the upper limit of the frequency is lowered.

4. The method according to claim 1, characterized in that, The processor's operating parameters include N processor operating parameters, where N is an integer greater than 1; determining the upper frequency limit of the electronic device's DDR based on the processor's operating parameters includes: Determine the N frequency values ​​corresponding to the operating parameters of the N processors; The maximum frequency value among the N frequency values ​​is determined as the upper frequency limit.

5. The method according to claim 1, characterized in that, Determining the upper limit of the DDR frequency of the electronic device based on the operating parameters of the processor of the electronic device includes: When the electronic device is not under high load, the upper limit of the DDR frequency of the electronic device is determined based on the operating parameters of the processor of the electronic device.

6. A frequency adjustment device, characterized in that, Applied to electronic devices, the frequency adjustment device includes: a determining module and an adjusting module; The determining module is used to determine the upper limit of the DDR frequency of the electronic device based on the operating parameters of the processor of the electronic device; The adjustment module is used to lower the operating frequency of the DDR when the operating frequency of the DDR is higher than the upper frequency limit determined by the determining module, such that the adjusted operating frequency of the DDR is lower than or equal to the upper frequency limit.

7. The apparatus according to claim 6, characterized in that, The determining module is further configured to, after determining the upper limit of the DDR frequency of the electronic device based on the operating parameters of the processor of the electronic device, determine the load change information of the processor based on the operating parameters of the processor; The adjustment module is further configured to adjust the upper frequency limit based on the processor load change information determined by the determining module.

8. The apparatus according to claim 7, characterized in that, The adjustment module is specifically used for: If an increase in processor load is detected, the upper frequency limit is increased; or, If a decrease in the processor's load is detected, the upper limit of the frequency is lowered.

9. The apparatus according to claim 6, characterized in that, The processor's operating parameters include N processor operating parameters, where N is an integer greater than 1; The determining module is specifically used to determine the N frequency values ​​corresponding to the operating parameters of the N processors; and to determine the maximum frequency value among the N frequency values ​​as the upper frequency limit.

10. The apparatus according to claim 6, characterized in that, The determining module is specifically used to determine the upper limit of the DDR frequency of the electronic device based on the operating parameters of the processor of the electronic device when the electronic device is not under high load.

11. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that can run on the processor, the program or instructions being executed by the processor to implement the steps of the frequency adjustment method as described in any one of claims 1 to 5.

12. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the frequency adjustment method as described in any one of claims 1 to 5.

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