Enhanced GaN HEMT device based on composite gate and gate terminal extension and preparation method thereof

Abstract

The invention discloses an enhanced GaN HEMT (High Electron Mobility Transistor) device based on a composite gate and gate terminal expansion and a preparation method thereof, the p-InGaN and p-GaN / p + GaN layer heterojunction polarization effect in the composite gate structure of the enhanced GaN HEMT device can generate two-dimensional hole gas on an interface, and more holes are injected into a channel to be compounded with electrons when high leakage voltage is turned off; the electron concentration of the lower channel layer near the gate is reduced, so that electron capture of the buffer layer on the channel layer is inhibited, the dynamic performance of the device is improved, the reliability of the device is enhanced, the gate terminal expansion structure is utilized to expand the composite gate structure, the off-state electric field distribution of the device is optimized, and the reliability of the device is improved. The electric field peak value of the edge of the gate field plate can be redistributed and weakened, the current collapse effect is effectively restrained, and the preparation method of the device is simple in process and low in cost. According to the scheme, the gate stability and the dynamic performance of the device can be improved, and a reliable device basis is provided for a GaN power system with higher frequency, higher efficiency and higher power density.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor devices, and particularly relates to an enhanced GaN HEMT device based on a composite gate and gate terminal extension and a preparation method thereof. BACKGROUND

[0002] Gallium nitride (GaN) based high electron mobility transistors (HEMTs) have become the core devices in high-power and high-frequency application fields due to their excellent characteristics of wide band gap, high breakdown field strength and high electron mobility. Conventional GaN HEMT devices are depletion mode, and have a high concentration of two-dimensional electron gas (2DEG), which requires the use of a negative turn-on voltage. This not only poses a risk of circuit misactivation, but also greatly increases the power consumption of the circuit. In order to provide failure protection for power switching systems, the device is required to be enhancement mode. Therefore, an enhancement mode GaN HEMT device is urgently needed in the industry.

[0003] At present, the implementation methods of the enhancement mode GaN HEMT device mainly include P-type gate structure, recessed gate structure, and fluorine ion implantation structure. Among them, the P-type gate structure is considered to be the leading structure for commercialization. However, the p-GaN HEMT also has its own defects, such as dynamic on-resistance (R ON ) attenuation and threshold voltage (V TH ) instability at high frequencies, which greatly affects the efficiency and performance of the device. SUMMARY

[0004] In view of the above problems, the purpose of the present application is to provide an enhanced GaN HEMT device based on a composite gate and gate terminal extension and a preparation method thereof, which can effectively suppress dynamic R ON attenuation and V TH instability at the same time, improve gate stability and dynamic performance of the device, and provide a reliable device basis for GaN power systems with higher frequency, higher efficiency and higher power density.

[0005] The specific technical scheme to achieve the purpose of the present application is as follows:

[0006] An enhanced GaN HEMT device based on a composite gate and gate terminal extension, comprising:

[0007] a substrate;

[0008] a nucleation layer, which is arranged on the substrate;

[0009] a buffer layer, which is arranged on the nucleation layer;

[0010] a channel layer, which is arranged on the buffer layer;

[0011] a barrier layer, which is arranged on the channel layer;

[0012] A composite gate structure, wherein the composite gate structure is disposed on the barrier layer;

[0013] A gate terminal extension structure, wherein the gate terminal extension structure is a structure generated by extending a composite gate structure;

[0014] A gate, wherein the gate is disposed on the composite gate structure;

[0015] The source and drain are symmetrically arranged on the channel layer and respectively located on both sides of the barrier layer and the composite gate structure.

[0016] Furthermore, the composite gate structure sequentially includes a p-GaN layer, a p-InGaN layer, and a p-GaN layer. + -GaN layer;

[0017] The p-GaN layer is disposed on the barrier layer and is used to form a gate control with the barrier layer;

[0018] The p-InGaN layer is disposed on the p-GaN layer and is used to generate a two-dimensional hole gas concentration to increase the hole concentration and reduce the gate resistance.

[0019] The p + - A GaN layer is disposed above the p-InGaN layer and below the gate to realize an ohmic gate contact;

[0020] The thickness of the p-GaN layer is set to 5-20 nm, and the thickness of the p-InGaN layer is set to 50-70 nm. + - The thickness of the GaN layer is set to 5-20 nm;

[0021] In the p-InGaN layer, the In content is 5%-20%, and the Ga content is 80%-95%, with the total content of both being 100%.

[0022] Furthermore, the gate termination extension structure is a p-GaN layer termination extension structure formed by the p-GaN layer of the composite gate structure extending laterally towards the drain side, and is an integral structure with the p-GaN layer of the composite gate structure, used to modulate the electric field distribution at the gate edge and improve the breakdown voltage and reliability of the device.

[0023] The gate termination extension structure is located on the barrier layer, with a thickness of 0-20 nm and an extension length of 1000-5000 nm;

[0024] The specific shape of the gate terminal extension structure is a long strip with uniform thickness, a stepped structure with progressively decreasing thickness, or a triangle with linearly decreasing thickness.

[0025] Furthermore, the substrate material includes sapphire, silicon, and silicon carbide;

[0026] The nucleation layer is made of AlN and has a thickness of 100-250 nm; the buffer layer is made of GaN and has a thickness of 1000-2000 nm; the channel layer is made of GaN and has a thickness of 100-300 nm; the barrier layer is made of AlGaN and has a thickness of 10-20 nm, wherein the Al content is 10%-30%, the Ga content is 70%-90%, and the total content of both is 100%.

[0027] Furthermore, the p-GaN layer and p-InGaN layer are doped with Mg at a concentration of 3 × 10⁻⁶. 17 -3×10 20 cm -3 .

[0028] Furthermore, the gate length is 2000-6000 nm, the distance between the gate and the source is 2000-4000 nm, and the distance between the gate and the drain is 10000-30000 nm.

[0029] This solution also provides a method for fabricating the above-mentioned enhanced GaN HEMT device based on composite gate and gate termination extension, including the following steps:

[0030] Step 1: Epitaxially grow the core layer, buffer layer, channel layer, barrier layer and composite gate structure sequentially on the substrate to complete the deposition of the epitaxial layer;

[0031] Step 2: The p-InGaN layer and p-type gate structure of the composite gate structure... + - The GaN layer undergoes a first selective etching process to form a stepped structure;

[0032] Step 3: Perform a second selective etching on the p-GaN layer of the composite gate structure to form a gate termination extension structure connected to the p-GaN layer;

[0033] Step 4: Epitaxially deposit and grow a passivation layer on the device surface, etch the passivation layer to form source and drain windows, perform metal evaporation using electron beam evaporation, and obtain the source and drain electrodes after stripping. Perform rapid thermal annealing in N2 atmosphere to form ohmic contacts.

[0034] Step 5: Multi-energy fluorine ion implantation is used to form a fluorine ion implantation region through planar isolation. Then, the passivation layer is etched to form a gate window. Electron beam evaporation is used to form a metal evaporation to form a gate contact. Finally, rapid thermal annealing is performed in an O2 atmosphere to form a Ti / Au stack as a probe pad.

[0035] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0036] (1) In the composite gate structure of the present invention, p-InGaN and p-GaN / p + The heterojunction polarization of the GaN layer generates two-dimensional holes at the interface, and injects more holes and electrons into the channel during high drain voltage turn-off, which reduces the electron concentration of the channel layer below the gate, thereby suppressing the electron trapping of the channel layer by the buffer layer, improving the dynamic performance of the device, and enhancing the reliability of the device.

[0037] (2) The present invention optimizes the off-state electric field distribution of the device by introducing a termination extension structure near the drain side of the gate region. This method can redistribute and weaken the electric field peak at the edge of the gate field plate, effectively suppressing the current collapse effect.

[0038] (3) The preparation method of the present invention has high process compatibility, low material cost, and relatively simple manufacturing steps.

[0039] The present invention will be further described below with reference to specific embodiments. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the enhanced GaN HEMT device structure based on composite gate and gate termination extension according to the present invention.

[0041] Figure 2 The dynamic R of the device provided in the embodiments of the present invention and the device with different structures ON Degradation comparison chart.

[0042] Figure 3 This is a comparison chart of the threshold voltage stability of the device provided in the embodiments of the present invention and devices with different structures under dynamic gate / drain voltage stress.

[0043] Figure 4 This is a diagram showing the effect of step 1 in an embodiment of the present invention.

[0044] Figure 5 This is a diagram showing the effect of step 2 in an embodiment of the present invention.

[0045] Figure 6 This is a diagram showing the effect of step 3 in an embodiment of the present invention.

[0046] Figure 7 This is a diagram showing the effect of step 4 in an embodiment of the present invention.

[0047] Figure 8 This is a diagram showing the effect of step 5 in an embodiment of the present invention. Detailed Implementation

[0048] Example

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0051] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0052] An enhanced GaN HEMT device based on a composite gate and gate termination extension includes:

[0053] The substrate is made of materials including sapphire, silicon, and silicon carbide.

[0054] A nucleation layer is disposed on the substrate;

[0055] A buffer layer is disposed on the nucleation layer;

[0056] A channel layer is disposed on the buffer layer;

[0057] A barrier layer, wherein the barrier layer is disposed on the channel layer;

[0058] In this embodiment, the nucleation layer is made of AlN with a thickness of 100-250 nm; the buffer layer is made of GaN with a thickness of 1000-2000 nm; the channel layer is made of GaN with a thickness of 100-300 nm; and the barrier layer is made of AlGaN with a thickness of 10-20 nm, wherein the Al content is 10%-30%, the Ga content is 70%-90%, and the total content of both is 100%.

[0059] The p-GaN layer is disposed on the barrier layer and is used to form a gate control with the barrier layer;

[0060] The p-InGaN layer is disposed on the p-GaN layer and is used to generate a two-dimensional hole gas concentration to increase the hole concentration and reduce the gate resistance.

[0061] The p + - A GaN layer is disposed above the p-InGaN layer and below the gate to realize an ohmic gate contact;

[0062] The thickness of the p-GaN layer is set to 5-20 nm, and the thickness of the p-InGaN layer is set to 50-70 nm. + - The thickness of the GaN layer is set to 5-20 nm;

[0063] In the p-InGaN layer, the In content is 5%-20%, and the Ga content is 80%-95%, with the total content of both being 100%.

[0064] The p-GaN and p-InGaN layers are doped with Mg at a concentration of 3 × 10⁻⁶. 17 -3×10 20 cm -3 .

[0065] In this composite gate structure, p-InGaN and p-GaN / p + The heterojunction polarization of the GaN layer generates two-dimensional holes at the interface. During high drain voltage turn-off, more holes are injected into the channel for recombination with electrons, reducing the electron concentration in the lower channel layer near the gate. This suppresses electron trapping in the channel layer by the buffer layer, thus helping to suppress dynamic R ON Attenuation and V TH Instability improves gate stability and device dynamic performance.

[0066] The gate termination extension structure is a p-GaN termination extension structure formed by the lateral extension of the p-GaN layer of the composite gate structure towards the drain side, and is integral with the p-GaN layer of the composite gate structure. The thickness of the gate termination extension structure is 5-20 nm, and the extension length is 1000-5000 nm. The specific shape of the gate termination extension structure is a uniformly thick elongated strip, a stepped structure with gradually decreasing thickness, or a linearly tapering triangle. Extending the p-GaN layer of the composite gate is beneficial for modulating the electric field distribution at the gate edge, improving the breakdown voltage and reliability of the device.

[0067] A gate electrode is disposed on the composite gate structure; a source electrode and a drain electrode are symmetrically disposed on the channel layer and respectively disposed on both sides of the barrier layer and the composite gate structure.

[0068] The gate length is 2000-6000 nm, the distance between the gate and the source is 2000-4000 nm, and the distance between the gate and the drain is 10000-30000 nm.

[0069] To verify the technical effectiveness of the proposed structure, simulation verification was performed using Sentaurus TCAD. Figure 2 The dynamic on-resistance R of the device provided in Example 1 and devices with different structures is given. ON With the drain voltage V in the off state DS-OFF Comparison of degradation patterns. The CONV structure device is an enhancement-mode GaN HEMT device without either a composite gate structure or a gate termination extension structure; the GTE device is an enhancement-mode GaN HEMT device with only a gate termination extension structure; and the CG device is an enhancement-mode GaN HEMT device with only a composite gate structure. Experiments demonstrate that the device provided in Example 1 significantly suppresses dynamic R... ON The increase in stress level is best observed in both low-stress and high-stress regions, demonstrating stronger resistance to dynamic trapping degradation.

[0070] Figure 3 The dynamic gate voltage stress V of devices with different structures is given. GSQ / Drain voltage stress V DSQ The comparison of threshold voltage stability is shown in the figure. The results indicate that the introduction of the composite gate structure significantly suppresses the dynamic threshold voltage (ΔV). TH Meanwhile, the elongated gate p-GaN layer termination extension structure further improves the ΔV under dynamic drain stress by optimizing the gate-drain electric field distribution. TH Performance.

[0071] This solution also provides a method for fabricating the above-mentioned enhanced GaN HEMT device based on composite gate and gate termination extension, including the following steps:

[0072] Step 1: Epitaxially grow a core layer, buffer layer, channel layer, barrier layer, and composite gate structure sequentially on the substrate to complete the epitaxial layer deposition, such as... Figure 4 As shown;

[0073] Step 2: The p-InGaN layer and p-type gate structure of the composite gate structure... + The GaN layer undergoes a first selective etching process to form a stepped structure, such as... Figure 5 As shown;

[0074] Step 3: Perform a second selective etching on the p-GaN layer of the composite gate structure to form a gate termination extension structure connected to the p-GaN layer, such as... Figure 6 As shown;

[0075] Step 4: A 50 nm SiO2 passivation layer is grown on the device surface using plasma-enhanced chemical vapor deposition (PECVD), followed by metal evaporation using electron beam evaporation. After stripping, the source and drain electrodes are obtained, and then thermally annealed at 810 °C in a N2 atmosphere for 30 seconds to form ohmic contacts. Figure 7 As shown;

[0076] The annealing temperature is 800-850℃, and the annealing time is 30-35s;

[0077] Step 5: Planar isolation is achieved using multi-energy fluorine ion implantation to form the fluorine ion implantation region. A passivation layer is then etched to form the gate window. Metal deposition is performed using electron beam evaporation to form the gate contact. Finally, a Ti / Au stack is formed as the probe pad through thermal annealing at 550°C in an O2 atmosphere for 4 minutes, completing the fabrication process. Figure 8 As shown;

[0078] The annealing temperature is 500-600 ℃, and the annealing time is 200-300 s.

[0079] In addition, the epitaxial growth method in steps 1 and 4 is one of MOCVD, HVPE, PECVD and MBE;

[0080] The passivation layer is made of SiO2 or Si3N4, the source electrode is made of one or more of Ti, Al, Ni, Au, TiN and Pt, and the drain electrode is made of one or more of Ti, Al, Ni, Au, TiN and Pt.

[0081] The preparation method of this invention has high process compatibility, uses low-cost materials, and has relatively simple manufacturing steps.

[0082] The embodiments described above are merely one implementation method of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An enhanced GaN HEMT device based on a composite gate and gate termination extension, characterized in that, include: Substrate; A nucleation layer is disposed on the substrate; A buffer layer is disposed on the nucleation layer; A channel layer, wherein the channel layer is disposed on the buffer layer; A barrier layer, wherein the barrier layer is disposed on the channel layer; A composite gate structure, wherein the composite gate structure is disposed on the barrier layer; A gate terminal extension structure, wherein the gate terminal extension structure is a structure generated by extending a composite gate structure; A gate, wherein the gate is disposed on the composite gate structure; The source and drain are symmetrically arranged on the channel layer and respectively located on both sides of the barrier layer and the composite gate structure.

2. The enhanced GaN HEMT device based on composite gate and gate termination extension according to claim 1, characterized in that, The composite gate structure sequentially includes a p-GaN layer, a p-InGaN layer, and a p-GaN layer. + -GaN layer; The p-GaN layer is disposed on the barrier layer and is used to form a gate control with the barrier layer; The p-InGaN layer is disposed on the p-GaN layer and is used to generate a two-dimensional hole gas concentration to increase the hole concentration and reduce the gate resistance. The p + - A GaN layer is disposed above the p-InGaN layer and below the gate to realize an ohmic gate contact; The thickness of the p-GaN layer is set to 5-20 nm, and the thickness of the p-InGaN layer is set to 50-70 nm. + - The thickness of the GaN layer is set to 5-20 nm; In the p-InGaN layer, the In content is 5%-20%, and the Ga content is 80%-95%, with the total content of both being 100%.

3. The enhanced GaN HEMT device based on composite gate and gate termination extension according to claim 2, characterized in that, The gate termination extension structure is a p-GaN termination extension structure formed by the p-GaN layer of the composite gate structure extending laterally towards the drain side, and is an integral structure with the p-GaN layer of the composite gate structure. It is used to modulate the electric field distribution at the gate edge and improve the breakdown voltage and reliability of the device. The gate termination extension structure is located on the barrier layer, with a thickness of 5-20 nm and an extension length of 1000-5000 nm; The specific shape of the gate terminal extension structure is a long strip with uniform thickness, a stepped structure with progressively decreasing thickness, or a triangle with linearly decreasing thickness.

4. The enhanced GaN HEMT device based on composite gate and gate termination extension according to claim 1, characterized in that, The substrate material includes sapphire, silicon, and silicon carbide; The nucleation layer is made of AlN and has a thickness of 100-250 nm; the buffer layer is made of GaN and has a thickness of 1000-2000 nm; the channel layer is made of GaN and has a thickness of 100-300 nm; the barrier layer is made of AlGaN and has a thickness of 10-20 nm, wherein the Al content is 10%-30%, the Ga content is 70%-90%, and the total content of both is 100%.

5. The enhanced GaN HEMT device based on composite gate and gate termination extension according to claim 3, characterized in that, The p-GaN and p-InGaN layers are doped with Mg at a concentration of 3 × 10⁻⁶. 17 -3×10 20 cm -3 .

6. The enhanced GaN HEMT device based on composite gate and gate termination extension according to claim 1, characterized in that, The gate length is 2000-6000 nm, the distance between the gate and the source is 2000-4000 nm, and the distance between the gate and the drain is 10000-30000 nm.

7. The method for fabricating an enhancement-mode GaN HEMT device based on a composite gate and gate termination extension according to any one of claims 1-6, characterized in that, Includes the following steps: Step 1: Epitaxially grow the core layer, buffer layer, channel layer, barrier layer and composite gate structure sequentially on the substrate to complete the epitaxial layer deposition; Step 2: The p-InGaN layer and p-type gate structure of the composite gate structure... + - The GaN layer undergoes a first selective etching process to form a stepped structure; Step 3: Perform a second selective etching on the p-GaN layer of the composite gate structure to form a gate termination extension structure connected to the p-GaN layer; Step 4: Epitaxially deposit and grow a passivation layer on the device surface, etch the passivation layer to form source and drain windows, perform metal evaporation using electron beam evaporation, and obtain the source and drain electrodes after stripping. Perform rapid thermal annealing in N2 atmosphere to form ohmic contacts. Step 5: Multi-energy fluorine ion implantation is used to form a fluorine ion implantation region through planar isolation. Then, the passivation layer is etched to form a gate window. Electron beam evaporation is used to form a metal evaporation to form a gate contact. Finally, rapid thermal annealing is performed in an O2 atmosphere to form a Ti / Au stack as a probe pad.

8. The method for fabricating an enhancement-mode GaN HEMT device based on a composite gate and gate termination extension according to claim 7, characterized in that, The epitaxial growth method in steps 1 and 4 is one of MOCVD, HVPE, PECVD and MBE.

9. The fabrication method of the enhancement-mode GaN HEMT device based on composite gate and gate termination extension according to claim 7, characterized in that, The passivation layer is made of SiO2 or Si3N4, the source electrode is made of one or more of Ti, Al, Ni, Au, TiN and Pt, and the drain electrode is made of one or more of Ti, Al, Ni, Au, TiN and Pt.

10. The method for fabricating an enhancement-mode GaN HEMT device based on a composite gate and gate termination extension according to claim 7, characterized in that, In step 4, the annealing temperature is 800-850℃ and the annealing time is 30-35s; in step 5, the annealing temperature is 500-600℃ and the annealing time is 200-300s.

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