Composite seed layer and copper gate heterojunction battery

Abstract

The invention provides a composite seed layer and a copper gate heterojunction battery, and relates to the technical field of battery manufacturing. The metal oxide intermediate layer is introduced into the traditional metal seed layer, so that the problem of insufficient adhesive force between the pure metal seed layer and the transparent conductive oxide film in the prior art is effectively solved. The metal oxide intermediate layer can form a more stable interface with the transparent conductive oxide film, and the overall adhesive force of the composite seed layer is remarkably enhanced, so that the stripping or layering phenomenon possibly occurring in the subsequent copper electroplating process is avoided. Besides, the structure also inhibits the erosion of a process solution in an electroplating or cleaning process, thereby improving the conversion efficiency and long-term reliability of the copper gate heterojunction cell, and overcoming the problems of unstable cell performance and low yield caused by performance defects of the seed layer in the prior art.

Description

Technical Field

[0001] This application relates to the field of battery manufacturing technology, and more specifically, to a composite seed layer and copper grid heterojunction battery. Background Technology

[0002] Heterojunction solar cells (HJTs) have become one of the important development directions of current high-efficiency photovoltaic technology due to their high conversion efficiency and excellent temperature characteristics. In the manufacturing of traditional heterojunction cells, the metal grid lines are usually formed using a screen-printed silver paste process. However, silver, as a precious metal, is expensive, which restricts further cost reduction of the cells. To address this, the industry is actively developing "copper grid heterojunction cells" technology, which uses copper to replace silver. This technology involves fabricating grid lines using copper interconnect processes, aiming to significantly reduce material costs while maintaining high performance.

[0003] In the fabrication process of copper-grid heterojunction solar cells, a seed layer is typically deposited on a transparent conductive oxide (TCO) film. This seed layer serves as the conductive substrate and adhesion base for subsequent copper electroplating. Currently, existing technologies commonly employ methods such as magnetron sputtering or thermal evaporation to deposit pure copper or a copper-nickel alloy onto the TCO layer on the silicon wafer surface to form this seed layer.

[0004] However, the applicant discovered that the aforementioned prior art has at least the following shortcomings that urgently need improvement: the pure copper or copper-nickel alloy seed layers prepared by existing methods often have poor film density, and structural defects such as micropores are easily formed inside the film. These defects not only weaken the conductivity uniformity of the seed layer itself, but also become weak points in subsequent processes such as patterning, electroplating, and post-cleaning, leading to process solution penetration or localized stress concentration, thereby damaging the underlying battery structure and ultimately causing battery performance degradation, limiting further improvements in the efficiency and reliability of copper grid heterojunction batteries.

[0005] Therefore, in view of the problems of insufficient compactness and many defects in the existing copper grid heterojunction solar cell seed layer, there is an urgent need for a new seed layer structure scheme.

[0006] There is currently no effective technical solution to the above problems. Summary of the Invention

[0007] The purpose of this application is to provide a composite seed layer and copper grid heterojunction solar cell, which effectively solves the problems of insufficient interfacial adhesion between the pure metal seed layer and the transparent conductive oxide film, suppression of corrosion by process solutions in electroplating or cleaning processes, and stress mismatch in the prior art.

[0008] This application provides a composite seed layer for use in copper grid heterojunction solar cells, comprising a seed bottom layer, a middle layer and a seed top layer stacked sequentially. The bottom layer of the seed is set on the transparent conductive oxide film of the copper grid heterojunction cell, and the top layer of the seed is connected to the electrode of the copper grid heterojunction cell. The bottom and top layers of the seed are made of metal, while the middle layer is made of metal oxide.

[0009] By introducing a metal oxide intermediate layer, the adhesion between the seed layer and the transparent conductive oxide film is effectively improved, while the corrosion of the process solution during electroplating or cleaning is suppressed, thereby improving the overall performance and stability of the copper grid heterojunction solar cell.

[0010] Optionally, the metal oxide material corresponding to the intermediate layer includes one of indium tin oxide, aluminum-doped zinc oxide, and tin dioxide.

[0011] By selecting specific metal oxide materials, the physicochemical properties of the intermediate layer can be further optimized, such as improving its conductivity or enhancing its interfacial bonding with adjacent layers, thereby improving the overall performance of the composite seed layer.

[0012] Optionally, the thickness of the intermediate layer is 1nm-15nm.

[0013] This technical solution precisely controls the thickness of the intermediate layer within a specific range, ensuring good adhesion while minimizing the impact on overall conductivity and avoiding stress problems caused by excessive thickness.

[0014] Optionally, the metal materials corresponding to the seed bottom layer and the seed top layer include pure copper or a copper-nickel alloy.

[0015] Optionally, the thickness of the seed layer is 40nm-60nm.

[0016] Optionally, the thickness of the top layer of the seed is 30nm-50nm.

[0017] In a second aspect, this application provides a copper grid heterojunction solar cell, comprising: an N-type silicon wafer, wherein an intrinsic amorphous silicon layer, a doped amorphous silicon layer, a transparent conductive oxide film and a copper electrode are sequentially stacked on the light-receiving side of the N-type silicon wafer in a direction away from the N-type silicon wafer, and a composite seed layer as described above is disposed between the transparent conductive oxide film and the copper electrode. An intrinsic amorphous silicon layer, a doped amorphous silicon layer, a transparent conductive oxide film, and a copper electrode are sequentially stacked on the back side of an N-type silicon wafer in a direction away from the N-type silicon wafer. A composite seed layer, as described above, is disposed between the transparent conductive oxide film and the copper electrode.

[0018] By integrating the aforementioned composite seed layer into a copper grid heterojunction solar cell, the shortcomings of traditional seed layers in terms of adhesion, conductivity, and cost are effectively solved, thereby significantly improving the cell's conversion efficiency, reliability, and long-term stability.

[0019] Optionally, the N-type silicon wafer has a thickness ranging from 50µm to 150µm, a minority carrier lifetime of ≥800µs, and a resistivity ranging from 0.3Ω·cm to 2.1Ω·cm.

[0020] This technical solution optimizes the physical parameters of N-type silicon wafers, maximizing the photoelectric conversion efficiency of the battery and reducing carrier recombination losses, thereby improving the overall performance of the battery.

[0021] Optionally, the thickness of the intrinsic amorphous silicon layer on the light-receiving side ranges from 3 nm to 6 nm, and the thickness of the doped amorphous silicon layer ranges from 4 nm to 7 nm. The thickness of the intrinsic amorphous silicon layer on the backlight side ranges from 4nm to 7nm, and the thickness of the doped amorphous silicon layer ranges from 4nm to 10nm.

[0022] Optionally, the transparent conductive oxide film disposed on the light-receiving side and the backlight side is one of indium tin oxide, indium tungsten oxide, aluminum-doped zinc oxide, and doped tin dioxide, or is a superimposed structure formed by any two of the following materials: indium tin oxide, indium tungsten oxide, aluminum-doped zinc oxide, and doped tin dioxide; wherein the weight ratio of indium oxide to tin oxide in indium tin oxide ranges from 99:1 to 90:10.

[0023] As can be seen from the above, the composite seed layer and copper grid heterojunction solar cell provided in this application effectively solve the problem of insufficient adhesion between the pure metal seed layer and the transparent conductive oxide film in the prior art by introducing a metal oxide intermediate layer into the traditional metal seed layer. The metal oxide intermediate layer can form a more stable interface with the transparent conductive oxide film, significantly enhancing the overall adhesion of the composite seed layer, thereby avoiding peeling or delamination that may occur during subsequent copper electroplating. In addition, this structure also inhibits the erosion of the process solution during electroplating or cleaning, thereby improving the conversion efficiency and long-term reliability of the copper grid heterojunction solar cell, overcoming the problems of unstable cell performance and low yield caused by seed layer performance defects in the prior art.

[0024] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0025] Figure 1 This is a schematic diagram showing the position of a composite seed layer and a copper grid heterojunction cell provided in an embodiment of this application.

[0026] Figure 2An experimental data table for a copper grid heterojunction solar cell provided in the embodiments of this application.

[0027] Labeling explanation: 101, Seed bottom layer; 102, Intermediate layer; 103, Seed top layer; 200, N-type silicon wafer; 201, Intrinsic amorphous silicon layer; 202, Doped amorphous silicon layer; 203, Transparent conductive oxide film; 204, Copper electrode. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0029] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] Please refer to Figure 1 This application provides a composite seed layer and a copper grid heterojunction solar cell, which effectively solves the problems of insufficient interfacial adhesion between the pure metal seed layer and the transparent conductive oxide film, suppression of corrosion by process solutions in electroplating or cleaning processes, and stress mismatch in the prior art.

[0031] This application provides a composite seed layer for use in copper grid heterojunction solar cells, comprising a seed bottom layer 101, a middle layer 102 and a seed top layer 103 stacked sequentially. The seed bottom layer 101 is disposed on the transparent conductive oxide film 203 of the copper grid heterojunction cell, and the seed top layer 103 is connected to the electrode of the copper grid heterojunction cell. The bottom layer 101 and the top layer 103 of the seed are both made of metal, while the middle layer 102 is made of metal oxide.

[0032] The composite seed layer proposed in this application is a key component in copper-grid heterojunction solar cells. The "seed layer" refers to a thin film pre-deposited on a non-conductive or low-conductivity substrate during the copper electroplating process. Its main function is to provide a conductive path and serve as the nucleus base for subsequent metal electroplating, ensuring uniform and robust deposition of the electroplated layer. In the copper-grid heterojunction solar cell, this composite seed layer is disposed on the transparent conductive oxide film 203 and connected to the electrodes of the copper-grid heterojunction solar cell, providing a foundation for the subsequent formation of the copper electrode 204.

[0033] Specifically, the composite seed layer comprises a seed bottom layer 101, an intermediate layer 102, and a seed top layer 103 stacked sequentially. The seed bottom layer 101 is disposed on the transparent conductive oxide film 203 of the copper grid heterojunction solar cell, and its main function is to form a good interfacial contact with the transparent conductive oxide film 203 and provide a basis for the deposition of the intermediate layer 102. The seed top layer 103 connects to the electrodes of the copper grid heterojunction solar cell, and its function is to provide good conductive connection and adhesion interface for the electrodes.

[0034] As one implementation method, the materials for the seed bottom layer 101 and the seed top layer 103 can be selected from metallic materials with good conductivity and adhesion. For example, pure copper can be used as the material for the seed bottom layer 101 and the seed top layer 103, as pure copper has excellent conductivity and can effectively reduce resistance loss. Alternatively, a copper-nickel alloy can also be used as the material for the seed bottom layer 101 and the seed top layer 103, as the copper-nickel alloy maintains good conductivity while providing higher mechanical strength and better corrosion resistance.

[0035] During the deposition process, traditional pure copper or copper-nickel alloy seed layers are prone to stress concentration at the interface due to differences in material properties, leading to film peeling or cracking and affecting the long-term reliability of the battery. Furthermore, they are susceptible to corrosion from process solutions during electroplating or post-cleaning processes.

[0036] This application achieves several technical advantages by setting a metal oxide intermediate layer 102 between the seed bottom layer 101 and the seed top layer 103. First, the metal oxide intermediate layer 102 can effectively alleviate the stress between the seed bottom layer 101 and the transparent conductive oxide film 203, improving the adhesion and stability of the interface. Second, the metal oxide can help form a dense composite seed layer, effectively inhibiting the erosion of process solutions during electroplating or cleaning processes, thereby maintaining the stability of the battery's electrical performance.

[0037] In some embodiments, the metal oxide material corresponding to the intermediate layer 102 includes one of indium tin oxide, aluminum-doped zinc oxide, and tin dioxide.

[0038] In some implementations, the thickness of the intermediate layer 102 is 1 nm to 15 nm.

[0039] The solution presented in this application effectively solves the aforementioned problems by limiting the thickness of the intermediate layer 102 to the range of 1nm-15nm. When the thickness of the intermediate layer 102 is not less than 1nm, the metal oxide material can form a sufficiently dense thin film structure, thereby effectively preventing the chemical solution from eroding the underlying transparent conductive oxide film 203 and avoiding negative impacts on battery performance. Simultaneously, when the thickness of the intermediate layer 102 is not greater than 15nm, it ensures that the resistivity of the intermediate layer 102 itself is not excessively high, thus avoiding a significant increase in the overall series resistance of the composite seed layer and ensuring effective charge carrier transport. By precisely controlling the thickness of the intermediate layer 102, an optimal balance between barrier performance and electrical performance is achieved, thereby significantly improving the overall performance and reliability of the copper grid heterojunction solar cell.

[0040] In some embodiments, the metal materials corresponding to the seed bottom layer 101 and the seed top layer 103 include pure copper or a copper-nickel alloy.

[0041] In some implementations, the thickness of the seed layer 101 is 40nm-60nm.

[0042] By limiting the thickness of the seed substrate 101 to 40nm-60nm, a balance between performance and cost can be achieved while ensuring good adhesion and providing a stable conductive path, taking into account material cost and film stress.

[0043] In some implementations, the thickness of the seed top layer 103 is 30nm-50nm.

[0044] By precisely controlling the thickness of the seed top layer 103 within the range of 30nm-50nm, a balance can be effectively struck between conductivity and material consumption. If the seed top layer 103 is too thin, its conductivity may be insufficient for effective current transfer, leading to increased series resistance in the cell and consequently reducing the fill factor and conversion efficiency. Conversely, if the seed top layer 103 is too thick, while conductivity is guaranteed, it increases material cost and may introduce significant internal stress during deposition, affecting film adhesion and stability, and potentially even causing cracking or peeling. Therefore, by setting this thickness range, it is possible to ensure that the seed top layer 103 provides excellent electrical contact while maintaining good mechanical stability.

[0045] In a second aspect, this application provides a copper grid heterojunction solar cell, comprising: an N-type silicon wafer 200, wherein an intrinsic amorphous silicon layer 201, a doped amorphous silicon layer 202, a transparent conductive oxide film 203 and a copper electrode 204 are sequentially stacked on the light-receiving side of the N-type silicon wafer 200 in a direction away from the N-type silicon wafer 200, and a composite seed layer as described above is disposed between the transparent conductive oxide film 203 and the copper electrode 204; On the backlight side of the N-type silicon wafer 200, an intrinsic amorphous silicon layer 201, a doped amorphous silicon layer 202, a transparent conductive oxide film 203, and a copper electrode 204 are sequentially stacked in a direction away from the N-type silicon wafer 200. A composite seed layer as described above is disposed between the transparent conductive oxide film 203 and the copper electrode 204.

[0046] On the light-receiving side of the N-type silicon wafer 200, an intrinsic amorphous silicon layer 201, an (N-type) doped amorphous silicon layer 202, a transparent conductive oxide film 203, and a copper electrode 204 are sequentially stacked along the direction away from the N-type silicon wafer 200. The intrinsic amorphous silicon layer 201 is disposed on the front surface of the N-type silicon wafer 200, and its main function is to passivate the silicon wafer surface, reduce surface recombination losses, thereby improving the open-circuit voltage and conversion efficiency of the cell. The (N-type) doped amorphous silicon layer 202 forms an isomorphic structure with the N-type silicon wafer 200, creating a front surface field. Its function is to effectively promote the export of majority carriers (electrons) and significantly reduce recombination losses on the front surface. The copper electrode 204 is disposed on the transparent conductive oxide film 203, serving as the main grid line and fine grid line of the cell for collecting current.

[0047] On the backlight side of the N-type silicon wafer 200, an intrinsic amorphous silicon layer 201, a (P-type) doped amorphous silicon layer 202, a transparent conductive oxide film 203, and a copper electrode 204 are sequentially stacked along the direction away from the N-type silicon wafer 200. The intrinsic amorphous silicon layer 201 on the backlight side is also used to passivate the back of the silicon wafer, while the (P-type) doped amorphous silicon layer 202 forms a PN junction (emitter) with the N-type silicon wafer 200, effectively separating and transporting photogenerated carriers, further improving the efficiency of the cell. The transparent conductive oxide film 203 and the copper electrode 204 on the backlight side function similarly to those on the light-receiving side, for collecting current from the back side.

[0048] The aforementioned composite seed layer is disposed between the transparent conductive oxide film 203 on both the light-receiving and back-light-receiving sides and the copper electrode 204. This composite seed layer serves as the conductive substrate and adhesion base for electroplating the copper electrode 204. Its unique layered structure (seed bottom layer 101, metal oxide intermediate layer 102, and seed top layer 103) effectively improves the interface characteristics between the seed layer and the transparent conductive oxide film 203 and the copper electrode 204, enhances adhesion, and inhibits erosion by the process solution during electroplating or cleaning, thereby ensuring the stability of the copper electrode 204 and the long-term reliability of the battery. After depositing the transparent conductive oxide film 203, the composite seed layer layers can be sequentially deposited using methods such as magnetron sputtering or atomic layer deposition. Finally, the copper electrode 204 is formed through patterning and electroplating processes.

[0049] The copper-grid heterojunction solar cell proposed in this application represents a significant improvement over traditional heterojunction solar cells using silver grid lines. Traditional silver-grid solar cells face the challenge of high silver material costs, while this application, by employing a copper electrode 204, can significantly reduce the manufacturing cost of the cell, thereby enhancing its market competitiveness. Furthermore, by introducing a composite seed layer between the transparent conductive oxide film 203 and the copper electrode 204, this application effectively solves the problems of insufficient adhesion, high interfacial stress, and process solution erosion that may exist with pure copper seed layers. This ensures the conductivity of the seed layer as a starting layer without affecting the bonding force between seed layers, and can significantly improve the film density and reduce film porosity defects, thereby improving the performance of the copper-grid heterojunction solar cell. Practical data shows that, in an experimental comparison between the first group of copper-grid heterojunction solar cells (a 50nm thick seed bottom layer 101, a 5nm thick intermediate layer 102, and a 50nm thick seed top layer 103) and the reference group (a 100nm thick pure copper seed layer), the photoelectric conversion efficiency difference is only 0.266. The second group of copper-grid heterojunction solar cells in this application (a seed bottom layer 101 with a thickness of 60 nm, an intermediate layer 102 with a thickness of 10 nm, and a seed top layer 103 with a thickness of 40 nm) was compared experimentally with the reference group (a pure copper seed layer with a thickness of 100 nm), and the photoelectric conversion efficiency differed by 0.157%. The third group of copper-grid heterojunction solar cells in this application (a seed bottom layer 101 with a thickness of 40 nm, an intermediate layer 102 with a thickness of 15 nm, and a seed top layer 103 with a thickness of 60 nm) was compared experimentally with the reference group (a pure copper seed layer with a thickness of 100 nm), and the photoelectric conversion efficiency differed by 0.170%. Therefore, the photoelectric conversion efficiency of the copper-grid heterojunction solar cells proposed in this application can be improved by approximately 0.1-0.3%. Figure 2As shown, this significantly improves the reliability of the copper electrode 204 and the long-term stability of the battery. Therefore, the solution presented in this application not only achieves effective cost control but also optimizes battery performance and reliability, providing a feasible technical path for the large-scale production of high-efficiency, low-cost copper grid heterojunction solar cells.

[0050] In some embodiments, the N-type silicon wafer 200 has a thickness ranging from 50 μm to 150 μm, a minority carrier lifetime of ≥800 μs, and a resistivity ranging from 0.3 Ω·cm to 2.1 Ω·cm.

[0051] This application's solution effectively solves the performance degradation problem caused by improper N-type silicon wafer 200 parameters in traditional solar cells by precisely controlling the thickness, minority carrier lifetime, and resistivity of the N-type silicon wafer 200. Specifically, limiting the thickness of the N-type silicon wafer 200 to the range of 50µm-150µm ensures sufficient photon absorption while guaranteeing efficient collection of photogenerated carriers, avoiding insufficient light absorption or increased carrier recombination due to excessive thickness or thinness. The minority carrier lifetime setting of ≥800µs ensures a longer diffusion length for photogenerated carriers in the N-type silicon wafer 200, thereby improving carrier collection efficiency and contributing to a higher open-circuit voltage. Furthermore, by controlling the resistivity range to 0.3Ω·cm-2.1Ω·cm, the conductivity of the N-type silicon wafer 200 is optimized, the series resistance of the battery is reduced, thereby improving the fill factor and helping to form an ideal built-in electric field, further improving the overall performance of the battery. This enables the battery to utilize light energy more efficiently during photoelectric conversion, reduce energy loss, and thus achieve higher output power and longer service life.

[0052] In some embodiments, the thickness of the intrinsic amorphous silicon layer 201 disposed on the light-receiving side ranges from 3 nm to 6 nm, and the thickness of the doped amorphous silicon layer 202 is 4 nm to 7 nm. The thickness of the intrinsic amorphous silicon layer 201 on the backlight side ranges from 4nm to 7nm, and the thickness of the doped amorphous silicon layer 202 ranges from 4nm to 10nm.

[0053] This application's solution effectively solves the performance degradation problem caused by improper thickness by precisely controlling the thickness of the intrinsic amorphous silicon layer 201 and the doped amorphous silicon layer 202 in the copper grid heterojunction solar cell. Specifically, on the light-receiving side, setting the thickness of the intrinsic amorphous silicon layer 201 to 3nm-6nm ensures sufficient passivation of the N-type silicon wafer 200 surface. Based on this, setting the thickness of the (N-type) doped amorphous silicon layer 202 to 4nm-7nm forms a highly efficient front surface field, promoting the effective separation and transport of photogenerated carriers and further reducing parasitic absorption. On the back-lighting side, setting the thickness of the intrinsic amorphous silicon layer 201 to 4nm-7nm provides excellent back surface passivation. Simultaneously, setting the thickness of the (P-type) doped amorphous silicon layer 202 to 4nm-10nm provides a high-quality PN junction, effectively separating and transporting photogenerated carriers, further improving the cell's efficiency. It is precisely because of the optimization of the thickness of these key layers that the open-circuit voltage, fill factor and short-circuit current of the battery have been significantly improved.

[0054] In some embodiments, the transparent conductive oxide film 203 disposed on the light-receiving side and the backlight side is one of indium tin oxide, indium tungsten oxide, aluminum-doped zinc oxide, and doped tin dioxide, or is a superimposed structure formed by any two of the following materials: indium tin oxide, indium tungsten oxide, aluminum-doped zinc oxide, and doped tin dioxide; wherein the weight ratio of indium oxide to tin oxide in indium tin oxide ranges from 99:1 to 90:10.

[0055] Specifically, using indium tin oxide, indium tungsten oxide, aluminum-doped zinc oxide, or doped tin dioxide as the transparent conductive oxide thin film 203 material ensures that the film maintains high transmittance while providing excellent conductivity, thereby effectively reducing the series resistance of the battery and minimizing the transmission loss of photogenerated carriers. Furthermore, by forming a stacked structure of any two materials, the photoelectric performance of the film can be further optimized and material costs reduced. For example, surface reflection can be reduced through refractive index matching, or carrier transport can be improved by constructing a multilayer structure, thereby enhancing light trapping capability and carrier collection efficiency. For another example, by introducing low-indium or indium-free stacked transparent conductive oxide thin films, production costs can be further reduced. In principle, transparent conductive oxide thin films must not only ensure high transmittance and high conductivity to ensure efficient collection of photogenerated carriers, but also minimize indium costs.

[0056] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0057] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A composite seed layer applied to a copper grid heterojunction solar cell, characterized in that, It includes a seed bottom layer (101), a middle layer (102) and a seed top layer (103) stacked in sequence. The seed bottom layer (101) is disposed on the transparent conductive oxide film (203) of the copper grid heterojunction cell, and the seed top layer (103) is connected to the electrode of the copper grid heterojunction cell; The bottom layer (101) and top layer (103) of the seed are made of metal, while the middle layer (102) is made of metal oxide.

2. The composite seed layer according to claim 1, characterized in that, The metal oxide material corresponding to the intermediate layer (102) includes one of indium tin oxide, aluminum-doped zinc oxide, and tin dioxide.

3. The composite seed layer according to claim 1, characterized in that, The thickness of the intermediate layer (102) is 1nm-15nm.

4. The composite seed layer according to claim 1, characterized in that, The metal materials corresponding to the bottom layer (101) and top layer (103) of the seed include pure copper or copper-nickel alloy.

5. The composite seed layer according to claim 1, characterized in that, The thickness of the seed layer (101) is 40nm-60nm.

6. The composite seed layer according to claim 1, characterized in that, The thickness of the top layer (103) of the seed is 30nm-50nm.

7. A copper grid heterojunction solar cell, comprising: An N-type silicon wafer (200) is characterized in that an intrinsic amorphous silicon layer (201), a doped amorphous silicon layer (202), a transparent conductive oxide film (203), and a copper electrode (204) are sequentially stacked on the light-receiving side in a direction away from the N-type silicon wafer (200), and a composite seed layer as described in any one of claims 1-6 is disposed between the transparent conductive oxide film (203) and the copper electrode (204); An intrinsic amorphous silicon layer (201), a doped amorphous silicon layer (202), a transparent conductive oxide film (203), and a copper electrode (204) are sequentially stacked on the backlight side in a direction away from the N-type silicon wafer (200), and a composite seed layer as described in any one of claims 1-6 is disposed between the transparent conductive oxide film (203) and the copper electrode (204).

8. The copper grid heterojunction solar cell according to claim 7, characterized in that, The thickness of N-type silicon wafers (200) ranges from 50µm to 150µm, the minority carrier lifetime is ≥800µs, and the resistivity ranges from 0.3Ω·cm to 2.1Ω·cm.

9. The copper grid heterojunction solar cell according to claim 7, characterized in that, The thickness of the intrinsic amorphous silicon layer (201) on the light-receiving side ranges from 3 nm to 6 nm, and the thickness of the doped amorphous silicon layer (202) ranges from 4 nm to 7 nm. The thickness of the intrinsic amorphous silicon layer (201) on the backlight side ranges from 4 nm to 7 nm, and the thickness of the doped amorphous silicon layer (202) ranges from 4 nm to 10 nm.

10. The copper grid heterojunction solar cell according to claim 7, characterized in that, The transparent conductive oxide film (203) disposed on the light-receiving side and the back-light-receiving side is one of indium tin oxide, indium tungsten oxide, aluminum-doped zinc oxide and doped tin dioxide, or is a superimposed structure formed by any two of the following materials: indium tin oxide, indium tungsten oxide, aluminum-doped zinc oxide and doped tin dioxide; wherein, the weight ratio of indium oxide to tin oxide in indium tin oxide is in the range of 99:1-90:10.

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