Sensing, storing and computing integrated device based on atomic layer Van der Waals heterojunction and preparation method thereof

Abstract

The invention relates to the technical field of advanced materials, integrated circuits and microelectronic devices, and provides an atomic layer Van der Waals heterojunction-based sensing, storage and calculation integrated device and a preparation method thereof. The device comprises a substrate, a first gate electrode, a first two-dimensional Van der Waals alternating magnetic material layer, a second gate electrode, a first two-dimensional Van der Waals ferromagnetic material layer, a two-dimensional Van der Waals insulating material layer, a second two-dimensional Van der Waals ferromagnetic material layer, a third gate electrode and a second two-dimensional Van der Waals alternating magnetic material layer which are sequentially stacked from bottom to top, and a fourth gate electrode and an encapsulation layer. According to the invention, the integration of the sensing of optical signals, the nonvolatile storage of information and the logic calculation function is realized in a single device unit, and the sensing, storage and calculation integrated function of a single device constructed by an atomic layer is realized. On the basis, by combining and interconnecting a plurality of device units, basic logic functions such as an AND gate, an OR gate and a NOT gate can be further realized, and a solid foundation is laid for expanding application scenarios.

Description

Technical Field

[0001] This invention relates to the fields of advanced materials, integrated circuits and microelectronic devices, and more specifically, to an integrated sensing, memory and computing device based on an atomic-layer van der Waals heterojunction and its fabrication method. Background Technology

[0002] Driven by the rapid development of artificial intelligence, the Internet of Things, and big data technologies, the traditional von Neumann computing architecture is facing severe challenges. Its core bottleneck lies in the frequent data migration between storage and computing units, creating the "memory wall" problem—the speed and energy efficiency of data exchange become key constraints on overall system performance. To overcome this limitation, the sensor-memory-computing (SMC) architecture (integrating sensing, storage, and computing functions) has emerged. This architecture mimics the biological nervous system, enabling direct execution of computational tasks within storage units, thereby significantly reducing data migration overhead and improving system energy efficiency and response speed. However, the implementation of existing SMC devices is still limited by device heterogeneity and integration complexity: memory units and peripheral circuits (such as signal amplification and logic operation modules) typically employ different materials and structural designs, resulting in physical separation. As device dimensions shrink to the nanometer scale, interface impedance mismatch and process compatibility issues further hinder performance improvements.

[0003] In recent years, two-dimensional van der Waals materials and their heterojunctions have provided new approaches to addressing the aforementioned challenges. These materials achieve atomically flat interfaces through weak van der Waals stacking, eliminating the need for lattice matching and effectively avoiding interface defects introduced by chemical bonds. Furthermore, two-dimensional van der Waals materials exhibit unique potential in multimodal sensing: their optical, electrical, and magnetic properties can be flexibly controlled by the number of layers, stacking angle, and external fields (such as polarization, electric fields, and magnetic fields). Devices based on van der Waals ferroelectric tunnel junctions have achieved speeds up to 10... 7 The switching ratio significantly improves the accuracy of in-memory computing; and the mid-infrared detector of the van der Waals heterojunction can respond to both wavelength and polarization information simultaneously, providing a solid hardware foundation for inductive-computing fusion.

[0004] However, existing integrated sensing, in-memory, and computing devices still face several key drawbacks. First, the Curie temperature of most two-dimensional van der Waals magnetic materials is too low, limiting practical applications. Although metallic ferromagnets such as Fe3GaTe2 and Fe5GeTe2 can raise the Curie temperature to room temperature, their interface spin injection efficiency with semiconductor materials still needs improvement. Second, the bandgap modulation mechanism is limited. The bandgap alignment of traditional heterojunctions (such as type I and type II) mainly relies on mechanical strain or chemical doping, which easily leads to lattice distortion and has a limited modulation range. Finally, there are bottlenecks in large-scale fabrication. Two-dimensional van der Waals ferromagnetic and alternating magnetic materials are sensitive to the environment, making wafer-level stacking difficult. Existing transfer technologies (such as PDMS dry transfer) are prone to leaving adhesive layers, leading to interface contamination and performance degradation.

[0005] To address these challenges, some research has attempted breakthroughs through material innovation and structural design. For example, constructing a homogeneous transistor-memory architecture and utilizing two-dimensional van der Waals ferromagnetic and ferroelectric materials for integrated sensing, memory, and computing has been explored, but this suffers from insufficient magnetic control. Developing atomic substitution strategies to control bandgap alignment has also failed to solve the magnetic integration problem. Therefore, there is an urgent need to develop a novel van der Waals heterojunction device. This device must possess effective room-temperature magnetic control, efficient bandgap engineering, and clean transfer processes to meet the pressing application requirements of high-performance integrated sensing, memory, and computing. Summary of the Invention

[0006] In view of this, the present invention proposes an integrated sensing, storage, and computing device based on an atomic-layer van der Waals heterojunction and its fabrication method. The integrated sensing, storage, and computing device is constructed by combining two-dimensional van der Waals ferromagnetic materials with alternating magnetic materials. It integrates photosensing, non-volatile storage, and logic computing functions using a single device, thereby improving response speed, reducing cost, and minimizing device size, thus solving the problems existing in the prior art.

[0007] To achieve the above objectives, this invention proposes an integrated sensing, memory, and computing device based on an atomic-layer van der Waals heterojunction, comprising, from bottom to top, a substrate, a first gate electrode, a first two-dimensional van der Waals alternating magnetic material layer, a second gate electrode, a first two-dimensional van der Waals ferromagnetic material layer, a two-dimensional van der Waals insulating material layer, a second two-dimensional van der Waals ferromagnetic material layer, a third gate electrode, a second two-dimensional van der Waals alternating magnetic material layer, a fourth gate electrode, and an encapsulation layer;

[0008] The thickness of the first two-dimensional van der Waals alternating magnetic material layer, the first two-dimensional van der Waals ferromagnetic material layer, the two-dimensional van der Waals insulating material layer, the second two-dimensional van der Waals ferromagnetic material layer, and the second two-dimensional van der Waals alternating magnetic material layer are all 1 to 10 atomic layers.

[0009] Furthermore, the substrate is a flexible substrate made of Si, SiO2, SiC, AlN, Ga2O3, or PDMS.

[0010] Furthermore, the materials of the first gate electrode layer, the second gate electrode layer, the third gate electrode layer, and the fourth gate electrode layer are independently selected from Au / Cr composite electrode, graphene, TiS2, NbS2, or α-In2Se3.

[0011] Furthermore, the materials of the first two-dimensional van der Waals alternating magnetic material layer and the second two-dimensional van der Waals alternating magnetic material layer are independently selected from RuO2, CrSb, MnTe, Fe2Se2, Fe2Te2, transition metal selenium oxide, or transition metal tellurium oxide.

[0012] Furthermore, the materials of the first two-dimensional van der Waals ferromagnetic material layer and the second two-dimensional van der Waals ferromagnetic material layer are independently selected from Fe3GeTe2, Fe3GaTe2, magnetic metal chalcogenides, magnetic metal halides, or magnetic metal carbides.

[0013] Furthermore, the two-dimensional van der Waals insulating material layer is independently selected from h-BN, Bi2Te3, MnBi2Te4, Bi2O2Se, Bi2SeO5 or transition metal chalcogenides.

[0014] Furthermore, the encapsulation layer is independently selected from h-BN, Ga2O3, HfO2, or Al2O3.

[0015] On the other hand, the present invention proposes a method for fabricating the above-mentioned integrated sensing, storage, and computing device, comprising:

[0016] S1. Form a first gate electrode layer on the substrate;

[0017] S2. A first two-dimensional van der Waals alternating magnetic material layer is formed on the first gate electrode layer;

[0018] S3. A first two-dimensional van der Waals ferromagnetic material layer is formed on the first two-dimensional van der Waals alternating magnetic material layer, and then a second gate electrode layer is formed.

[0019] S4. A two-dimensional van der Waals insulating material layer is formed on the first two-dimensional van der Waals ferromagnetic material layer;

[0020] S5. A second two-dimensional van der Waals ferromagnetic material layer is formed on the two-dimensional van der Waals insulating material layer, and then a third gate electrode layer is formed.

[0021] S6. A second two-dimensional van der Waals alternating magnetic material layer is formed on the second two-dimensional van der Waals ferromagnetic material layer;

[0022] S7. A fourth gate electrode layer is formed on the second two-dimensional van der Waals alternating magnetic material layer, and then an encapsulation layer is formed to obtain the integrated sensing, storage, and computing device.

[0023] Furthermore, the gate electrode layer formation process in steps S1, S3, S5 and S7 includes any one or more of the following: magnetron sputtering or electron beam evaporation combined with photolithography etching, liquid metal printing combined with annealing, and photolithography patterning combined with pulsed laser deposition.

[0024] Furthermore, the two-dimensional van der Waals material formation process in steps S2, S3, S4, S5 and S6 includes any one or more of chemical vapor deposition, molecular beam epitaxy, and polymer-assisted dry transfer technology.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] Traditional integrated circuit chips face the limitation of separating storage and computation, requiring frequent information exchange between the two, increasing the complexity of information transmission and system energy consumption, and hindering further improvements in information processing efficiency. To achieve high-efficiency optical information sensing, non-volatile storage, and logic computation, and to avoid the complex processes of information acquisition, conversion, processing, and transmission to the computing unit at the sensor end, and subsequent processing and conversion by the computing unit and transmission to the storage unit, developing novel integrated intelligent vision devices with sensing, computing, and storage functions is of crucial significance.

[0027] This invention, for the first time, constructs an integrated sensing-memory-computing device based on a heterojunction of atomic-layer-thick two-dimensional van der Waals ferromagnetic and alternating magnetic materials, filling a gap in the field of atomic-layer van der Waals heterojunction integrated sensing-memory-computing devices. Compared to traditional bulk and thin-film materials, this device significantly reduces device size, facilitating the replacement of traditional semiconductor materials and enabling high-density integration in integrated circuits. Simultaneously, it integrates visible light sensing, non-volatile storage, and logic computation functions within a single device. By combining and interconnecting multiple such devices, basic logic functions such as AND, OR, and NOT gates are successfully implemented, providing a hardware foundation for constructing an integrated sensing-memory-computing architecture, particularly suitable for neuromorphic computing scenarios such as artificial vision systems and spiking neural networks. Attached Figure Description

[0028] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. In the drawings:

[0029] Figure 1 This is a schematic diagram of the integrated sensing, storage, and computing device proposed in this invention;

[0030] Figure 2 This is a schematic diagram of a NOT gate circuit composed of an integrated sensing, storage, and computing device in an embodiment of the present invention.

[0031] Figure 3 This is a schematic diagram of an AND gate circuit composed of an integrated sensing, storage, and computing device in an embodiment of the present invention.

[0032] Figure 4 This is a schematic diagram of an OR gate circuit composed of an integrated sensing, storage, and computing device in an embodiment of the present invention.

[0033] Reference numerals: 100-substrate, 101-first gate electrode, 102-first two-dimensional van der Waals alternating magnetic material layer, 103-second gate electrode, 104-first two-dimensional van der Waals ferromagnetic material layer, 105-two-dimensional van der Waals insulating material layer, 106-second two-dimensional van der Waals ferromagnetic material layer, 107-third gate electrode, 108-second two-dimensional van der Waals alternating magnetic material layer, 109-fourth gate electrode, 110-encapsulation layer. Detailed Implementation

[0034] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the disclosure to those skilled in the art. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0035] It should be noted that the terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, parts, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, parts, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0036] Furthermore, the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0037] Example 1

[0038] This invention provides an integrated sensing, storage, and computing device based on an atomic-layer van der Waals heterostructure, along with its fabrication and application methods. By combining two-dimensional van der Waals ferromagnetic materials with alternating magnetic materials, an integrated sensing, storage, and computing device is constructed. This single device integrates photosensing, non-volatile storage, and logic computing functions, achieving improved response speed, reduced cost, and smaller device size. Figure 1 As shown, the proposed integrated sensing, storage, and computing device includes:

[0039] Substrate 100;

[0040] A first gate electrode 101 is formed on the substrate 100;

[0041] A first two-dimensional van der Waals alternating magnetic material layer 102 is formed on the first gate electrode 101;

[0042] The second gate electrode 103 and the first two-dimensional van der Waals ferromagnetic material layer 104 are formed on the first two-dimensional van der Waals alternating magnetic material layer 102 in a horizontally parallel or vertically stacked manner.

[0043] A two-dimensional van der Waals insulating material layer 105 is formed on the first two-dimensional van der Waals magnetic material layer 104;

[0044] The second two-dimensional van der Waals ferromagnetic material layer 106 and the third gate electrode 107 are formed on the two-dimensional van der Waals insulating material layer 105 in a horizontally parallel or vertically stacked manner.

[0045] A second two-dimensional van der Waals alternating magnetic material layer 108 is formed on the second two-dimensional van der Waals ferromagnetic material layer 106.

[0046] The fourth gate electrode 109 and the encapsulation layer 110 are formed on the two-dimensional van der Waals alternating magnetic material layer 108.

[0047] In a preferred embodiment, the substrate 100 is made of Si, SiO2, SiC, AlN, Ga2O3, or a PDMS flexible substrate.

[0048] In a preferred embodiment, the first 101, the second 103, the third 107, and the fourth 109 gate electrodes are Au / Cr composite electrodes, graphene, TiS2, NbS2, or α-In2Se3.

[0049] In a preferred embodiment, the first 102 and the second 108 two-dimensional van der Waals alternating magnetic material layers are RuO2, CrSb, MnTe, Fe2Se2, Fe2Te2, transition metal selenium oxide, or transition metal tellurium oxide.

[0050] In a preferred embodiment, the first 104 and the second 106 two-dimensional van der Waals ferromagnetic material layers are Fe3GeTe2, Fe3GaTe2, magnetic metal chalcogenides, magnetic metal halides, or magnetic metal carbides.

[0051] In a preferred embodiment, the two-dimensional van der Waals insulating material layer 105 is h-BN, Bi2Te3, MnBi2Te4, Bi2O2Se, Bi2SeO5, or a transition metal chalcogenide.

[0052] In a preferred embodiment, the encapsulation layer 110 is h-BN, Ga2O3, HfO2, or Al2O3.

[0053] In traditional devices, memory cells and peripheral circuits are typically designed with different materials and structures, leading to physical separation. Interface impedance mismatch and process compatibility issues hinder performance improvement. However, the device structure proposed in this embodiment integrates optical sensing, non-volatile storage, and logic computing functions within the same device cell. By stacking multiple layers of two-dimensional van der Waals materials, a high degree of functional integration is achieved, avoiding the performance bottlenecks caused by physical separation in traditional devices.

[0054] Regarding material selection, the low Curie temperature of traditional two-dimensional van der Waals magnetic materials limits their practical applications. The two-dimensional van der Waals ferromagnetic and alternating magnetic materials used in this embodiment have higher Curie temperatures, enabling them to operate effectively at room temperature and solving the temperature limitation problem of traditional materials. Furthermore, the aforementioned materials achieve atomically flat interfaces through weak van der Waals force stacking, eliminating the need for lattice matching and effectively avoiding interface defects introduced by chemical bonds, thus improving the stability and performance of the device.

[0055] In terms of bandgap modulation, traditional heterojunctions mainly rely on mechanical strain or chemical doping for band alignment, which easily leads to lattice distortion and limits the modulation range. This invention, by designing a multilayer van der Waals heterojunction structure and utilizing the combined properties of different materials, achieves more flexible bandgap modulation without the need for complex doping or strain engineering, thus solving the problem of the single bandgap modulation mechanism in traditional devices.

[0056] This embodiment further proposes a method for fabricating the above-mentioned integrated sensing, storage, and computing device, including:

[0057] S1. A first gate electrode layer 101 is formed on the substrate 100;

[0058] S2. A first two-dimensional van der Waals alternating magnetic material layer 102 is formed on the first gate electrode layer 101;

[0059] S3. A first two-dimensional van der Waals ferromagnetic material layer 104 is formed on the first two-dimensional van der Waals alternating magnetic material layer 102, and then a second gate electrode layer 103 is formed.

[0060] S4. A two-dimensional van der Waals insulating material layer 105 is formed on the first two-dimensional van der Waals ferromagnetic material layer 104.

[0061] S5. A second two-dimensional van der Waals ferromagnetic material layer 106 is formed on the two-dimensional van der Waals insulating material layer 105, and then a third gate electrode layer 107 is formed.

[0062] S6. A second two-dimensional van der Waals alternating magnetic material layer 108 is formed on the third gate electrode layer 107;

[0063] S7. A fourth gate electrode layer 109 is formed on the second two-dimensional van der Waals alternating magnetic material layer 108, and then an encapsulation layer 110 is formed.

[0064] In a preferred embodiment, the gate electrode formation process in steps S1, S3, S5, and S7 includes one or more of the following methods, and the specific steps are as follows:

[0065] (A) Magnetron sputtering or electron beam evaporation, combined with photolithography and etching processes:

[0066] 1. Select a photoresist on the substrate surface of the electrode to be deposited and perform pre-baking;

[0067] 2. Use a photomask for ultraviolet exposure and development to form the desired electrode pattern;

[0068] 3. Using magnetron sputtering or electron beam evaporation in a vacuum chamber (background vacuum ≤ 1×10⁻⁶) -4 The preferred magnetron sputtering process parameters are: sputtering power 50-200 W, working gas is high-purity argon (purity ≥99.999%), working pressure 0.5-2.0 Pa, and substrate temperature 20-200℃; the preferred electron beam evaporation process parameters are: evaporation rate 0.1-2.0 Å / s.

[0069] 4. Use wet etching (such as a specific metal etching solution) or dry etching (such as reactive ion etching, RIE) processes to remove the metal film in areas not protected by photoresist;

[0070] 5. Use stripping solution to remove residual photoresist to obtain a patterned gate electrode structure;

[0071] 6. Optionally, annealing can be performed in an inert gas atmosphere (such as N2 or Ar) (temperature 150-350℃, time 10-60 minutes) to improve electrode contact performance and stability.

[0072] (B) Liquid metal printing combined with annealing:

[0073] 1. Using micro-contact printing, inkjet printing, or stencil-assisted coating techniques, liquid metal (such as gallium-based alloy) ink is used to form conductive patterns at predetermined positions on the substrate of the electrode to be deposited;

[0074] 2. Place the substrate with the liquid metal pattern in an inert gas atmosphere (such as N2 or Ar) or a vacuum environment;

[0075] 3. Perform annealing treatment at a temperature range of 150-300℃ for 10-120 minutes to solidify the liquid metal and form good ohmic contact with the substrate, thereby obtaining a patterned gate electrode structure.

[0076] (C) Photolithography combined with pulsed laser deposition:

[0077] 1. Spin-coat photoresist onto the substrate surface of the electrode to be deposited, and pre-bake;

[0078] 2. Use a photomask for ultraviolet exposure to develop the window area for the desired electrode pattern;

[0079] 3. Place the substrate in the vacuum chamber of the pulsed laser deposition (PLD) equipment (baseline vacuum ≤ 1 × 10⁻⁶). -5 Pa);

[0080] 4. Use an excimer laser (such as KrF, wavelength 248nm) or a solid-state laser (such as Nd:YAG, wavelength 266nm or 355nm) to bombard the target material (such as graphene target, TiS2 target, NbS2 target, α-In2Se3 target, or metal target), with a laser energy density of 1-5 J / cm². 2 The repetition frequency is 1-10 Hz;

[0081] 5. Selectively deposit electrode materials (such as graphene, TiS2, NbS2, α-In2Se3 or metal thin films) within the patterned window area. During the deposition process, the substrate temperature is controlled at 200-600℃ (adjusted according to the specific material), and the deposition time is determined according to the required thickness (typically 10-100 nm).

[0082] 6. After deposition, the residual photoresist is removed using a stripping solution to obtain a patterned gate electrode structure;

[0083] 7. Optionally, perform subsequent annealing (under the same conditions as step 6 of method A).

[0084] In a preferred embodiment, the two-dimensional van der Waals material formation process in steps S2, S3, S4, S5, and S6 includes any one or more of the following methods, and the specific steps are as follows:

[0085] (A) Chemical vapor deposition:

[0086] 1. Place the target substrate in the quartz tube of the tubular furnace;

[0087] 2. Evacuate to a base pressure ≤10. -2 Pa, introduce high-purity inert carrier gas (such as Ar or N2, purity ≥99.999%).

[0088] 3. Heat the reaction tube to the specific growth temperature (usually 400-900℃ depending on the material) and stabilize the temperature;

[0089] 4. Introduce precursor gases with precisely controlled flow rates (such as organometallic sources, halides, hydrides, sulfur / selenium / tellurium vapors, etc.), and if necessary, introduce reducing gases (such as H2) or reactive gases;

[0090] 5. At the set temperature and pressure (normal pressure or low pressure, such as 10...) -1 -10 3 Growth is carried out under the conditions of Pa and gas phase composition, and the growth time is precisely controlled according to the required number of atomic layers (1-10 layers) (typical values ​​range from several minutes to several hours).

[0091] 6. After growth is complete, stop the introduction of precursors, cool the reaction tube to room temperature under a carrier gas atmosphere, and remove the sample.

[0092] (B) Molecular beam epitaxy:

[0093] 1. Place the target substrate in the MBE ultra-high vacuum chamber (background vacuum ≤ 1×10⁻⁶). -8 Pa);

[0094] 2. Perform high-temperature annealing on the substrate (temperature determined according to the substrate material, such as 300-800℃) to clean the surface;

[0095] 3. Reduce the substrate temperature to a specific growth temperature (typically 200-500℃, adjusted according to the material);

[0096] 4. Control the beam intensity of each element source furnace (such as solid metal source, chalcogen element source) to accurately deliver atomic or molecular beams to the substrate surface;

[0097] 5. Epitaxial growth is carried out under ultra-high vacuum and precisely controlled beam conditions. The growth mode and number of layers are monitored in real time using reflected high-energy electron diffraction to grow to the required number of atomic layers (1-10 layers).

[0098] 6. After growth is complete, turn off the source furnace and cool the sample to room temperature under ultra-high vacuum before removing it.

[0099] (C) Polymer-assisted dry transfer technology:

[0100] 1. Spin-coat a polymer support layer (such as polymethyl methacrylate PMMA or polycarbonate PC) onto a growth substrate (such as sapphire, mica, SiO2 / Si) on which the target two-dimensional van der Waals material (such as RuO2, CrSb, Fe3GeTe2, h-BN, etc.) has been pre-grown.

[0101] 2. The polymer / two-dimensional material film is released from the growth substrate by selective etching (such as etching the SiO2 layer on SiO2 / Si with KOH solution) or mechanical exfoliation.

[0102] 3. Use a clean transfer platform (such as a PDMS stamp, polydimethylsiloxane PDMS, or heat release tape) to retrieve polymer / 2D material films floating on the surface of deionized water or a specific etching solution;

[0103] 4. Precisely align and attach the polymer / 2D material film on the transfer platform to the surface of the target layer (such as the gate electrode or another 2D material layer);

[0104] 5. Key Controls: During or after lamination, the temperature of the entire laminated structure (including the target substrate and transfer platform) is precisely controlled within the range of 30-150°C. This temperature range helps improve interlayer adhesion and reduce bubbles and wrinkles. The specific temperature is optimized based on the material system and polymer type.

[0105] 6. Slowly remove the transfer platform (for heat-release tape, it needs to be heated to its release temperature).

[0106] 7. Use a suitable organic solvent (such as acetone or chlorobenzene) to dissolve and remove the polymer support layer;

[0107] 8. Place the sample in an inert gas atmosphere (such as N2 or Ar) or in a vacuum for gentle annealing (temperature 100-250℃, time 10-60 minutes) to remove residual solvent, improve interlayer contact and interface quality, and ensure that the heterojunction interface is clean and tightly bonded.

[0108] In a preferred embodiment, the thickness of the two-dimensional van der Waals material in steps S2, S3, S4, S5 and S6 is 1 to 10 atomic layers.

[0109] In summary, traditional fabrication processes for two-dimensional van der Waals materials are environmentally sensitive and difficult to achieve wafer-level stacking. Existing transfer technologies are prone to leaving adhesive layers, leading to interface contamination and performance degradation. This invention employs a polymer-assisted dry transfer technique to peel off pre-prepared two-dimensional van der Waals materials from the growth substrate and transfer them to the target layer. During the transfer process, the substrate temperature is controlled within the range of 30-150°C, ensuring interface cleanliness and material performance, thus solving the bottleneck problems in traditional fabrication processes.

[0110] This embodiment further provides a method for using the aforementioned integrated sensing, memory, and computing device. Utilizing the device's non-volatile storage and electrically controlled switching characteristics, input-related state switching is achieved by designing the connection method between devices and applying a specific V_comp sequence. The functions and states of the core device unit are defined as follows:

[0111] 1. Light sensing and initial state writing:

[0112] By applying a bias voltage V_write between the fourth gate electrode 109 and the bottom electrode 100, and simultaneously applying 400-800 nm wavelength light to the second two-dimensional van der Waals alternating magnetic material layer 108, a photocurrent is generated. This current, through the spin splitting moment of the two-dimensional van der Waals alternating magnetic material, generates a spin polarization current perpendicular to the plane and is injected into the second two-dimensional van der Waals ferromagnetic material layer 106, inducing its magnetic moment reversal.

[0113] By applying a voltage difference V_write between the first and third gate electrodes 101 and 107, or by receiving light of a specific wavelength hv, a photocurrent can be generated in the second two-dimensional van der Waals alternating magnetic material layer 108. Then, through the spin splitting moment of the alternating magnetic material, the photocurrent is converted into a longitudinal spin polarization current J. s The spin polarization current J injected into the second two-dimensional van der Waals ferromagnetic material layer 106 and the two-dimensional van der Waals insulating material layer 105 is also injected. s The magnetic moments of the first two-dimensional van der Waals ferromagnetic material layer 104 are flipped by the spin orbital moment. The resistance state of the tunnel junction represents the stored logic state: the high-resistance state HRS corresponds to logic '0', in which case the magnetic moment directions of the first 104 and second 106 two-dimensional van der Waals ferromagnetic material layers are antiparallel; the low-resistance state LRS corresponds to logic '1', in which case the magnetic moment directions of the first 104 and second 106 van der Waals ferromagnetic material layers are parallel. The initial state V_write and hν determine whether '0' or '1' is written, which depends on the polarity control J of V_write. s The spin polarization direction and the intensity / wavelength of the light affect J s Size, make sure it's large enough to flip.

[0114] It is understandable that, during the optical sensing and initial state writing process, the device proposed in this embodiment uses photocurrent and spin orbital moment to achieve magnetic moment reversal, directly converting the optical signal into a storage state without the need for additional conversion and transmission processes.

[0115] 2. Electrically controlled magnetic flip Compute / Re-write:

[0116] By applying a pulse voltage V_comp between the first gate electrode 101 and the third gate electrode 107, a vertical electric field is generated to tunnel through the two-dimensional van der Waals insulating material layer 105, and the relative magnetic moment reversal is generated between the first two-dimensional van der Waals ferromagnetic material layer 104 and the second two-dimensional van der Waals ferromagnetic material layer 106 through spin orbital moment and orbital moment.

[0117] By applying a voltage difference V_comp between the second 103 and the third 107 gate electrodes, a strong vertical electric field can be generated within the tunnel junction region. This electric field significantly enhances the Rashba effect at the interface by modulating the strength of interlayer coupling, generating a strong spin-orbit moment, and simultaneously enhancing the orbital Hall effect, producing orbital current and orbital torque. Furthermore, the polarity of V_comp determines the direction of the spin-orbit moment and the orbital moment, thereby controlling the direction of the magnetic moment of the intermediate tunnel junction to be parallel or antiparallel, thus achieving the switching between high and low resistance states.

[0118] In a preferred embodiment, the specific implementation of the electrically controlled magnetic reversal includes:

[0119] When the V_comp pulse width is 1-100 ns and the electric field strength is 0.1-5 V / nm, the Rashba field formed at the interface of the two-dimensional van der Waals insulating material layer 105 enhances the orbital torque, satisfying the magnetic moment reversal condition:

[0120]

[0121] in For the orbital Hall angle, The thickness of the ferromagnetic layer, This is the critical overturning torque.

[0122] It is understood that the device described in this embodiment can achieve rapid magnetic moment reversal by applying a pulse voltage in the electrically controlled magnetic reversal, thereby completing the logic calculation function and significantly improving the response speed and energy efficiency.

[0123] 3. Status Read:

[0124] The current I_read flowing through the entire heterojunction is measured by applying a small read voltage V_read between the first 101 and the fourth 109 gate electrodes. By comparing I_read with a reference current or by directly measuring the voltage drop, the tunnel magnetoresistance effect caused by the change in the magnetic moment angle can be detected, thus determining whether the device is in HRS'0' or LRS'1'.

[0125] Furthermore, by combining and interconnecting multiple device units, the logical functions of AND gates, OR gates, and NOT gates can be realized, providing a hardware foundation for building complex neuromorphic computing systems.

[0126] Understandably, in traditional devices, the separation of storage and computation leads to frequent information exchange, increasing system complexity and energy consumption. The device proposed in this embodiment avoids complex information transfer between different units by integrating optical sensing, non-volatile storage, and logic computation functions.

[0127] Furthermore, traditional devices lack sufficient control over magnetic materials, while the device of this invention achieves efficient magnetic control and state switching through the design of a multilayer van der Waals heterojunction structure. In terms of usage, it simplifies the information processing flow and improves efficiency; in terms of function, it achieves high-performance integrated sensing, storage, and computing, solving the bottleneck problem of traditional devices.

[0128] Example 2

[0129] This embodiment provides a method for implementing a NOT Gate inverter using the integrated inductor-memory-computing device described in Embodiment 1. Utilizing the device's non-volatile storage and electrically controlled switching characteristics, input-related state switching is achieved by designing the device's connection method and applying a specific V_comp sequence. The circuit connection method is as follows: Figure 2 As shown, the specific design steps include the following:

[0130] S1. Write the initial state IN. Based on the externally given input IN, write the corresponding state to the device through V_write and or hv.

[0131] S2. Perform the inversion operation `compute`, applying a voltage difference V_comp of fixed polarity between the second gate electrode 103 and the third gate electrode 107. For example, the third gate electrode is positive and the second gate electrode is negative. The spin orbital moment and orbital moment generated by V_comp always attempt to flip the magnetic state of the device to the opposite state. The direction of the effective moment generated by V_comp is fixed and independent of the current state. Regardless of whether the current state is '0' or '1', this torque will drive the magnetic moment to flip to the other steady state.

[0132] S3. Read the output OUT. The output status is read by applying V_read, and the result is NOT IN.

[0133] Understandably, traditional inverters suffer from problems such as separation of storage and computation, complex signal conversion, limited integration, and high power consumption. This embodiment achieves inversion operation through simple voltage pulse control, eliminating the need for complex circuit design and signal processing, thus reducing manufacturing costs and improving system reliability. This embodiment utilizes the fast electro-magnetic reversal characteristic to achieve logic operations by applying pulse voltage, significantly outperforming the delays caused by signal conversion and transmission in traditional inverters. Furthermore, based on non-volatile memory, this device retains its stored state after power failure, eliminating the need for additional storage units and further reducing power consumption.

[0134] Example 3

[0135] This embodiment provides a method for implementing an AND gate using the integrated sensor-memory-computing device described in Embodiment 1. Utilizing the device's non-volatile storage and electrically controlled switching characteristics, by designing a series connection of two devices, Unit A and Unit B, and an additional reference device, Ref Unit, a specific V_comp sequence is applied to achieve input-related state switching. The circuit connection is as follows: Figure 3 As shown, the specific design steps include the following:

[0136] S1. Write input states IN1 and IN2. Apply illumination V_write_A1 to Unit A or write IN1 directly through V_write_A2, storing the IN1 value as a magnetic state. Similarly, apply illumination V_write_B1 to Unit B or write IN2 directly through V_write_B2, storing the IN2 value as a magnetic state. For the reference device Ref Unit, apply preset illumination V_write_ref1 or write LRS'1' directly.

[0137] S2. In the calculation phase, a fixed-polarity V_comp is applied between the third gate electrode 107 and the second gate electrode 103 of the device, where the third gate electrode 107 is connected to the positive terminal of V_comp, and the second gate electrode 103 is connected to the negative terminal of V_comp. This V_comp attempts to flip all devices to the '0' state HRS. The intensity of the spin-orbit moment generated by V_comp... It is proportional to the vertical current I_vertical flowing through the tunnel junction.

[0138] When IN1=0, IN2=0, State_A=HRS, and State_B=HRS, the total resistance R_total is at its maximum, and I_vertical is at its minimum. Weakest, insufficient to flip any device. Unit A and Unit B maintain HRS'0';

[0139] When IN1=0, IN2=1, State_A=HRS, and State_B=LRS, the total resistance R_total is moderate. Unit A may not be able to flip to the high resistance state, but Unit B may be able to or not be able to flip to the low resistance state. The design needs to ensure that Unit B is flipped from LRS to HRS'0' while Unit A remains at HRS'0'.

[0140] When IN1=1, IN2=0, State_A=LRS, and State_B=HRS, as above, the total resistance R_total remains medium, Unit A is flipped from LRS to HRS'0', while Unit B remains HRS'0';

[0141] When IN1=1, IN2=1, State_A=LRS, and State_B=LRS, the total resistance R_total is at its minimum. Meanwhile, I_vertical is at its maximum. It is the most powerful, capable of flipping both devices from LRS'1' to HRS'0'.

[0142] Therefore, the current threshold I for spin orbital moment reversal must be precisely controlled. c (such that I_vertical < I when any input is '0') c < I_vertical when both inputs IN1 and IN2 are '1'); and When any input is '0' < Critical torque < (When both inputs IN1 and IN2 are '1'). The current is sufficient to flip the Ref Unit to HRS'0 if and only if IN1=1 and IN2=1.

[0143] In the S3 reading phase, the Ref Unit is pre-written into LRS'1' before step S2. When V_comp is applied, the Ref Unit is concatenated with Unit A and Unit B, undergoing the same I_vertical and... The Ref Unit will only be flipped to HRS'0' when I_vertical is large enough that IN1=1 and IN2=1. Otherwise, if I_vertical is not large enough, the Ref Unit remains at LRS'1'. When the Ref Unit is read as HRS'0', the output OUT=1 because the AND condition is not met, and the Ref Unit is not flipped; when the Ref Unit is read as LRS'1', the output OUT=0 because the AND condition is met, and the Ref Unit is flipped.

[0144] Understandably, traditional AND gate circuits typically consist of multiple transistors, which suffer from problems such as separation of storage and computation, complex signal conversion, limited integration, high power consumption, and insufficient magnetic control capability. This embodiment solves the problem of low magnetic moment reversal efficiency in traditional magnetic materials by precisely controlling the current threshold of spin-orbit moment reversal, ensuring correct logic operations under different input conditions and improving the reliability and accuracy of logic operations. The flat two-dimensional material interface and absence of lattice mismatch in van der Waals heterojunctions reduce leakage current and interface defects, further optimizing power consumption.

[0145] Example 4

[0146] This embodiment provides a method for implementing an OR gate using the integrated sensor-memory-computing device described in Embodiment 1. Utilizing the non-volatile storage and electrically controlled switching characteristics of the device, the input-related state switching is achieved by designing the connection of the three devices, Unit A, Unit B, and Out Unit, and applying a specific V_comp sequence. The circuit connection is as follows: Figure 4 As shown, the specific design steps include the following:

[0147] S1. Write the input states IN1 and IN2. Apply the illumination of IN1 to Unit A via V_write_A1 or directly write IN1 via V_write_A2, and store the IN1 value as a magnetic state. Similarly, apply the illumination of IN2 to Unit B via V_write_B1 or directly write IN2 via V_write_B2, and store the IN2 value as a magnetic state. For the output device Out Unit, apply the preset illumination via V_write_out1 or directly write HRS'0' to it.

[0148] S2. In the calculation phase, the third gate electrode 107 of the three devices is connected to the positive terminal of voltage V_comp, and the second gate electrode 103 of the three devices is connected to the negative terminal of voltage V_comp. By applying an electric field V_comp, the polarity is fixed, and the Out Unit is flipped to LRS'1'. When Unit A or Unit B is LRS'1', the equivalent resistance between the second gate electrode 103 and the third gate electrode 107 decreases, making the electric field strong enough to flip the Out Unit; when both inputs IN1 and IN2 are HRS'0', the equivalent resistance between the second gate electrode 103 and the third gate electrode 107 is high, making the electric field weak enough not to flip the Out Unit.

[0149] S3. During the reading phase, the resistance between the first gate electrode 101 and the fourth gate electrode 109 of the Out Unit is measured, and the resistance status is directly output as a result.

[0150] It is understood that this embodiment completes the state reading by measuring the resistance between the first gate electrode and the fourth gate electrode of the output unit. This eliminates the need for complex signal amplification or conversion circuits, significantly shortens the total time of logic operations, simplifies the overall circuit design, and reduces manufacturing costs and system complexity.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. An integrated sensing and computing device based on atomically thin van der Waals heterojunctions, characterized in that, The substrate (100), the first gate electrode (101), the first two-dimensional van der Waals alternating magnetic material layer (102), the second gate electrode (103), the first two-dimensional van der Waals ferromagnetic material layer (104), the two-dimensional van der Waals insulating material layer (105), the second two-dimensional van der Waals ferromagnetic material layer (106), the third gate electrode (107), the second two-dimensional van der Waals alternating magnetic material layer (108), the fourth gate electrode (109) and the packaging layer (110) are sequentially stacked from bottom to top. The thicknesses of the first two-dimensional van der Waals alternating magnetic material layer (102), the first two-dimensional van der Waals ferromagnetic material layer (104), the two-dimensional van der Waals insulating material layer (105), the second two-dimensional van der Waals ferromagnetic material layer (106) and the second two-dimensional van der Waals alternating magnetic material layer (108) are all 1-10 atomic layers.

2. The atomically sharp van der Waals heterojunction-based sensing and computing integrated device of claim 1, wherein The substrate (100) is a Si, SiO2, SiC, AlN, Ga2O3 or PDMS flexible substrate.

3. The atomically sharp van der Waals heterojunction-based sensing and computing integrated device of claim 1, wherein The materials of the first gate electrode layer (101), the second gate electrode layer (103), the third gate electrode layer (107) and the fourth gate electrode layer (109) are independently selected from Au / Cr composite electrodes, graphene, TiS2, NbS2 or alpha-In2Se3.

4. The atomistic layer van der Waals hetero-junction based sensing and computing integrated device of claim 1, wherein, The materials of the first two-dimensional van der Waals alternating magnetic material layer (102) and the second two-dimensional van der Waals alternating magnetic material layer (108) are independently selected from RuO2, CrSb, MnTe, Fe2Se2, Fe2Te2, transition metal selenium oxide or transition metal tellurium oxide.

5. The atomistic layer van der Waals heterostructure-based neuromorphic and in-memory computing integrated device of claim 1, wherein The materials of the first two-dimensional van der Waals ferromagnetic material layer (104) and the second two-dimensional van der Waals ferromagnetic material layer (106) are independently selected from Fe3GeTe2, Fe3GaTe2, magnetic metal chalcogenide, magnetic metal halide or magnetic metal carbide.

6. The atomistic layer van der Waals heterostructure-based neuromorphic and in-memory computing integrated device of claim 1, wherein The two-dimensional van der Waals insulating material layer (105) is independently selected from h-BN, Bi2Te3, MnBi2Te4, Bi2O2Se, Bi2SeO5 or transition metal chalcogenide.

7. The atomistic layer van der Waals heterostructure-based neuromorphic and in-memory computing integrated device of claim 1, wherein The packaging layer (110) is independently selected from h-BN, Ga2O3, HfO2 or Al2O3.

8. A method for preparing the computing and storing integrated device according to any one of claims 1-7, characterized in that, The method comprises the following steps: S1, forming a first gate electrode layer (101) on a substrate (100); S2, forming a first two-dimensional van der Waals alternating magnetic material layer (102) on the first gate electrode layer (101); S3, forming a first two-dimensional van der Waals ferromagnetic material layer (104) on the first two-dimensional van der Waals alternating magnetic material layer (102), and then forming a second gate electrode layer (103); S4, forming a two-dimensional van der Waals insulating material layer (105) on the first two-dimensional van der Waals ferromagnetic material layer (104); S5, forming a second two-dimensional van der Waals ferromagnetic material layer (106) on the two-dimensional van der Waals insulating material layer (105), and then forming a third gate electrode layer (107); S6, forming a second two-dimensional van der Waals alternating magnetic material layer (108) on the second two-dimensional van der Waals ferromagnetic material layer (106); S7. Forming a fourth gate electrode layer (109) on the second two-dimensional van der Waals alternating magnetic material layer (108), and then forming an encapsulation layer (110) to obtain the memory and logic integrated device.

9. The method of claim 8, wherein the method further comprises: The gate electrode layer forming process in steps S1, S3, S5 and S7 includes any one or more of magnetron sputtering or electron beam evaporation combined with photolithography and etching, liquid metal printing combined with annealing, photolithography patterning combined with pulsed laser deposition.

10. The method of claim 8, wherein the method further comprises: The two-dimensional van der Waals material layer forming process in steps S2, S3, S4, S5 and S6 includes any one or more of chemical vapor deposition, molecular beam epitaxy, and polymer-assisted dry transfer technology.

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