Method of manufacturing semiconductor-on-insulator wafer having charge trapping layer of controlled stress

Abstract

A method of making a multilayer structure includes providing a single crystal semiconductor handling substrate including a front surface, a back surface, a circumferential edge connecting the front and back surfaces, and a central plane between the front and back surfaces. The single crystal semiconductor treatment substrate has a minimum body region resistivity of at least about 500 Ohm-cm. The method also includes depositing a semiconductor layer on the front surface of the single crystal semiconductor treatment substrate. Deposition of the semiconductor layer is performed by two or more cycles of depositing a portion of the semiconductor layer and interrupting the deposition to anneal the portion of the semiconductor layer after depositing the portion of the semiconductor layer.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Patent Application No. 18 / 162,951, filed February 1, 2023, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates generally to the field of semiconductor wafer manufacturing. More specifically, the present disclosure relates to a method of preparing a handle substrate for manufacturing a semiconductor-on-insulator (e.g., silicon-on-insulator) structure, and more particularly, the present disclosure relates to a method for manufacturing a polycrystalline semiconductor layer on a handle wafer of a semiconductor-on-insulator structure, wherein the stress of the polycrystalline semiconductor layer is controlled without creating crystalline slip defects in the handle wafer. BACKGROUND

[0004] Semiconductor wafers are generally prepared from a single crystal ingot (e.g., a silicon ingot) that is trimmed and lapped to have one or more flats or notches for proper orientation of the wafer in subsequent processes. The ingot is then cut into individual wafers. Although reference will be made herein to semiconductor wafers constructed of silicon, other materials (e.g., germanium, silicon carbide, silicon germanium, or gallium arsenide) can be used to prepare semiconductor wafers.

[0005] Semiconductor wafers (e.g., silicon wafers) can be used to prepare composite layer structures. Composite layer structures (e.g., semiconductor-on-insulator, and more specifically, silicon-on-insulator (SOI) structures) generally include a handle wafer or layer, a device layer, and an insulating (i.e., dielectric) film (typically an oxide layer) between the handle and device layers. Generally, the thickness of the device layer is generally between 0.01 microns to 20 microns, such as a thickness between 0.05 microns to 20 microns. Generally, composite layer structures such as silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and silicon-on-quartz are produced by bringing two wafers into intimate contact and then performing a heat treatment to strengthen the bond.

[0006] After thermal annealing, the bonded structure is subjected to further processing to remove a substantial portion of the donor wafer to achieve layer transfer. For example, a wafer thinning technique (e.g., etching or lapping) commonly referred to as bonded SOI (i.e., BESOI) can be used in which a silicon wafer is bonded to a handle wafer and then etched away slowly until only a thin layer of silicon remains on the handle wafer. See, for example, U.S. Patent No. 5,189,500, the disclosure of which is incorporated herein by reference as if set forth in its entirety. This method is time consuming and expensive, wastes one of the substrates, and generally does not have suitable thickness uniformity for layers thinner than a few microns.

[0007] Another common method of implementing layer transfer utilizes hydrogen implantation followed by thermal induced layer splitting. Particles (e.g., hydrogen atoms or a combination of hydrogen atoms and helium atoms) are implanted at a specific depth below the front surface of the donor wafer. The implanted particles form a splitting plane in the donor wafer at the specific depth at which they were implanted. The surface of the donor wafer is cleaned to remove organic compounds deposited on the wafer during the implantation process.

[0008] The front surface of the donor wafer is then bonded to a handle wafer by a hydrophilic bonding process to form a bonded wafer. Prior to bonding, the donor wafer and / or the handle wafer can be activated by exposing the surface of the wafer to a plasma containing, for example, oxygen or nitrogen. In a process commonly referred to as surface activation, exposure to the plasma changes the structure of the surface, activating the surface of one or both of the donor wafer and the handle wafer to be hydrophilic. The wafers are then pressed together and a bond is formed between them. This bond can be relatively weak and can be strengthened prior to further processing.

[0009] In some processes, the hydrophilic bond between the donor wafer and the handle wafer (i.e., the bonded wafer) is strengthened by heating or annealing the bonded wafer pair. In some processes, wafer bonding can occur at low temperatures (e.g., between about 300°C and 500°C). In some processes, wafer bonding can occur at high temperatures (e.g., between about 800°C and 1100°C). The high temperatures cause covalent bonds to form between the adjacent surfaces of the donor wafer and the handle wafer, thus solidifying the bond between the donor wafer and the handle wafer. At the same time that the bonded wafers are heated or annealed, the particles implanted earlier in the donor wafer weaken the splitting plane.

[0010] A portion of the donor wafer is then separated (i.e., split) from the bonded wafer along the splitting plane to form an SOI wafer structure. Splitting can be performed by placing the bonded wafer in a fixture in which a mechanical force is applied perpendicular to opposing sides of the bonded wafer to pull the portion of the donor wafer away from the bonded wafer. According to some methods, a suction cup is used to apply the mechanical force. Separation of the portion of the donor wafer is initiated by applying a mechanical wedge at the edge of the bonded wafer at the splitting plane to initiate crack propagation along the splitting plane. The mechanical force applied by the suction cup then pulls the portion of the donor wafer away from the bonded wafer, thus forming an SOI wafer.

[0011] According to other methods, the bonded pair can instead be subjected to high temperatures for a period of time to separate the portion of the donor wafer from the bonded wafer. Exposure to the high temperatures causes a crack to initiate and propagate along the splitting plane, thus separating the portion of the donor wafer. This method can promote better uniformity of the transferred layer and allow for recycling of the donor wafer, but generally requires heating the implanted and bonded pair to temperatures close to 500°C.

[0012] The use of high resistivity semiconductor-on-insulator (e.g., silicon-on-insulator) wafers for radio frequency (RF) related devices (e.g., antenna switches) offers benefits over conventional substrates in terms of cost and integration. In using conductive substrates for high frequency applications, it is necessary but not sufficient to use a substrate wafer with high resistivity in order to reduce parasitic power loss and minimize inherent harmonic distortion. Thus, the resistivity of the handle wafer for RF devices is typically greater than about 500 Ohm-cm or greater than about 1000 Ohm-cm. Referring now to Figure 1 , a silicon-on-insulator structure 2 is shown that includes a very high resistivity silicon wafer 4, a buried oxide (BOX) layer 6, and a silicon device layer 10. This substrate is prone to forming a high conductivity charge inversion or accumulation layer 12 at the BOX / handle interface to cause generation of free carriers (electrons or holes) that reduce the effective resistivity of the substrate and cause parasitic power loss and device nonlinearity when the device is operated at RF frequencies. These inversion / accumulation layers can be due to BOX fixed charges, oxide trapped charges, interface trapped charges, and even DC bias applied to the device itself.

[0013] Thus, there is a need for a method to trap charges in any induced inversion or accumulation layer so that the high resistivity of the substrate is maintained even in very near surface regions. A charge trapping layer (CTL) between a high resistivity handle substrate and a buried oxide (BOX) is known to improve the performance of RF devices fabricated using SOI wafers. Several methods have been suggested to form these high interface trapping layers. For example, referring now to Figure 2 , one method of creating a semiconductor-on-insulator 20 (e.g., silicon-on-insulator or SOI) with a CTL for RF device applications is based on depositing an undoped polysilicon thin film 28 on a silicon substrate 22 with high resistivity and then forming a stack of oxide 24 and a top silicon layer 26 thereon. The polysilicon layer 28 acts as a high defectivity layer between the silicon substrate 22 and the buried oxide layer 24. See Figure 2 , Figure 2 A polysilicon thin film is depicted in a silicon-on-insulator structure 20 as a charge trapping layer 28 between a high resistivity substrate 22 and a buried oxide layer 24. An alternative method is to implant heavy ions to create a near surface damage layer. A device (e.g., a radio frequency (RF) device) is built in the top silicon layer 26.

[0014] Academic research has shown that a polysilicon layer between the oxide and the substrate improves device isolation, reduces transmission line losses, and reduces harmonic distortion. See, for example: H. S. Gamble et al., "Microwave Guided Wave Lett." 9(10), pp. 395-397, 1999; D. Lederer, R. Lobet, and J. P. Raskin, "Enhanced high resistivity SOI wafers for RF applications," IEEE Intl. SOI Conf., pp. 46-47, 2004; D. Lederer and J. P. Raskin, "New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increased substrate resistivity," IEEE Electron Device Letters, vol. 26, no. 11, pp. 805-807, 2005; D. Lederer, B. Aspar, C. Laghae, and J. P. Raskin, "Performance of RF passive structures and SOI MOSFETs transferred on a passivated HR SOI substrate," IEEE International SOI Conference, pp. 29-30, 2006; and Daniel C.Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer, by Kerret et al., Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008 IEEE Topical Meeting, pp. 151-154, 2008. SUMMARY

[0015] Embodiments disclosed herein include methods of fabricating a semiconductor-on-insulator (e.g., silicon-on-insulator) wafer having a semiconductor charge trapping layer deposited onto a semiconductor handle substrate, where stress in the semiconductor charge trapping layer is controlled without creating crystalline slip defects in the handle wafer. Suitably, the stress in the semiconductor charge trapping layer is controlled such that compressive stress induced by depositing the semiconductor charge trapping layer is converted to tensile stress. The methods described herein can include annealing the semiconductor charge trapping layer at a relatively low temperature. The annealing can occur intermittently during deposition of the semiconductor charge trapping layer, where deposition is paused after depositing a portion of the semiconductor charge trapping layer and annealing the deposited portion. The deposited portion can be annealed at an annealing temperature that is close to or substantially equal to the deposition temperature.

[0016] In one aspect, a method of fabricating a multilayer structure is provided. The method includes providing a single-crystalline semiconductor handle substrate. The single-crystalline semiconductor handle substrate includes two generally parallel major surfaces, one of which is a front surface of the single-crystalline semiconductor handle substrate and another of which is a back surface of the single-crystalline semiconductor handle substrate; a circumferential edge connecting the front and back surfaces of the single-crystalline semiconductor handle substrate; and a central plane between the front and back surfaces of the single-crystalline semiconductor handle substrate. The single-crystalline semiconductor handle substrate has a minimum bulk resistivity of at least about 500 Ohm-cm. The method also includes depositing a semiconductor layer on the front surface of the single-crystalline semiconductor handle substrate. Depositing the semiconductor layer is performed by two or more cycles of depositing a portion of the semiconductor layer and interrupting the deposition after depositing the portion of the semiconductor layer to anneal the portion of the semiconductor layer.

[0017] In another aspect, a method of preparing a multilayer structure is provided. The method includes providing a single crystalline semiconductor handle substrate. The single crystalline semiconductor handle substrate includes two generally parallel major surfaces, one of which is a front surface of the single crystalline semiconductor handle substrate and another of which is a back surface of the single crystalline semiconductor handle substrate; a circumferential edge connecting the front and back surfaces of the single crystalline semiconductor handle substrate; and a central plane located between the front and back surfaces of the single crystalline semiconductor handle substrate. The single crystalline semiconductor handle substrate has a minimum bulk resistivity of at least about 500 Ohm-cm. The method also includes depositing a polycrystalline semiconductor seed layer on the front surface of the single crystalline semiconductor handle substrate and annealing the polycrystalline semiconductor seed layer. The method also includes depositing a first layer of polycrystalline semiconductor material on the annealed polycrystalline semiconductor seed layer at a deposition temperature and annealing the first layer of polycrystalline semiconductor material at a temperature less than the temperature at which the polycrystalline semiconductor seed layer was annealed.

[0018] Other advantages and features of the disclosed embodiments are partly apparent and partly pointed out below. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a depiction of a silicon-on-insulator wafer including a high resistivity substrate and a buried oxide layer.

[0020] Figure 2 is a depiction of a silicon-on-insulator wafer (SOI wafer) including a polysilicon charge trapping layer located between a high resistivity substrate and a buried oxide layer.

[0021] Figure 3 is a depiction of an exemplary single crystalline semiconductor handle substrate for use in preparing a multilayer structure according to the methods of the present disclosure.

[0022] Figure 4 is a depiction of a multilayer structure prepared according to the methods of the present disclosure, the multilayer structure including Figure 3 a handle substrate having a semiconductor charge trapping layer deposited on a front surface thereof.

[0023] Figure 5 is a depiction of an exemplary single crystalline semiconductor donor substrate for use in preparing a multilayer structure according to the methods of the present disclosure, the donor substrate having a dielectric layer formed on a front surface thereof.

[0024] Figure 6 is a depiction of a multilayer structure prepared according to the methods of the present disclosure, the multilayer structure including a Figure 4 semiconductor charge trapping layer bonded to a dielectric layer of a donor substrate. Figure 5

[0025] ​Figure 7 is a depiction of a multilayer structure prepared according to the methods of the present disclosure, the multilayer structure comprising a handle substrate having a semiconductor charge trapping layer, a dielectric layer, and a semiconductor device layer deposited on a front surface thereof.

[0026] Figure 8 A probability plot showing a comparison of changes in 3-point wafer bow after deposition of a polycrystalline semiconductor layer and single deposition post-anneal and after deposition of a polycrystalline semiconductor layer with intermittent anneal performed during.

[0027] Figure 9 A probability plot showing a comparison of changes in 3-point wafer bow after deposition of a polycrystalline semiconductor layer and single deposition post-anneal and after deposition of a polycrystalline semiconductor layer with intermittent anneal performed during, wherein the deposited polycrystalline semiconductor layer has been polished.

[0028] Figure 10 A probability plot showing a comparison of changes in wafer SFQR after deposition of a polycrystalline semiconductor layer and single deposition post-anneal and after deposition of a polycrystalline semiconductor layer with intermittent anneal performed during. DETAILED DESCRIPTION

[0029] In example embodiments, methods are provided that include depositing a semiconductor charge trapping layer (also referred to herein as a "semiconductor layer" or a "charge trapping layer") on a single crystalline semiconductor handle substrate (e.g., a single crystalline semiconductor handle layer, such as a single crystalline silicon handle wafer). The charge trapping layer can be deposited in various processes, for example, by chemical vapor deposition. The single crystalline semiconductor handle wafer including the charge trapping layer can be used to fabricate a semiconductor-on-insulator (e.g., silicon-on-insulator) structure. Suitably, the charge trapping layer includes a polycrystalline semiconductor material (e.g., silicon, SiGe, SiC, and Ge) and the polycrystalline semiconductor material is deposited onto an exposed front surface of a single crystalline semiconductor handle substrate (e.g., wafer) having a high resistivity. The charge trapping layer can also be referred to as a "polycrystalline semiconductor layer." In some embodiments, the charge trapping layer can additionally and / or alternatively include an amorphous semiconductor material. In some embodiments, a dielectric layer (also referred to herein as a "buried oxide layer" or a "BOX layer") is bonded to and / or formed on the polycrystalline semiconductor layer (e.g., via bonding a single crystalline semiconductor handle substrate having a dielectric layer to the polycrystalline layer) to form a multilayer structure including the handle substrate, the polycrystalline semiconductor layer, and the dielectric layer. The polycrystalline semiconductor layer acts as a high density trapping region to prevent and / or quench the conductivity of the high resistivity handle substrate, which can otherwise occur at the interface between the high resistivity handle substrate and the dielectric layer. The polycrystalline semiconductor layer also prevents induced charge inversion or accumulation layer formation in the semiconductor-on-insulator structure prepared by the methods described herein, which can contribute to power loss and non-linear behavior in electronic devices designed for radio frequency (RF) device operation.

[0030] One problem associated with depositing a semiconductor material to produce a charge trapping layer is that the deposited semiconductor material can have internal compressive stress created by diffusing deposited semiconductor (e.g., silicon) atoms into the semiconductor (e.g., polycrystalline semiconductor, such as polysilicon) grain boundaries. The compressive stress in the deposited semiconductor layer can cause warping and / or bowing of the resulting semiconductor-on-insulator (SOI) structure that makes the structure unsuitable for subsequent use in device fabrication. SOI structures with high warping and / or bowing can be difficult to handle on equipment with precise wafer handling automation and cause problems with focus during photolithography steps, among other issues. Thus, semiconductor handling substrates with deposited charge trapping layers must have a suitable degree of warping and bowing. This can be controlled during the semiconductor layer deposition process or can be corrected in subsequent processing (e.g., polishing). In addition, other aspects of SOI structure fabrication can also negatively affect and / or contribute to warping and bowing of the structure, such as forming a dielectric (e.g., buried oxide) layer on the semiconductor charge trapping layer. For example, the compressive stress created by the semiconductor layer deposition and buried oxide layer formation (e.g., by thermal oxidation or chemical vapor oxide deposition) is additive and, when combined, can cause warping and / or bowing of the SOI structure to be outside of specification.

[0031] In some processes, the stress in the deposited semiconductor charge trapping layer (or "semiconductor layer") can be controlled by a post-deposition anneal step that allows interstitial atoms in the semiconductor layer to diffuse out of the grain boundaries. This creates a tensile stress in the semiconductor layer that can appropriately offset the compressive stress created by the buried oxide layer and facilitate minimizing the overall warping and bowing of the wafer. Typically, the semiconductor layer is annealed at a temperature greater than the temperature used for semiconductor layer deposition, such as a temperature greater than 1000 °C or greater than 1050 °C. However, the additional heat treatment can cause other defects in the handling substrate. For example, the high temperature and time required for interstitial semiconductor atoms to diffuse out of the grain boundaries can cause crystalline slip defects in the handling substrate. Even when warping and bowing issues are corrected, the slip defects will also make the handling substrate unsuitable for subsequent device fabrication. High resistivity handling substrates (e.g., handling substrates with a resistivity of at least about 500 Ohm-cm) for SOI structures and RF devices are particularly susceptible to crystalline slip due to the lack of lattice and interstitial atoms (e.g., dopant atoms and / or interstitial oxygen atoms) that can otherwise strengthen the wafer.

[0032] The example methods described herein include depositing a semiconductor charge trapping layer (or "semiconductor layer") on a single-crystalline semiconductor handle substrate and annealing the semiconductor layer at or near (e.g., within 10 °C, within 5 °C, or within 1 °C) the deposition temperature. Suitably, the example methods described herein provide a semiconductor layer having tensile stress rather than compressive stress due to interstitial atom diffusion out of grain boundaries of the deposited semiconductor material induced by annealing the semiconductor layer. The tensile stress in the semiconductor layer counteracts compressive stress introduced subsequently, e.g., by a dielectric layer bonded to and / or formed on the semiconductor layer, thereby controlling overall bowing and warping of the multilayer structure. Advantageously, annealing the semiconductor layer to create tensile stress (performed according to the methods described herein) also reduces or eliminates unwanted defects that would otherwise be generated in the single-crystalline semiconductor handle wafer by higher thermal processing. For example, in various embodiments, the single-crystalline semiconductor handle wafer is a high-resistivity wafer (e.g., having a resistivity greater than about 500 Ohm-cm), and the example methods described herein include annealing the semiconductor layer intermittently to diffuse interstitial atoms from grain boundaries at a relatively lower temperature (e.g., less than 1000 °C) to reduce or eliminate crystalline slip defects that would otherwise occur in the high-resistivity wafer at higher annealing temperatures.

[0033] In the example methods described herein, the semiconductor charge trapping layer (or “semiconductor layer”) is suitably produced by two or more cycles of depositing a portion of the semiconductor layer and interrupting the deposition process to anneal the deposited portion. In other words, deposition of the semiconductor layer is performed by a cyclical process in which a portion of the semiconductor layer is deposited, deposition is interrupted by pausing the deposition gas flow, the portion of the semiconductor layer is annealed (suitably at or near the deposition temperature), and a next portion of the semiconductor layer is deposited on the previously annealed portion. Each portion of the semiconductor layer charge trapping layer can also be referred to herein as a “layer of semiconductor material.” Thus, in the example methods, the semiconductor layer is produced by depositing a first layer of semiconductor material, annealing the first layer of semiconductor material, depositing a second layer of semiconductor material on the annealed first layer, annealing the second layer of semiconductor material, and so on. By depositing the semiconductor layer in this manner, the semiconductor layer can include, for example, two or more annealed layers, such as three or more annealed layers of semiconductor material, or between 3 and about 50 annealed layers, or between 3 and about 40 annealed layers, or between 3 and about 30 annealed layers, or between 3 and about 25 annealed layers, or between 3 and about 20 annealed layers, or between 3 and about 10 annealed layers of semiconductor material. A large number of layers of semiconductor material can be deposited and annealed to produce the semiconductor charge trapping layer, limited in part by throughput requirements and the minimum practical layer thickness that can be deposited, which can be about 20 nanometers. In some embodiments, the thickness of each annealed layer of semiconductor material (i.e., each portion of the semiconductor charge trapping layer) can be between 0.05 micrometers (pm) and 5 pm, such as between 0.1 pm and 1 pm, and the semiconductor charge trapping layer can have a thickness between 0.1 pm and 50 pm, such as between 1 pm and 10 pm. The thickness of each portion of the semiconductor charge trapping layer can depend on the desired thickness of the charge trapping layer and the number of cycles performed to produce the charge trapping layer. Each deposited portion of the semiconductor charge trapping layer is suitably annealed at or near the deposition temperature, and the annealing is performed to diffuse interstitial atoms out of the grain boundaries of the deposited layers of semiconductor material. It has been observed that intermittent annealing of portions of the semiconductor layer at or near the deposition temperature contributes to significantly improved site planarity, which can be measured as site front reference minimum square focal plane range (SFQR). Furthermore, the intermittent annealing during deposition can reduce or eliminate the need for annealing of the semiconductor layer after higher temperature deposition. This reduction otherwise correlates with processing time associated with ramp-up deposition post-annealing, thereby improving overall efficiency and throughput.

[0034] The methods described herein can also facilitate control of the bow and warp of semiconductor-on-insulator structures, such as silicon-on-insulator, which include a dielectric layer of a single-crystalline semiconductor donor substrate bonded to a semiconductor charge trapping layer of a handle substrate. The dielectric layer can be formed as a semiconductor oxide film, such as a silicon oxide film, on a front surface of the donor substrate, such as a single-crystalline silicon donor substrate. Due to the difference in the coefficient of thermal expansion between silicon oxide and silicon, high intrinsic compressive stress is generated in the oxide film on the silicon wafer, for example. In embodiments in which the oxide on the surface of the donor structure contributes to the dielectric oxide film, the final semiconductor-on-insulator structure has oxide from only one wafer and thus is distorted by the compressive oxide stress. The tensile stress generated in the semiconductor layer counteracts the compressive stress in the dielectric layer, thereby reducing the overall bow and warp of the semiconductor-on-insulator structure. It has also been observed that polishing, such as by chemical mechanical polishing, of the semiconductor layer generated by the intermittent anneal according to the present disclosure results in greater tensile stress, which contributes to the negative bow of the handle substrate and further balances the compressive stress induced by the dielectric layer, thereby reducing the bow and warp of the final semiconductor-on-insulator structure.

[0035] Reference is now made to the drawings, Figure 3 which show a single-crystalline semiconductor substrate 100 for use in the example methods described herein. The substrate 100 can be used as a semiconductor handle substrate, such as a single-crystalline semiconductor handle wafer. The substrate 100 can also be used as a semiconductor donor substrate, such as a single-crystalline semiconductor donor wafer (e.g. Figure 5 The donor substrate 200 shown in FIG. 1). As the description proceeds, the terms "substrate" and "wafer" can be used interchangeably. In general, the substrate 100 includes two major parallel surfaces. One of the parallel surfaces is a front surface 102 of the substrate, and the other parallel surface is a back surface 104 of the substrate 100. The substrate 100 also includes a circumferential edge 106 connecting the front surface 102 and the back surface 104, a bulk region 108 between the front surface 102 and the back surface 104, and a center plane C P between the front surface 102 and the back surface 104. The substrate 100 additionally includes an imaginary center axis C P that is generally perpendicular to the center plane C A . The radial length of the substrate 100 is measured as the distance between the center axis C A and the circumferential edge 106. The diameter of the substrate 100 is measured across the circumferential edge 106. Additionally, because semiconductor substrates 100, such as silicon wafers, typically have some total thickness variation (TTV), warp, and bow, the midpoint between each point on the front surface 102 and each point on the back surface 104 can not fall exactly in a plane. In practice, however, the TTV, warp, and bow are typically quite small such that the point immediately adjacent the midpoint can be referred to as falling within an imaginary center plane C P that is approximately equidistant between the front surface 102 and the back surface 104.

[0036] Prior to any operations described herein, the front surface 102 and rear surface 104 of substrate 100 may be substantially identical. For convenience only and generally to distinguish the surfaces on which the exemplary methods are performed, surface 102 or 104 is referred to as the "front surface" or "rear surface," respectively. In the context of this disclosure, the front surface 102 of a single-crystal semiconductor disposal substrate 100 (e.g., a single-crystal silicon disposal wafer) refers to a bonding structure or a semiconductor-on-insulator structure (e.g., a semiconductor-on-insulator structure). Figure 6 and 7 The main surface of the substrate 100 is the inner surface of the structure shown in the diagram. A charge trapping layer 110 is formed on the previously surface 102. Figure 4 (As shown in the diagram). Therefore, the back surface 104 of the single-crystal semiconductor treatment substrate 100 refers to the main surface of the outer surface of the bonding structure or the semiconductor-on-insulator structure.

[0037] In some embodiments, the front surface 102 of the single-crystal semiconductor substrate 100 may include a dielectric layer (e.g., a silicon dioxide layer) that forms the buried oxide (BOX) layer in the final structure. For example, when the substrate 100 is a single-crystal semiconductor donor structure 200 ( Figure 5 When (as shown in the diagram), dielectric layer 210 may be formed on the front surface 202 of the donor substrate 200 forming the BOX layer in the final structure. The rear surface 204 of the single-crystal semiconductor treatment substrate 200 (e.g., a single-crystal silicon donor wafer) refers to a bonding structure or a semiconductor-on-insulator structure (e.g., a single-crystal silicon donor wafer). Figure 6 and 7 The main surface of the outer surface of the structure shown in the diagram. As described above for substrate 100, Figure 5 The substrate 200 shown also includes a circumferential edge 206 connecting the front surface 202 and the rear surface 204, a body region 208 located between the front surface 202 and the rear surface 204, and a central plane C located between the front surface 202 and the rear surface 204. P2 Generally perpendicular to the central plane C P2 Imaginary central axis C A2 The radial length of substrate 200 was measured to be the central axis C. A2 The distance between the substrate 200 and the circumferential edge 206, and the diameter of the substrate 200 is measured across the circumferential edge 206. As described in further detail below, during the bonding and wafer thinning operations, the single-crystal semiconductor donor substrate 200 forms a semiconductor-on-insulator (e.g., silicon-on-insulator) composite structure 400. Figure 7 Semiconductor device layer 402 (as shown in the figure).

[0038] The single-crystal semiconductor handle substrate 100 and the single-crystal semiconductor donor substrate 200 can be single-crystal semiconductor wafers. In various embodiments, the semiconductor wafers include a semiconductor material selected from the group consisting of silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. Single-crystal semiconductor wafers, such as the single-crystal silicon handle wafer 100 and the single-crystal silicon donor wafer 200, typically have a nominal diameter of at least about 150 mm, at least about 200 mm, at least about 300 mm, or at least about 450 mm. Wafer thickness can vary from about 250 pm to about 1500 pm, such as between about 300 pm to about 1000 pm, suitably in a range of about 500 pm to about 1000 pm. In some particular embodiments, the wafer thickness can be about 775 pm. Wafer thickness is measured as the distance between opposing major surfaces, such as between the front surface 102, 202 and the back surface 104, 204.

[0039] In certain embodiments, the single-crystal semiconductor handle substrate 100 and the single-crystal semiconductor donor substrate 200 include single-crystal silicon wafers cut from single-crystal ingots grown according to the Czochralski crystal growth method or the float zone growth method. Such methods, as well as silicon cutting, lapping, etching, and polishing techniques, are disclosed, for example, in Semiconductor Silicon Crystal Technology by F. Shimura, Academic Press, 1989, and Silicon Chemical Etching, edited by J. Grabmaier, Springer- Verlag, New York, 1982, the entire disclosures of which are incorporated herein by reference. Suitably, the wafers are polished and cleaned by methods known to those of skill in the art. See, for example, Handbook of Semiconductor Silicon Technology by W. C. O’Mara et al., Noyes Publications. The wafers can also be cleaned, for example, in SC1 / SC2 solutions. Suitably, the single-crystal silicon handle wafer 100 and the single-crystal silicon donor wafer 200 have mirror-polished front surface finishes that are free of surface defects, such as scratches and large particles.

[0040] In some embodiments, the single-crystalline semiconductor handle substrate 100 and the single-crystalline semiconductor donor substrate 200 have a concentration of interstitial oxygen generally achieved by Czochralski growth methods. In some embodiments, the substrates 100 and 200 have a concentration of interstitial oxygen between about 4 PPMA and about 18 PPMA. In some embodiments, the substrates 100 and 200 have a concentration of interstitial oxygen between about 10 PPMA and about 35 PPMA. Suitably, the substrates 100 and 200 have a concentration of interstitial oxygen no more than about 10 ppma. Interstitial oxygen can be measured according to SEMI MF 1188-1105.

[0041] In some embodiments, the single-crystalline semiconductor handle substrate 100 (e.g., a single-crystalline silicon handle wafer) has a relatively high minimum bulk resistivity. The single-crystalline semiconductor donor substrate 200 can also have a relatively high minimum bulk resistivity. High resistivity single-crystalline semiconductor substrates are generally cut from single-crystalline ingots grown by the Czochralski method or the float zone method. Single-crystalline semiconductor donor substrates cut from Czochralski grown ingots can be subjected to thermal annealing at temperatures ranging from about 600 °C to about 1000 °C to eliminate thermal donors caused by oxygen incorporated during crystal growth. In some embodiments, the single-crystalline semiconductor wafer has a minimum bulk resistivity of at least about 500 Ohm-cm, at least about 1000 Ohm-cm, or even at least about 3000 Ohm-cm, such as between about 500 Ohm-cm and about 100,000 Ohm-cm, between about 1000 Ohm-cm and about 100,000 Ohm-cm, between about 500 Ohm-cm and about 10,000 Ohm-cm, between about 750 Ohm-cm and about 10,000 Ohm-cm, between about 1000 Ohm-cm and about 10,000 Ohm-cm, between about 2000 Ohm-cm and about 10,000 Ohm-cm, between about 3000 Ohm-cm and about 10,000 Ohm-cm, or between about 3000 Ohm-cm and about 5000 Ohm-cm. Methods for preparing high resistivity wafers are known in the art, and such high resistivity wafers are available from commercial suppliers (e.g., Global Wafers Co., Ltd.).

[0042] In some embodiments, the back surface 104, 204 of the single-crystalline semiconductor substrates 100, 200 can be intentionally damaged by a sandblasting process or by an alkaline etch. In other embodiments, the back surface 104, 204 of the substrates 100, 200 is a polished surface free of surface defects (e.g., scratches and large particles).

[0043] The front surface 102 and optionally the back surface 104 of the single crystal semiconductor handle substrate 100 can be treated, for example, by an oxidation process to form an interface layer prior to forming the charge trapping layer 110. The interface layer can include a material selected from silicon dioxide, silicon nitride, and silicon oxynitride. In certain embodiments, the interface layer can comprise silicon dioxide. To form a silicon dioxide interface layer, the front surface 102 of the substrate 100 is oxidized prior to forming the charge trapping layer 110 such that the front surface 102 of the substrate 100 includes an oxide film. Oxidizing the front surface 102 can be accomplished by thermal oxidation (where some portion of the deposited semiconductor material film is consumed), CVD oxide deposition, and / or atomic layer deposition. In some embodiments, the single crystal semiconductor handle substrate 100, e.g., a single crystal silicon handle wafer, can be thermally oxidized in a furnace, e.g., an ASM A400 or ASM A412. In the oxidation environment, the temperature can range from 750 °C to 1200 °C. The oxidation environment atmosphere can be a mixture of an inert gas, e.g., Ar or N2, and O2. The oxygen content can vary from 1% to 10% or higher. In some embodiments, the oxidation environment atmosphere can be up to 100% oxygen ("dry oxidation"). In some embodiments, the oxidation environment atmosphere can include oxygen and ammonia, which is suitable for depositing silicon oxynitride. In some embodiments, the environment atmosphere can include a mixture of an inert gas, e.g., Ar or N2, and an oxidizing gas, e.g., O2 and water vapor ("wet oxidation"). In some embodiments, the environment atmosphere can include a mixture of an inert gas, e.g., Ar or N2, and an oxidizing gas, e.g., O2 and water vapor ("wet oxidation"), and a nitriding gas, e.g., ammonia. In some embodiments, the environment atmosphere can include a mixture of an inert gas, e.g., Ar or N2, and a nitriding gas, e.g., ammonia, which is suitable for depositing silicon nitride. In an exemplary embodiment, the single crystal semiconductor handle substrate 100 can be loaded into a vertical furnace, e.g., an ASM A400 or ASM A412. The temperature is ramped to the oxidation temperature with a mixture of N2and O2. At the desired temperature, water vapor can be introduced into the gas stream. After the desired oxide film thickness is obtained, the water vapor and O2are turned off and the furnace temperature is lowered and the substrate 100 is unloaded from the furnace. The oxidation layer on the front surface 102, the back surface 104, or both can be between about 100 Angstroms to about 100,000 Angstroms.

[0044] In some embodiments, the oxide layer can be relatively thin, for example between about 5 Angstroms to about 25 Angstroms, for example between about 10 Angstroms to about 15 Angstroms. A thin oxide layer can be obtained by exposure to an aqueous solution including an oxidizing agent, such as an SC1 and / or SC2 cleaning solution, on both sides of the semiconductor wafer. In some embodiments, the SC1 solution includes 5 parts of deionized water, 1 part of an aqueous H4OH solution (ammonium hydroxide, 29% by weight of NH3), and 1 part of an aqueous H2O2 solution (hydrogen peroxide, 30%). In some embodiments, the substrate 100 can be oxidized by exposure to an aqueous solution including an oxidizing agent, such as an SC2 solution. In some embodiments, the SC2 solution includes 5 parts of deionized water, 1 part of an aqueous HC1 solution (hydrochloric acid, 39% by weight), and 1 part of an aqueous H2O2 solution (hydrogen peroxide, 30%).

[0045] In some embodiments, the exposed front surface 102 of the single-crystalline semiconductor handle substrate 100 is not oxidized prior to forming the charge trapping layer 110.

[0046] Prior to forming the charge trapping layer 110 and optionally after oxidizing the front surface 102 of the single-crystalline semiconductor handle substrate 100, the single-crystalline semiconductor handle substrate 100 can be subjected to a pre-treatment operation including exposing the surfaces 102, 104 to an ambient atmosphere including a reducing agent and / or an etchant. Exposure to an ambient atmosphere including a reducing agent and / or an etchant can advantageously clean the front surface 102 and optionally the back surface 104 of the substrate 100, which can include an interfacial oxide front surface layer, and texture the front surface 102 for subsequent semiconductor material deposition. The handle substrate 100 can undesirably cause contaminants, such as organic contaminants and boron, aluminum, phosphorous, and the like, to deposit on the front and back surfaces 102, 104 of the handle substrate 100. The contaminants can interrupt the nucleation process of the subsequently deposited charge trapping layer 110 or become unwanted dopants in the handle substrate 100 that alter the resistivity of the substrate 100 and / or the charge trapping layer 110. This can result in increased radio frequency signal distortion and power loss. Exposing the surfaces 102, 104 of the substrate 100 to an ambient atmosphere including a reducing agent and / or an etchant can clean or otherwise remove these contaminants. For example, a reducing agent, such as hydrogen, can react with common contaminants, such as boron oxide and aluminum oxide, and etchant gases, such as chlorine or hydrogen chloride, react with aluminum, boron, and phosphorous to form volatile chloride products that are carried away from the surfaces 102 of the substrate 100 by the hydrogen gas.

[0047] When semiconductor oxides (e.g., silicon oxide) are present on the surfaces 102, 104 of the single-crystalline semiconductor handle substrate 100, carbon atoms in organic contaminants can replace semiconductor atoms and form carbon oxides that are cleaned from the surfaces 102, 104 by a hydrogen carrier gas. Performing cleaning and etching operations prior to deposition of the semiconductor material can facilitate obtaining a pure, efficient charge trapping layer 110. Additionally, the cleaning and etching process can open pores in the interfacial oxide front surface layer to form a textured oxide structure and thus expose the front surface 102 to precursors prior to deposition of the charge trapping layer 110. The density and size of the pores in the textured oxide front surface layer can be controlled during the cleaning and etching operations by temperature, time, and gas flow. For example, the size of the pores can be controlled in a range between about 5 nanometers to about 1000 nanometers, such as between about 5 nanometers to about 500 nanometers, or between about 5 nanometers to about 200 nanometers, which enables control of the semiconductor material grain size as well as the thin film stress of the charge trapping layer 110. The open pores in the interfacial oxide front surface layer provide nucleation sites for the charge trapping layer 110. The textured oxide front surface layer can be controlled such that a uniform density of open pores is achieved across the front surface 102 without removing the entire oxide front surface layer. The remaining oxide can increase the thermal stability of the charge trapping layer 110. For example, in subsequent thermal processing of the semiconductor-on-insulator structure and RF device fabrication, the charge trapping layer 110, which suitably includes a polycrystalline or amorphous structure, can be converted to a single-crystalline structure by recrystallization, which is facilitated by direct contact of the polycrystalline or amorphous semiconductor grains with the single-crystalline (i.e., monocrystalline) semiconductor handle substrate 100. The remaining oxide at the interface between the semiconductor charge trapping layer 110 and the front surface 102 of the substrate 100 can effectively prevent the recrystallization process and thus prevent the charge trapping layer 110 from converting to a single-crystalline structure that lacks charge trapping functionality.

[0048] The cleaning and etching operations can be advantageously performed in the same chamber (e.g., CVD reaction chamber) in which deposition of the charge trapping layer 110 is performed. As described above, the reducing atmosphere can include an etchant for further enhancing the cleaning operation. For example, the ambient atmosphere for cleaning can include hydrogen, hydrogen chloride, chlorine, or any combination of hydrogen, hydrogen chloride, and chlorine. Additionally, the cleaning can be performed at a high temperature (e.g., greater than about 850 °C, such as between about 850 °C to about 1100 °C, or between about 850 °C to about 1000 °C). The pressure within the chamber can be atmospheric pressure or at a reduced pressure (e.g., between about 1 Torr to about 760 Torr, such as between about 1 Torr to about 400 Torr). At the desired temperature for cleaning, the substrate can be exposed to the ambient atmosphere including hydrogen, hydrogen chloride, chlorine, or any combination of hydrogen, hydrogen chloride, and chlorine for a duration between about 1 second to about 300 seconds (e.g., between about 5 seconds to about 60 seconds, or between about 10 seconds to about 40 seconds).

[0049] After performing suitable operations to prepare and process the front surface 102 of the single crystalline semiconductor handle substrate 100, a semiconductor material is deposited onto the exposed front surface 102 of the substrate 100. Depositing the semiconductor material creates a charge trapping layer 110 (shown in FIG. 1) on the front surface 102 of the substrate 100. Figure 4 The charge trapping layer 110 can also be referred to herein as a semiconductor charge trapping layer 110 or a semiconductor layer 110.

[0050] Semiconductor materials suitable for forming the charge trapping layer 110 are suitably capable of forming a highly defective layer between the single crystalline semiconductor substrate 100 and a dielectric layer (e.g., the dielectric layer 210 described below) subsequently bonded to and / or formed on the charge trapping layer 110. Such semiconductor materials include polycrystalline semiconductor materials and amorphous semiconductor materials. Semiconductor materials that can be polycrystalline or amorphous include, for example, silicon (Si), silicon germanium (SiGe), carbon-doped silicon, or silicon carbide (SiC), and germanium (Ge). Silicon germanium includes alloys of silicon and germanium in any molar ratio. For example, when the semiconductor material includes silicon germanium, the molar percentage of germanium can be at least about 1 mole%, at least about 5 mole%, at least about 20 mole%, at least about 50 mole%, at least about 90 mole%, or at least about 99.9 mole%. Carbon-doped silicon includes compounds of silicon and carbon, the molar ratio of which can vary. As used herein, the term “polysilicon” is meant to include semiconductor materials having small semiconductor crystals with random crystal orientation. For example, the size of the polysilicon grains can be as small as about 20 nanometers. The smaller the grain size of the deposited polycrystalline semiconductor material, the higher the defect rate in the charge trapping layer 110. The term “amorphous” is meant to indicate semiconductor materials in a non-crystalline allotrope form that lacks short- and long-range order. Silicon grains having a crystallinity of no more than about 10 nanometers can also be considered substantially amorphous silicon.

[0051] The charge trapping layer 110 suitably has a resistivity of at least about 1000 Ohm-cm or at least about 3000 Ohm-cm (e.g., between about 1000 Ohm-cm to about 100,000 Ohm-cm, between about 1000 Ohm-cm to about 10,000 Ohm-cm, between about 2000 Ohm-cm to about 10,000 Ohm-cm, between about 3000 Ohm-cm to about 10,000 Ohm-cm, or between about 3000 Ohm-cm to about 5000 Ohm-cm).

[0052] The semiconductor material for deposition onto the front surface 102 of the single crystalline semiconductor handle substrate 100 can be deposited by means known in the art to produce the charge trapping layer 110. For example, the semiconductor material can be deposited using metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or molecular beam epitaxy (MBE). Silicon precursors for LPCVD or PECVD include methylsilane, tetrasilane (silane), trisilane, disilane, pentasilane, neopentasilane, tetrasilane, dichlorosilane (SiH2Cl2), trichlorosilane (SiHC13), silicon tetrachloride (SiCl4), and the like. For example, polysilicon can be deposited onto a surface oxide layer by pyrolysis of silane (SiH4) in a temperature range between about 550 °C to about 690 °C, such as between about 580 °C to about 650 °C. Chamber pressure can range from 70 mTorr to about 400 mTorr. In some embodiments, deposition can occur at or below atmospheric pressure, such as at a pressure between about 1 Torr to about 760 Torr, between about 10 Torr to about 760 Torr, or between about 1 Torr to about 400 Torr. Amorphous silicon can be deposited by plasma enhanced chemical vapor deposition (PECVD) at temperatures generally in a range between about 75 °C to about 300 °C. Silicon germanium, particularly amorphous silicon germanium, can be deposited by chemical vapor deposition at temperatures up to about 300 °C by including organogermanium compounds such as isobutyl germanium, alkyl germanium trichloride, and dimethylamine germanium trichloride. Carbon-doped silicon can be deposited by thermal plasma chemical vapor deposition in an epitaxial reactor using precursors such as silicon tetrachloride and methane. Suitable carbon precursors for CVD or PECVD include methylsilane, methane, ethane, ethylene, and the like. For LPCVD deposition, methylsilane is a particularly preferred precursor as it provides both carbon and silicon. For PECVD deposition, preferred precursors include silane and methane. In some embodiments, the silicon layer can include a carbon concentration of at least about 1% on an atomic basis, such as between about 1% on an atomic basis to about 10% on an atomic basis. Precursor gases for depositing the semiconductor material can be mixed with a carrier gas such as hydrogen, for example trichlorosilane in hydrogen to deposit polysilicon. The concentration of the precursor gas can be determined based on the desired deposition effect, such as deposition rate.

[0053] In certain embodiments, the charge trapping layer 110 is formed by depositing a poly crystalline semiconductor material. The charge trapping layer 110 can also be referred to herein as a poly crystalline semiconductor charge trapping layer 110 or a poly crystalline semiconductor layer 110.

[0054] In some embodiments, deposition of the semiconductor material to produce the charge trapping layer 110 is performed in an epitaxial deposition atmospheric reactor that fills exposed outer layers available, for example, for a semiconductor-on-insulator structure. For example, deposition of the semiconductor material can be performed in an ASM E3000 epi reactor that includes a gas panel for supplying necessary process gases, such as H2, HC1, dichlorosilane, and / or trichlorosilane, to a quartz reaction chamber at desired flow rates. The quartz reaction chamber can be rectangular cross-section and include a silicon carbide-coated graphite susceptor that supports the substrate 100 during processing. The susceptor can rotate the substrate 100 and have a recess or pocket sized appropriately to support the substrate 100, such as a 300 mm wafer. The substrate 100 is seated in the recess of the susceptor during processing and is supported on the backside by a flange in the recess that is in close proximity to, such as within a few millimeters of, the peripheral edge 106 of the substrate 100 and contacts the substrate 100 at a height that holds the front surface 102 of the substrate 100 slightly above the top surface of the susceptor. The area of the susceptor below the substrate 100 and within the support flange of the susceptor can be perforated to allow venting of the back surface 104 of the substrate 100 facing the susceptor. The substrate 100 can be delivered to the reaction chamber by a robot that handles the substrate 100 without substantially introducing contaminants or causing damage to the surfaces 102, 104 of the substrate. The reaction chamber is positioned adjacent to heating elements, such as flat panel lamp banks, which nominally can be parallel to and above and below the substrate 100 and susceptor, heating the substrate 100 and susceptor to desired process temperatures. The desired gas flow rates, susceptor rotation speeds, and temperatures are typically varied at various times throughout the process. Changes in process parameters, such as gas flow rates, rotation speeds, temperatures, and wafer loading and unloading, are controlled by a computer automation based on a predetermined "recipe" that has been developed to produce a substrate 100 with desired characteristics at the completion of processing. Desired characteristics that control process parameters include crystalline slip, resistivity, deposited film thickness (such as thickness of the semiconductor layer 110), film quality parameters (such as resistivity of the semiconductor layer 110), semiconductor material grain size, surface roughness, wafer flatness after deposition (such as site flatness, often characterized by SFQR parameters), and other characteristics of the high resistivity substrate 100. An exemplary epitaxial reactor suitable for deposition of the semiconductor layer 110 is an epsilon E3000 single wafer epitaxial reactor manufactured by ASM International. Other reaction chambers include those sold by Applied Materials under the trademark Centura.Advantageously, performing semiconductor layer deposition in these reactors can enable several different processes that are used in semiconductor-on-insulator and RF device fabrication for running on the same processing tool (e.g., semiconductor charge trapping layer deposition, post-split top semiconductor device layer smoothing by vapor phase etching with HC1, top semiconductor device layer thickening by epitaxial deposition, and standard blanket epitaxial layer deposition).

[0055] The reaction chamber within which deposition of the semiconductor layer 110 is performed can be at any suitable pressure (e.g., atmospheric) during deposition. For example, deposition can occur at or below atmospheric pressure (e.g., at a pressure between about 1 Torr and about 760 Torr, between about 10 Torr and about 760 Torr, or between about 1 Torr and about 400 Torr). Deposition time can vary depending on the deposition temperature, concentration, and desired thickness of the semiconductor layer 110. In some embodiments, the semiconductor layer 110 is at least about 0.1 pm thick or at least about 0.5 pm, at least about 1 pm, at least about 2.5 pm, or at least about 4 pm thick (e.g., from about 0.1 pm to about 50 pm, from about 0.25 pm to about 20 pm, or from about 1 pm to about 10 pm).

[0056] The semiconductor material used to form the semiconductor charge trapping layer 110 can be deposited at any suitable temperature based on the semiconductor material to be deposited, the deposition method, and other considerations, and the deposition temperature can be selected to enhance or promote certain properties of the semiconductor layer 110. For example, the deposition temperature of the semiconductor material can be suitable to increase the surface area of the semiconductor layer 110. In some embodiments, the semiconductor layer 110 is deposited at a suitable temperature to reduce the grain size of the deposited semiconductor material. As described above, the semiconductor layer 110 can be deposited using chemical or physical vapor deposition (e.g., metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD)). In some embodiments, the semiconductor layer 110 includes polysilicon deposited by CVD, and suitable silicon precursors for CVD include methylsilane, tetrasilane (silane), trisilane, disilane, pentasilane, neopentasilane, tetrasilane, dichlorosilane (SiH2Cl2), trichlorosilane (SiHC13), silicon tetrachloride (SiCl4), and the like. For example, the silicon precursor used to deposit polysilicon by CVD can be selected from silane, dichlorosilane (SiH2Cl2), and trichlorosilane (SiHC13). In embodiments where a silicon precursor is used to deposit polysilicon, the polysilicon can be deposited at a temperature between about 800 °C to about 1150 °C. In some embodiments, the deposition temperature for the polysilicon semiconductor layer 110 is less than about 1125 °C, less than about 1100 °C, less than about 1075 °C, less than about 1050 °C, less than about 1000 °C, or less than about 900 °C, or a temperature from about 800 °C to about 1150 °C, from about 800 °C to about 1100 °C, or from about 850 °C to about 1000 °C. The temperature can also contribute to a high growth rate, thereby contributing to yield and cost reduction. The CVD deposition rate can be at least about 0.1 microns / minute, for example, between about 0.1 microns / minute to about 10 microns / minute or between about 0.1 microns / minute to about 2 microns / minute. It should be appreciated that the deposition temperature for certain precursor gases, which depends on whether the semiconductor material includes, for example, polysilicon or amorphous silicon, SiGe, SiC, or Ge, can be selected based on known suitable temperatures (e.g., according to published methods).

[0057] In an example method for fabricating the semiconductor layer 110, deposition of the semiconductor material is temporarily interrupted at least once, and preferably more than once. Between deposition phases for fabricating the semiconductor layer 110, the supply of precursor gas to the reaction chamber is temporarily suspended and the previously deposited semiconductor material is annealed at or near the deposition conditions (e.g., at or near the deposition temperature and pressure). Following the temporary anneal, the supply of precursor gas to the reaction chamber is resumed for the next deposition phase. Thus, the semiconductor layer 110 is suitably fabricated by two or more cycles of depositing a portion of the semiconductor layer 110 and interrupting the deposition process to anneal the deposited portion. In other words, deposition of the semiconductor layer 110 is performed by a cyclic process in which a portion of the semiconductor layer 110 is deposited, the deposition is interrupted by temporarily stopping the flow of precursor gas, the portion of the semiconductor layer 110 is annealed, and a portion of the semiconductor material 110 is deposited on the previously annealed portion. Each portion of the semiconductor charge trapping layer 110 can also be referred to herein as a "semiconductor material layer." Thus, in an example method, the semiconductor layer 110 is fabricated by depositing a first layer of semiconductor material, annealing the first layer of semiconductor material, depositing a second layer of semiconductor material on the annealed first layer, annealing the second layer of semiconductor material, and so on. By depositing the semiconductor layer 110 in this manner, the semiconductor layer 110 can comprise, for example, two or more annealed layers of semiconductor material, such as three or more annealed layers, or between 3 and about 50 annealed layers, or between 3 and about 40 annealed layers, or between 3 and about 30 annealed layers, or between 3 and about 25 annealed layers, or between 3 and about 20 annealed layers, or between 3 and about 10 annealed layers of semiconductor material. The number of annealed layers of semiconductor material that fabricate the semiconductor layer 110 is equal to the number of cycles in which a portion of the semiconductor layer 110 is deposited and the deposition process is interrupted to anneal the deposited portion. Thus, two cycles will result in two annealed layers of semiconductor material, three cycles will result in three annealed layers, ten cycles will result in ten annealed layers, and so on. A large number of semiconductor material layers can be deposited and annealed to produce the semiconductor charge trapping layer 110, limited in part by the throughput requirements and the minimum practical layer thickness that can be deposited, which can be about 20 nanometers.

[0058] The duration of each cycle of depositing a portion of the semiconductor layer 110 and interrupting the deposition process to anneal the deposited portion can depend on the desired thickness of each annealed layer of semiconductor material. In some embodiments, each deposited layer of semiconductor material can be at least about 0.1 pm, at least about 0.2 pm, at least about 0.5 pm thick, for example between about 0.05 pm and about 5 pm, between about 0.1 pm and about 5 pm, or between about 0.1 pm and about 1 pm. The deposited layers of semiconductor material can have the same thickness or the thickness can vary between layers. The duration of depositing each layer of semiconductor material for each cycle can be between about 1 second (s) and about 60 s, for example between about 1 s and about 15 s, between about 1 s and about 10 s, between about 10 s and about 30 s, between about 15 s and about 30 s, between about 15 s and about 20 s, between about 20 s and about 30 s, or between about 30 s and about 45 s. The duration of annealing each semiconductor deposited layer for each cycle can be between 1 s and about 60 s, for example between about 1 s and about 15 s, between about 1 s and about 10 s, between about 10 s and about 30 s, between about 15 s and about 30 s, between about 15 s and about 20 s, between about 20 s and about 30 s, or between about 30 s and about 45 s. The thickness of each layer of semiconductor material is selected based on the desired number of cycles used to fabricate the semiconductor layer 110 and the desired thickness of the semiconductor layer 110. In some embodiments, the semiconductor layer 110 is at least about 0.1 pm thick or at least about 0.5 pm, at least about 1 pm, at least about 2.5 pm, or at least about 4 pm thick (e.g., from about 0.1 pm to about 50 pm, from about 0.25 pm to about 20 pm, or from about 1 pm to about 10 pm). The total duration of annealing the layers of semiconductor material can be known or empirically determined as an appropriate annealing time to diffuse interstitial atoms from grain boundaries of the semiconductor layer 110 having a given thickness at a given temperature and distributed across cycles according to the thickness of the layers of material deposited in each cycle. For example, the annealing time can be uniformly distributed across each cycle, where the cycles result in approximately equal thicknesses of layers of semiconductor material. Thus, when a total annealing time of about 140 s is determined to be appropriate for a semiconductor layer 110 produced by 7 cycles of depositing and annealing layers of semiconductor material having approximately equal thicknesses, each cycle would include about 20 s of annealing.

[0059] Each layer of semiconductor material deposited and annealed to produce the semiconductor layer 110 is deposited at a deposition temperature and annealed at an anneal temperature. As described above, deposition is interrupted by stopping the flow of precursor gas to the reaction chamber. After the deposition is interrupted, the previously deposited layer of semiconductor material is annealed within the ambient atmosphere of the reaction chamber, which can contain hydrogen gas, hydrogen chloride, and / or chlorine gas. The anneal operations performed throughout the cycle process produce the semiconductor layer 110 that suitably has tensile stress rather than compressive stress. Compressive stress in the semiconductor layer 110 can otherwise be produced during deposition of the semiconductor material. Each anneal operation can be performed at reduced pressure or at atmospheric pressure, for example between about 1 Torr to about 760 Torr or between about 10 Torr to about 760 Torr. Suitably, when deposition of the semiconductor material is interrupted, no intentional temperature increase is produced within the reaction chamber, such that the anneal temperature is substantially the same as or very close to the deposition temperature. The anneal temperature can suitably be within about 10 °C of the deposition temperature, within about 5 °C of the deposition temperature, or within about 1 °C of the deposition temperature. It will be appreciated that some incidental temperature variation can occur upon stopping the precursor gas supply due to, for example, temperature differences between the precursor gas and the ambient atmosphere during annealing. In other embodiments, a slight temperature increase or decrease can be intentionally produced between the deposition temperature and the anneal temperature, for example by varying the heat supplied to heating elements positioned adjacent to the reaction chamber. At least one of the deposition temperature and the anneal temperature, or both the deposition temperature and the anneal temperature, can be the same across each cycle performed to produce the semiconductor layer 110, or the deposition temperature and / or the anneal temperature can vary for each cycle. Suitably, the deposition temperature and the anneal temperature for each cycle are each a relatively low temperature of less than about 1100 °C, less than about 1050 °C, or less than about 1000 °C. The deposition temperature and the anneal temperature can also each be greater than about 800 °C, greater than about 850 °C, or greater than about 900 °C. For example, the deposition temperature and the anneal temperature for each cycle can be between about 800 °C to about 1100 °C, for example between about 850 °C to about 1000 °C, between about 900 °C to about 1000 °C, between about 925 °C to about 975 °C, between about 925 °C to about 950 °C, or between about 950 °C to about 1000 °C.

[0060] Each anneal operation of each cycle is performed to induce tensile thin film stress in a layer of semiconductor material (i.e., a portion of the semiconductor layer 110) deposited during the respective cycle. That is, each anneal operation induces a transformation of the compressive stress induced during deposition of the semiconductor material layer into tensile stress by causing interstitial atoms to diffuse out of the grain boundaries of the semiconductor material. Distributing the anneal operations across multiple cycles during deposition can facilitate improved ability to diffuse interstitial atoms out of the grain boundaries of the semiconductor layer 110 compared to an anneal operation performed at the same total duration and at the same temperature but after deposition of the entire layer 110. This is because the anneal is performed against a relatively thinner layer of pre-annealed semiconductor material deposited and the distance for interstitial atoms to diffuse out from the grain boundaries of the deposited semiconductor material is reduced. Thus, the time required for interstitial atoms to diffuse out via anneal at a given temperature is reduced. Each anneal operation can produce other desirable properties in addition to tensile stress of the semiconductor layer 110, such as high purity, high resistivity, desirable grain size and uniformity of the semiconductor material, and clean exposed surfaces of the semiconductor layer 110. Further, performing the anneal operations at relatively lower temperatures reduces or eliminates defects in the high resistivity substrate 100 induced when otherwise annealed at higher temperatures, such as crystalline slip defects.

[0061] A semiconductor seed layer can be deposited onto the front surface 102 of the substrate 100 and annealed prior to the cycle process to deposit the semiconductor layer 110. The semiconductor seed layer serves to facilitate growth of subsequent layers of semiconductor material when fabricating the semiconductor layer 110 and to improve charge trapping efficiency of the semiconductor layer 110. The semiconductor layer 110 can thus include the semiconductor seed layer and the layers of semiconductor material deposited and annealed during the cycle process described above. The semiconductor seed layer can include one or more semiconductor materials, such as silicon, SiGe, SiC, and Ge. The semiconductor material used to produce the semiconductor seed layer can be the same as the material of the substantially deposited semiconductor material layer or can be a different semiconductor material. For example, when depositing a polycrystalline semiconductor layer 110, the semiconductor seed layer can be a polycrystalline semiconductor seed layer. The polycrystalline semiconductor seed layer can include a polycrystalline semiconductor material, such as, for example, polysilicon, SiGe, SiC, and / or Ge. The semiconductor seed layer is suitably deposited and annealed in the same reaction chamber as the semiconductor material layers deposited and annealed during the cycle process.

[0062] The semiconductor seed layer suitably has a thickness that is less than the thickness of the semiconductor layer 110. In some embodiments, the semiconductor seed layer can have a thickness approximately equal to that of each of the semiconductor material layers deposited and annealed during the cycle process. In some embodiments, the semiconductor seed layer can be deposited to a thickness less than about 20 pm, less than about 10 pm, less than about 5 pm, less than about 3 pm, less than about 2 pm, less than about 1 pm, or less than about 0.5 pm, such as between about 50 nanometers (nm) and about 20 pm, or between about 50 nm and about 10 pm, or between about 50 nm and about 5 pm, or between about 50 nm and about 3 pm, or between about 50 nm and about 2 pm, or between about 50 nm and about 1 pm, or between about 50 nm and about 500 nm, or between about 50 nm and about 200 nm. The thickness of the semiconductor seed layer is set by the size of the semiconductor nuclei. To achieve effective stress release, the semiconductor seed layer needs to cover the substrate surface while leaving a void of less than about 50 nm that enables hydrogen gas (H2) access to the interface between the semiconductor seed layer and the oxide. Hydrogen gas reduces the interfacial oxide and promotes atomic diffusion at the grain boundaries of the semiconductor seed layer to the substrate 100 and thus releases the thin film stress. When the semiconductor seed layer is thick enough to completely prevent H2access to the interfacial oxide, the subsequent anneal process cannot effectively release the thin film stress. On the other hand, when the semiconductor seed layer is discontinuous and the open area between two adjacent nuclei is wider than about 50 nm, large nuclei form after the oxide layer removal during the seed layer anneal process. The large nuclei will grow into large grains (i.e., diameter > 1 pm) after the semiconductor layer 110 is deposited, which reduces the capture efficiency.

[0063] The semiconductor seed layer is subjected to a high temperature anneal, which is then followed by a cycle process to deposit and anneal each of the semiconductor material layers. Annealing the semiconductor seed layer contributes to desired charge trapping layer properties, such as obtaining a clean surface, a high purity thin film, a high resistivity film, a desired crystal nucleus size and uniformity, and a reduction of compressive thin film stress. In some embodiments, the semiconductor seed layer is subjected to a high temperature anneal to create tensile stress in the semiconductor seed layer. The temperature at which the semiconductor seed layer is deposited is generally greater than the anneal temperature of each of the semiconductor material layers annealed during the cycle process. For example, the semiconductor seed layer can be annealed at a temperature greater than about 1000 °C, greater than about 1025 °C, or greater than about 1050 °C, such as between about 1000 °C to about 1200 °C, between about 1000 °C to about 1100 °C, between about 1025 °C to about 1050 °C, or between about 1050 °C to about 1100 °C. The semiconductor seed layer can be annealed for a duration of time between about 1 second to about 300 seconds, such as between about 5 seconds to about 60 seconds, or between about 10 seconds to about 40 seconds. The semiconductor seed layer can be annealed in an ambient atmosphere that can contain hydrogen, hydrogen chloride, chlorine, or any combination of hydrogen, hydrogen chloride, and chlorine. The semiconductor seed layer can be performed at a reduced pressure or at atmospheric pressure, such as between about 1 Torr to about 760 Torr, or between about 10 Torr to about 760 Torr. The grain size and stress of the semiconductor seed layer is controlled by the anneal temperature, duration, and gas flow.

[0064] Since the semiconductor seed layer can be annealed at a relatively high temperature, the example methods described herein can include cooling the single crystal semiconductor handle substrate 100 after annealing the semiconductor seed layer. For example, the example methods can include cooling the substrate 100 to a temperature less than about 1000 °C after annealing the semiconductor seed layer and before performing the cycle process of depositing and annealing the semiconductor material layers (i.e., portions of the semiconductor layer 110). Then, once the substrate 100 is cooled to the desired temperature, the cycle process is initiated.

[0065] In some embodiments, an oxide film can be formed on top of the deposited semiconductor layer 110. This can be accomplished by means known in the art, such as thermal oxidation (where some portions of the deposited semiconductor material film are consumed), CVD oxide deposition, and / or atomic layer deposition. For example, the semiconductor layer 110 can be thermally oxidized in a furnace, such as an ASM A400 or ASM A412. In the oxidation environment, the temperature can range from about 750 °C to about 1200 °C. The oxidation environment atmosphere can be a mixture of an inert gas (such as Ar or N2) and O2. The oxygen content can vary from 1% to 10% or higher. In some embodiments, the oxidation environment atmosphere can be up to 100% oxygen ("dry oxidation"). In some embodiments, the oxidation environment atmosphere can include oxygen and ammonia, which is suitable for depositing silicon oxynitride. In some embodiments, the environment atmosphere can include a mixture of an inert gas (such as Ar or N2) and an oxidizing gas (such as O2 and water vapor) ("wet oxidation"). In some embodiments, the environment atmosphere can include a mixture of an inert gas (such as Ar or N2) and an oxidizing gas (such as O2 and water vapor) ("wet oxidation") and a nitriding gas (such as ammonia). In some embodiments, the environment atmosphere can include a mixture of an inert gas (such as Ar or N2) and a nitriding gas (such as ammonia, which is suitable for depositing silicon nitride). The single crystal semiconductor handle substrate 100 with the semiconductor layer 110 formed on its front surface 102 can be loaded into a vertical furnace, such as an ASM A400 or ASM A412. The temperature is ramped up to the oxidation temperature with a mixture of N2 and O2. At the desired temperature, water vapor can be introduced into the gas stream. After the desired oxide film thickness is obtained, the water vapor and O2 are turned off and the furnace temperature is reduced and the substrate 100 is unloaded from the furnace. In some embodiments, the semiconductor layer 110 can be oxidized for a duration sufficient to provide an oxide layer of at least about 0.01 pm thick.

[0066] In some embodiments, the semiconductor layer 110 as produced above is subsequently planarized to reduce the surface roughness of the exposed surface of the semiconductor layer 110 and optimize Figure 4 the warpage and bow of the substrate 100 shown in FIG. 1 for subsequent operations in the fabrication of a semiconductor-on-insulator structure. For example, the semiconductor layer 110 can be subjected to a polishing operation, such as a chemical mechanical polishing ("CMP") operation. The semiconductor layer 110 can have a relatively rough surface. For example, the deposited semiconductor layer 110 can have a surface roughness as measured by RMS 2x2µm2 roughness of less than about 5 Angstroms, such as between about 1 Angstrom to about 2 Angstroms, where the root mean square 2x2µm2 , roughness curve contains equidistant points ordered along the trace, and y i ​is the vertical distance from the mean line to the data point. The surface is prepared for subsequent bonding operations described further below with a surface roughness preferably less than 2 Angstroms. In addition to polishing, cleaning the substrate 100 having the semiconductor layer 110 is optional. As desired, the wafer can be cleaned, for example, in standard SC1 and / or SC2 solutions.

[0067] The single-crystalline semiconductor handle substrate 100 comprising the semiconductor layer 110 prepared according to the methods described herein is then bonded as a single-crystalline semiconductor donor substrate 200 (shown in Figure 4 Figure 5 The single-crystalline semiconductor donor substrate 200 (shown in

[0068] As described above, the semiconductor donor substrate 200 can include a dielectric layer 210 formed on a front surface 202 thereof. Suitable dielectric layers 210 can include a material selected from silicon dioxide, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and combinations thereof. In some embodiments, the dielectric layer 210 includes an oxide layer having a thickness of at least about 10 nm (e.g., between about 10 nm and about 10,000 nm, between about 10 nm and about 5,000 nm, or between about 100 nm and about 800 nm).

[0069] ​In some embodiments, the front surface 202 of the single crystalline semiconductor donor substrate 200 (e.g., a single crystalline silicon donor substrate) can be thermally oxidized (where some portion of the deposited semiconductor material will be consumed) to make a dielectric layer 210 (e.g., a semiconductor oxide film, such as a silicon dioxide film), or a semiconductor oxide (e.g., silicon dioxide) film can be grown by CVD oxide deposition to form the dielectric layer 210. The oxidation operation performed on the front surface 202 of the donor substrate 200 can be similar to the operations described above for the front surface 102 of the handle substrate 100. In some embodiments, the front surface 202 of the single crystalline semiconductor donor substrate 200 can be thermally oxidized in a furnace (e.g., an ASM A400 or ASM A412) in the same manner described above. In some embodiments, the donor substrate 200 is oxidized to provide a dielectric layer 210 on the front surface 202 that is at least about 10 nm thick (e.g., between about 10 nm and about 10,000 nm, between about 10 nm and about 5000 nm, or between about 100 nm and about 800 nm).

[0070] The semiconductor device layer 402 in the semiconductor-on-insulator composite structure 400 (shown in FIG. 4) is derived from the single crystalline semiconductor donor substrate 200. The semiconductor device layer 402 can be transferred onto the semiconductor handle substrate 100 by, for example, wafer thinning techniques that etch the semiconductor donor substrate 200 or by splitting the semiconductor donor substrate 200 including the split plane 212. Figure 7

[0071] The split plane 212 can be formed in the donor substrate 200 by ion implantation techniques. The ion implantation can be performed in a commercially available tool, such as an Applied Materials Quantum H. The implant ions include He, H, H2, or combinations thereof. The ion implantation is performed at a density and duration sufficient to form the split plane 212 in the semiconductor donor substrate 200. The implant density can be in a range from about 10 12 ions / cm 2 to about 10 17 ions / cm 2 , such as from about 10 14 ions / cm 2 to about 10 17 ions / cm 2 . The implant energy can be in a range from about 1 keV to about 3,000 keV, such as from about 10 keV to about 3,000 keV. The implant depth determines the final semiconductor-on-insulator structure 400 (shown in FIG. 4). Figure 7 ​The thickness of the single crystal semiconductor device layer 402 (as shown in the middle). In some embodiments, it can be desirable to subject the single crystal semiconductor donor substrate 200 to a cleaning operation after implantation. In some preferred embodiments, the cleaning can include piranha cleaning followed by a deionized water rinse and cleaning using SC1 and / or SC2 solutions.

[0072] In some embodiments, the single crystal semiconductor donor substrate 200 having ion implant regions formed from helium and / or hydrogen ion implants is annealed at a temperature sufficient to form a thermally activated split plane 212 in the donor substrate 200. An example of a suitable tool can be a simple box furnace, such as a Blue M model. In some preferred embodiments, the ion implanted single crystal semiconductor donor substrate 200 is annealed at a temperature from about 200 °C to about 350 °C, from about 225 °C to about 325 °C, preferably about 300 °C. The occurrence of thermal annealing can be for a duration from about 2 hours to about 10 hours, such as from about 2 hours to about 8 hours. Thermal annealing in these temperature ranges is sufficient to form the thermally activated split plane 212. After thermal annealing for activation of the split plane, the front surface 202 of the single crystal semiconductor donor substrate 200 surface, which can optionally include the dielectric layer 210, and optionally the back surface 204 can be cleaned using the cleaning operations described above.

[0073] In some embodiments, the ion implanted and optionally cleaned and optionally annealed single crystal semiconductor donor substrate 200 is subjected to oxygen plasma and / or nitrogen plasma surface activation. In some embodiments, the oxygen plasma surface activation tool is a commercially available tool, such as the tool available from EV Group, such as the EVG® 810LT Low Temperature Plasma Activation System. The ion implanted and optionally cleaned single crystal semiconductor donor substrate 200 is loaded into the chamber. The chamber is evacuated and filled with O2 to a pressure less than atmospheric pressure to thereby generate a plasma. The single crystal semiconductor donor substrate 200 is exposed to this plasma for a desired time, which can be in the range from about 1 second to about 120 seconds. The oxygen plasma surface oxidation is performed to make the front surface 202 of the single crystal semiconductor donor substrate 200 and optionally the dielectric layer 210 formed on the front surface 202 hydrophilic and suitable for bonding to a single crystal semiconductor handle substrate prepared according to the methods described above.

[0074] Reference is made to Figure 6hydrophilic front surface layer of the single crystalline semiconductor donor substrate 200 (e.g., the hydrophilic exposed surface of the dielectric layer 210) and the exposed surface of the semiconductor layer 110 on the front surface 102 of the single crystalline semiconductor handle substrate 100 are brought into intimate contact to thereby form a bonded structure 300. In the illustrated embodiment, the bonded structure 300 includes a dielectric layer 210 (e.g., a buried oxide layer) facilitated by the oxidized front surface 202 of the single crystalline semiconductor donor substrate 200 interfacing with the semiconductor charge trapping layer 110. In some embodiments, the dielectric layer 210 (e.g., a buried oxide layer) has a thickness of at least about 10 nm (e.g., between about 10 nm to about 10,000 nm, between about 10 nm to about 5000 nm, or between about 100 nm to about 800 nm).

[0075] Since the mechanical bond between the semiconductor charge trapping layer 110 and the dielectric layer 210 is relatively weak, the bonded structure 300 is further annealed to solidify the bond. In some embodiments, the bonded structure 300 is annealed at a temperature sufficient to form a thermally activated split plane 212 in the single crystalline semiconductor donor substrate 200. An example of a suitable tool can be a simple box furnace (e.g., a Blue M model). In some embodiments, the bonded structure 300 is annealed at a temperature from about 200 °C to about 350 °C, from about 225 °C to about 325 °C, preferably about 300 °C. The thermal anneal can occur for a duration from about 0.5 hours to 10 hours, preferably about 2 hours. Thermal annealing in these temperature ranges is sufficient to form the thermally activated split plane 212. After the thermal anneal to activate the split plane 212, the bonded structure 300 can be split to yield Figure 7 the final split composite structure 400 shown in FIG. 4B.

[0076] After the thermal anneal of the bonded structure 300, the bond between the single crystalline semiconductor donor substrate 200 and the single crystalline semiconductor handle substrate 100 is strong enough to initiate a layer transfer by splitting the bonded structure 300 at the split plane 212. The splitting can occur according to techniques known in the art. In some embodiments, the bonded structure 300 can be placed at a conventional split point, attached on one side (e.g., on one of the back surfaces 104, 204) to a fixed chuck and on the other side (e.g., on the other of the back surfaces 104, 204) by an additional chuck attached on a hinged arm. A crack is initiated near the chuck attachment and the arm can be pivoted about the hinge to split the donor substrate 200 apart. The splitting removes a portion of the semiconductor donor substrate 200, thereby leaving the semiconductor device layer 402 (preferably a silicon device layer) on the insulator-on-semiconductor composite structure 400 Figure 7 shown in FIG. 4B.

[0077] After splitting, the split structure 400 can be subjected to high temperature annealing to further enhance the bonding between the transferred device layer 402 and the single crystal semiconductor handle substrate 100. An example of a suitable tool can be a vertical furnace, such as an ASM A400 or an ASM A412. In some preferred embodiments, the split structure 400 is annealed at a temperature from about 1000 °C to about 1200 °C, preferably at about 1000 °C. The occurrence of thermal annealing can be sustained for a duration from about 0.5 hours to about 8 hours. Thermal annealing in these temperature ranges is sufficient to enhance the bonding between the transferred device layer 402 and the single crystal semiconductor handle substrate 100.

[0078] After splitting and high temperature annealing, the exposed surfaces of the split structure 400, such as the exposed surface 104 and / or the exposed surface of the transferred device layer 402, are sufficiently smooth due to the high temperature annealing. In some embodiments, an epitaxial layer (not shown) can be deposited on the exposed surface of the transferred device layer 402. Referring to Figure 7 The completed multi-layer structure 400, i.e., the semiconductor-on-insulator structure 400, includes a high resistivity single crystal semiconductor handle substrate 100, such as a single crystal silicon handle substrate, a semiconductor charge trapping layer 110, a dielectric layer 210, such as a semiconductor oxide layer, e.g., a silicon dioxide layer, prepared from oxidation of the front surface 202 of the single crystal semiconductor donor substrate 200, and a semiconductor device layer 402 prepared by splitting and / or thinning the donor substrate 200. Oxidation can be further performed, for example, on the exposed surface 104 for reducing the bow or warp of the structure 400. The final structure 400 can then be subjected to end-of-line metrology inspection and cleaned for the last time using a typical SC1-SC2 process.

[0079] The following non-limiting examples further illustrate the present application.

[0080] Example 1. Comparison of 3-point wafer bow variation under different anneal conditions after deposition of a polycrystalline semiconductor layer.

[0081] Various low temperature anneal conditions for a deposited polycrystalline silicon layer are compared to a control in which there is no post-deposition anneal. In one method, a post-deposition anneal is performed for a period of time after deposition of the polycrystalline silicon layer and the temperature is maintained at the polycrystalline silicon layer deposition temperature. In another method, an anneal of the same duration is performed at the same temperature, but the anneal is distributed by intermittently pausing the deposition process according to the deposition anneal cycle process disclosed herein. Specifically, a portion of the deposition of the polycrystalline silicon layer is performed and 7 cycles of annealing the deposited portion of the polycrystalline silicon layer are performed for a total duration approximately equal to the deposition and anneal duration of the PDA method. For each of the three conditions evaluated, a polycrystalline silicon seed layer having a different number of seed anneals at a temperature in excess of 1000 °C is formed prior to deposition of the polycrystalline silicon layer.

[0082] By annealing the polysilicon material intermittently during deposition, the distance that grain boundary atoms diffuse out of the gap is reduced, thus, the time required for their removal is reduced. As a result, wafers are produced with acceptable levels of bow and warp, which indicates that the polysilicon layer has a desired level of tensile stress. The levels of bow and warp can be higher than those produced by annealing at higher temperatures (e.g., greater than 1000 °C), but the intermittent low temperature anneal operation provides the advantage of significantly reducing or eliminating the level of crystallographic slip defects in the high resistivity substrate. In addition, enhanced levels of bow and warp are achieved in processes where the anneal time of the polysilicon seed layer is increased. Furthermore, performing the intermittent anneal during the polysilicon deposition shows to be more effective at reducing 3-point wafer bow than a single post-deposition anneal step of the same duration.

[0083] Figure 8 and 9 The post-deposition 3-point wafer bow of a polysilicon layer according to the present disclosure is compared after a higher temperature post-deposition anneal (labeled POR) and after an intermittent low temperature anneal (labeled New Invention). As shown in Figure 8 When comparing the post-deposition data of the high temperature anneal and the new intermittent anneal process, the new intermittent anneal process shows a higher compressive stress (positive bow value) than the POR process (tensile stress in the POR wafer, negative bow value). However, as shown in Figure 9 After a subsequent CMP process, more negative bow (more tensile stress) is observed in the new intermittent anneal process, which helps to better balance the compressive stress induced by the buried oxide layer and reduces the final semiconductor-on-insulator wafer bow and warp.

[0084] Example 2. Comparison of wafer SFQR for different anneal conditions after polysilicon semiconductor layer deposition.

[0085] The comparison of the method described above in Example 1 is also performed for site flatness of the post-deposition wafer. In addition to controlling the post-deposition 3-point wafer bow and crystallographic slip, it is also important to control the increase in site flatness (measured as SFQR) during the polysilicon deposition. During the polysilicon process, polysilicon is intentionally deposited on the front side of the handle wafer. However, since the reaction chamber is filled with reactants, it can also diffuse around the edges of the wafer and deposit on the back side of the handle wafer. The backside deposition is often non-uniform, and thus the SFQR site flatness measurement is affected. Although all of the conditions tested show an improvement in SFQR as the seed layer anneal time is increased, the post-deposition wafer produced with the intermittent pause and anneal during deposition shows the greatest improvement in site flatness, especially at the edge sites where site flatness is worst. When comparing the results of the new intermittent anneal process to the high temperature post-deposition anneal process, the SFQR results of the intermittent deposition process are significantly better, as shown in Figure 10

[0086] ​As used herein, the terms "about," "substantially," "approximately," and "near" when used in reference to a dimension, concentration, temperature, or other physical or chemical property or characteristic are meant to encompass variations that can exist in the upper and / or lower limits of such ranges due to, for example, rounding, measurement methodology, and other statistical variations.

[0087] When introducing elements of the present disclosure and the embodiments thereof, the articles "a," "an," and "the" are intended to mean that there are one or more of the elements. The terms "comprising," "including," "containing," and "having" are intended to be inclusive and mean that there can be additional elements other than the listed elements. Use of the term "about" in connection with a geographic location, is for the convenience of the reader and is not intended to limit the scope of the description to a precise location.

[0088] As various changes could be made in the above constructions and methods without departing from the scope of the disclosure, it is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.

Claims

1. A method of preparing a multilayer structure, the method comprising: providing a single crystalline semiconductor handle substrate comprising: two generally parallel major surfaces, one of which is a front surface of the single crystalline semiconductor handle substrate and the other of which is a back surface of the single crystalline semiconductor handle substrate; a circumferential edge connecting the front and back surfaces of the single crystalline semiconductor handle substrate; and a central plane located between the front and back surfaces of the single crystalline semiconductor handle substrate, wherein the single crystalline semiconductor handle substrate has a minimum bulk resistivity of at least about 500 Ohm-cm; and depositing a semiconductor layer on the front surface of the single crystalline semiconductor handle substrate, wherein depositing the semiconductor layer is performed by two or more cycles of depositing a portion of the semiconductor layer and interrupting the deposition after depositing the portion of the semiconductor layer to anneal the portion of the semiconductor layer.

2. The method of claim 1, wherein the cycles of depositing the semiconductor layer comprise: depositing the portion of the semiconductor layer at a deposition temperature; and annealing the portion of the semiconductor layer at an anneal temperature.

3. The method of claim 2, wherein the deposition temperature and the anneal temperature are within 10 °C of each other.

4. The method of claim 2, wherein the deposition temperature and the anneal temperature are within 5 °C of each other.

5. The method of claim 2, wherein the deposition temperature and the anneal temperature are within 1 °C of each other.

6. The method of claim 2, wherein no ramping occurs between the deposition temperature and the anneal temperature.

7. The method of claim 2, wherein the deposition temperature and the anneal temperature are each less than 1000 °C.

8. The method of claim 2, wherein the deposition temperature and the anneal temperature are each greater than 850 °C.

9. The method of claim 2, wherein the deposition temperature and the anneal temperature are each between 850 °C and 1000 °C.

10. The method of claim 2, wherein at least one of the deposition temperature and the anneal temperature is the same for each of the two or more cycles.

11. The method of claim 10, wherein each of the deposition temperature and the anneal temperature is the same for each cycle.

12. The method of any one of the preceding claims, wherein depositing the semiconductor layer is performed by at least three cycles of depositing the portion of the semiconductor layer and interrupting the deposition after depositing the portion of the semiconductor layer to anneal the portion of the semiconductor layer.

13. The method of any one of the preceding claims, wherein depositing the semiconductor layer is performed by between three and ten cycles of depositing the portion of the semiconductor layer and interrupting the deposition after depositing the portion of the semiconductor layer to anneal the portion of the semiconductor layer.

14. The method of any one of the preceding claims, wherein each cycle of depositing the semiconductor layer produces a respective portion of the semiconductor layer having a thickness between 0.05 microns and 5 microns.

15. The method of any one of the preceding claims, wherein each cycle of depositing the semiconductor layer produces a respective portion of the semiconductor layer having a thickness between 0.1 microns and 1 micron.

16. The method of any one of the preceding claims, wherein the semiconductor layer has a thickness between 0.1 microns and 50 microns.

17. The method of any one of the preceding claims, wherein the semiconductor layer has a thickness between 1 micron and 10 microns.

18. The method of any one of the preceding claims, further comprising planarizing the semiconductor layer after depositing the semiconductor layer.

19. The method of claim 18, wherein planarizing the semiconductor layer comprises polishing the semiconductor layer using chemical mechanical polishing.

20. The method of any one of the preceding claims, wherein depositing the semiconductor layer further comprises depositing a semiconductor seed layer and annealing the semiconductor seed layer prior to performing the two or more cycles of depositing the portion of the semiconductor layer and annealing the portion of the semiconductor layer after depositing the portion of the semiconductor layer.

21. The method of claim 20, wherein the annealing the semiconductor seed layer is performed at a temperature greater than the annealing during the two or more cycles.

22. The method of claim 20, wherein the annealing the semiconductor seed layer is performed at a temperature greater than 1000 °C and the annealing during the two or more cycles is performed at a temperature less than 1000 °C.

23. The method of claim 20, further comprising cooling the single-crystal semiconductor handle substrate to a temperature less than 1000 °C after annealing the semiconductor seed layer and prior to performing the two or more cycles of depositing the portion of the semiconductor layer and annealing the portion of the semiconductor layer.

24. The method of any one of claims 20-23, wherein the semiconductor layer comprises a polycrystalline semiconductor material and the semiconductor seed layer is a polycrystalline semiconductor seed layer.

25. The method of any one of claims 20-24, wherein the semiconductor seed layer has a thickness less than 3 microns.

26. The method of any one of the preceding claims, wherein depositing the semiconductor layer is performed using chemical vapor deposition.

27. The method of any one of the preceding claims, wherein the semiconductor layer comprises a polycrystalline or amorphous semiconductor material selected from the group consisting of silicon, silicon germanium (SiGe), silicon carbide (SiC), and germanium (Ge).

28. The method of any of the preceding claims, wherein the single-crystalline semiconductor handle substrate comprises silicon.

29. The method of any of the preceding claims, wherein the single-crystalline semiconductor handle substrate comprises a silicon wafer sliced from a single-crystalline silicon ingot grown by the Czochralski method or the float zone method.

30. The method of any of the preceding claims, wherein the single-crystalline semiconductor handle substrate has a bulk resistivity between 500 Ohm-cm to 100,000 Ohm-cm, between 1000 Ohm-cm to 100,000 Ohm-cm, between 1000 Ohm-cm to 10,000 Ohm-cm, between 2000 Ohm-cm to 10,000 Ohm-cm, between 3000 Ohm-cm to 10,000 Ohm-cm, or between 3000 Ohm-cm to 5000 Ohm-cm.

31. The method of any of the preceding claims, further comprising: bonding an exposed front surface layer of a single-crystalline semiconductor donor substrate to the semiconductor layer, the single-crystalline semiconductor donor substrate comprising two generally parallel major surfaces, one of which is a front surface of the single-crystalline semiconductor donor substrate and the other of which is a back surface of the single-crystalline semiconductor donor substrate, a circumferential edge connecting the front and back surfaces of the single-crystalline semiconductor donor substrate, and a central plane between the front and back surfaces of the single-crystalline semiconductor donor substrate, the single-crystalline semiconductor donor substrate further comprising a split plane to thereby form a bonded structure comprising the single-crystalline semiconductor handle substrate, the semiconductor layer, and the single-crystalline semiconductor donor substrate.

32. The method of claim 31, wherein the exposed front surface layer of the single-crystalline semiconductor donor substrate comprises a dielectric layer, and bonding the exposed front surface layer of a single-crystalline semiconductor donor substrate to the semiconductor layer comprises bonding the dielectric layer to the semiconductor layer to thereby form a bonded structure comprising the single-crystalline semiconductor handle substrate, the semiconductor layer, the dielectric layer, and the single-crystalline semiconductor donor substrate.

33. The method of claim 32, wherein the single-crystalline semiconductor donor substrate comprises a split plane, the method further comprising splitting the bonded structure at the split plane to thereby form a split structure comprising the single-crystalline semiconductor handle substrate, the semiconductor layer, the dielectric layer, and a single-crystalline semiconductor device layer.

34. A method of fabricating a multilayer structure, the method comprising: A single crystal semiconductor handle substrate is provided that includes two generally parallel major surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate; a circumferential edge connecting the front and back surfaces of the single crystal semiconductor handle substrate; and a central plane between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk resistivity of at least about 500 Ohm-cm; depositing a polycrystalline semiconductor seed layer on the front surface of the single crystal semiconductor handle substrate; annealing the polycrystalline semiconductor seed layer; depositing a first layer of polycrystalline semiconductor material on the annealed polycrystalline semiconductor seed layer at a deposition temperature; and annealing the first layer of polycrystalline semiconductor material at a temperature less than the temperature at which the polycrystalline semiconductor seed layer is annealed.

35. The method of claim 34, wherein the polycrystalline semiconductor seed layer is annealed at a temperature greater than 1000 °C and the first layer of polycrystalline semiconductor material is annealed at a temperature less than 1000 °C.

36. The method of claim 34 or claim 35, further comprising: depositing the first layer of polycrystalline semiconductor material at a deposition temperature; and annealing the first layer of polycrystalline semiconductor material at an annealing temperature less than the temperature at which the polycrystalline semiconductor seed layer is annealed.

37. The method of claim 36, wherein the deposition temperature and the annealing temperature are within 10 °C of each other.

38. The method of claim 36, wherein the deposition temperature and the annealing temperature are within 5 °C of each other.

39. The method of claim 36, wherein the deposition temperature and the annealing temperature are within 1 °C of each other.

40. The method of claim 36, wherein no temperature ramp occurs between the deposition temperature and the annealing temperature.

41. The method of claim 36, wherein the deposition temperature and the annealing temperature are each less than 1000 °C.

42. The method of claim 36, wherein the deposition temperature and the annealing temperature are each greater than 850 °C.

43. The method of claim 36, wherein the deposition temperature and the annealing temperature are each between 850 °C and 1000 °C.

44. The method of any of claims 34-43, further comprising: depositing a second layer of polycrystalline semiconductor material on the annealed first layer of polycrystalline semiconductor material; and annealing the second layer of polycrystalline semiconductor material at a temperature less than the temperature at which the polycrystalline semiconductor seed layer is annealed.

45. The method of claim 44, further comprising: depositing a third layer of polycrystalline semiconductor material on the annealed second polycrystalline semiconductor layer; and annealing the third layer of polycrystalline semiconductor material at a temperature less than the temperature at which the polycrystalline semiconductor seed layer is annealed.

46. The method of claim 45, wherein each of the first, second, and third layers of poly crystalline semiconductor material has a thickness between 0.05 microns and 5 microns.

47. The method of any claim 45, wherein each of the first, second, and third layers of poly crystalline semiconductor material has a thickness between 0.1 microns and 1 micron.

48. The method of claim 45, wherein a charge trapping layer comprising the first, second, and third layers of poly crystalline semiconductor material has a thickness between 0.1 microns and 50 microns.

49. The method of claim 45, wherein a charge trapping layer comprising the first, second, and third layers of poly crystalline semiconductor material has a thickness between 1 micron and 10 microns.

50. The method of any of claims 34-49, further comprising cooling the single crystalline semiconductor handle substrate to a temperature less than 1000 °C after annealing the poly crystalline semiconductor seed layer and before depositing the first layer of poly crystalline semiconductor material.

51. The method of any of claims 34-50, wherein the poly crystalline semiconductor seed layer has a thickness less than 3 microns.

52. The method of any of claims 34-51, wherein depositing the first layer of poly crystalline semiconductor material is performed using chemical vapor deposition.

53. The method of any of claims 34-52, wherein the first layer of poly crystalline semiconductor material comprises a semiconductor material selected from the group consisting of silicon, silicon germanium (SiGe), silicon carbide (SiC), and germanium (Ge).

54. The method of any of claims 34-53, wherein the single crystalline semiconductor handle substrate comprises silicon.

55. The method of any of claims 34-54, wherein the single crystalline semiconductor handle substrate comprises a silicon wafer sliced from a single crystalline silicon ingot grown by the Czochralski method or the float zone method.

56. The method of any of claims 34-55, wherein the single crystalline semiconductor handle substrate has a bulk resistivity between 500 Ohm-cm and 100,000 Ohm-cm, between 1000 Ohm-cm and 100,000 Ohm-cm, between 1000 Ohm-cm and 10,000 Ohm-cm, between 2000 Ohm-cm and 10,000 Ohm-cm, between 3000 Ohm-cm and 10,000 Ohm-cm, or between 3000 Ohm-cm and 5000 Ohm-cm.

57. The method of any of claims 34-56, further comprising: bonding an exposed front surface layer of a single crystalline semiconductor donor substrate to a charge trapping layer of a single crystalline semiconductor handle substrate comprising a first layer of polycrystalline semiconductor material, the single crystalline semiconductor donor substrate comprising two substantially parallel major surfaces, one of which is a front surface of the single crystalline semiconductor donor substrate and the other of which is a back surface of the single crystalline semiconductor donor substrate, a circumferential edge connecting the front and back surfaces of the single crystalline semiconductor donor substrate, and a central plane between the front and back surfaces of the single crystalline semiconductor donor substrate, the single crystalline semiconductor donor substrate further comprising a split plane to thereby form a bonded structure comprising the single crystalline semiconductor handle substrate, the charge trapping layer, and the single crystalline semiconductor donor substrate.

58. The method of claim 57, wherein the exposed front surface layer of the single crystalline semiconductor donor substrate comprises a dielectric layer, and bonding the exposed front surface layer of a single crystalline semiconductor donor substrate to the charge trapping layer comprises bonding the dielectric layer to the charge trapping layer to thereby form a bonded structure comprising the single crystalline semiconductor handle substrate, the charge trapping layer, the dielectric layer, and the single crystalline semiconductor donor substrate.

59. The method of claim 58, wherein the single crystalline semiconductor donor substrate comprises a split plane, the method further comprising splitting the bonded structure at the split plane to thereby form a split structure comprising the single crystalline semiconductor handle substrate, the charge trapping layer, the dielectric layer, and a single crystalline semiconductor device layer.

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