In-memory processor and memory device including the same

Abstract

In accordance with some embodiments of the present disclosure, an in-memory processor included in a memory device may be provided. The in-memory processor may include an instruction list circuit configured to store a first instruction including a first register index field; the calculation register array comprises a plurality of calculation registers; a processing management circuit configured to store a register index rule table including a first register index rule corresponding to a value of the first register index field and an address log, and the processing management circuitry is configured to identify a first compute register of the plurality of compute registers based on a first register index rule and the address log; and a computing circuit configured to perform a first computing operation for the first instruction based on the first computing register.

Description

Cross Reference to Related Applications

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0095143, filed on July 18, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The disclosure relates to a semiconductor memory device. More specifically, the disclosure relates to an in-memory processor configured to perform a computation and a memory device including the same. BACKGROUND

[0003] Generally, the operating speed of a storage system including a memory device and a host device can be bottlenecked by the communication speed between the memory device and the host device. Accordingly, various techniques for solving the bottleneck due to the communication speed are being researched. For example, recently, an in-memory processing (PIM) technique in which a memory device performs an in-memory processing operation has been researched.

[0004] The memory device can include an in-memory processor. The in-memory processor can perform a predefined computation operation in response to a request from the host device. However, the number of computation operations that can be performed by the in-memory processor can be limited due to various reasons such as the width of a command / address signal channel formed between the host device and the memory device. SUMMARY

[0005] The disclosure attempts to solve the above-described technical problems. More specifically, the disclosure attempts to provide an in-memory processor configured to perform a large number of computation operations and a memory device including the same.

[0006] Some embodiments of the disclosure provide an in-memory processor included in a memory device, the in-memory processor can include an instruction list circuit configured to store a first instruction including a first register index field, a computation register array including a plurality of computation registers, a processing management circuit configured to store a register index rule table including a first register index rule corresponding to a value of the first register index field and an address log, the processing management circuit being configured to identify a first computation register of the plurality of computation registers based on the first register index rule and the address log, and a computation circuit configured to perform a first computation operation for the first instruction based on the first computation register.

[0007] Some embodiments of the present disclosure provide an in-memory processor included in a memory device, the in-memory processor can include: an instruction list circuit configured to store a first instruction; a plurality of computation registers; a processing management circuit configured to determine a first register index based on a first register index rule in response to receiving a first execution request for the first instruction at a first time point, and determine a second register index based on a second register index rule in response to receiving a second execution request for the first instruction at a second time point after the first time point; and a computation circuit configured to perform a first computation operation for the first instruction based on a first computation register of the plurality of computation registers corresponding to the first register index, and perform a second computation operation for the first instruction based on a second computation register of the plurality of computation registers corresponding to the second register index.

[0008] Some embodiments of the present disclosure provide a memory device configured to perform a computation operation, the memory device can include: an in-memory processor configured to perform the computation operation based on a target computation register of a plurality of computation registers; and a control logic circuit configured to change a register index rule used to determine the target computation register in response to a command provided from an external device. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a block diagram illustrating a storage system according to some embodiments of the present disclosure.

[0010] Figure 2 is a block diagram of a memory device of Figure 1 more specifically illustrating.

[0011] Figure 3 is a block diagram of an in-memory processor of Figure 2 more specifically illustrating.

[0012] Figure 4 is a table illustrating a configuration of an instruction list circuit of Figure 3 more specifically illustrating.

[0013] Figure 5 is a diagram illustrating a configuration of an instruction of Figure 4 more specifically illustrating.

[0014] Figure 6 is a diagram illustrating a register index rule table of Figure 3 more specifically illustrating.

[0015] Figure 7 is a diagram illustrating an operation of an in-memory processor according to some embodiments more specifically illustrating.

[0016] Figure 8 is a diagram illustrating an operation of an in-memory processor according to some embodiments more specifically illustrating.Figure 7 a timing diagram of the operation of a memory device according to some embodiments.

[0017] Figure 9 is a diagram showing the operation of an in-memory processor according to some embodiments.

[0018] Figure 10 is a timing diagram of the operation of a memory device according to some embodiments. Figure 9

[0019] Figure 11 is a flowchart showing the operation of a memory device according to some embodiments of the present disclosure.

[0020] Figure 12 is a diagram showing step S1400 of Figure 11

[0021] Figure 13 is a diagram showing step S1430 of Figure 12

[0022] Figure 14 is a diagram showing step S1433 of Figure 13

[0023] Figure 15 is a block diagram showing a storage system according to some embodiments.

[0024] Figure 16 is a block diagram showing the configuration of a processing management circuit of Figure 15 Figure 3

[0025] Figure 17 is a diagram showing a method of changing an access key by a memory controller of Figure 15

[0026] Figure 18 is a flowchart showing the operation of a memory controller of Figure 15

[0027] Figure 19 and Figure 20 show a method of storing a plurality of register index rules in a register index rule table of Figure 3

[0028] Figure 21 is a block diagram showing a storage system according to some embodiments.

[0029] Figure 22 is a command truth table showing the configuration of a processing command implemented according to some embodiments. DETAILED DESCRIPTION​​​​​​​​​

[0030] Hereinafter, embodiments of the disclosure will be described clearly and specifically so that those skilled in the art to which the disclosure pertains can easily implement the disclosure. Details such as detailed configurations and structures are provided only to help overall understanding of the embodiments of the disclosure. Therefore, those skilled in the art can transform the embodiments described herein without departing from the technical spirit and scope of the disclosure. Also, descriptions of well-known functions and structures are omitted for the sake of clarity and conciseness. Components in the following drawings or detailed description can be shown in the drawings or connected with components other than those described in the detailed description. Terms used herein are defined in consideration of functions of the disclosure and are not limited to specific functions. Definitions of the terms can be determined based on details described in the detailed description.

[0031] Components described with reference to terms such as drivers or blocks used in the detailed description can be implemented in the form of software, hardware, or a combination thereof. For example, the software can be machine code, firmware, embedded code, and / or application software. For example, the hardware can include circuitry, electronic circuitry, processors, computers, integrated circuit cores, pressure sensors, inertial sensors, micro electro mechanical systems (MEMS), passive elements, or a combination thereof.

[0032] Figure 1 is a block diagram illustrating a storage system according to some embodiments of the disclosure. Referring to Figure 1 , the storage system MS can include a memory controller 10 and a memory device 100. The memory device 100 can include a memory cell array 110 and an in-memory processor 120.

[0033] In some embodiments, the storage system MS can be included in various types of electronic devices including a smart phone, a notebook computer, a personal computer, a tablet computer, etc.

[0034] In some embodiments, the memory controller 10 can be included in one of various types of processors including a central processing unit (CPU), a graphics processing unit (GPU), etc.

[0035] Hereinafter, for brief description, it is assumed that the memory device 100 is a dynamic random access memory (DRAM) device, and the memory controller 10 and the memory device 100 communicate with each other based on a low power double data rate (LPDDR) interface. However, the scope of the disclosure is not limited thereto. For example, the memory controller 10 and the memory device 100 can communicate with each other based on a double data rate (DDR) interface.

[0036] The memory controller 10 transmits a command CMD and / or an address ADDR to the memory device 100 to control the operation of the memory device 100. For example, the memory controller 10 can provide the command CMD and the address ADDR to the memory device 100 based on a plurality of command / address signals C / A.

[0037] The memory device 100 can operate in response to the control of the memory controller 10. For example, in response to the command CMD and the address ADDR, the memory device 100 can store data in the memory cell array 110 or provide data stored in the memory cell array 110 to the memory controller 10.

[0038] The memory device 100 can perform various computing operations in response to the control of the memory controller 10. For example, the in-memory processor 120 can perform various computing operations based on a processing command (hereinafter, referred to as "PROC") provided from the memory controller 10.

[0039] In some embodiments, the in-memory processor 120 can perform a computing operation based on one or more operands. For example, the in-memory processor 120 can perform various computations including addition, multiplication, multiply and accumulate (MAC), etc. In this case, although the memory controller 10 does not read one or more operands from the memory device 100, the memory controller 10 can receive a result of a computation based on one or more operands from the memory device. Accordingly, according to embodiments of the disclosure, a bottleneck phenomenon of the operation of the memory system MS due to communication between the memory controller 10 and the memory device 100 can be minimized.

[0040] Figure 2 is a block diagram of a memory device more specifically illustrating Figure 1 Referring to Figure 2 , the memory device 100 can include a memory cell array 110, an in-memory processor 120, a command / address (C / A) decoder 130, a control logic circuit 140, a row decoder 150, and an input / output (I / O) circuit 160.

[0041] The memory cell array 110 can include a plurality of memory cells arranged in a row direction and a column direction. The plurality of memory cells can be connected to a plurality of word lines WL extending in the row direction and a plurality of bit lines BL extending in the column direction.

[0042] The command / address decoder 130 can receive a command / address signal C / A provided from the memory controller 10. The command / address decoder 130 can decode a plurality of command / address signals C / A into a command CMD and an address ADDR.

[0043] The control logic circuit 140 can receive the command CMD and the address ADDR from the command / address decoder 130. The control logic circuit 140 can control overall operations of the memory device 100 based on the command CMD and the address ADDR. For example, the control logic circuit 140 can control operations of the in-memory processor 120, the row decoder 150, and the input / output circuit 160.

[0044] The row decoder 150 can control the plurality of word lines WL based on the control of the control logic circuit 140. For example, the row decoder 150 can activate one of the plurality of word lines WL in response to the control of the control logic circuit 140.

[0045] The input / output circuit 160 can receive the data DATA from the memory controller 10 or transmit the data DATA to the memory controller 10.

[0046] The input / output circuit 160 can be physically and / or electrically connected to the memory cell array 110 through the plurality of bit lines BL. The input / output circuit 160 can read the data DATA stored in the memory cell array 110 or store the data DATA in the memory cell array 110 by controlling the plurality of bit lines BL.

[0047] The in-memory processor 120 can include a plurality of computation registers CR. The in-memory processor 120 can perform a computation operation based on the plurality of computation registers CR. For example, the in-memory processor 120 can perform a computation operation based on data stored in the computation registers CR or store a computation result generated by performing the computation operation in the computation registers CR.

[0048] In some embodiments, each of one or more operands of the computation operation performed by the in-memory processor 120 can be data stored in the computation registers CR or data provided from the memory cell array 110 through the input / output circuit 160.

[0049] In some embodiments, the in-memory processor 120 can provide a computation result generated by performing the computation operation to the memory controller 10 through the input / output circuit 160.

[0050] The computation operation that can be performed by the in-memory processor 120 can be predetermined. For example, the in-memory processor 120 can store a plurality of instructions INST. Each of the plurality of instructions INST can indicate a type of computation to be performed by the in-memory processor 120, a location of an operand, a location to store a computation result, and the like. Reference will be made to Figure 4 The configuration of each of the plurality of instructions INST will be described in more detail.

[0051] The control logic circuit 140 can control the operation of the in-memory processor 120 based on the processing command PROC. For example, the control logic circuit 140 can provide an execution request REQ EXE indicating one of the plurality of instructions INST to the in-memory processor 120 in response to the processing command PROC. In this case, the in-memory processor 120 can execute the instruction INST indicated by the execution request REQ EXE.

[0052] The number of instructions INST stored in the in-memory processor 120 can be limited. For example, the number of instructions INST stored in the in-memory processor 120 can be determined based on the width of a channel through which the command / address signals C / A are transmitted between the memory controller 10 and the memory device 100. In other words, the number of instructions INST that can be executed by the in-memory processor 120 can not be large enough. As a result, the number of computing operations that can be instructed by the memory controller 10 to the in-memory processor 120 can be limited. For example, the memory controller 10 can request only one of the plurality of instructions INST stored in the in-memory processor 120 to be executed, and it can be difficult for the memory controller 10 to instruct the in-memory processor 120 to perform an arbitrary computing operation based on an arbitrary computing register CR (e.g., an arbitrary combination of a computing operation and a computing register CR).

[0053] In some embodiments, the control logic circuit 140 can provide the in-memory processor 120 with an address ADDR corresponding to the processing command PROC. Some of the plurality of instructions INST can indicate one or more of a location of an operand and a location to store a result of a computation based on the address ADDR. For example, some of the plurality of instructions INST can indicate one or more of a computing register storing an operand and a computing register storing a result of a computation based on the address ADDR corresponding to the processing command PROC. That is, some of the plurality of instructions INST can represent a computing register CR for executing the instruction INST based on the address ADDR. In this case, the in-memory processor 120 can execute the instruction INST based on the computing register CR determined by the address ADDR. Accordingly, the memory controller 10 can control detailed operations of the in-memory processor 120 based on the address ADDR. For example, based on the address ADDR, the memory controller 10 can instruct the in-memory processor 120 to execute the instruction INST based on which computing register CR. Therefore, according to embodiments of the disclosure, since the memory controller 10 can more freely control the in-memory processor 120, the operation efficiency of the memory system MS can be improved.

[0054] In some embodiments, the in-memory processor 120 can store a plurality of register index rules (hereinafter, referred to as "RIRs") for a plurality of instructions INST. The in-memory processor 120 can identify a computational register CR for executing an instruction INST based on the plurality of register index rules RIRs and an address ADDR.

[0055] In some embodiments, the memory controller 10 can change one or more of the plurality of register index rules RIRs corresponding to the plurality of instructions INST. In this case, a computational register CR for executing an instruction INST can be identified based on the changed register index rules. That is, the memory controller 10 can change a computational register CR to be used for executing a corresponding instruction INST by changing a register index rule RIR corresponding to the specific instruction INST. Accordingly, according to embodiments of the disclosure, since the memory controller 10 can more freely control the in-memory processor 120, the operation efficiency of the storage system MS can be improved.

[0056] Figure 3 is a block diagram of an in-memory processor 120 more specifically illustrating Figure 2 Referring to Figures 1 to 3 , the in-memory processor 120 can include an instruction list circuit 121, a processing management circuit 122, a computation circuit 123, and a computational register array 124.

[0057] The instruction list circuit 121 can include a plurality of instructions INST. For example, the instruction list circuit 121 can include a first instruction INST1 to an n-th instruction INSTn. The first instruction INST1 to the n-th instruction INSTn can respectively correspond to different combinations of a type of computation to be performed by the in-memory processor 120, a location of an operand, and a location to store a result of the computation. The configuration of the first instruction INST1 to the n-th instruction INSTn will be described more specifically below with reference to Figure 4

[0058] In some embodiments, the first instruction INST1 to the n-th instruction INSTn can be identified based on instruction identifiers (hereinafter, referred to as "IDs") different from each other. For example, the first instruction INST1 to the n-th instruction INSTn can respectively correspond to a first instruction identifier to an n-th instruction identifier.

[0059] The processing management circuit 122 can control the overall operation of the in-memory processor 120. For example, the processing management circuit 122 can communicate with the instruction list circuit 121, the computation circuit 123, and the computational register array 124.

[0060] The computation circuit 123 can perform a computation operation. For example, the computation circuit 123 can perform a computation operation based on a computational register CR from the computational register array 124 and an operand from the instruction list circuit 121.​Figure 2 The input / output circuit 160 provides one or more operands shown in the middle to perform various types of computing operations.

[0061] The computing register array 124 can include a plurality of computing registers CR. For example, the computing register array 124 can include a plurality of computing registers CRa_1 to CRa_p of a first computing register type CRTa and a plurality of computing registers CRb_1 to CRb_q of a second computing register type CRTb. Hereinafter, for a brief description, some embodiments in which the plurality of computing registers CR included in the computing register array 124 are classified into two types will be representatively described. However, the scope of the present disclosure is not limited to the number of computing register types CRT of the computing registers CR included in the computing register array 124.

[0062] In some embodiments, the plurality of computing registers of the same computing register type can be identified based on different register indexes. For example, the plurality of computing registers CRa_1 to CRa_p can respectively correspond to register indexes "1" to "p"; and the plurality of computing registers CRb_1 to CRb_q can respectively correspond to register indexes "1" to "q". That is, each of the plurality of computing registers CR can be identified from each other based on the computing register type and the register index. The detailed method of identifying each of the plurality of computing registers CR will be described more specifically with reference to the following drawings.

[0063] In some embodiments, each of the plurality of computing registers CRa_1 to CRa_p of the first computing register type CRTa can be a register for storing scalar data, and the plurality of computing registers CRb_1 to CRb_q of the second computing register type CRTb can be a register for storing vector data. For example, the capacity of each of the plurality of computing registers CRa_1 to CRa_p can be 32 bits, and the capacity of each of the plurality of computing registers CRb_1 to CRb_q can be an integer multiple of 32 bits. However, the scope of the present disclosure is not limited thereto.

[0064] Each of the plurality of computing registers CR can store an operand or a computing result for a computing operation to be performed by the computing circuit 123.

[0065] The processing management circuit 122 can receive an execution request REQ_EXE from the control logic circuit 140. The execution request REQ_EXE can represent one of the first instruction INST1 to the n-th instruction INSTn. For example, the execution request REQ_EXE can include an instruction identifier ID of one of the first instruction INST1 to the n-th instruction INSTn.

[0066] The processing management circuit 122 can execute one instruction INST in response to the execution request REQ_EXE. For example, the processing management circuit 122 can execute the instruction INST corresponding to the instruction identifier ID included in the execution request REQ_EXE. In this case, the processing management circuit 122 can control the computing circuit 123 and the computing register array 124 to execute the operation indicated by the instruction INST corresponding to the execution request REQ_EXE. For example, the processing management circuit 122 can supply the operand stored in the input / output circuit 160 and / or the computing register array 124 to the computing circuit 123, or store the computation result generated from the computing circuit 123 in the computing register array 124.

[0067] Meanwhile, one or more of the first instruction INST1 to the n-th instruction INSTn can represent the location of the operand and / or the location to store the computation result based on the address ADDR. When one of such instructions INST is executed, the processing management circuit 122 can identify the location of the operand and / or the location to store the computation result based on the address ADDR supplied from the control logic circuit 140.

[0068] More specifically, the processing management circuit 122 can manage an address log LOG. The processing management circuit 122 can receive the address ADDR from the control logic circuit 140. For example, the processing management circuit 122 can receive the address ADDR corresponding to the processing command PROC from the control logic circuit 140. The processing management circuit 122 can store the received address ADDR in the address log LOG.

[0069] The processing management circuit 122 can manage a register index rule table RIRT. The register index rule table RIRT can include a plurality of register index rules RIR. The processing management circuit 122 can identify the location of the operand and / or the location to store the computation result corresponding to the instruction INST to be executed by converting the address ADDR stored in the address log LOG using one of the plurality of register index rules RIR. The specific method in which the processing management circuit 122 identifies the "location of the operand" and / or the "location to store the computation result" based on the address log LOG and the register index rule table RIRT will be described more specifically with reference to the following drawings.

[0070] In some embodiments, the processing management circuit 122 can communicate with the input / output circuit 160 in response to control by the control logic circuit 140. For example, the processing management circuit 122 can store an operand provided from the input / output circuit 160 in one of the plurality of computation registers CR, or provide the operand to the computation circuit 123. As another example, the processing management circuit 122 can provide a computation result generated by the computation circuit 123 to the memory controller 10 through the input / output circuit 160.

[0071] Figure 4 is a table showing a configuration of the instruction list circuit of Figure 3 more specifically. Referring to Figures 1 to 4 , the instruction list circuit 121 can include a first instruction INST1 to an n-th instruction INSTn.

[0072] Hereinafter, for simplicity of description, it is assumed that each of the first instruction INST1 to the n-th instruction INSTn instructs to generate one computation result by executing a computation operation having two operands. In this case, the in-memory processor 120 can generate a computation result by executing a computation using a first operand and a second operand based on one instruction INST. In this case, a location where the first operand is stored will be referred to as a first source (source #1), a location where the second operand is stored will be referred to as a second source (source #2), and a location where the computation result is to be stored will be referred to as a destination. However, the scope of the present disclosure is not limited thereto.

[0073] The first instruction INST1 to the n-th instruction INSTn can be identified based on a first instruction identifier ID1 to an n-th instruction identifier IDn, respectively. For example, when the execution request REQ_EXE includes the first instruction identifier ID1, the processing management circuit 122 can execute the first instruction INST1.

[0074] Each of the first instruction INST1 to the n-th instruction INSTn can include an operation type field OP, an output format field OF, a destination type field TD, a first source type field TSa, a second source type field TSb, a destination register location field LD, a first source register location field LSa, and a second source register location field LSb.

[0075] Hereinafter, for simplicity of description, the operation type field OP, the output format field OF, the destination type field TD, the first source type field TSa, the second source type field TSb, the destination register location field LD, the first source register location field LSa, and the second source register location field LSb included in the ith instruction INSTi are referred to as operation type field OPI, output format field OFI, destination type field TDI, first source type field TSAl, second source type field TSBl, destination register location field LDI, first source register location field LSAl, and second source register location field LSBl, respectively. For example, the first instruction INST1 can include operation type field OP1, output format field OF1, destination type field TD1, first source type field TSa1, second source type field TSb1, destination register location field LD1, first source register location field LSa1, and second source register location field LSb1.

[0076] Each of the operation type fields OP1 to OPn can represent a type of in-memory processing computation. For example, each of the operation type fields OP1 to OPn can represent one of various types of operations such as addition, multiplication, multiply and accumulate (MAC), etc. However, the scope of the present disclosure is not limited to the particular types of in-memory processing operations represented by the operation type fields OP.

[0077] Each of the output format fields OF1 to OFn can represent a data type of a computation result. For example, each of the output format fields OF1 to OFn can represent one of various types of data types including FP32, FP16, INT8, etc. As a more detailed example, when the output format field OF1 represents the FP32 data type, the computation circuit 123 can generate a computation result having the FP32 data type by executing the first instruction INST1. However, the scope of the present disclosure is not limited to the particular data types represented by the output format fields OF.

[0078] Each of the destination type fields TD1 through TDn can represent a type of storage space in which to store a result of the computation. For example, each of the destination type fields TD1 through TDn can represent one of various storage space types including the first compute register type CRTa, the second compute register type CRTb, the storage cell array 110, and so on. As a more detailed example, when the destination type field TD1 represents the first compute register type CRTa, the processing management circuit 122 can execute the first instruction INST1 and store the generated result in one of the plurality of compute registers CRa_1 through CRa_p; when the destination type field TD1 represents the second compute register type CRTb, the processing management circuit 122 can execute the first instruction INST1 and store the generated result in one of the plurality of compute registers CRb_1 through CRb_q; and when the destination type field TD1 represents the storage cell array 110, the processing management circuit 122 can execute the first instruction INST1 and store the generated result in the storage cell array 110.

[0079] Each of the first source type fields TSa1 through TSan can represent a type of storage space in which to store a first operand. For example, each of the first source type fields TSa1 through TSan can represent one of various storage space types including, for example, the first compute register type CRTa, the second compute register type CRTb, the storage cell array 110, and so on. As a more detailed example, when the first source type field TSa1 represents the first compute register type CRTa, the processing management circuit 122 can read the first operand for execution of the first instruction INST1 from one of the plurality of compute registers CRa_1 through CRa_p and provide the first operand to the compute circuit 123; when the first source type field TSa1 represents the second compute register type CRTb, the processing management circuit 122 can read the second operand for execution of the first instruction INST1 from one of the plurality of compute registers CRb_1 through CRb_q and provide the second operand to the compute circuit 123; and when the first source type field TSa1 represents the storage cell array 110, the processing management circuit 122 can read the first operand for execution of the first instruction INST1 from the storage cell array 110 and provide the first operand to the compute circuit 123.

[0080] Similarly, each of the second source type fields TSb1 through TSbn can represent a type of storage space in which to store a second operand. For example, each of the second source type fields TSb1 through TSbn can represent one of various storage space types including the first compute register type CRTa, the second compute register type CRTb, the storage cell array 110, and so on.

[0081] Hereinafter, for the sake of brief description, when the destination type field TD indicates any compute register type (e.g., the first compute register type CRTa or the second compute register type CRTb), a compute register for storing a result of a computation can be referred to as a destination register or a destination compute register. Similarly, when the first source type field TSa indicates any compute register type (e.g., the first compute register type CRTa or the second compute register type CRTb), a compute register storing a first operand can be referred to as a first source register or a first source compute register. Similarly, when the second source type field TSb indicates any compute register type (e.g., the first compute register type CRTa or the second compute register type CRTb), a compute register storing a second operand can be referred to as a second source register or a second source compute register. In addition, a compute register for a computation operation performed by the in-memory processor 120 can be referred to as a target compute register. For example, each of the destination register, the first source register, and the second source register can be referred to as a target compute register.

[0082] Each of the destination register location fields LD1 to LDn can more specifically indicate a location of the destination register. That is, each of the destination register location fields LD1 to LDn can indicate which compute register among compute registers having a compute register type indicated by the corresponding destination type field TD is to be used to store a result of a computation. For example, each of the destination register location fields LD1 to LDn can indicate a register index. As a more detailed example, when the destination type field TD1 indicates the first compute register type CRTa, the destination register location field LD1 can indicate, based on one of the register indexes “1” to “p”, which compute register among the plurality of compute registers CRa_1 to CRa_p is the destination register.

[0083] In some embodiments, when the destination type field TD indicates the memory cell array 110, the destination register location field LD corresponding thereto can not be used. However, the scope of the present disclosure is not limited thereto.

[0084] Each of the first source register position fields LSa1 to LSan can more specifically indicate a location of the first source register. That is, each of the first source register position fields LSa1 to LSan can indicate which of the calculation registers having the calculation register type indicated by the corresponding first source type field TSa is to store the first operand. For example, each of the first source register position fields LSa1 to LSan can indicate one register index. As a more detailed example, when the first source type field TSa indicates the second calculation register type CRTb, the first source register position field LSa1 can indicate which of the plurality of calculation registers CRb_1 to CRb_q is the first source register based on one of the register indexes “1” to “q”.

[0085] In some embodiments, when the first source type field TSa indicates the storage unit array 110, the first source register position field LSa corresponding thereto can not be used. However, the scope of the present disclosure is not limited thereto.

[0086] Similarly thereto, each of the second source register position fields LSb1 to LSbn can more specifically indicate a calculation register storing the second operand. For example, similarly to the description of the first source register position fields LSa1 to LSan, each of the second source register position fields LSb1 to LSbn can indicate the second source register based on one register index.

[0087] In some embodiments, when the second source type field TSb indicates the storage unit array 110, the second source register position field LSb corresponding thereto can not be used. However, the scope of the present disclosure is not limited thereto.

[0088] Figure 5 is a more specific diagram illustrating Figure 4 an instruction of Figures 1 to 5 Hereinafter, a configuration of the first instruction INST1 will be representatively described. However, the scope of the present disclosure is not limited thereto, and the second instruction INST2 to the n-th instruction INSTn can also be implemented by a similar scheme thereto.

[0089] The first instruction INST1 can include a destination register position field LD1, a first source register position field LSa1, and a second source register position field LSb1. Each of the destination register position field LD1, the first source register position field LSa1, and the second source register position field LSb1 can include an address alignment field FLD_AA and a register index field FLD_IDX.

[0090] The address alignment field FLD AA of each of the destination register position field LD1, the first source register position field LSa1, and the second source register position field LSb1 can indicate whether the corresponding calculation register is identified based on an address alignment scheme. For example, the address alignment field FLD AA of each of the destination register position field LD1, the first source register position field LSa1, and the second source register position field LSb1 can indicate that the register index is indicated based on an address ADDR or by a register index field FLD IDX. Hereinafter, a specific scheme of determining the register index value indicated by the destination register position field LD1, the first source register position field LSa1, and the second source register position field LSb1 according to the value of the address alignment field FLD AA will be described.

[0091] When the address alignment field FLD AA of the destination register position field LD1 is "1", the processing management circuit 122 can determine the destination register based on the address ADDR. For example, the processing management circuit 122 can identify one of the plurality of register index rules RIR stored in the register index rule table RIRT based on the value of the register index field FLD IDX of the destination register position field LD1, and calculate or determine one register index by assigning the address ADDR stored in the address log LOG to the identified register index rule RIR. In this case, the processing management circuit 122 can store the calculation result in the calculation register corresponding to the calculated register index. As a more detailed example, the destination type field TD can indicate the first calculation register type CRTa, and the value of the register index field FLD IDX of the destination register position field LD1 can be "0b00001". In this case, the processing management circuit 122 can identify the register index rule RIR corresponding to "0b00001" among the plurality of register index rules RIR stored in the register index rule table RIRT, or determine a register index "i" (where i denotes an arbitrary integer) by assigning the address ADDR stored in the address log LOG to the identified register index rule RIR. In this case, the processing management circuit 122 can determine the calculation register CRa_i as the destination register, and store the calculation result in the calculation register CRa_i. Hereinafter, the scheme of determining one of the plurality of register index rules RIR stored in the register index rule table RIRT based on the register index field FLD IDX, and the scheme of calculating the register index based on the identified register index rule RIR and the address log LOG will be described in more detail. Figures 6 to 10 The scheme of determining one of the plurality of register index rules RIR stored in the register index rule table RIRT based on the register index field FLD IDX, and the scheme of calculating the register index based on the identified register index rule RIR and the address log LOG will be described in more detail.

[0092] Similarly, when the address alignment field FLD AA of the first source register location field LSal is "1", the processing management circuit 122 can determine the first source register based on the address ADDR. For example, the first source type field TSal can represent the second compute register type CRTb, and the value of the register index field FLD IDX of the first source type field TSal can be "0b00011". In this case, the processing management circuit 122 can identify the register index rule RIR corresponding to "0b00011" among the plurality of register index rules RIR stored in the register index rule table RIRT, and calculate or determine the register index "j" (where j represents an arbitrary integer) by assigning the address ADDR stored in the address log LOG to the identified register index rule RIR.

[0093] In this case, the processing management circuit 122 can determine the compute register CRb_j as the first source register, and acquire the first operand from the compute register CRb_j.

[0094] On the contrary, when the address alignment field FLD AA of the second source register location field LSbl is "0", the processing management circuit 122 can determine the second source register regardless of the address ADDR. For example, the processing management circuit 122 can determine the value of the register index field FLD IDX of the second source register location field LSbl as the register index represented by the second source register location field LSbl. In this case, the processing management circuit 122 can acquire the second operand from the compute register corresponding to the register index field FLD IDX of the second source register location field LSbl. As a more detailed example, when the second source type field TSbl represents the first compute register type CRTa, and the value of the register index field FLD IDX of the second source register location field LSbl is "0b10110", the processing management circuit 122 can read the second operand from the compute register CRa_0b10110.

[0095] In some embodiments, the code length of the register index field FLD IDX can be too short to represent each of the plurality of compute registers CR included in the compute register array 124. For example, the power of 2 for the code length of the register index field FLD IDX as a base can be less than “p” or “q”. As a result, it can be difficult to represent some of the plurality of compute registers CR only with (e.g., without using the address ADDR) the register location field (e.g., one of the destination register location field LD, the first source register location field LSa, and the second source register location field LSb) when the address alignment field FLD AA is “0”. In contrast, according to embodiments of the present disclosure, the register location field can represent each of the plurality of compute registers CR based on the address ADDR.

[0096] Figure 6 is a diagram illustrating a register index rule table of Figure 3 in more detail. Referring to Figures 1 to 6 , the register index rule table RIRT can include a plurality of register index rules RIR. For example, the register index rule table RIRT can include a first register index rule RIR1, a second register index rule RIR2, a third register index rule RIR3, and a fourth register index rule RIR4. However, the scope of the present disclosure is not limited to the number of register index rules included in the register index rule table RIRT.

[0097] Each of the first register index rule RIR1, the second register index rule RIR2, the third register index rule RIR3, and the fourth register index rule RIR4 can represent a different rule (e.g., formula) for the address ADDR stored in the address log LOG. For example, the first register index rule RIR1 can represent a concatenation of the second bit to the 0th bit of the column address CA (i.e., CA[2:0]) stored in the address log LOG; the second register index rule RIR2 can represent a concatenation of the third bit to the 0th bit of the column address CA (i.e., CA[3:0]) stored in the address log LOG; the third register index rule RIR3 can represent a value obtained by multiplying the 0th bit of the row address RA (i.e., RA[0]) stored in the address log LOG by a concatenation of the fourth bit to the third bit of the column address CA (i.e., CA[4:3]) by “2” and then adding “8”; and the fourth register index rule RIR4 can represent a value obtained by multiplying a concatenation of the second bit to the 0th bit of the row address RA (i.e., CA[2:0]) stored in the address log LOG by “2”. However, the scope of the present disclosure will not be limited to the specific configuration of the register index rules RIR.

[0098] Further, for brief description, some embodiments in which each of the plurality of register index rules RIR is defined based on a row address RA and a column address CA will be representatively described. However, the scope of the present disclosure is not limited thereto. For example, some of the plurality of register index rules RIR can be defined based on various types of addresses including a stack identifier, a memory bank address, etc.

[0099] Each of the plurality of register index rules RIR can correspond to a different access key AK. For example, a first register index rule RIR1, a second register index rule RIR2, a third register index rule RIR3, and a fourth register index rule RIR4 can correspond to a first access key AK1, a second access key AK2, a third access key AK3, and a fourth access key AK4, respectively.

[0100] The first access key AK1, the second access key AK2, the third access key AK3, and the fourth access key AK4 can correspond to different values (e.g., binary codes), respectively. For example, the first access key AK1, the second access key AK2, the third access key AK3, and the fourth access key AK4 can correspond to "0b00000", "0b00001", "0b00010", and "0b00011", respectively.

[0101] The processing management circuit 122 can select one of the plurality of register index rules RIR based on the plurality of access keys AK. More specifically, when the address alignment field FLD_AA of the first source register location field LSa1 is "1", the processing management circuit 122 can identify an access key AK corresponding to the register index field FLD_IDX of the first source register location field LSa1. For example, when the value of the register index field FLD_IDX of the first source register location field LSa1 is "0b00011", the processing management circuit 122 can select the fourth register index rule RIR4 corresponding to the fourth access key AK4.

[0102] The processing management circuit 122 can calculate or determine a register index based on the address ADDR stored in the address log LOG according to the selected register index rule RIR. For example, the processing management circuit 122 can calculate or determine a register index by assigning the address ADDR stored in the address log LOG to the fourth register index rule RIR4.

[0103] The processing management circuit 122 can determine the calculation register for the in-memory processing operation based on the calculated register index. For example, when the first source type field TSa1 indicates the first calculation register type CRTa, and the first source register position field LSa1 indicates the register index "i", the processing management circuit 122 can read the first operand from the calculation register CRa_i.

[0104] Through such a scheme, the processing management circuit 122 can identify the first source register, the second source register, and the destination register based on the address ADDR.

[0105] In some embodiments, the processing management circuit 122 can manage one register index rule table RIRT. In this case, the processing management circuit 122 can identify all of the first source register, the second source register, and the destination register based on one register index rule table RIRT.

[0106] According to embodiments of the present disclosure, the calculation register for executing one instruction INST can vary depending on the address ADDR stored in the address log LOG. In this case, one instruction INST can indicate a plurality of calculation operations for different combinations of a plurality of data stored in a plurality of calculation registers CR. Therefore, according to embodiments of the present disclosure, since the number of calculation operations that can be instructed by the memory controller 10 can increase, the degree of freedom of the in-memory processing operation controlled by the memory controller 10 can be improved.

[0107] The following will be described with reference to Figures 7 to 10 The address ADDR stored in the address log LOG will be described more specifically.

[0108] Figure 7 is a diagram that more specifically illustrates the operation of the in-memory processor according to some embodiments. Referring to Figures 1 to 7 , the in-memory processor 120 can perform an in-memory processing operation based on the first operand OPRa stored in the calculation register array 124 and the second operand OPRb stored in the memory cell array 110. That is, the calculation circuit 123 can perform a calculation operation with respect to the first operand OPRa provided from the calculation register array 124 and the second operand OPRb provided from the memory cell array 110.

[0109] As a more detailed example, the processing management circuit 122 can receive an execution request REQ EXE representing the first instruction INST1 from the control logic circuit 140. For example, the processing management circuit 122 can receive the execution request REQ EXE including the first instruction identifier ID1. The processing management circuit 122 can execute the first instruction INST1 in response to the execution request REQ EXE. Hereinafter, for a brief description, some embodiments in which the processing management circuit 122 executes the first instruction INST1 will be representatively described.

[0110] The first instruction INST1 can include a first source type field TSa1 and a second source type field TSb1. The first source type field TSa1 can represent the second computation register type CRTb. The second source type field TSb1 can represent the storage unit array 110. That is, hereinafter, for a brief description, some embodiments in which the first source type field TSa1 represents the second computation register type CRTb will be representatively described. However, the scope of the present disclosure is not limited thereto. For example, the first source type field TSa1 can also represent the first computation register type CRTa.

[0111] The first instruction INST1 can include a first source register position field LSa1 and a second source register position field LSb1.

[0112] The first source register position field LSa1 can represent a register index. For example, when the address alignment field FLD AA of the first source register position field LSa1 is "0", the first source register position field LSa1 can represent the register index field FLD IDX of the first source register position field LSa1 as a register index; when the address alignment field FLD AA of the first source register position field LSa1 is "1", the first source register position field LSa1 can represent a result obtained by allocating the address ADDR included in the address log LOG to a register index rule RIR determined based on a value of the register index field FLD IDX of the first source register position field LSa1 as a register index. In this case, the processing management circuit 122 can acquire the first operand OPRa from a computation register corresponding to the register index represented by the first source register position field LSa1 among the computation registers CRb_1 to CRb_q having the second computation register type CRTb, and provide the first operand OPRa to the computation circuit 123. For example, when the register index represented by the first source register position field LSa1 is "j", the processing management circuit 122 can provide data stored in the computation register CRb_j (i.e., the first operand OPRa) to the computation circuit 123. Hereinafter, the address ADDR stored in the address log LOG will be described in more detail. Figure 8 The address ADDR stored in the address log LOG will be described in more detail.

[0113] Since the second source type field TSb1 indicates the storage unit array 110, the second source register location field LSb1 can not be used. That is, regardless of the second source register location field LSb1, the processing management circuit 122 can receive the second operand OPRb from the storage unit array 110 and provide the second operand OPRb to the computing circuit 123. Specific schemes of providing the second operand OPRb from the storage unit array 110 will be described below with reference to Figure 8 More specific schemes of providing the second operand OPRb from the storage unit array 110 will be described.

[0114] The first instruction INST1 can include an operation type field OP1. The processing management circuit 122 can notify the computing circuit 123 of a computation type indicated by the operation type field OP1. For example, the processing management circuit 122 can instruct the computing circuit 123 to perform one of various operation types including addition, multiplication, MAC, and the like.

[0115] The first instruction INST1 can include an output format field OF1. The processing management circuit 122 can notify the computing circuit 123 of a data type indicated by the output format field OF1. For example, the processing management circuit 122 can instruct the computing circuit 123 to generate a computation result corresponding to one of various data types including FP32, FP16, INT8, and the like.

[0116] The computing circuit 123 can receive the first operand OPRa and the second operand OPRb. The computing circuit 123 can perform a computation for the first operand OPRa and the second operand OPRb based on the computation type instructed by the processing management circuit 122. For example, the computing circuit 123 can generate a computation result by multiplying the first operand OPRa by the second operand OPRb. The computing circuit 123 can provide the computation result to the processing management circuit 122.

[0117] The first instruction INST1 can include a destination type field TD1. The destination type field TD1 can indicate the first computation register type CRTa. That is, hereinafter, for brief description, some embodiments in which the destination type field TD1 indicates the first computation register type CRTa will be representatively described. However, the scope of the present disclosure is not limited thereto. For example, the destination type field TD1 can indicate the second computation register type CRTb.

[0118] The first instruction INST1 can include a destination register location field LD1. The destination register location field LD1 can represent a register index. For example, similarly to the description of the first source register location field LSa1, the destination register location field LD1 can represent a register index based on the address alignment field FLD AA and the register index field FLD IDX of the destination register location field LD1. In this case, the processing management circuit 122 can store the calculation result in the calculation register CRa_i among the calculation registers CRa_1 to CRa_p corresponding to the register index represented by the destination register location field LD1. For example, when the register index represented by the destination register location field LD1 is "i", the processing management circuit 122 can supply the calculation result to the calculation register CRa_i.

[0119] In some embodiments, the processing management circuit 122 can output the calculation result stored in the calculation register CRa_i to the memory controller 10 through the input / output circuit 160 in response to a read command for the calculation register CRa_i issued from the memory controller 10.

[0120] Figure 8 is a timing chart that more specifically illustrates the operation of the memory device according to an embodiment of the present technology. Referring to Figure 7 , the memory device 100 can perform an in-memory processing operation based on the first operand OPRa stored in the calculation register array 124 and the second operand OPRb stored in the memory cell array 110. Figures 1 to 8

[0121] The memory controller 10 can provide the row address RA and the column address CA of the memory cell array 110 in which the second operand OPRb is stored to the memory device 100 based on one or more activation commands ACT and a processing command PROC.

[0122] More specifically, the memory controller 10 can provide the first activation command ACT1 to the memory device 100 at a first time point t1. The memory controller 10 can provide the second activation command ACT2 to the memory device 100 at a second time point t2. The memory controller 10 can provide the processing command PROC to the memory device 100 at a fourth time point t4.

[0123] ​Each of the first activation command ACT1 and the second activation command ACT2 can include some row addresses RA in the memory cell array 110 that store the second operand OPRb. For example, the first activation command ACT1 can include bits 17 to 11 of the row addresses RA in the memory cell array 110 that store the second operand OPRb (i.e., RA[17:11]). The second activation command ACT2 can include bits 10 to 0 of the row addresses RA in the memory cell array 110 that store the second operand OPRb (i.e., RA[10:0]).

[0124] The control logic circuit 140 can provide the row addresses RA included in the first activation command ACT1 and the second activation command ACT2 to the processing management circuit 122. The processing management circuit 122 can store the row addresses RA in the address log LOG. For example, the processing management circuit 122 can store bits 17 to 0 of the row addresses RA (i.e., RA[17:0]) in the address log LOG.

[0125] The memory device 100 can activate word lines WL corresponding to the row addresses RA indicated by the first activation command ACT1 and the second activation command ACT2 in response to the first activation command ACT1 and the second activation command ACT2. In this case, at a third time point t3 between the second time point t2 and the fourth time point t4, data stored in the memory cells connected to the activated word lines WL will be able to be stored in the input / output circuit 160 (e.g., a sense amplifier).

[0126] The processing command PROC can include a column address CA in the memory cell array 110 that stores the second operand OPRb. For example, the processing command PROC can include bits 5 to 0 of the column address CA in the memory cell array 110 that stores the second operand OPRb (i.e., CA[5:0]).

[0127] The control logic circuit 140 can provide the column address CA included in the processing command PROC to the processing management circuit 122. The processing management circuit 122 can store the column address CA in the address log LOG. For example, the processing management circuit 122 can store bits 5 to 0 of the column address CA (i.e., CA[5:0]) in the address log LOG.

[0128] The processing command PROC can include a first instruction identifier ID1 corresponding to the first instruction INST1.

[0129] The memory device 100 can perform an in-memory processing operation in response to the processing command PROC. For example, the memory device 100 can perform the in-memory processing operation between the fourth time point t4 and a fifth time point t5.

[0130] That is, the control logic circuit 140 can provide the execution request REQ EXE including the first instruction identifier ID1 to the processing management circuit 122. The control logic circuit 140 can provide the second operand OPRb from the input / output circuit 160 to the processing management circuit 122 by controlling the input / output circuit 160 based on the column address CA.

[0131] The processing management circuit 122 can receive the second operand OPRb from the input / output circuit 160. Meanwhile, the processing management circuit 122 can read the first operand OPRa from the computation register array 124 in response to the execution request REQ EXE. The processing management circuit 122 can provide the first operand OPRa and the second operand OPRb to the computation circuit 123. The computation circuit 123 can store a computation result generated by performing a computation operation based on the first operand OPRa and the second operand OPRb in the computation register array 124.

[0132] In some embodiments, the processing management circuit 122 can identify the computation register in which the first operand OPRa is stored based on the address log LOG. For example, when the first source register location field LSal of the instruction INST corresponding to the instruction identifier ID included in the execution request REQ EXE includes the address alignment field FLD AA representing "1", the processing management circuit 122 can provide the computation circuit 123 with the first operand OPRa stored in the first source register identified based on the address log LOG and the register index rule table RIRT.

[0133] In some embodiments, the memory device 100 can output the computation result stored in the computation register array 124 to the memory controller 10 in response to a read command (not shown) provided from the memory controller 10.

[0134] In some embodiments, the addresses stored in the address log LOG can be initialized after the in-memory processing operation is completed. For example, the addresses ADDR stored in the address log LOG can be deleted (e.g., invalidated) after the fifth time point t5.

[0135] In some embodiments, the control logic circuit 140 can provide the row address RA to the processing management circuit 122 whenever the first activation command ACT1 and the second activation command ACT2 are received. In this case, the processing management circuit 122 can update the address log LOG based on the received row address RA. For example, the processing management circuit 122 can overwrite the newly received row address RA to the address log LOG. In this case, the row address RA and the column address CA stored in the address log LOG can correspond to the processing command PROC. For example, the address log LOG can include the row address RA included in the activation command ACT corresponding to the processing command PROC, and the column address CA included in the processing command PROC. In other words, the address log LOG can include the column address CA included in the processing command PROC, and the row address RA included in the activation command ACT issued immediately before the processing command PROC.

[0136] Figure 9 is a diagram illustrating operations of an in-memory processor according to some embodiments in more detail. Referring to Figures 1 to 6 and Figure 9 The in-memory processor 120 can perform an in-memory processing operation based on a first operand OPRa and a second operand OPRb both stored in the compute register array 124. That is, the compute circuit 123 can perform a compute operation on the first operand OPRa and the second operand OPRb both provided from the compute register array 124.

[0137] As a more detailed example, the processing management circuit 122 can receive an execution request REQ_EXE representing the second instruction INST2 from the control logic circuit 140. For example, the processing management circuit 122 can receive the execution request REQ_EXE including the second instruction identifier ID2. The processing management circuit 122 can execute the second instruction INST2 in response to the execution request REQ_EXE. Hereinafter, for brief description, some embodiments in which the processing management circuit 122 executes the second instruction INST2 will be representatively described.

[0138] The second instruction INST2 can include a first source type field TSa2 and a second source type field TSb2. The first source type field TSa2 and the second source type field TSb2 can represent the first compute register type CRTa. That is, hereinafter, for brief description, some embodiments in which the first source type field TSa2 and the second source type field TSb2 both represent the first compute register type CRTa will be representatively described. However, the scope of the present disclosure is not limited thereto. For example, one or more of the first source type field TSa2 and the second source type field TSb2 can represent the second compute register type CRTb.

[0139] The second instruction INST2 can include a first source register location field LSa2 and a second source register location field LSb2. The first source register location field LSa2 and the second source register location field LSb2 can each represent a register index for a first source register and a second source register, respectively. For example, each of the first source register location field LSa2 and the second source register location field LSb2 can represent one register index based on the address alignment field FLD AA and the register index field FLD IDX corresponding thereto. In this case, the processing management circuit 122 can receive the first operand OPRa from the first source register determined based on the first source type field TSa2 and the first source register location field LSa2. The processing management circuit 122 can receive the second operand OPRb from the second source register determined based on the second source type field TSb2 and the second source register location field LSb2. The scheme of determining one computation register based on the first source type field TSa2 and the first source register location field LSa2, and the scheme of determining one computation register based on the second source type field TSb2 and the second source register location field LSb2 are similar to the schemes described above with reference to Figures 1 to 8 The schemes described above are similar, and thus a detailed description is omitted.

[0140] The computation circuit 123 can receive the first operand OPRa and the second operand OPRb. The computation circuit 123 can perform a computation for the first operand OPRa and the second operand OPRb based on the computation type indicated by the processing management circuit 122. The computation circuit 123 can provide the computation result to the processing management circuit 122. The processing management circuit 122 can store the computation result in the computation register determined based on the destination type field TD2 and the destination register location field LD2.

[0141] Figure 10 is a timing diagram illustrating operations of a memory device according to an embodiment of Figure 9 more detail. Referring to Figures 1 to 6 and Figures 9 to 10 The memory device 100 can perform an in-memory processing operation based on the first operand OPRa and the second operand OPRb stored in the computation register array 124. Hereinafter, differences from the embodiments described above with reference to Figure 8 will be mainly described.

[0142] The memory controller 10 can issue a process command PROC at a fourth point in time t4. The process command PROC can include a second instruction identifier ID2. The memory device 100 can execute the second instruction INST2. That is, the memory device 100 can perform an in-memory processing operation on the first operand OPRa and the second operand OPRb stored in the compute register array 124. That is, the memory device 100 can perform the in-memory processing operation regardless of the data stored in the memory cell array 110.

[0143] Accordingly, the memory controller 10 can not issue (e.g., omit issuing) the first activation command ACT1 and the second activation command ACT2 at the first point in time t1 and the second point in time t2, respectively. That is, the memory device 100 can perform the in-memory processing operation based on the first operand OPRa and the second operand OPRb despite the memory controller 10 only issuing the process command PROC. As a more detailed example, when the address alignment field FLD AA of each of the first source register location field LSa2 and the second source register location field LSb2 is “0”, the memory device 100 can perform the in-memory processing operation regardless of the row address RA. In this case, the memory device 100 will also be able to perform the in-memory processing operation regardless of the column address CA included in the process command PROC.

[0144] However, the scope of the present disclosure is not limited thereto, and the memory controller 10 can issue the first activation command ACT1 and the second activation command ACT2 prior to the fourth point in time t4. In this case, the memory device 100 can perform dummy activation operations prior to the fourth point in time t4. For example, the memory device 100 can activate word lines corresponding to the row addresses RA included in the first activation command ACT1 and the second activation command ACT2. The process management circuit 122 can store the row addresses RA included in the first activation command ACT1 and the second activation command ACT2 in the address log LOG. Further, the process management circuit 122 can store the column address CA included in the process command PROC in the address log LOG. In this case, the process management circuit 122 can perform the in-memory processing operation based on the addresses stored in the address log LOG. For example, when the address alignment field FLD AA of one or more of the “destination register location field LD2, the first source register location field LSa2, and the second source register location field LSb2” is “1”, the memory device 100 will be able to perform the in-memory processing operation based on the addresses stored in the address log LOG.

[0145] That is, according to embodiments of the present disclosure, when the instruction INST corresponding to the processing command PROC can be executed regardless of the address ADDR, the memory controller 10 can not issue the activate command ACT before the processing command PROC, and the memory device 100 can perform the in-memory processing operation regardless of the activate command ACT issued from the memory controller 10. However, when the instruction INST corresponding to the processing command PROC is executed based on the address ADDR, the memory controller 10 can also issue the activate command ACT before the processing command PROC. In this case, the row address RA included in the activate command ACT and / or the column address CA included in the processing command PROC can be used to identify the calculation register (e.g., the destination register, the first source register, or the second source register) to be used for the in-memory processing operation.

[0146] Figure 11 is a flowchart illustrating an operation of a memory device according to embodiments of the present disclosure. Referring to Figures 1 to 11 In step S1100, the memory device 100 can receive the processing command PROC.

[0147] In step S1200, the memory device 100 can update the address log LOG. For example, the memory device 100 can store the row address RA included in the activate command ACT corresponding to the processing command PROC, and the column address CA included in the processing command PROC in the address log LOG.

[0148] In step S1300, the memory device 100 can identify the instruction INST corresponding to the processing command PROC. For example, the control logic circuit 140 can provide the execution request REQ_EXE including the instruction identifier ID included in the processing command PROC to the processing management circuit 122. The processing management circuit 122 can identify one instruction INST corresponding to the instruction identifier ID from the instruction list circuit 121.

[0149] For simplicity of description, in Figure 11 In step S1100 and step S1300, some embodiments of performing step S1200 are representatively described, but the scope of the present disclosure is not limited thereto. For example, the memory device 100 can store the row address RA in the address log LOG before performing step S1100, or perform step S1200 after performing step S1300. That is, the scope of the present disclosure is not limited to the specific order of performing step S1200.

[0150] In step S1400, the storage device 100 can identify one or more computation registers CR for executing the instruction INST based on the register index rule table RIRT. For example, the processing management circuit 122 can identify a computation register CR (e.g., a destination register) for storing a computation result based on the destination type field TD and the destination register location field LD included in the instruction INST identified in the above step S1300, can identify a computation register CR (e.g., a first source register) storing a first operand OPRa based on the first source type field TSa and the first source register location field LSa, and can identify a computation register CR (e.g., a second source register) storing a second operand OPRb based on the second source type field TSb and the second source register location field LSb.

[0151] In step S1500, the storage device 100 can execute the instruction INST based on the one or more computation registers CR. For example, the computation circuit 123 can perform a computation operation based on the operands OPR stored in the first and second source registers identified in the above step S1400, or store a computation result in the destination register.

[0152] Figure 12 is more specifically shown Figure 11 the step S1400 of the Fig. 1. Referring to Figures 1 to 12 , the step S1400 can include steps S1410 to S1430 discussed below. For brief description, in the following, an operation in which the processing management circuit 122 identifies a computation register CR for storing a computation result based on the destination type field TD and the destination register location field LD will be representatively described. However, the scope of the present disclosure is not limited thereto, and in a scheme similar thereto, the processing management circuit 122 can identify a computation register CR storing a first operand OPRa based on the first source type field TSa and the first source register location field LSa, and can identify a computation register CR storing a second operand OPRb based on the second source type field TSb and the second source register location field LSb.

[0153] In step S1410, the processing management circuit 122 can identify the destination type field TD of the instruction INST.

[0154] In step S1420, the processing management circuit 122 can determine whether or not the destination register needs to be identified. For example, when the destination type field TD of the instruction INST indicates one of the first and second computation register types CRTa and CRTb, the processing management circuit 122 can determine that the destination register needs to be identified. In contrast, when the destination type field TD of the instruction INST indicates the storage unit array 110, the processing management circuit 122 can determine that the destination register does not need to be identified.

[0155] In step S1420, when it is determined that the destination register needs to be identified, the following step S1430 can be executed.

[0156] In step S1420, when it is determined that the destination register does not need to be identified, the step S1400 can be terminated.

[0157] In step S1430, the processing management circuit 122 can identify the computation register corresponding to the destination register based on the destination register location field LD of the instruction INST. Step S1430 of FIG. 14 is more specifically described below with reference to Figure 13 Step S1430 of FIG. 14 is more specifically described below with reference to

[0158] Figure 13 is a diagram more specifically illustrating Figure 12 Step S1430 of FIG. 14. With reference to Figures 1 to 13 , step S1430 can include the following steps S1431 to S1433.

[0159] In step S1431, the processing management circuit 122 can determine whether or not the address alignment field FLD AA is "0". For example, the processing management circuit 122 can determine whether or not the address alignment field FLD AA included in the destination register location field LD is "0". When the address alignment field FLD AA is "0", the following step S1432 can be executed. When the address alignment field FLD AA is not "0" (for example, is "1"), the following step S1433 can be executed.

[0160] In step S1432, the processing management circuit 122 can determine the computation register CR having a register index corresponding to the value of the register index field FLD IDX as the destination register. For example, when the register index field FLD IDX included in the destination register location field LD is "k", the processing management circuit 122 can determine the computation register corresponding to the register index "k" among the computation registers of the computation register type indicated by the destination type field TD as the destination register.

[0161] In step S1433, the processing management circuit 122 can determine the destination register based on the register index field FLD IDX and the address log LOG. The following describes step S1433 with reference to Figure 14 Step S1433 is described more specifically.

[0162] Figure 14 is a diagram that more specifically illustrates Figure 13 Step S1433. With reference to Figures 1 to 14 , step S1433 can include the following steps S1433_1 to S1433_4.

[0163] In step S1433_1, the processing management circuit 122 can identify the access key AK corresponding to the value of the register index field FLD IDX. For example, the processing management circuit 122 can identify the access key AK having the same value as the register index field FLD IDX.

[0164] In step S1433_2, the processing management circuit 122 can identify the register index rule RIR corresponding to the access key AK. For example, the processing management circuit 122 can identify the register index rule RIR corresponding to the access key AK identified in step S1433_1.

[0165] In step S1433_3, the processing management circuit 122 can calculate or determine the register index based on the address log LOG and the register index rule RIR. For example, the processing management circuit 122 can calculate or determine the register index by assigning the row address RA and / or the column address CA included in the address log LOG to the register index rule RIR identified in step S1433_2.

[0166] In step S1433_4, the processing management circuit 122 can determine the calculation register corresponding to the calculated register index as the destination register. For example, when the register index calculated in step S1433_3 is “k”, the processing management circuit 122 can determine the calculation register having the register index “k” among the calculation registers of the calculation register type indicated by the destination type field TD as the destination register.

[0167] Figure 15 is a block diagram illustrating a storage system according to some embodiments. With reference to Figures 1 to 15 , the storage system MS can include the memory controller 10 and the memory device 100.

[0168] The memory device 100 can include the in-memory processor 120. The in-memory processor 120 can include the instruction list circuit 121 and the register index rule table RIRT. The configuration and operation of the memory device 100 are the same as described above with reference toFigures 1 to 14 The described configurations and operations are similar, and thus detailed descriptions are omitted.

[0169] The memory controller 10 can include a command / address compiler 11. The command / address compiler 11 can manage an instruction list LST and a register index rule table RIRT_CTRL.

[0170] The instruction list LST can include the first instruction INST1 to the nth instruction INSTn described above with reference to FIG. 2. The register index rule table RIRT_CTRL can include the plurality of register index rules RIR described above with reference to FIG. 3. That is, the instruction list LST can be synchronized with the instruction list managed by the instruction list circuit 121, and the register index rule table RIRT_CTRL can be synchronized with the register index rule table RIRT. Accordingly, the memory controller 10 can manage the plurality of instructions INST used in the memory device 100 based on the instruction list LST, and manage the plurality of register index rules RIR used in the memory device 100 based on the register index rule table RIRT_CTRL. Figure 4 Figure 6 The instruction list LST can include the first instruction INST1 to the nth instruction INSTn described above with reference to FIG. 2. The register index rule table RIRT_CTRL can include the plurality of register index rules RIR described above with reference to FIG. 3. That is, the instruction list LST can be synchronized with the instruction list managed by the instruction list circuit 121, and the register index rule table RIRT_CTRL can be synchronized with the register index rule table RIRT. Accordingly, the memory controller 10 can manage the plurality of instructions INST used in the memory device 100 based on the instruction list LST, and manage the plurality of register index rules RIR used in the memory device 100 based on the register index rule table RIRT_CTRL.

[0171] The command / address compiler 11 can identify a computation operation requested by an application (e.g., an artificial intelligence model, etc.) driven by the memory system MS. The command / address compiler 11 can issue a command / address signal (C / A) corresponding to the required computation operation based on the instruction list LST and the register index rule table RIRT_CTRL. For example, the command / address compiler 11 can issue a processing command PROC including an instruction identifier ID for the required instruction INST based on the instruction list LST. In addition, when the instruction INST required for the computation operation requested by the application indicates one or more of a destination register, a first source register, and / or a second source register based on the address log LOG, the command / address compiler 11 can issue the processing command PROC and an activation command ACT corresponding thereto, so that an appropriate address ADDR can be stored in the address log LOG based on the register index rule table RIRT_CTRL.

[0172] ​However, it can be difficult to indicate all of the computation operations requested by the application for driving the storage system MS using only the register index rule table RIRT. For example, it can be difficult to represent a combination of computation registers required for the computation operation requested by the application, or it can be difficult to represent an address ADDR of data required for the computation operation requested by the application, using only the plurality of register index rules RIR included in the register index rule table RIRT. That is, due to the limitation in the number of instructions stored in the instruction list circuit 121, and the limitation in the number of register index rules stored in the register index rule table RIRT, there can be a case where the command / address compiler 11 is difficult to compile a command / address signal (C / A) representing the computation operation requested by the application. In this case, the memory controller 10 can change the plurality of instructions INST stored in the instruction list circuit 121, or can change the register index rule table RIRT, and then indicate the computation operation to the memory device 100.

[0173] In some embodiments, the total capacity of the plurality of instructions INST stored in the instruction list circuit 121 can be relatively large. For example, the total capacity of the plurality of instructions INST stored in the instruction list circuit 121 can be several tens of bytes (or more). That is, the capacity of the plurality of instructions INST can be too large to be stored in one register. As a result, when the memory controller 10 is configured to update all of the plurality of instructions INST stored in the instruction list circuit 121, a large delay can occur depending on the time required for the memory controller 10 to transmit the plurality of instructions INST to the memory device 100, and the time required to store the plurality of instructions INST in the instruction list circuit 121. In this case, the operation speed of the storage system MS can deteriorate.

[0174] In some embodiments, the memory controller 10 can be configured to update one of the plurality of instructions INST stored in the instruction list circuit 121. In this case, the memory controller 10 can provide one instruction INST to the memory device 100 every time there is a case where it is difficult to compile a command / address signal (C / A). In this case, the operation speed of the memory device 100 can significantly deteriorate as the memory device 100 repeatedly performs a read operation and a write operation.

[0175] In some embodiments, the memory controller 10 can be configured to update the register index rule table RIRT. For example, the memory controller 10 provides the register index rule table RIRT to the memory device 100 to update the register index rule table RIRT. However, in this case, a large delay can occur according to the time required for the memory controller 10 to transmit the plurality of register index rules RIR to the memory device 100, and the time required to store the plurality of register index rules RIR in the processing management circuit 122. In this case, the operation speed of the memory system MS can be deteriorated.

[0176] The command / address compiler 11 according to the embodiments of the present disclosure can appropriately change some of the plurality of access keys AK included in the register index rule table RIRT. In this case, the register index rule RIR for identifying the calculation register used by the execution instruction INST can be changed. Accordingly, the command / address compiler 11 can appropriately instruct all of the calculation operations requested by the application by changing some of the plurality of access keys AK. This will be described below with reference to Figure 17 and Figure 18 The scheme in which the command / address compiler 11 changes some of the plurality of access keys AK will be described in more detail.

[0177] In some embodiments, the command / address compiler 11 can update some of the plurality of access keys AK by issuing a register write command. For example, when each of the plurality of access keys AK is assigned to a different mode register, the command / address compiler 11 can change the access key stored in one mode register by issuing a mode register write command. However, the scope of the present disclosure is not limited thereto.

[0178] That is, the command / address compiler 11 can update only some of the plurality of access keys AK, instead of updating the register index rule RIR or updating the plurality of instructions INST. For example, the command / address compiler 11 can instruct the required calculation operation after providing only one or more access keys AK to the memory device 100, instead of re-providing the plurality of register index rules RIR or the plurality of instructions INST to the memory device 100. In this case, since the frequency of updating the plurality of register index rules RIR and the frequency of updating the plurality of instructions INST can be minimized, it will be possible to enhance the performance of the memory system MS.

[0179] Figure 16 is a block diagram illustrating some configurations of the processing management circuit of Figure 15 according to the embodiments of the present disclosure. Reference is made to Figure 3 Figures 1 to 16 ​The processing management circuit 122 can include an access key register array ARR_AKR and a register index rule memory RIRM.

[0180] The access key register array ARR_AKR can include a first access key register AKR1 to an rth access key register AKRr. The first access key register AKR1 to the rth access key register AKRr can store a first access key AK1 to an rth access key AKr, respectively.

[0181] The register index rule memory RIRM can include a first register index rule memory circuit RIRMC1 to an rth register index rule memory circuit RIRMCr. The first register index rule memory circuit RIRMC1 to the rth register index rule memory circuit RIRMCr can store a first register index rule RIR1 to an rth register index rule RIRr, respectively.

[0182] Each of the first access key AK1 to the rth access key AKr can be used to select one of the first register index rule RIR1 to the rth register index rule RIRr based on a value of the register index field FLD IDX. The above with reference to Figure 6 The scheme using the first access key AK1 to the rth access key AKr is described above, and thus a detailed description is omitted.

[0183] The first access key register AKR1 to the rth access key register AKRr can correspond to the first register index rule memory circuit RIRMC1 to the rth register index rule memory circuit RIRMCr, respectively. For example, the first access key register AKR1 to the rth access key register AKRr can be used to access the first register index rule memory circuit RIRMC1 to the rth register index rule memory circuit RIRMCr, respectively. As a more detailed example, the first access key register AKR1 can be used to access the first register index rule RIR1 stored in the first register index rule memory circuit RIRMC1, and the second access key register AKR2 can be used to access the second register index rule RIR2 stored in the second register index rule memory circuit RIRMC2.

[0184] Thus, although the destination register location field LD of the specific instruction INST is predetermined, the register index rule RIR for identifying the destination register can vary according to which register index rule memory circuit RIRMC corresponds to the access key AK corresponding thereto. For example, although the register index field FLD IDX of the destination register location field LD of the specific instruction INST indicates "0b00001", the access key AK corresponding thereto is changed from the second access key AK2 to the third access key AK3, and thus the register index rule for identifying the destination register can be changed from the second register index rule RIR2 to the third register index rule RIR3. In this case, the calculation register indicated by the destination register location field LD of the specific instruction INST can change. As a result, the in-memory processor 120 will be able to execute the corresponding instruction INST based on the changed calculation register (i.e., perform another calculation operation). That is, according to an embodiment of the present disclosure, the memory controller 10 changes the access key AK to change the calculation register CR used by the in-memory processor 120 to execute the specific instruction INST. A detailed example scheme of changing the access key AK by the memory controller 10 will be described below with reference to Figure 17 A specific scheme of changing the access key AK by the memory controller 10 will be described more specifically.

[0185] In some embodiments, each of the first access key register AKR1 to the rth access key register AKRr can be implemented as a mode register. In this case, the command / address compiler 11 issues a mode register write (MRW) command to change the access key AK stored in one of the first access key register AKR1 to the rth access key register AKRr. However, the scope of the present disclosure is not limited thereto.

[0186] Figure 17 is a diagram more specifically illustrating a method of changing the access key by the memory controller of Figure 15 , which will be described below with reference to Figures 1 to 17 to describe a detailed example scheme of changing the access key AK stored in the register index rule table RIRT and RIRT_CTRL.

[0187] Reference is made to Figures 1 to 17, the memory controller 10 can change one or more access keys AK. For example, the memory controller 10 can change the value (e.g., code value) of the second access key AK2 from "0b00001" to "0b00011". In this case, although the register index field FLD IDX of one or more of the register location fields (e.g., the destination register location field LD, the first source register location field LSa, and the second source register location field LSb) of the particular instruction INST indicates "0b00011", the processing management circuit 122 can calculate or determine the register index based on the second register index rule RIR2.

[0188] In contrast, although the register index field FLD IDX of one or more of the register location fields (e.g., the destination register location field LD, the first source register location field LSa, and the second source register location field LSb) of the particular instruction INST indicates "0b00001", the processing management circuit 122 can calculate or determine the register index based on another register index rule other than the second register index rule RIR2. For example, the memory controller 10 can change the fourth access key AK4 from "0b00011" to "0b00001". In this case, the processing management circuit 122 can calculate or determine the register index corresponding to the particular instruction INST based on the second register index rule RIR2 other than the fourth register index rule RIR4.

[0189] In some embodiments, the memory controller 10 can change one access key AK by issuing one register write command. For example, the memory controller 10 can change the second access key AK2 by issuing the first register write command, and change the fourth access key AK4 by issuing the second register write command. However, the scope of the present disclosure is not limited thereto. For example, the memory controller 10 can also change two or more access keys AK by issuing one register command.

[0190] In some embodiments, the memory controller 10 can exchange two different access keys AK with each other by issuing two register write commands. For example, the memory controller 10 can exchange the codes corresponding to the second access key AK2 and the fourth access key AK4 with each other by issuing the first register write command and the second register write command. However, the scope of the present disclosure is not limited thereto. For example, when the second access key AK2 is changed to "0b00011", the memory controller 10 can also change the fourth access key AK4 to an arbitrary code (e.g., "0b11111") other than the code (e.g., "0b00001") of the existing second access key AK2.

[0191] In some embodiments, the memory controller 10 can manage the register index rule table RIRT and RIRT_CTRL such that each of the plurality of access keys AK corresponds to a different code. For example, when two or more access keys AK correspond to the same code, the memory controller 10 can change one code among the access keys AK (e.g., the earliest changed code). As a more detailed example, when the second access key AK2 and the fourth access key AK4 both correspond to "0b00011", the memory controller 10 can change the fourth access key AK4.

[0192] Figure 18 is a flowchart showing the operation of the memory controller in more detail. Figure 15 Referring to Figures 1 to 18 In step S2100, the memory controller 10 can determine a memory-in processing operation requested by an application.

[0193] In step S2200, the memory controller 10 can determine whether or not the command / address compilation is possible. For example, the command / address compiler 11 can determine whether or not the command / address signal C / A representing the memory-in processing operation determined in the above step S2100 can be compiled.

[0194] When it is determined in step S2200 that the compilation is not possible, the following step S2300 can be executed. When it is determined in step S2200 that the compilation is possible, the following step S2400 can be executed.

[0195] In step S2300, the memory controller 10 can issue a command for updating at least one access key AK. For example, the command / address compiler 11 can issue one or more register write commands for one or more access key registers AKR. In this case, the in-memory processor 120 can change the access keys stored in the one or more access key registers AKR in response to the register write command.

[0196] In step S2400, the memory controller 10 can issue a processing command PROC for the memory-in processing determined in the above step S2100. For example, the command / address compiler 11 can issue a command / address signal C / A representing the processing command PROC corresponding to the memory-in processing operation determined in the above step S2100.

[0197] Figures 19 to 20 shows a method of storing a plurality of register index rules in the register index rule table of Figure 3

[0198] First, referring to Figures 1 to 19 ​The register index rule table RIRT can be implemented as a register index rule table RIRTa. The register index rule table RIRTa can include a first register index rule RIR1, a second register index rule RIR2, a third register index rule RIR3, and a fourth register index rule RIR4.

[0199] The register index rule table RIRTa can include a bit mask table BMTa. The bit mask table BMTa can store a mask bit for each bit of a row address RA and a column address CA provided from the address log LOG. For example, the bit mask table BMTa can include a plurality of mask bits corresponding to the 17th bit to the 0th bit of the row address RA (e.g., RA[17:0]) and the 5th bit to the 0th bit of the column address CA (e.g., CA[5:0]), respectively.

[0200] The register index rule table RIRTa can represent address bits corresponding to the plurality of register index rules RIR based on the bit mask table BMTa. For example, when address bits required to represent the first register index rule RIR1 are the 2nd bit to the 0th bit of the column address CA (e.g., CA[2:0]), the bit mask table BMTa can represent a mask bit corresponding to the first register index rule RIR1 and the 2nd bit to the 0th bit of the column address CA (e.g., CA[2:0]) as "1". Similarly, when address bits required to represent the third register index rule RIR3 are the 0th bit of the row address RA (e.g., RA[0]) and the 4th bit to the 3rd bit of the column address CA (e.g., CA[4:3]), the bit mask table BMTa can represent a mask bit corresponding to the third register index rule RIR3 and the 0th bit of the row address RA (e.g., RA[0]) and the 4th bit to the 3rd bit of the column address CA (e.g., CA[4:3]) as "1". Through such a scheme, the bit mask table BMTa can represent address bits used to represent the plurality of register index rules RIR, respectively.

[0201] In some embodiments, the bit mask table BMTa can represent a bit corresponding to an address not required to represent a register index rule RIR as "0".

[0202] According to embodiments of the present disclosure, therefore, the processing management circuit 122 can calculate or determine the register index based on a result of concatenating the address bits represented by the bit mask table BMTa. For example, when the address bits represented by the bit mask table BMTa for the first register index rule RIR1 are the second bit to the 0th bit of the column address CA (e.g., CA[2:0]), the processing management circuit 122 can determine the register index based on a value of concatenating the second bit to the 0th bit of the column address CA stored in the address log LOG. As a more detailed example, when the second bit to the 0th bit of the column address CA stored in the address log LOG are “CA[2]=1”, “CA[1]=0”, “CA[0]=0”, the processing management circuit 122 can calculate or determine the register index based on “0b100” (e.g., 4).

[0203] In some embodiments, the bit positions of the respective bits when the processing management circuit 122 concatenates the address bits represented by the bit mask table BMTa can be predetermined. For example, when the address bits represented by the bit mask table BMTa for the first register index rule RIR1 are the second bit to the 0th bit of the column address CA (e.g., CA[2:0]), the processing management circuit 122 can concatenate the second bit to the 0th bit of the column address CA (e.g., CA[2:0]) in a predetermined order. As a more detailed example, the processing management circuit 122 can concatenate the second bit of the column address CA (e.g., CA[2]) as the most significant bit, the first bit of the column address CA (e.g., CA[1]) as the middle bit, and the 0th bit of the column address CA (e.g., CA[0]) as the least significant bit. However, the scope of the present disclosure is not limited thereto.

[0204] The register index rule table RIRTa can include a plurality of scale values and a plurality of offset values corresponding to the plurality of register index rules RIR, respectively. For example, the register index rule table RIRTa can store a scale value “1” corresponding to the first register index rule RIR1, and store a scale value “2” corresponding to the third register index rule RIR3. The register index rule table RIRTa can store an offset value “0” corresponding to the first register index rule RIR1, and store an offset value “8” corresponding to the third register index rule RIR3.

[0205] The processing management circuit 122 can calculate or determine the register index for each of the plurality of register index rules RIR based on the scale value and the offset value according to a result of concatenating the address bits represented by the bit mask table BMTa. For example, the processing management circuit 122 can calculate or determine the register index by multiplying the result of concatenating the address bits represented by the bit mask table BMTa by the corresponding scale value and then adding the offset value.

[0206] As a more detailed example, when the processing management circuit 122 concatenates the result of the address bits represented by the bit mask table BMTa for the first register index rule RIR1 is “0b100” (e.g., 4), the processing management circuit 122 can calculate or determine the register index “4” by multiplying “4” by the scale value “1” and then adding the bias value “0”.

[0207] Similarly, when the processing management circuit 122 concatenates the result of the address bits represented by the bit mask table BMTa for the third register index rule RIR3 is “0b111” (e.g., 7), the processing management circuit 122 can calculate or determine the register index “22” by multiplying “7” by the scale value “2” and then adding the bias value “8”.

[0208] Next, referring to Figures 1 to 20 , the register index rule table RIRT can be implemented as a register index rule table RIRTb. The register index rule table RIRTb can include the first register index rule RIRa, the second register index rule RIRb, the third register index rule RIRC, and the fourth register index rule RIRD.

[0209] The register index rule table RIRTb can include a bit mask table BMTb. The register index rule table RIRTb can represent address bits corresponding to the plurality of register index rules RIR, respectively, based on the bit mask table BMTb. For example, when the address bits required to represent the third register index rule RIRC are the 0th bit of the row address RA (e.g., RA[0]) and the fourth to third bits of the column address CA (e.g., CA[4:3]), the bit mask table BMTb can represent the mask bits corresponding to the third register index rule RIRC and the 0th bit of the row address RA (e.g., RA[0]) and the fourth to third bits of the column address CA (e.g., CA[4:3]) as “1”. Similarly, the bit mask table BMTb can represent the mask bits corresponding to the fourth register index rule RIRD and the 0th bit of the row address RA (e.g., RA[0]) and the fourth to third bits of the column address CA (e.g., CA[4:3]) as “1”.

[0210] The processing management circuit 122 can calculate or determine the register index based on the result of concatenating the address bits represented by the bit mask table BMTb. The scheme in which the processing management circuit 122 concatenates the address bits represented by the bit mask table BMTa is described above with reference to Figure 19 , and thus a detailed description is omitted.

[0211] The register index rule table RIRTb can include a plurality of concatenation order flag bits corresponding to a plurality of register index rules RIRs, respectively. For example, the register index rule table RIRTb can store a concatenation order flag bit "0" corresponding to the third register index rule RIRc and store a concatenation order flag bit "1" corresponding to the fourth register index rule RIRd.

[0212] The processing management circuit 122 can determine the bit position of the corresponding bit when concatenating the address bits represented by the bit mask table BMTb based on the concatenation order flag bit. For example, when the concatenation order flag bit is "0", the processing management circuit 122 can determine the bit corresponding to the row address RA as a higher significant bit than the bit corresponding to the column address CA. When the concatenation order flag bit is "1", the processing management circuit 122 can determine the bit corresponding to the column address CA as a higher significant bit than the bit corresponding to the row address RA.

[0213] As a more detailed example, all address bits required for the third register index rule RIRc and the fourth register index rule RIRd can be the 0th bit of the row address RA (e.g., RA[0]) and the fourth to third bits of the column address CA (e.g., CA[4:3]). However, the concatenation order flag bit corresponding to the third register index rule RIRc can be "0" and the concatenation order flag bit corresponding to the fourth register index rule RIRd can be "1". In this case, with respect to the third register index rule RIRc, the processing management circuit 122 can concatenate the 0th bit of the row address RA (e.g., RA[0]) as a higher significant bit and the fourth to third bits of the column address CA (e.g., CA[4:3]) as a lower significant bit. In contrast, with respect to the fourth register index rule RIRd, the processing management circuit 122 can concatenate the 0th bit of the row address RA (e.g., RA[0]) as a lower significant bit and the fourth to third bits of the column address CA (e.g., CA[4:3]) as a higher significant bit.

[0214] Figure 21 is a block diagram illustrating a memory system according to some embodiments. Referring to Figures 1 to 21 , the memory system MS can include a memory controller 20 and a memory device 200. The configuration and operation of the memory controller 20 are similar to those of the memory controller 10 described above with reference to Figures 1 to 20 , and thus a detailed description is omitted.

[0215] The memory device 200 can include a plurality of memory banks BNK. For example, the memory device 200 can include a first memory bank BNK1 and a second memory bank BNK2.

[0216] Each of the first bank BNK1 and the second bank BNK2 can include the in-memory processor 220 and the memory cell array 210. For example, the first bank BNK1 can include the first memory cell array 210a and the first in-memory processor 220a, and the second bank BNK2 can include the second memory cell array 210b and the second in-memory processor 220b.

[0217] In some embodiments, the first memory cell array 210a and the first in-memory processor 220a can correspond to the memory cell array 110 and the in-memory processor 120 described above with reference to FIG. 1, respectively. Figures 1 to 20 The first memory cell array 210a and the first in-memory processor 220a can correspond to the memory cell array 110 and the in-memory processor 120 described above with reference to FIG. 1, respectively.

[0218] The first in-memory processor 220a and the second in-memory processor 220b can operate independently of each other. For example, the first in-memory processor 220a can perform a computing operation based on operands provided from the first memory cell array 210a, or store a result of the computing in the first memory cell array 210a. The second in-memory processor 220b can perform a computing operation based on operands provided from the second memory cell array 210b, or store a result of the computing in the second memory cell array 210b.

[0219] The memory controller 20 can include a data pin PH_DQ, a first clock pin PH_CK1, a second clock pin PH_CK2, and a plurality of command / address pins PH_CA.

[0220] The memory device 200 can include a data pin PM_DQ, a first clock pin PM_CK1, a second clock pin PM_CK2, and a plurality of command / address pins PM_CA.

[0221] The data pin PH_DQ, the first clock pin PH_CK1, the second clock pin PH_CK2, and the plurality of command / address pins PH_CA can be connected to the data pin PM_DQ, the first clock pin PM_CK1, the second clock pin PM_CK2, and the plurality of command / address pins PM_CA, respectively, through different channels.

[0222] The memory controller 20 can provide or receive a data signal DQ to or from the memory device 200 through a channel connected to the data pin PH_DQ. In this case, the data signal DQ can carry the data DATA described above with reference to FIG. 1. For brevity of description, Figures 1 to 20 Figure 21 ​It is shown in that each of the memory controller 20 and the memory device 200 is connected through one data pin, but the present disclosure is not limited thereto. For example, each of the memory controller 20 and the memory device 200 can include 8 or 16 pins, or 32 data pins.

[0223] The memory controller 20 can provide a clock signal CK_t to the memory device 200 through a channel connected to a first clock pin PH_CK1. The memory controller 20 can provide an inverted clock signal CK_c to the memory device 200 through a channel connected to a second clock pin PH_CK2. The clock signal CK_t and the inverted clock signal CK_c can have phases complementary to each other.

[0224] The memory controller 20 can provide a plurality of command / address signals C / A to the memory device 200 through channels connected to a plurality of command / address pins PH_CA. For example, the memory controller 20 can provide a first command / address signal C / A #1 to a first command / address pin PM_CA1 through a first command / address pin PH_CA1, a second command / address signal C / A #2 to a second command / address pin PM_CA2 through a second command / address pin PH_CA2, and a third command / address signal C / A #3 to a third command / address pin PM_CA3 through a third command / address pin PH_CA3. For simplicity of description, Figure 21 It is shown in that each of the memory controller 20 and the memory device 200 is connected through three command / address pins, but the present disclosure is not limited thereto. For example, each of the memory controller 20 and the memory device 200 can include 7 or 14 command / address pins.

[0225] The memory device 200 can identify the command / address signals C / A based on the clock signal CK_t and the inverted clock signal CK_c. For example, the memory device 200 can identify the plurality of command / address signals C / A based on rising edges or falling edges of the clock signal CK_t.

[0226] The memory controller 20 can integrally control the plurality of in-memory processors 220 based on the plurality of command / address signals C / A. For example, the memory controller 20 can provide a processing command PROC to both the first bank BNK1 and the second bank BNK2 based on the plurality of command / address signals C / A. In this case, both the first in-memory processor 220a and the second in-memory processor 220b can perform in-memory processing operations in response to the processing command PROC.

[0227] Figure 22 is a command truth table showing a configuration of a processing command implemented according to some embodiments. Hereinafter, for simplicity of description, reference will be made toFigures 1 to 22 The configuration of the processing command PROC defined based on the first command / address signal C / A #1 to the seventh command / address signal C / A #7 is described as an example. However, the scope of the present disclosure is not limited thereto.

[0228] The processing command PROC can be defined based on the logic levels of the first command / address signal C / A #1 to the seventh command / address signal C / A #7 at the time points at which the rising edge and the falling edge of the clock signal CK_t occur. That is, the memory controller 20 can provide the processing command PROC to the memory device 200 by setting the logic levels of the first command / address signal C / A #1 to the seventh command / address signal C / A #7 at the time points at which the rising edge and the falling edge of the clock signal CK_t occur.

[0229] The memory device 200 can identify the processing command PROC based on the first command / address signal C / A #1 to the third command / address signal C / A #3 being logic high H, logic low L, and logic high H, respectively, at the time point at which the rising edge of the clock signal CK_t occurs. In this case, the memory device 200 can determine the fourth command / address signal C / A #4 to the seventh command / address signal C / A #7 to be the 0th bit (CA[0]), the 3rd bit (CA[3]), the 4th bit (CA[4]), and the 5th bit (CA[5]) of the column address CA, respectively, at the time point at which the rising edge of the clock signal CK_t occurs. The memory device 200 can determine the first command / address signal C / A #1, the second command / address signal C / A #2, the third command / address signal C / A #3, and the fourth command / address signal C / A #4 to be the 0th bit to the 3rd bit (ID[0:3]) of the instruction identifier ID, respectively, at the time point at which the falling edge of the clock signal CK_t occurs. The memory device 200 can determine the fifth command / address signal C / A #5 and the sixth command / address signal C / A #6 to be the 1st bit (CA[1]) and the 2nd bit (CA[2]) of the column address CA, respectively, at the time point at which the falling edge of the clock signal CK_t occurs. However, the scope of the present disclosure is not limited thereto.

[0230] In some embodiments, the memory device 200 can determine whether to enter the auto-precharge mode based on the seventh command / address signal C / A #7 at the time point at which the falling edge of the clock signal CK_t occurs. However, the scope of the present disclosure is not limited thereto.

[0231] In some embodiments, the number of instruction identifiers ID that can be represented by the processing command PROC can be determined based on the number of bits for the instruction identifier ID included in the processing command PROC. That is, the number of instruction identifiers ID that can be represented by the processing command PROC can be limited based on the width of the channel through which the plurality of command / address signals C / A are transmitted. However, according to embodiments of the present disclosure, although the number of instruction identifiers ID that can be represented by the processing command PROC is limited, the number of computing operations that the in-memory processor 220 can perform based on one instruction INST can increase, and thus the operation efficiency of the memory system MS can be enhanced.

[0232] The above-described content is for implementing specific embodiments of the present disclosure. The present disclosure will not only include the above-described embodiments, but also embodiments that can be easily designed or easily modified. In addition, the present disclosure will also include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present disclosure should not be limited to the embodiments, but should be defined by the appended claims of the present disclosure and equivalents of the appended claims.

Claims

1. An in-memory processor included in a memory device, comprising: an instruction list circuit configured to store a first instruction including a first register index field; a compute register array including a plurality of compute registers; a processing management circuit configured to store a register index rule table and an address log, wherein the register index rule table includes a first register index rule corresponding to a value of the first register index field, and wherein the processing management circuit is configured to identify a first compute register of the plurality of compute registers based on the first register index rule and the address log; and a compute circuit configured to perform a first compute operation for the first instruction based on the first compute register.

2. The in-memory processor of claim 1, wherein, the register index rule table includes a plurality of access keys and a plurality of register index rules respectively corresponding to the plurality of access keys, and wherein the processing management circuit is configured to identify a first access key corresponding to the first register index field from among the plurality of access keys, and to identify the first compute register based on the first register index rule corresponding to the first access key.

3. The in-memory processor of claim 2, wherein, the processing management circuit includes: a plurality of register index rule memory circuits configured to respectively store the plurality of register index rules; and a plurality of access key registers respectively corresponding to the plurality of register index rule memory circuits and respectively storing the plurality of access keys.

4. The in-memory processor of claim 3, wherein, the processing management circuit is configured to change an access key stored in one of the plurality of access key registers in response to a request from outside the in-memory processor.

5. The in-memory processor of claim 2, wherein, the register index rule table includes the plurality of register index rules based on a bit mask table for at least one of a row address and a column address stored in the address log.

6. The in-memory processor of claim 1, wherein, the address log includes a column address included in a processing command provided to the memory device and indicative of the first instruction.

7. The in-memory processor of claim 6, wherein, the address log further includes a row address included in one or more activation commands provided to the memory device prior to the processing command.

8. The in-memory processor of claim 1, wherein, a number of the plurality of compute registers is greater than a power of two of a code length of the first register index field as a radix.

9. The in-memory processor of claim 1, wherein, the first instruction further includes a first address alignment field, wherein the instruction list circuit is further configured to store a second instruction including a second register index field and a second address alignment field, wherein the processing management circuit is configured to: identify the first compute register based on the first register index rule when a value of the first address alignment field is a first value; and identify a second compute register having a register index corresponding to a value of the second register index field when a value of the second address alignment field is a second value, wherein the compute circuit is further configured to perform a second compute operation for the second instruction based on the second compute register.

10. The processor-in-memory of claim 1, wherein, The compute circuitry is configured to store a first computation result generated by performing the first computation operation in the first computation register, or receive a first operand for the first computation operation from the first computation register.

11. An in-memory processor included in a memory device, the in-memory processor comprising: instruction list circuitry configured to store a first instruction; a plurality of computation registers; processing management circuitry configured to determine a first register index based on a first register index rule in response to receiving a first execution request for the first instruction at a first point in time, and determine a second register index based on a second register index rule in response to receiving a second execution request for the first instruction at a second point in time after the first point in time; and compute circuitry configured to perform a first computation operation for the first instruction based on a first computation register of the plurality of computation registers corresponding to the first register index, and perform a second computation operation for the first instruction based on a second computation register of the plurality of computation registers corresponding to the second register index.

12. The in-memory processor of claim 11, wherein, The processing management circuitry comprises: first register index rule storage circuitry configured to store the first register index rule; second register index rule storage circuitry configured to store the second register index rule; a first access key register configured to access the first register index rule storage circuitry; and a second access key register configured to access the second register index rule storage circuitry, and wherein the first access key register is configured to store a first access key, and the second access key register is configured to store a second access key.

13. The in-memory processor of claim 12, wherein, The first instruction includes a first register index field, and wherein the processing management circuitry is configured to identify an access key register storing an access key corresponding to a value of the first register index field, and determine a register index based on a register index rule stored in a register index rule storage circuitry corresponding to the identified access key register.

14. The in-memory processor of claim 13, wherein, The processing management circuitry is configured to change a value of the second access key based on a value of the first access key between the first point in time and the second point in time.

15. The in-memory processor of claim 14, wherein, The processing management circuitry is configured to change a value of the second access key to a value of the first access key based on a second register write command for the second access key register being provided to the memory device from outside the in-memory processor between the first point in time and the second point in time.

16. The in-memory processor of claim 11, wherein, The processing management circuitry further comprises an address log, and wherein the processing management circuitry is configured to: determine the first register index further based on a first row address and a first column address stored in the address log at the first point in time, and determine the second register index further based on a second row address and a second column address stored in the address log at the second point in time.

17. The in-memory processor of claim 16, wherein, The first column address is stored in the address log based on a first processing command corresponding to the first execution request provided to the memory device, and wherein the second column address is stored in the address log based on a second processing command corresponding to the second execution request provided to the memory device.

18. The in-memory processor of claim 17, wherein, The first row address is stored in the address log based on a first activation command provided to the memory device prior to the first processing command, and wherein the second row address is stored in the address log based on a second activation command provided to the memory device prior to the second processing command.

19. A memory device configured to perform a compute operation, comprising: an in-memory processor configured to perform the compute operation based on a target compute register among a plurality of compute registers; and control logic configured to change a register index rule for determining the target compute register in response to a command provided from an external device.

20. The memory device of claim 19, wherein, The in-memory processor includes: a plurality of register index rule memory circuits configured to store a plurality of register index rules, respectively; and a plurality of access key registers corresponding to the plurality of register index rule memory circuits, respectively, and configured to store a plurality of access keys, respectively, and wherein the control logic is configured to change the register index rule for determining the target compute register by changing at least one access key among the plurality of access keys in response to the command from the external device.

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