Topological structure generation method, communication method, device, chip and program product

Abstract

The invention relates to the technical field of computers, and discloses a topological structure generation method, a communication method, equipment, a chip and a program product. The topological structure parameters comprise a plurality of master port identifiers, a plurality of slave port identifiers, a mapping relationship between a plurality of master ports and a plurality of slave ports and first data bit widths of the plurality of master ports and the plurality of slave ports, and the mapping relationship comprises that at least two master ports in the plurality of master ports correspond to the same slave port in the plurality of slave ports, and / or at least two slave ports in the plurality of slave ports correspond to the same slave port in the plurality of slave ports. At least two slave ports in the plurality of slave ports correspond to the same master port in the plurality of master ports; determining communication parameters based on the topological structure parameters, wherein the communication parameters comprise the number of arbiters and arbitration parameters; and generating a topological structure file based on the communication parameters, the plurality of master ports and the plurality of slave ports, the topological structure file comprising connection lines among the plurality of master ports, the plurality of slave ports and the at least one arbiter. A user does not need to manually configure an arbiter and calculate, and the labor cost is saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a topology generation method, a communication method, equipment, a chip and a program product. BACKGROUND

[0002] With the increasing integration of system on chip (SoC), the number of on-chip master devices (processor cores, controllers, etc.) and slave devices (registers, memories, etc.) is increasing, and users (chip designers) need to manually configure the topology between each port (access port and accessed port) in the bus interconnection matrix used for interconnection communication between the master device and the slave device.

[0003] However, for scenarios in which multiple access ports (hereinafter referred to as slave ports) need to concurrently access the same accessed port (hereinafter referred to as master port), or a certain slave port needs to receive access responses of different master ports in parallel, the user usually needs to manually configure an arbitrator and design the corresponding path, and the user usually needs to perform repeated iterative calculations, which consumes a large amount of labor cost and time cost. SUMMARY

[0004] The purpose of the present application is to provide a topology generation method, a communication method, equipment, a chip and a program product.

[0005] The first aspect of the present application provides a topology generation method, comprising: obtaining topology parameters, wherein the topology parameters comprise a plurality of master port identifiers, a plurality of slave port identifiers, a mapping relationship between the plurality of master ports and the plurality of slave ports, and a first data bit width of the plurality of master ports and the plurality of slave ports, wherein the mapping relationship comprises at least one of the following: at least two master ports in the plurality of master ports correspond to the same slave port in the plurality of slave ports, and at least two slave ports in the plurality of slave ports correspond to the same master port in the plurality of master ports; determining communication parameters based on the topology parameters, wherein the communication parameters comprise an arbitrator number and arbitration parameters of the arbitrator; and generating a topology file based on the communication parameters, the plurality of master ports and the plurality of slave ports, wherein the topology file comprises a connection between the plurality of master ports, the plurality of slave ports and at least one arbitrator.

[0006] In the embodiments of the present application, for the scenario that multiple slave ports need to access the same master port concurrently, or a certain slave port needs to receive access response of different master ports in parallel, the electronic device can determine the number of arbiters required by the component topology and other communication parameters such as arbitration parameters of the arbiters based on the obtained topology structure parameters such as the plurality of master port identifiers, the plurality of slave port identifiers, the mapping relationship between the plurality of master ports and the plurality of slave ports, and the first data bit widths of the plurality of master ports and the plurality of slave ports, and generate a corresponding topology structure file based on the determined communication parameters and the obtained topology structure parameters.

[0007] In this way, the user (chip designer) does not need to manually configure the arbiters and design the corresponding paths, and does not need to manually perform iterative calculation, thereby saving labor cost and time cost.

[0008] In a possible implementation of the first aspect, the communication parameters further include data bit widths of target data of the plurality of master ports, and data bit widths of target data of the plurality of slave ports; and the determination of the communication parameters based on the topology structure parameters includes: when the first data bit width corresponding to a first slave port in the plurality of slave ports is greater than the first data bit width of the first master port corresponding to the first slave port, determining that the data bit width of the target data of the first master port is the first data bit width of the first slave port, and the data bit width of the target data of the first slave port is the first data bit width of the first slave port; or when the first data bit width corresponding to the first slave port in the plurality of slave ports is less than the first data bit width of the first master port corresponding to the first slave port, determining that the data bit width of the target data of the first slave port is the first data bit width of the first master port, and the data bit width of the target data of the first master port is the first data bit width of the first master port.

[0009] In the embodiments of the present application, for the case that the first data bit widths of the plurality of master ports and the plurality of slave ports are different, the electronic device can also process the target data of each port to make the target data meet the requirements of the input or output port.

[0010] In a possible implementation of the first aspect, the arbitration parameters of the arbiters include bit width parameters; and the determination of the communication parameters based on the topology structure parameters includes: determining at least one master port and at least one slave port connected to each of the arbiters; obtaining the first data bit width of the at least one master port connected to each of the arbiters, and the first data bit width of the at least one slave port connected to each of the arbiters; and setting the bit width parameters of each of the arbiters to be greater than or equal to the maximum value of the first data bit width of the at least one master port connected to each of the arbiters and the first data bit width of the at least one slave port connected to each of the arbiters.

[0011] In a possible implementation of the first aspect, the arbitration parameter of the arbitrator includes a port mapping; and determining the communication parameter based on the topology parameter includes: determining at least one master port and at least one slave port connected to each arbitrator; determining the port mapping of each arbitrator based on the at least one master port and the at least one slave port connected to each arbitrator, so that any one of the plurality of master ports is connected to the corresponding slave port through a unique path, wherein the port mapping includes: port identifier or address information of the corresponding master port of each arbitrator, and / or port identifier or address information of the corresponding slave port of each arbitrator.

[0012] In the embodiment of the application, the electronic device can determine the appropriate number of arbitrators and the arbitration parameter of the arbitrator based on the obtained topology parameter, without the need for the user to manually set the number of arbitrators or manually calculate the arbitration parameter, thereby further saving the labor cost and time cost.

[0013] In a possible implementation of the first aspect, the at least one arbitrator constitutes an N-level arbitration structure, where N is an integer greater than 1.

[0014] In a possible implementation of the first aspect, the topology parameter further includes bus protocol information of the plurality of master ports and bus protocol information of the plurality of slave ports, and the communication parameter further includes bus protocol configuration information; and determining the communication parameter based on the topology parameter includes: configuring the bus protocol of the master port and the corresponding slave port to be the same protocol based on the mapping relationship between the plurality of master ports and the plurality of slave ports.

[0015] In the embodiment of the application, for the case where the communication protocols of the plurality of master ports and the plurality of slave ports are not unified, the electronic device can also complete the unified configuration of the communication protocols without the need for the user to manually configure, thereby further saving the labor cost and time cost.

[0016] In a possible implementation of the first aspect, the bus protocol includes at least one of the following: AXI, APB, and AHB.

[0017] In a possible implementation of the first aspect, the number of arbitrators and the port mapping can be set by the user.

[0018] In the embodiment of the application, the number of arbitrators and the port mapping can be set by the user, thereby improving the flexibility of topology generation.

[0019] In a possible implementation of the first aspect, it is detected that the topology between the plurality of master ports, the plurality of slave ports, and the at least one arbitrator cannot be constructed based on the number of arbitrators and the port mapping set by the user; and error prompt information is generated.

[0020] In a possible implementation of the first aspect, the method further includes providing the user with a recommended number of arbitrators and a corresponding topology.

[0021] The second aspect of the present application provides a communication method applied to a system on chip, the system on chip including: master nodes corresponding to a plurality of master ports, slave nodes corresponding to a plurality of slave ports, and an interconnection network, wherein the interconnection network includes at least one arbitrator, and the interconnection network is determined based on a topology structure file generated by any one of the topology structure generation methods in the first aspect; and the communication method includes: the slave nodes corresponding to the plurality of slave ports sending access requests through the plurality of slave ports, the access requests being used to access the master nodes corresponding to the plurality of master ports, wherein at least two of the plurality of master ports correspond to a same slave port of the plurality of slave ports, and / or at least two of the plurality of slave ports correspond to a same master port of the plurality of master ports; and the interconnection network obtaining the access requests sent by the plurality of slave ports, and sending the access requests sent by the plurality of slave ports to the master nodes corresponding to the plurality of master ports through the master ports corresponding to the slave ports.

[0022] In a possible implementation of the second aspect, the communication method further includes: the master nodes corresponding to the plurality of master ports sending access request response information through the plurality of master ports, the access request response information corresponding to the access requests received by the master nodes in a one-to-one manner; and the interconnection network obtaining the access request response information sent by the plurality of master ports, and sending the access request response information sent by the pluralityity of master ports to the slave nodes corresponding to the plurality of slave ports through the slave ports corresponding to the master ports.

[0023] The third aspect of the present application provides an electronic device, including: a memory configured to store instructions for execution by one or more processors of the electronic device, and a processor, which is one of the processors of the electronic device, configured to execute any one of the topology structure generation methods in the first aspect.

[0024] The fourth aspect of the present application provides a chip, including a processing circuit, a storage medium, and computer program code stored in the storage medium; the computer program code is executed by the processing circuit to implement any one of the topology structure generation methods in the first aspect, and / or any one of the communication methods in the second aspect.

[0025] The fifth aspect of the present application provides a computer readable storage medium, the computer readable storage medium storing instructions, the instructions being executed to implement any one of the topology structure generation methods in the first aspect, and / or any one of the communication methods in the second aspect.

[0026] The sixth aspect of the present application provides a program product including instructions for implementing any of the topology generation methods in the first aspect and / or any of the communication methods in the second aspect when the instructions are executed. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application or the prior art, the drawings needed in the description of the specific embodiments or the prior art will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0028] Figure 1 According to the embodiments of the present application, an implementation flowchart of a topology generation method is shown;

[0029] Figure 2 According to the embodiments of the present application, a schematic diagram of a topology is shown;

[0030] Figure 3 According to the embodiments of the present application, a schematic diagram of another topology is shown;

[0031] Figure 4 According to the embodiments of the present application, an implementation flowchart of a communication method is shown;

[0032] Figure 5 According to some embodiments of the present application, a structural schematic diagram of an electronic device 100 is shown;

[0033] Figure 6 According to the embodiments of the present application, a logic block diagram for implementing a topology generation method by executing a script file is shown. DETAILED DESCRIPTION

[0034] The illustrative embodiments of the present application include but are not limited to a topology generation method, a communication method, a device, a chip and a program product.

[0035] For ease of description, the following takes the access port as the slave port and the accessed port as the master port as an example to describe the scheme provided by the embodiments of the present application in detail. It can be understood that in other embodiments, the access port can also be called the master port, and the accessed port can also be called the slave port, which is not limited by the present application.

[0036] As described above, for the scenario that multiple slave ports need to access the same master port concurrently, or a certain slave port needs to receive access response of different master ports in parallel, the user usually needs to manually configure the arbiter and design the corresponding path, and the user usually needs to perform repeated iterative calculation, which consumes a large amount of labor cost and time cost.

[0037] To solve the above technical problems, the present application provides a topology structure generation method, which comprises: obtaining topology structure parameters, wherein the topology structure parameters comprise a plurality of master port identifiers, a plurality of slave port identifiers, a mapping relationship between the plurality of master ports and the plurality of slave ports, and a first data bit width of the plurality of master ports and the plurality of slave ports, wherein the mapping relationship comprises at least one of the following: at least two master ports in the plurality of master ports correspond to the same slave port in the plurality of slave ports, and at least two slave ports in the plurality of slave ports correspond to the same master port in the plurality of master ports; determining communication parameters based on the topology structure parameters, wherein the communication parameters comprise the number of arbiters and arbitration parameters of the arbiters; and generating a topology structure file based on the communication parameters, the plurality of master ports and the plurality of slave ports, wherein the topology structure file comprises the connection between the plurality of master ports, the plurality of slave ports and at least one arbiter.

[0038] It can be understood that, for the scenario that multiple slave ports need to access the same master port concurrently, or a certain slave port needs to receive access response of different master ports in parallel, the electronic device can determine the number of arbiters and arbitration parameters of the arbiters required by the component topology based on the obtained topology structure parameters such as the plurality of master port identifiers, the plurality of slave port identifiers, the mapping relationship between the plurality of master ports and the plurality of slave ports, and the first data bit width of the plurality of master ports and the plurality of slave ports, and generate the corresponding topology structure file based on the determined communication parameters and the obtained topology structure parameters.

[0039] In this way, the user (chip designer) does not need to manually configure the arbiter and design the corresponding path, and does not need to manually perform iterative calculation, which can save labor cost and time cost.

[0040] In order to better understand the technical solutions provided by the embodiments of the present application, some technical solutions of the present application will be described in detail below.

[0041] Figure 1 An implementation flowchart of a topology structure generation method is shown according to an embodiment of the present application. It can be understood that, Figure 1 The execution subject of each step of the flowchart is an electronic device 100. In order to simplify the description, the execution subject of each step will not be repeatedly described when the flowchart is introduced below. Figure 1 The execution subject of each step of the flowchart will not be repeatedly described when the flowchart is introduced below. Figure 1 As shown in the figure, the flowchart comprises but is not limited to the following steps:

[0042] S101: acquire topology parameters, wherein the topology parameters comprise a plurality of master port identifications, a plurality of slave port identifications, a mapping relationship between the plurality of master ports and the plurality of slave ports, and a first data bit width of the plurality of master ports and the plurality of slave ports.

[0043] In some embodiments, the master port identification is used to identify different master ports, i.e., different master ports correspond to different master port identifications. The slave port identification is used to identify different slave ports, i.e., different slave ports correspond to different slave port identifications.

[0044] For example, the topology parameters can include master port identifications: master port M0, master port M1, master port M2, and master port M3, and slave port identifications: slave port S0, slave port S1, slave port S2, and slave port S3.

[0045] For another example, the topology parameters can include master port identifications: master port M0, master port M1, master port M2, and master port M3, and slave port identifications: slave port S0, slave port S1, slave port S2, slave port S3, slave port S4, and slave port S5.

[0046] It can be understood that the number of master port identifications and the number of slave port identifications can be the same, and the number of master port identifications and the number of slave port identifications can also be different, which is not limited by the present application.

[0047] In some embodiments, the mapping relationship includes at least one of the following: at least two master ports in the plurality of master ports correspond to the same slave port in the plurality of slave ports, and at least two slave ports in the plurality of slave ports correspond to the same master port in the plurality of master ports. That is, the plurality of slave ports need to access the same master port concurrently, and / or a certain slave port needs to receive access responses of different master ports in parallel.

[0048] For example, taking master port M0, master port M1, master port M2, master port M3, slave port S0, slave port S1, slave port S2, and slave port S3 as an example, the mapping relationship can be: slave port S0 corresponds to master port M0, master port M2, and master port M3, i.e., the access request sent through slave port S0 is used to access the nodes corresponding to master port M0, master port M2, and master port M3 respectively; slave port S1 corresponds to master port M1 and master port M2, i.e., the access request sent through slave port S1 is used to access the nodes corresponding to master port M1 and master port M2 respectively; slave port S2 corresponds to master port M2 and master port M3, i.e., the access request sent through slave port S2 is used to access the nodes corresponding to master port M2 and master port M3 respectively; and slave port S3 corresponds to master port M2 and master port M3, i.e., the access request sent through slave port S3 is used to access the nodes corresponding to master port M2 and master port M3 respectively.

[0049] For example, taking master port M0, master port M1, master port M2, master port M3, slave port S0, slave port S1, slave port S2, slave port S3, slave port S4 and slave port S5 as an example, the mapping relationship can be: slave port S0 corresponds to master port M0, master port M1 and master port M2, that is, an access request sent through slave port S0 is used to access nodes corresponding to master port M0, master port M1 and master port M2 respectively; slave port S1 corresponds to master port M1 and master port M2, that is, an access request sent through slave port S1 is used to access nodes corresponding to master port M1 and master port M2 respectively; slave port S2 corresponds to master port M1 and master port M2, that is, an access request sent through slave port S2 is used to access nodes corresponding to master port M1 and master port M2 respectively; slave port S3 corresponds to master port M2 and master port M3, that is, an access request sent through slave port S3 is used to access nodes corresponding to master port M2 and master port M3 respectively; slave port S4 corresponds to master port M2 and master port M3, that is, an access request sent through slave port S4 is used to access nodes corresponding to master port M2 and master port M3 respectively; and slave port S5 corresponds to master port M2 and master port M3, that is, an access request sent through slave port S5 is used to access nodes corresponding to master port M2 and master port M3 respectively.

[0050] It can be understood that the above mapping relationship is only an example, and the mapping relationship is not limited thereto, and any mapping relationship that satisfies the condition that at least two master ports of the plurality of master ports correspond to the same slave port of the plurality of slave ports or at least two slave ports of the plurality of slave ports correspond to the same master port of the plurality of master ports is within the protection scope of the present application.

[0051] In some embodiments, the topology parameter further includes bus protocol information of the plurality of master ports and bus protocol information of the plurality of slave ports. The bus protocol includes at least one of AXI, APB and AHB.

[0052] It can be understood that AXI, APB and AHB are all AMBA protocols (advanced microcontroller bus architecture, a kind of on-chip bus protocol standard). However, the bus protocol information of the plurality of master ports and the bus protocol information of the plurality of slave ports in the embodiments of the present application are not limited thereto, and the bus protocol information of the plurality of master ports and the bus protocol information of the plurality of slave ports can also be other communication protocols for system on chip (such as SoC).

[0053] It can be understood that the bus protocols of the various master ports and the various slave ports can be completely the same, partially the same or completely different, and the present application does not limit this.

[0054] In some embodiments, the topology parameter can be set by a user. For example, input configuration information (or referred to as a configuration file) including the topology parameter and other user-set information, the electronic device 100 acquires the user-input configuration information and acquires the topology parameter. The format of the configuration information can be in text form, table form, picture form, etc., which is not limited in the present application.

[0055] In some embodiments, on the slave port side, the user can configure P interfaces and the communication protocols of the P interfaces. On the master port side, the user can configure Q interfaces and the communication protocols of the Q interfaces. Wherein, P is an integer greater than 0 and Q is an integer greater than 1, or P is an integer greater than 1 and Q is an integer greater than 0. For example, P is any one of the integer values from 32 to 1024, and Q is any one of the integer values from 32 to 1024. The protocol of each interface can be any one of the following: AXI, APB, AHB.

[0056] S102: determining the communication parameter based on the topology parameter, wherein the communication parameter includes the number of arbiters and the arbitration parameter of the arbiters.

[0057] In some embodiments, corresponding to the case that at least one arbiter only constitutes a one-level arbitration structure, each master port is connected with an independent arbiter, and each slave port is connected with the arbiter connected with the master port corresponding to the slave port, i.e., the number of arbiters is the number of master ports.

[0058] For example, assuming that the slave port S00 corresponds to the master port M00, and the slave port S01 corresponds to the master port M00 and the master port M01, the master port M00 is connected with the arbiter A00, and the master port M01 is connected with the arbiter A01 (i.e., the master port M00 and the master port M01 are connected with an independent arbiter, respectively). The slave port S00 is connected with the arbiter A00 (i.e., the slave port S00 is connected with the arbiter A00 connected with the master port M00 corresponding to the slave port S00), the slave port S01 is connected with the arbiter A00 (i.e., the slave port S01 is connected with the arbiter A00 connected with the master port M00 corresponding to the slave port S01), and the slave port S01 is connected with the arbiter A01 (i.e., the slave port S01 is connected with the arbiter A01 connected with the master port M01 corresponding to the slave port S01).

[0059] In some embodiments, the at least one arbitrator constitutes a 1-level arbitration structure. The master port corresponding to each slave port is connected to a separate arbitrator. The slave port is connected to the arbitrator connected to the master port corresponding to the slave port, and / or the slave port is directly connected to the master port corresponding to the slave port and not connected to an arbitrator. That is, the number of arbitrators is equal to the number of master ports corresponding to the slave ports. In this way, the number of arbitrators can be reduced, thereby saving chip manufacturing costs.

[0060] For example, still assuming that the slave port S00 corresponds to the master port M00, and the slave port S01 corresponds to the master port M00 and the master port M01, the master port M00 is connected to the arbitrator A00 (i.e., the master port M00 corresponding to the slave port S00 and the slave port S01 is connected to a separate arbitrator). The slave port S00 is connected to the arbitrator A00 (i.e., the slave port S00 is connected to the arbitrator A00 connected to the master port M00 corresponding to the slave port S00), the slave port S01 is connected to the arbitrator A00 (i.e., the slave port S01 is connected to the arbitrator A00 connected to the master port M00 corresponding to the slave port S01), and the slave port S01 is directly connected to the master port M01 (i.e., the slave port S01 is directly connected to the master port M01 corresponding to the slave port S01 and not connected to an arbitrator).

[0061] In some embodiments, the at least one arbitrator constitutes an N-level arbitration structure, where N is an integer greater than 1.

[0062] It can be understood that N can be determined based on the number of master ports and slave ports and communication latency, and N can also be configured by a user, which is not limited in the present application.

[0063] In some embodiments, the maximum number of arbitrators at each level can be the number of master ports when the at least one arbitrator constitutes an N-level arbitration structure.

[0064] For example, if the number of master ports is 32, the number of slave ports is also 32, and the at least one arbitrator constitutes a 3-level arbitration structure, the number of first-level arbitrators, the number of second-level arbitrators, and the number of third-level arbitrators are all 32.

[0065] In some embodiments, the number of N-level arbitrators (the arbitrators directly connected to the master ports) is the maximum number of arbitrators at the level when the at least one arbitrator constitutes an N-level arbitration structure.

[0066] Exemplarily, the maximum of the number of the Nth level arbiters is the number of the master ports. And the maximum of the number of arbiters of each level other than the Nth level arbiters can be determined by the following method: the maximum of the number of the 1st level arbiters (the arbiters directly connected with the slave ports) is half of the number of the master ports, the maximum of the number of the 2nd level arbiters (the arbiters directly connected with the 1st level arbiters) is half of the maximum of the number of the 2nd level arbiters, and so on. The number of arbiters can be reduced, thus the chip manufacturing cost can be saved.

[0067] For example, if the number of the master ports is 32, the number of the slave ports is also 32, and at least one arbiter constitutes a 3-level arbitration structure, the maximum of the number of the 1st level arbiters is 16, the maximum of the number of the 2nd level arbiters is 8, and the maximum of the number of the 3rd level arbiters is 32.

[0068] In some embodiments, the communication parameter includes a data bit width of target data of the plurality of master ports and a data bit width of target data of the plurality of slave ports. The first data bit width corresponding to a first slave port in the plurality of slave ports is greater than a first data bit width of a first master port corresponding to the first slave port, and the electronic device 100 determines the data bit width of target data of the first master port as the first data bit width of the first slave port, and the data bit width of target data of the first slave port as the first data bit width of the first slave port. The first data bit width corresponding to a first slave port in the plurality of slave ports is less than a first data bit width of a first master port corresponding to the first slave port, and the electronic device 100 determines the data bit width of target data of the first slave port as the first data bit width of the first master port, and the data bit width of target data of the first master port as the first data bit width of the first master port.

[0069] Wherein, the target data of the slave port is data output by the slave port or data input by the slave port, and the target data of the master port is data input by the master port or data output by the master port.

[0070] For example, assuming that the first data bit width of the slave port S0 is 128 bits, and the first data bit width of the master port M0 corresponding to the slave port S0 is 256 bits, the data bit width of the target data of the slave port S0 is 256, and the data bit width of the target data of the master port M0 is 256.

[0071] For another example, assuming that the first data bit width of the slave port S1 is 512 bits, and the first data bit width of the master port M2 corresponding to the slave port S1 is 256 bits, the data bit width of the target data of the master port M2 is 512, and the data bit width of the slave port S1 is 512.

[0072] It can be understood that when the first data bit widths of the plurality of master ports and the plurality of slave ports are different, the electronic device can also process the target data of each port to make the target data meet the requirements of the input or output port.

[0073] In some embodiments, the communication parameters include the number of arbiters and arbitration parameters of the arbiters, wherein the arbitration parameters of the arbiters include bit width parameters, and / or port mapping.

[0074] In some embodiments, the electronic device 100 can determine the bit width parameters of the arbiters by the following method: the electronic device 100 determines at least one master port and at least one slave port connected to each of the arbiters; obtains the first data bit width of the at least one master port connected to each of the arbiters, and the first data bit width of the at least one slave port connected to each of the arbiters; sets the bit width parameter of each of the arbiters to be greater than or equal to the maximum value of the first data bit width of the at least one master port connected to each of the arbiters, and the first data bit width of the at least one slave port connected to each of the arbiters.

[0075] Specifically, a breadth first search (BFS) algorithm can be used to determine the master ports and slave ports connected to each of the arbiters, and the maximum value on the path is taken as the bit width parameter of the arbiter.

[0076] For example, in the mapping relationship of the master port M0, the master port M1, the master port M2, the master port M3, the slave port S0, the slave port S1, the slave port S2, and the slave port S3, the slave port S0 corresponds to the master port M0, the master port M2, and the master port M3, the slave port S1 corresponds to the master port M1 and the master port M2, the slave port S2 corresponds to the master port M2 and the master port M3, and the slave port S3 corresponds to the master port M2 and the master port M3. Assuming that the first data bit width of the slave port S0 is 128, the first data bit width of the slave port S1 is 512, the first data bit width of the slave port S2 is 64, the first data bit width of the slave port S3 is 128, the first data bit width of the master port M0 is 256, the first data bit width of the master port M1 is 512, the first data bit width of the master port M2 is 256, and the first data bit width of the master port M3 is 32. Moreover, the number of arbiters is 8, and the 8 arbiters form a 3-level arbitration structure (L0_0, L0_1, L1_0, L1_1, L2_0, L2_1, L2_2, L2_3, wherein L0_0 and L0_1 are connected to slave ports, and L2_0, L2_1, L2_2, and L2_3 are connected to master ports).

[0077] It can be understood that L0_0 and L0_1 constitute a first-level arbiter, L1_0 and L1_1 constitute a second-level arbiter, and L2_0, L2_1, L2_2 and L2_3 constitute a third-level arbiter.

[0078] For the slave port S0: through the slave port S0 (128 bits), the master port M0 (256 bits), the master port M2 (256 bits), and the master port M3 (32 bits), the maximum value of the first data bit width is 256 bits.

[0079] For the slave port S1: through the slave port S1 (512 bits), the master port M1 (512 bits), and the master port M2 (256 bits), the maximum value of the first data bit width is 512 bits.

[0080] For the slave port S2: through the slave port S2 (64 bits), the master port M2 (256 bits), and the master port M3 (32 bits), the maximum value of the first data bit width is 256 bits.

[0081] For the slave port S3: through the slave port S3 (128 bits), the master port M2 (256 bits), and the master port M3 (32 bits), the maximum value of the first data bit width is 256 bits.

[0082] For the arbiter L0_0: through the slave port S0 (128 bits), the slave port S1 (512 bits), the master port M1 (512 bits), the master port M2 (256 bits), and the master port M3 (32 bits), the maximum value of the first data bit width is 512 bits. Therefore, the electronic device 100 sets the bit width parameter of the arbiter L0_0 to a value greater than or equal to 512 bits, for example, 512 bits.

[0083] For the arbiter L0_1: through the slave port S2 (64 bits), the slave port S3 (256 bits), the master port M2 (256 bits), and the master port M3 (32 bits), the maximum value of the first data bit width is 256 bits. Therefore, the electronic device 100 sets the bit width parameter of the arbiter L0_1 to a value greater than or equal to 256 bits, for example, 256 bits.

[0084] For the arbiter L1_0: through the slave port S0 (128 bits), the slave port S1 (512 bits), the master port M1 (512 bits), the master port M2 (256 bits), and the master port M3 (32 bits), the maximum value of the first data bit width is 512 bits. Therefore, the electronic device 100 sets the bit width parameter of the arbiter L1_0 to a value greater than or equal to 512 bits, for example, 512 bits.

[0085] For the arbiter L1_1: the maximum of the first data bit width is 256 bits through the slave port S2 (64 bits), the slave port S3 (256 bits), the master port M2 (256 bits), the master port M3 (32 bits). Therefore, the electronic device 100 sets the bit width parameter of the arbiter L1_1 to a value greater than or equal to 256 bits, for example 256 bits.

[0086] For the arbiter L2_0: the maximum of the first data bit width is 256 bits through the slave port S0 (128 bits), the master port M0 (256 bits). Therefore, the electronic device 100 sets the bit width parameter of the arbiter L2_0 to a value greater than or equal to 256 bits, for example 256 bits.

[0087] For the arbiter L2_1: the maximum of the first data bit width is 512 bits through the slave port S0 (128 bits), the slave port S1 (512 bits), the master port M1 (512 bits). Therefore, the electronic device 100 sets the bit width parameter of the arbiter L2_1 to a value greater than or equal to 512 bits, for example 512 bits.

[0088] For the arbiter L2_2: the maximum of the first data bit width is 512 bits through the slave port S0 (128 bits), the slave port S1 (512 bits), the slave port S2 (64 bits), the slave port S3 (256 bits), the master port M2 (256 bits). Therefore, the electronic device 100 sets the bit width parameter of the arbiter L2_2 to a value greater than or equal to 512 bits, for example 512 bits.

[0089] For the arbiter L2_3: the maximum of the first data bit width is 128 bits through the slave port S2 (64 bits), the slave port S3 (128 bits), the master port M3 (32 bits). Therefore, the electronic device 100 sets the bit width parameter of the arbiter L2_3 to a value greater than or equal to 128 bits, for example 128 bits.

[0090] For example, the mapping relationship of the master port M0, the master port M1, the master port M2, the master port M3, the slave port S0, the slave port S1, the slave port S2, the slave port S3, the slave port S4 and the slave port S5 is as follows: the slave port S0 corresponds to the master port M0, the master port M1 and the master port M2, the slave port S1 corresponds to the master port M1 and the master port M2, the slave port S2 corresponds to the master port M1 and the master port M2, the slave port S3 corresponds to the master port M2 and the master port M3, the slave port S4 corresponds to the master port M2 and the master port M3, and the slave port S5 corresponds to the master port M2 and the master port M3. Assuming that the first data bit width of the slave port S0 is 32, the first data bit width of the slave port S1 is 32, the first data bit width of the slave port S2 is 64, the first data bit width of the slave port S3 is 256, the first data bit width of the slave port S4 is 512, the first data bit width of the slave port S5 is 128, the first data bit width of the master port M0 is 256, the first data bit width of the master port M1 is 512, the first data bit width of the master port M2 is 128, and the first data bit width of the master port M3 is 64. Moreover, the number of the arbitrators is 8, and the 8 arbitrators form a 3-level arbitration structure (L0_0, L0_1, L1_0, L1_1, L2_0, L2_1, L2_2, L2_3, wherein the L0_0 and the L0_1 are connected with the slave ports, and the L2_0, the L2_1, the L2_2 and the L2_3 are connected with the master ports).

[0091] It can be understood that the L0_0 and the L0_1 form the first-level arbitrators, the L1_0 and the L1_1 form the second-level arbitrators, and the L2_0, the L2_1, the L2_2 and the L2_3 form the third-level arbitrators.

[0092] For the slave port S0: through the slave port S0 (128 bits), the master port M0 (256 bits), the master port M1 (512 bits) and the master port M2 (128 bits), the maximum value of the first data bit width is 512 bits.

[0093] For the slave port S1: through the slave port S1 (32 bits), the master port M1 (512 bits) and the master port M2 (128 bits), the maximum value of the first data bit width is 512 bits.

[0094] For the slave port S2: through the slave port S2 (64 bits), the master port M1 (512 bits) and the master port M2 (128 bits), the maximum value of the first data bit width is 512 bits.

[0095] For the slave port S3: through the slave port S3 (256 bits), the master port M2 (128 bits) and the master port M3 (64 bits), the maximum value of the first data bit width is 256 bits.

[0096] For slave port S4: the maximum of the first data bit width is 512 bits through slave port S4 (512 bits), master port M2 (128 bits), master port M3 (64 bits).

[0097] For slave port S5: the maximum of the first data bit width is 128 bits through slave port S5 (128 bits), master port M2 (128 bits), master port M3 (64 bits).

[0098] For arbiter L0_0: the maximum of the first data bit width is 512 bits through slave port S0 (32 bits), slave port S1 (32 bits), master port M1 (512 bits), master port M2 (128 bits). Therefore, the electronic device 100 sets the bit width parameter of the arbiter L0_0 to a value greater than or equal to 512 bits, for example 512 bits.

[0099] For arbiter L0_1: the maximum of the first data bit width is 512 bits through slave port S4 (512 bits), slave port S5 (128 bits), master port M2 (128 bits), master port M3 (64 bits). Therefore, the electronic device 100 sets the bit width parameter of the arbiter L0_1 to a value greater than or equal to 512 bits, for example 512 bits.

[0100] For arbiter L1_0: the maximum of the first data bit width is 128 bits through slave port S0 (32 bits), slave port S1 (32 bits), slave port S3 (64 bits), master port M2 (128 bits). Therefore, the electronic device 100 sets the bit width parameter of the arbiter L1_0 to a value greater than or equal to 128 bits, for example 128 bits.

[0101] For arbiter L1_1: the maximum of the first data bit width is 512 bits through slave port S3 (256 bits), slave port S4 (512 bits), slave port S5 (128 bits), master port M2 (128 bits). Therefore, the electronic device 100 sets the bit width parameter of the arbiter L1_1 to a value greater than or equal to 512 bits, for example 512 bits.

[0102] For arbiter L2_0: the maximum of the first data bit width is 256 bits through slave port S0 (32 bits), master port M0 (256 bits). Therefore, the electronic device 100 sets the bit width parameter of the arbiter L2_0 to a value greater than or equal to 256 bits, for example 256 bits.

[0103] For arbiter L2_1: the maximum of the first data bit width is 512 bits through slave port S0 (32 bits), slave port S1 (32 bits), slave port S2 (64 bits), master port M1 (512 bits). Therefore, the electronic device 100 sets the bit width parameter of the arbiter L2_1 to a value greater than or equal to 512 bits, for example 512 bits.

[0104] For the arbiter L2_2: the maximum value of the first data bit width is 512 bits through the slave port S0 (32 bits), the slave port S1 (32 bits), the slave port S2 (64 bits), the slave port S3 (256 bits), the slave port S4 (512 bits), the slave port S5 (128 bits), and the master port M2 (128 bits). Therefore, the electronic device 100 sets the bit width parameter of the arbiter L2_2 to a value greater than or equal to 512 bits, for example, 512 bits.

[0105] For the arbiter L2_3: the maximum value of the first data bit width is 512 bits through the slave port S3 (256 bits), the slave port S4 (512 bits), the slave port S5 (128 bits), and the master port M3 (64 bits). Therefore, the electronic device 100 sets the bit width parameter of the arbiter L2_3 to a value greater than or equal to 512 bits, for example, 512 bits.

[0106] In some embodiments, the electronic device 100 can determine the port mapping of the arbiter by the following method: the electronic device 100 determines at least one master port and at least one slave port connected to each arbiter; determines the port mapping of each arbiter based on the at least one master port and the at least one slave port connected to each arbiter, so that any one of the plurality of master ports is connected to the corresponding slave port through a unique path, wherein the port mapping includes: the port identifier or address information of the master port corresponding to each arbiter, and / or the port identifier or address information of the slave port corresponding to each arbiter.

[0107] For example, the electronic device 100 determines the forward mapping relationship of each arbiter and the master port (for example, the port identifier of the master port corresponding to each arbiter), that is, the transmission path of the access request; and the reverse mapping relationship of each arbiter and the slave port (for example, the port identifier of the slave port corresponding to each arbiter), that is, the transmission path of the access request response information.

[0108] In some embodiments, the electronic device 100 can also determine the forward mapping relationship of each slave port and the master port (for example, the port identifier of the master port corresponding to each slave port), that is, the transmission path of the access request; and the reverse mapping relationship of each master port and the slave port (for example, the port identifier of the slave port corresponding to each master port), that is, the transmission path of the access request response information, based on the mapping relationship between the plurality of master ports and the plurality of slave ports.

[0109] For example, the mapping relationship of the above master port M0, master port M1, master port M2, master port M3, slave port S0, slave port S1, slave port S2 and slave port S3 is as follows: the slave port S0 corresponds to the master port M0, the master port M2 and the master port M3, the slave port S1 corresponds to the master port M1 and the master port M2, the slave port S2 corresponds to the master port M2 and the master port M3, the slave port S3 corresponds to the master port M2 and the master port M3, and the number of arbiters is 8, 8 arbiters constitute a 3-level arbitration structure (L0_0, L0_1, L1_0, L1_1, L2_0, L2_1, L2_2, L2_3, wherein L0_0 and L0_1 are connected with slave ports, and L2_0, L2_1, L2_2 and L2_3 are connected with master ports).

[0110] The forward mapping relationship of the slave port S0: the path S0_P0 of the slave port S0 passes through the master port M0, and the path S0_P1 of the slave port S0 passes through the master port M2 and the master port M3. The electronic device 100 determines that the mapping parameter of the path S0_P0 is M0 (for example, denoted as "map (M0)"), and the mapping parameter of the path S0_P1 is M2 and M3 (for example, denoted as "map (M2, M3)").

[0111] The forward mapping relationship of the slave port S1: the path S1_P0 of the slave port S1 passes through the master port M1 and the master port M2. The electronic device 100 determines that the mapping parameter corresponding to the path S1_P0 is M1 and M2 (for example, denoted as "map (M1, M2)").

[0112] The forward mapping relationship of the slave port S2: the path S2_P0 of the slave port S2 passes through the master port M2 and the master port M3. The electronic device 100 determines that the mapping parameter corresponding to the path S2_P0 is M2 and M3 (for example, denoted as "map (M2, M3)").

[0113] The forward mapping relationship of the slave port S3: the path S3_P0 of the slave port S3 passes through the master port M2 and the master port M3. The electronic device 100 determines that the mapping parameter corresponding to the path S3_P0 is M2 and M3 (for example, denoted as "map (M2, M3)").

[0114] The forward mapping relationship of the arbiter L0_0: the path L0ARB0_P0 of the arbiter L0_0 passes through the master port M1, the master port M2 and the master port M3. The electronic device 100 determines that the mapping parameter corresponding to the path L0ARB0_P0 is M1, M2 and M3 (for example, denoted as "map (M1, M2, M3)").

[0115] The forward mapping relationship of the arbiter L0_1: the path L0ARB1_P0 of the arbiter L0_1 passes through the master port M2 and the master port M3, and the electronic device 100 determines that the mapping parameters corresponding to the path L0ARB1_P0 are M2 and M3 (for example, denoted as "map (M2, M3)").

[0116] The forward mapping relationship of the arbiter L1_0: the path L1ARB0_P0 of the arbiter L1_0 passes through the master port M1, the path L1ARB0_P1 of the arbiter L1_0 passes through the master port M2, and the path L1ARB0_P2 of the arbiter L1_0 passes through the master port M3, and the electronic device 100 determines that the mapping parameter of the path L1ARB0_P0 is M1 (for example, denoted as "map (M1)"), the mapping parameter of the path L1ARB0_P1 is M2 (for example, denoted as "map (M2)"), and the mapping parameter of the path L1ARB0_P2 is M3 (for example, denoted as "map (M3)").

[0117] The forward mapping relationship of the arbiter L1_1: the path L1ARB1_P0 of the arbiter L1_1 passes through the master port M2, and the path L1ARB1_P1 of the arbiter L1_1 passes through the master port M3, and the electronic device 100 determines that the mapping parameter corresponding to the path L1ARB1_P0 is M2 (for example, denoted as "map (M2)"), and the mapping parameter corresponding to the path L1ARB1_P1 is M3 (for example, denoted as "map (M3)").

[0118] The reverse mapping relationship of the arbiter L0_0: the path S0_P1 passes through the slave port S0, and the path S1_P0 passes through the slave port S1, and the electronic device 100 determines that the mapping parameter of the path S0_P1 is S0 (for example, denoted as "rmap (S0)"), and the mapping parameter of the path S1_P0 is S1 (for example, denoted as "rmap (S1)").

[0119] The reverse mapping relationship of the arbiter L0_1: the path S2_P0 passes through the slave port S2, and the path S3_P0 passes through the slave port S3, and the electronic device 100 determines that the mapping parameter corresponding to the path S2_P0 is S2 (for example, denoted as "rmap (S2)"), and the mapping parameter corresponding to the path S3_P0 is S3 (for example, denoted as "rmap (S3)").

[0120] The reverse mapping relationship of the arbiter L1_0: the path L0ARB0_P0 passes through the slave port S0 and the slave port S1, and the electronic device 100 determines that the mapping parameter corresponding to the path L0ARB0_P0 is S0 and S1 (for example, denoted as "rmap (S0, S1)").

[0121] The reverse mapping relationship of the arbiter L1_1: the path L0ARB1_P0 passes through the slave port S2 and the slave port S3, and the electronic device 100 determines that the mapping parameter corresponding to the path L0ARB1_P0 is S2 and S3 (for example, denoted as "rmap (S2, S3)").

[0122] The reverse mapping relationship of the arbiter L2_0 (or the master port M0): the path S0_P0 passes through the slave port S0, and the electronic device 100 determines that the mapping parameter of the path S0_P0 is S0 (for example, denoted as "rmap (S0)").

[0123] The reverse mapping relationship of the arbiter L2_1 (or the master port M1): the path L1ARB0_P0 passes through the slave port S1, and the electronic device 100 determines that the mapping parameter of the path L1ARB0_P0 is S1 (for example, denoted as "rmap (S1)").

[0124] The reverse mapping relationship of the arbiter L2_2 (or the master port M2): the path L1ARB0_P1 passes through the slave port S0 and the slave port S1, and the path L1ARB1_P0 passes through the slave port S2 and the slave port S3, and the electronic device 100 determines that the mapping parameter of the path L1ARB0_P1 is S0 and S1 (for example, denoted as "rmap (S0, S1)"), and the mapping parameter of the path L1ARB1_P0 is S2 and S3 (for example, denoted as "rmap (S2, S3)").

[0125] The reverse mapping relationship of the arbiter L2_3 (or the master port M3): the path L1ARB0_P2 passes through the slave port S0, and the path L1ARB1_P1 passes through the slave port S2 and the slave port S3, and the electronic device 100 determines that the mapping parameter of the path L1ARB0_P2 is S0 (for example, denoted as "rmap (S0)"), and the mapping parameter of the path L1ARB1_P1 is S2 and S3 (for example, denoted as "rmap (S2, S3)").

[0126] For example, the mapping relationship of the above-mentioned master port M0, master port M1, master port M2, master port M3, slave port S0, slave port S1, slave port S2, slave port S3, slave port S4 and slave port S5 is as follows: the slave port S0 corresponds to the master port M0, master port M1 and master port M2, the slave port S1 corresponds to the master port M1 and master port M2, the slave port S2 corresponds to the master port M1 and master port M2, the slave port S3 corresponds to the master port M2 and master port M3, the slave port S4 corresponds to the master port M2 and master port M3, the slave port S5 corresponds to the master port M2 and master port M3, and the number of arbiters is 8, and 8 arbiters form a three-level arbitration structure (L0_0, L0_1, L1_0, L1_1, L2_0, L2_1, L2_2, L2_3, wherein L0_0 and L0_1 are connected with slave ports, and L2_0, L2_1, L2_2 and L2_3 are connected with master ports).

[0127] The forward mapping relationship of the slave port S0: the path S0_P0 of the slave port S0 passes through the master port M0, and the path S0_P1 of the slave port S0 passes through the master port M1 and master port M2, and the electronic device 100 determines that the mapping parameter of the path S0_P0 is M0 (for example, denoted as "map (M0)", and the mapping parameter of the path S0_P1 is M1 and M2 (for example, denoted as "map (M1, M2)").

[0128] The forward mapping relationship of the slave port S1: the path S1_P0 of the slave port S1 passes through the master port M1 and master port M2, and the electronic device 100 determines that the mapping parameter corresponding to the path S1_P0 is M1 and M2 (for example, denoted as "map (M1, M2)").

[0129] The forward mapping relationship of the slave port S2: the path S2_P0 of the slave port S2 passes through the master port M1, and the path S2_P1 of the slave port S2 passes through the master port M2, and the electronic device 100 determines that the mapping parameter corresponding to the path S2_P0 is M1 (for example, denoted as "map (M1)", and the mapping parameter corresponding to the path S2_P1 is M2 (for example, denoted as "map (M2)").

[0130] The forward mapping relationship of the slave port S3: the path S3_P0 of the slave port S3 passes through the master port M2, and the path S3_P1 of the slave port S3 passes through the master port M3, and the electronic device 100 determines that the mapping parameter corresponding to the path S3_P0 is M2 (for example, denoted as "map (M2)", and the mapping parameter corresponding to the path S3_P1 is M3 (for example, denoted as "map (M3)").

[0131] The forward mapping relationship of the port S4: the path S4_P0 of the port S4 passes through the master port M2 and the master port M3, and the electronic device 100 determines that the mapping parameter corresponding to the path S4_P0 is M2 and M3 (for example, recorded as "map (M2, M3)").

[0132] The forward mapping relationship of the port S5: the path S5_P0 of the port S5 passes through the master port M2 and the master port M3, and the electronic device 100 determines that the mapping parameter corresponding to the path S5_P0 is M2 and M3 (for example, recorded as "map (M2, M3)").

[0133] The forward mapping relationship of the arbiter L0_0: the path L00_P0 of the arbiter L0_0 passes through the master port M1, and the path L00_P1 of the arbiter L0_0 passes through the master port M2, the electronic device 100 determines that the mapping parameter corresponding to the path L00_P0 is M1 (for example, recorded as "map (M1)"), and the electronic device 100 determines that the mapping parameter corresponding to the path L00_P1 is M2 (for example, recorded as "map (M2)").

[0134] The forward mapping relationship of the arbiter L0_1: the path L01_P0 of the arbiter L0_1 passes through the master port M2, and the path L01_P1 of the arbiter L0_1 passes through the master port M3, the electronic device 100 determines that the mapping parameter corresponding to the path L01_P0 is M2 (for example, recorded as "map (M2)"), and the electronic device 100 determines that the mapping parameter corresponding to the path L01_P1 is M3 (for example, recorded as "map (M3)").

[0135] The forward mapping relationship of the arbiter L1_0: the path L10_P0 of the arbiter L1_0 passes through the master port M2, and the electronic device 100 determines that the mapping parameter of the path L10_P0 is M2 (for example, recorded as "map (M2)").

[0136] The forward mapping relationship of the arbiter L1_1: the path L11_P0 of the arbiter L1_1 passes through the master port M2, and the electronic device 100 determines that the mapping parameter corresponding to the path L11_P0 is M2 (for example, recorded as "map (M2)").

[0137] The reverse mapping relationship of the arbiter L0_0: the path S0_P1 passes through the slave port S0, and the path S1_P0 passes through the slave port S1, the electronic device 100 determines that the mapping parameter of the path S0_P1 is S0 (for example, recorded as "rmap (S0)"), and the mapping parameter of the path S1_P0 is S1 (for example, recorded as "rmap (S1)").

[0138] The reverse mapping relationship of the arbitrator L0_1: the path S4_P0 passes through the slave port S4, and the path S5_P0 passes through the slave port S5. The electronic device 100 determines that the mapping parameter corresponding to the path S4_P0 is S4 (for example, denoted as "rmap(S4)"), and the mapping parameter corresponding to the path S5_P0 is S5 (for example, denoted as "rmap(S5)").

[0139] The reverse mapping relationship of the arbitrator L1_0: the path L00_P1 passes through the slave port S0 and the slave port S1, and the path S2_P1 passes through the slave port S2. The electronic device 100 determines that the mapping parameter corresponding to the path L00_P1 is S0 and S1 (for example, denoted as "rmap(S0, S1)"), and the mapping parameter corresponding to the path S2_P1 is S2 (for example, denoted as "rmap(S2)").

[0140] The reverse mapping relationship of the arbitrator L1_1: the path S3_P0 passes through the slave port S3, and the path L01_P0 passes through the slave port S4 and the slave port S5. The electronic device 100 determines that the mapping parameter corresponding to the path S3_P0 is S3 (for example, denoted as "rmap(S3)"), and the mapping parameter corresponding to the path L01_P0 is S4 and S5 (for example, denoted as "rmap(S4, S5)").

[0141] The reverse mapping relationship of the arbitrator L2_0 (or the master port M0): the path S0_P0 passes through the slave port S0. The electronic device 100 determines that the mapping parameter of the path S0_P0 is S0 (for example, denoted as "rmap(S0)").

[0142] The reverse mapping relationship of the arbitrator L2_1 (or the master port M1): the path L00_P0 passes through the slave port S0 and the slave port S1, and the path S2_P0 passes through the slave port S2. The electronic device 100 determines that the mapping parameter of the path L00_P0 is S0 and S1 (for example, denoted as "rmap(S0, S1)"), and the mapping parameter of the path S2_P0 is S2 (for example, denoted as "rmap(S2)").

[0143] The reverse mapping relationship of the arbitrator L2_2 (or the master port M2): the path L10_P0 passes through the slave port S0, the slave port S1, and the slave port S2, and the path L11_P0 passes through the slave port S3, the slave port S4, and the slave port S5. The electronic device 100 determines that the mapping parameter of the path L10_P0 is S0, S1, and S2 (for example, denoted as "rmap(S0, S1, S2)"), and the mapping parameter of the path L11_P0 is S3, S4, and S5 (for example, denoted as "rmap(S3, S4, S5)").

[0144] The reverse mapping relationship of the arbiter L2_3 (or the master port M3) is: the path S3_P1 passes through the slave port S3, and the path L01_P1 passes through the slave port S4 and the slave port S5. The electronic device 100 determines that the mapping parameter of the path S3_P1 is S3 (for example, denoted as "rmap (S3)", and the mapping parameter of the path L01_P1 is S4 and S5 (for example, denoted as "rmap (S4, S5)".

[0145] It can be understood that the electronic device 100 can determine the number of appropriate arbiters and the arbitration parameters of the arbiters based on the obtained topological structure parameters, without the need for the user to manually set the number of arbiters or manually calculate the arbitration parameters, thereby further saving the labor cost and time cost.

[0146] In some embodiments, the communication parameter includes bus protocol configuration information. Moreover, the electronic device 100 configures the bus protocols of the master ports and the corresponding slave ports to be the same protocol based on the mapping relationship between the plurality of master ports and the plurality of slave ports.

[0147] It can be understood that for the case where the communication protocols of the plurality of master ports and the plurality of slave ports are not unified, the electronic device can also complete the unified configuration of the communication protocols without the need for the user to manually configure, thereby further saving the labor cost and time cost.

[0148] S103: generating a topological structure file based on the communication parameter, the plurality of master ports, and the plurality of slave ports, wherein the topological structure file includes the connection between the plurality of master ports, the plurality of slave ports, and at least one arbiter.

[0149] For example, taking the mapping relationship of the above master port M0, master port M1, master port M2, master port M3, slave port S0, slave port S1, slave port S2, and slave port S3 as an example, the slave port S0 corresponds to the master port M0, the master port M2, and the master port M3, the slave port S1 corresponds to the master port M1 and the master port M2, the slave port S2 corresponds to the master port M2 and the master port M3, and the slave port S3 corresponds to the master port M2 and the master port M3. It is assumed that the first data bit width of the slave port S0 is 128, the first data bit width of the slave port S1 is 512, the first data bit width of the slave port S2 is 64, the first data bit width of the slave port S3 is 128, the first data bit width of the master port M0 is 256, the first data bit width of the master port M1 is 512, the first data bit width of the master port M2 is 256, and the first data bit width of the master port M3 is 32. Moreover, the number of arbiters is 8, and the 8 arbiters form a 3-level arbitration structure (L0_0, L0_1, L1_0, L1_1, L2_0, L2_1, L2_2, L2_3, wherein L0_0 and L0_1 are connected with the slave ports, and L2_0, L2_1, L2_2, and L2_3 are connected with the master ports). The topological structure corresponding to the generated topological structure file can be referred to in the following table 1.Figure 2 a schematic diagram of the topology shown.

[0150] As Figure 2 shown, the bit width parameter of the arbiter L0_0 is 512 bits, the bit width parameter of the arbiter L0_1 is 256 bits, the bit width parameter of the arbiter L1_0 is 512 bits, the bit width parameter of the arbiter L1_1 is 256 bits, the bit width parameter of the arbiter L2_0 is 256 bits, the bit width parameter of the arbiter L2_1 is 512 bits, the bit width parameter of the arbiter L2_2 is 512 bits, and the bit width parameter of the arbiter L2_3 is 128 bits.

[0151] The forward mapping relationship of the slave port S0 is "map (M0)" and "map (M2, M3)". The forward mapping relationship of the slave port S1 is "map (M1, M2)". The forward mapping relationship of the slave port S2 is "map (M2, M3)". The forward mapping relationship of the slave port S3 is "map (M2, M3)". The forward mapping relationship of the arbiter L0_0 is "map (M1, M2, M3)". The forward mapping relationship of the arbiter L0_1 is "map (M2, M3)". The forward mapping relationship of the arbiter L1_0 is "map (M1)", "map (M2)" and "map (M3)". The forward mapping relationship of the arbiter L1_1 is "map (M2)" and "map (M3)".

[0152] The reverse mapping relationship of the arbiter L0_0 is "rmap (S0)" and "rmap (S1)". The reverse mapping relationship of the arbiter L0_1 is "rmap (S2)" and "rmap (S3)". The reverse mapping relationship of the arbiter L1_0 is "rmap (S0, S1)". The reverse mapping relationship of the arbiter L1_1 is "rmap (S2, S3)". The reverse mapping relationship of the arbiter L2_0 (or the master port M0) is "rmap (S0)". The reverse mapping relationship of the arbiter L2_1 (or the master port M1) is "rmap (S1)". The reverse mapping relationship of the arbiter L2_2 (or the master port M2) is "rmap (S0, S1)" and "rmap (S2, S3)". The reverse mapping relationship of the arbiter L2_3 (or the master port M3) is "rmap (S0)" and "rmap (S2, S3)".

[0153] For example, the mapping relationship of the master port M0, the master port M1, the master port M2, the master port M3, the slave port S0, the slave port S1, the slave port S2, the slave port S3, the slave port S4, and the slave port S5 is as follows: the slave port S0 corresponds to the master port M0, the master port M1, and the master port M2; the slave port S1 corresponds to the master port M1 and the master port M2; the slave port S2 corresponds to the master port M1 and the master port M2; the slave port S3 corresponds to the master port M2 and the master port M3; the slave port S4 corresponds to the master port M2 and the master port M3; and the slave port S5 corresponds to the master port M2 and the master port M3. It is assumed that the first data bit width of the slave port S0 is 32, the first data bit width of the slave port S1 is 32, the first data bit width of the slave port S2 is 64, the first data bit width of the slave port S3 is 256, the first data bit width of the slave port S4 is 512, the first data bit width of the slave port S5 is 128, the first data bit width of the master port M0 is 256, the first data bit width of the master port M1 is 512, the first data bit width of the master port M2 is 128, and the first data bit width of the master port M3 is 64. In addition, the number of arbiters is 8, and the 8 arbiters form a three-level arbitration structure (L0_0, L0_1, L1_0, L1_1, L2_0, L2_1, L2_2, and L2_3, where L0_0 and L0_1 are connected with the slave ports, and L2_0, L2_1, L2_2, and L2_3 are connected with the master ports). The topology structure corresponding to the generated topology structure file can be referred to the schematic view of the topology structure shown in Figure 3 .

[0154] As shown in Figure 3 , the bit width parameter of the arbiter L0_0 is 512 bits, the bit width parameter of the arbiter L0_1 is 512 bits, the bit width parameter of the arbiter L1_0 is 128 bits, the bit width parameter of the arbiter L1_1 is 512 bits, the bit width parameter of the arbiter L2_0 is 256 bits, the bit width parameter of the arbiter L2_1 is 512 bits, the bit width parameter of the arbiter L2_2 is 512 bits, and the bit width parameter of the arbiter L2_3 is 512 bits.

[0155] The forward mapping relationship of the slave port S0 is "map(M0)" and "map(M1, M2)". The forward mapping relationship of the slave port S1 is "map(M1, M2)". The forward mapping relationship of the slave port S2 is "map(M1)" and "map(M2)". The forward mapping relationship of the slave port S3 is "map(M2)" and "map(M3)". The forward mapping relationship of the slave port S4 is "map(M2, M3)". The forward mapping relationship of the slave port S5 is "map(M2, M3)". The forward mapping relationship of the arbiter L0_0 is "map(M1)" and "map(M2)". The forward mapping relationship of the arbiter L0_1 is "map(M2)" and "map(M3)". The forward mapping relationship of the arbiter L1_0 is "map(M2)". The forward mapping relationship of the arbiter L1_1 is "map(M2)". The backward mapping relationship of the arbiter L0_0 is "rmap(S0)" and "rmap(S1)". The backward mapping relationship of the arbiter L0_1 is "rmap(S4)" and "rmap(S5)". The backward mapping relationship of the arbiter L1_0 is "rmap(S0, S1)" and "rmap(S2)". The backward mapping relationship of the arbiter L1_1 is "rmap(S3)" and "rmap(S4, S5)". The backward mapping relationship of the arbiter L2_0 (or the master port M0) is "rmap(S0)". The backward mapping relationship of the arbiter L2_1 (or the master port M1) is "rmap(S0, S1)" and "rmap(S2)". The backward mapping relationship of the arbiter L2_2 (or the master port M2) is "rmap(S0, S1, S2)" and "rmap(S3, S4, S5)". The backward mapping relationship of the arbiter L2_3 (or the master port M3) is "rmap(S3)" and "rmap(S4, S5)".

[0156] It can be understood that Figure 2 and Figure 3 The topology structure shown in the figure is only an exemplary illustration, and in actual applications, the form of the topology structure is not limited thereto.

[0157] It can be understood that in other embodiments, according to actual requirements, the steps shown in the above Figure 1 may be combined, deleted, or replaced by other steps that are beneficial to achieve the purpose of the present application, and the present application does not limit this.

[0158] In some embodiments, the number of arbiters and the port mapping can also be set by the user. Moreover, if the electronic device 100 detects that the number of arbiters and the port mapping set by the user cannot construct the topology between the plurality of master ports, the plurality of slave ports and the at least one arbiter, an error prompt information is generated. The error prompt information can be displayed in a visual form on the display screen of the electronic device 100, or the error prompt information can be played in the form of voice broadcast through the audio module of the electronic device 100, and the form of the error prompt information is not limited in the present application.

[0159] In some embodiments, after the electronic device generates the error prompt information, the user can also be provided with a recommended number of arbiters and a corresponding topology, which is based on Figure 1 the topology generation method shown in the figure to generate (for example Figure 2 or Figure 3 the topology shown in the figure).

[0160] It can be understood that the number of arbiters and the port mapping can be set by the user, which improves the flexibility of topology generation.

[0161] It can be understood that the topology file generated by the above topology generation method is used to realize the topology in the system on chip (SoC).

[0162] Therefore, the embodiments of the present application also provide a communication method applied to a system on chip, the system on chip comprising: a plurality of master nodes corresponding to a plurality of master ports, a plurality of slave nodes corresponding to a plurality of slave ports and an interconnection network, wherein the interconnection network comprises at least one arbiter, and the interconnection network is determined based on a topology file generated by the topology generation method provided by the embodiments of the present application. Moreover, the communication method comprises: the plurality of slave nodes corresponding to the plurality of slave ports send access requests through the plurality of slave ports, the access requests being used to access the plurality of master nodes corresponding to the plurality of master ports, wherein at least two master ports in the plurality of master ports correspond to the same slave port in the plurality of slave ports, and / or at least two slave ports in the plurality of slave ports correspond to the same master port in the plurality of master ports; the interconnection network acquires the access requests sent by the plurality of slave ports, and sends the access requests sent by the plurality of slave ports to the plurality of master nodes corresponding to the plurality of master ports through the master ports corresponding to the slave ports. Moreover, after the plurality of master nodes corresponding to the plurality of master ports receive the access requests, the plurality of master nodes send access request response information through the plurality of master ports, the access request response information corresponding to the access requests received by the master nodes in one-to-one correspondence; the interconnection network acquires the access request response information sent by the plurality of master ports, and sends the access request response information sent by the plurality of master ports to the plurality of slave nodes corresponding to the plurality of slave ports through the slave ports corresponding to the master ports.

[0163] For example, Figure 4Embodiments according to the present application show a flowchart of an implementation process of a communication method. As shown in Figure 4 The flowchart includes but is not limited to the following steps:

[0164] S401: The slave nodes corresponding to the slave ports send access requests through the slave ports, and the access requests are used to access the master nodes corresponding to the master ports.

[0165] In some embodiments, at least two master ports in the plurality of master ports correspond to the same slave port in the plurality of slave ports, and / or at least two slave ports in the plurality of slave ports correspond to the same master port in the plurality of master ports.

[0166] For example, Figure 2 The slave nodes corresponding to the slave ports S0, S1, S2 and S3 in the slave ports S0, S1, S2 and S3 send access requests. The access requests sent through the slave port S0 are used to access the master nodes corresponding to the master ports M0, M2 and M3. The access requests sent through the slave port S1 are used to access the master nodes corresponding to the master ports M1 and M2. The access requests sent through the slave port S2 are used to access the master nodes corresponding to the master ports M2 and M3. The access requests sent through the slave port S3 are used to access the master nodes corresponding to the master ports M2 and M3.

[0167] For another example, Figure 3 The slave nodes corresponding to the slave ports S0, S1, S2, S3, S4 and S5 in the slave ports S0, S1, S2, S3, S4 and S5 send access requests. The access requests sent through the slave port S0 are used to access the master nodes corresponding to the master ports M0, M1 and M2. The access requests sent through the slave port S1 are used to access the master nodes corresponding to the master ports M1 and M2. The access requests sent through the slave port S2 are used to access the master nodes corresponding to the master ports M1 and M2. The access requests sent through the slave port S3 are used to access the master nodes corresponding to the master ports M2 and M3. The access requests sent through the slave port S4 are used to access the master nodes corresponding to the master ports M2 and M3. The access requests sent through the slave port S5 are used to access the master nodes corresponding to the master ports M2 and M3.

[0168] S402: The interconnection network acquires the access requests sent by the slave ports, and sends the access requests sent by the slave ports to the master nodes corresponding to the master ports through the master ports corresponding to the slave ports.

[0169] For example, Figure 2The interconnection network (the illustrated topology) in FIG. 1 acquires the access request sent by the slave port S0, the slave port S1, the slave port S2 and the slave port S3. And the access request sent by the slave port S0 is sent to the master nodes corresponding to the master port M0, the master port M2 and the master port M3 through the master port M0, the master port M2 and the master port M3. The access request sent by the slave port S1 is sent to the master nodes corresponding to the master port M1 and the master port M2 through the master port M1 and the master port M2. The access request sent by the slave port S2 is sent to the master nodes corresponding to the master port M2 and the master port M3 through the master port M2 and the master port M3. The access request sent by the slave port S3 is sent to the master nodes corresponding to the master port M2 and the master port M3 through the master port M2 and the master port M3.

[0170] For another example, Figure 3 The interconnection network (the illustrated topology) in FIG. 2 acquires the access request sent by the slave port S0, the slave port S1, the slave port S2, the slave port S3, the slave port S4 and the slave port S5. And the access request sent by the slave port S0 is sent to the master nodes corresponding to the master port M0, the master port M1 and the master port M2 through the master port M0, the master port M1 and the master port M2. The access request sent by the slave port S1 is sent to the master nodes corresponding to the master port M1 and the master port M2 through the master port M1 and the master port M2. The access request sent by the slave port S2 is sent to the master nodes corresponding to the master port M1 and the master port M2 through the master port M1 and the master port M2. The access request sent by the slave port S3 is sent to the master nodes corresponding to the master port M2 and the master port M3 through the master port M2 and the master port M3. The access request sent by the slave port S4 is sent to the master nodes corresponding to the master port M2 and the master port M3 through the master port M2 and the master port M3. The access request sent by the slave port S5 is sent to the master nodes corresponding to the master port M2 and the master port M3 through the master port M2 and the master port M3.

[0171] S403: The master nodes corresponding to the plurality of master ports send the access request response information through the plurality of master ports.

[0172] In some embodiments, the access request response information corresponds to the access request received by the master node one by one.

[0173] S404: The interconnection network acquires the access request response information sent by the plurality of master ports, and sends the access request response information sent by the plurality of master ports to the slave nodes corresponding to the plurality of slave ports through the slave ports corresponding to the plurality of master ports.

[0174] It can be understood that in another embodiment, according to actual needs, the above Figure 4 It can be understood that in another embodiment, according to actual needs, the above

[0175] The embodiments of the present application also provide an electronic device (for example, the electronic device 100 described above), which comprises a memory for storing instructions executed by one or more processors of the electronic device, and a processor which is one of the processors of the electronic device and is configured to execute the topology generation method in the above embodiments.

[0176] For example, Figure 5 According to some embodiments of the present application, a structural schematic diagram of an electronic device 100 is shown. As shown in Figure 5 The electronic device 100 comprises one or more processors 101, a system memory 102, a non-volatile memory (NVM) 103, a communication interface 104, an input / output (I / O) device 105, and system control logic 106 for coupling the processor 101, the system memory 102, the non-volatile memory 103, the communication interface 104, and the input / output (I / O) device 105. Wherein:

[0177] The processor 101 can be configured to control the electronic device to execute the topology generation method of the present application. The processor 101 can comprise one or more processing units, for example, can comprise a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a micro-programmed control unit (MCU), an artificial intelligence (AI) processor, or a processing module or processing circuit of a programmable logic device (FPGA). The processing circuit can comprise one or more single-core or multi-core processors.

[0178] The system memory 102 is a volatile memory, for example, a random-access memory (RAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc. The system memory is used to temporarily store data and / or instructions.

[0179] The non-volatile memory 103 can include one or more tangible, non-transitory computer-readable media for storage of data and / or instructions. In some embodiments, the non-volatile memory 103 can include any suitable non-volatile memory and / or any suitable non-volatile storage device, such as flash memory, and / or a hard disk drive (HDD), compact disc (CD), digital versatile disc (DVD), solid-state drive (SSD), and / or the like. In some embodiments, the non-volatile memory 103 can also be a removable storage medium, such as a secure digital (SD) memory card, and / or the like.

[0180] In particular, the system memory 102 and the non-volatile memory 103 can include, respectively, a temporary copy and a permanent copy of the instructions 107. The instructions 107 can include instructions that, when executed by the processor 101, cause the electronic device 100 to implement the topology generation method provided by embodiments of the present application.

[0181] The communication interface 104 can include a transceiver to provide a wired or wireless communication interface to the electronic device 100 to enable communication to and from any other suitable device via one or more networks. In some embodiments, the communication interface 104 can be integrated with other components of the electronic device 100, such as the communication interface 104 can be integrated with the processor 101. In some embodiments, the electronic device 100 can communicate with other devices via the communication interface 104, such as the electronic device 100 can obtain the topology generation method to be executed from other electronic devices via the communication interface 104.

[0182] The input / output (I / O) device 105 can include input devices such as a keyboard, mouse, and / or the like, and / or output devices such as a display, and / or the like, through which a user can interact with the electronic device 100.

[0183] The system control logic 106 can include any suitable interface controllers to provide any suitable interfaces to other modules of the electronic device 100. For example, in some embodiments, the system control logic 106 can include one or more memory controllers to provide an interface to connect to the system memory 102 and the non-volatile memory 103.

[0184] In some embodiments, at least one of the processors 101 can be packaged together with logic for one or more controllers of the system control logic 106 to form a system in package (SiP). In other embodiments, at least one of the processors 101 can also be integrated on the same chip with logic for one or more controllers of the system control logic 106 to form a SoC.

[0185] It can be appreciated that the electronic device 100 can be any electronic device capable of running computer programs or program codes, including but not limited to a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, etc., without limitation.

[0186] It can be appreciated that Figure 5 The structure of the electronic device 100 shown is only an example, and in other embodiments, the electronic device 100 can include more or fewer components than shown, or combine some components, or split some components, or different arrangement of components. The components shown can be implemented in hardware, software, or a combination of software and hardware.

[0187] Embodiments of the present application also provide a chip, comprising a processing circuit, a storage medium, the storage medium storing computer program codes; the computer program codes are executed by the processing circuit to implement the topology generation method in the above embodiments, and / or the communication method in the above embodiments.

[0188] Embodiments of the present application also provide a computer readable storage medium, the computer readable storage medium storing instructions, the instructions being executed to implement the topology generation method in the above embodiments, and / or the communication method in the above embodiments.

[0189] Embodiments of the present application also provide a program product, the program product comprising instructions, the instructions being executed to implement the topology generation method in the above embodiments, and / or the communication method in the above embodiments.

[0190] For example, in some embodiments, the topology generation method in the above embodiments can be implemented by a script file (as an example of a program product) being executed.

[0191] For example, Figure 6 According to embodiments of the present application, a logic block diagram for implementing the topology generation method in the above embodiments by executing a script file is shown.

[0192] For example, Figure 6As shown, the script file is run by the compiler, in the process of running the script file, the configuration file of the user (such as the topology parameter and other information set by the user) is first acquired, the acquired configuration file is parsed, and it is checked whether it is valid (such as judging whether the topology can be constructed based on the acquired configuration file). If valid, it means that the topology can be constructed based on the acquired configuration file, then the template is constructed, the topology file in the target format is generated, and the topology file is output. If invalid, it means that the topology cannot be constructed based on the acquired configuration file, then the user is prompted to adjust the data (such as generating prompt information), and the configuration file generated by the user after adjusting the data is acquired, and the steps of file parsing, checking validity and the like are performed again until the topology file in the target format is generated and the topology file is output, or the user stops running the script file.

[0193] Embodiments of the mechanisms disclosed herein can be implemented in hardware, software, firmware, or any combination thereof. Embodiments of the application can be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0194] Program code can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as for example a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0195] The program code can be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The program code can be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language can be a compiled or interpreted language.

[0196] In some cases, the disclosed embodiments can be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments can also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) medium, which can be read and executed by one or more processors. For example, the instructions can be distributed over the network or by other computer readable media. Thus, a machine-readable medium can include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including without limitation, floppy diskettes, optical disks, optical fiber, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, flash memory, or tangible or other machine-readable media. Accordingly, a machine-readable medium includes any medium that is capable of storing or transmitting electronic instructions or information that can be used to program a computer to perform any of the methods disclosed herein.

[0197] In the drawings, some of the structural or methodological features can be shown in particular arrangements and / or orders. However, it should be understood that such particular arrangements and / or orders can not be required. Instead, in some embodiments, the features can be arranged in a different manner and / or order than shown in the illustrative drawings. Additionally, inclusion of structural or methodological features in a particular figure is not meant to imply that such features are required in all embodiments, and in some embodiments, these features can not be included or can be combined with other features.

[0198] It should be noted that each unit / module mentioned in the embodiments of the present application is a logical unit / module, in physical, one logical unit / module can be one physical unit / module, or a part of a physical unit / module, or be realized in a combination of multiple physical unit / modules, and the physical realization of the logical unit / module itself is not the most important, the combination of the functions realized by the logical unit / module is the key to solve the technical problems proposed in the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned embodiments of the devices of the present application do not introduce the units / modules which are not closely related to solving the technical problems proposed in the present application, which does not mean that the above-mentioned device embodiments do not have other units / modules.

[0199] It has to be understood that in the examples and the description of the patent, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusions, so that processes, methods, articles or devices that comprise a list of elements not only include those elements, but also other elements not explicitly listed, or other elements inherent to such processes, methods, articles or devices. Without further limitation, an element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article or device that includes the element.

[0200] While the application has been illustrated and described in connection with certain preferred embodiments thereof, it will be readily apparent to those of ordinary skill in the art that various changes in form and detail can be made therein without departing from the spirit and scope of the application.

Claims

1. A topology generation method characterized by comprising: The method comprises: obtaining a topology parameter, wherein the topology parameter comprises a plurality of master port identifiers, a plurality of slave port identifiers, a mapping relationship between the plurality of master ports and the plurality of slave ports, and a first data bit width of the plurality of master ports and the plurality of slave ports, wherein the mapping relationship comprises at least one of the following: at least two master ports in the plurality of master ports correspond to a same slave port in the plurality of slave ports, and at least two slave ports in the plurality of slave ports correspond to a same master port in the plurality of master ports; determining a communication parameter based on the topology parameter, wherein the communication parameter comprises a number of arbiters and an arbitration parameter of the arbiters; generating a topology file based on the communication parameter, the plurality of master ports, and the plurality of slave ports, wherein the topology file comprises a connection between the plurality of master ports, the plurality of slave ports, and at least one arbiter.

2. The topological structure generating method according to claim 1, characterized by, The communication parameter further comprises a data bit width of target data of the plurality of master ports, and a data bit width of target data of the plurality of slave ports. And The determining the communication parameter based on the topology parameter comprises: corresponding to a first data bit width of a first slave port in the plurality of slave ports being greater than a first data bit width of a first master port corresponding to the first slave port, determining a data bit width of target data of the first master port to be the first data bit width of the first slave port, and a data bit width of target data of the first slave port to be the first data bit width of the first slave port. Or corresponding to a first data bit width of a first slave port in the plurality of slave ports being less than a first data bit width of a first master port corresponding to the first slave port, determining a data bit width of target data of the first slave port to be the first data bit width of the first master port, and a data bit width of target data of the first master port to be the first data bit width of the first master port.

3. The topological structure generating method according to claim 2, wherein, The arbitration parameter of the arbiter comprises a bit width parameter; and The determining the communication parameter based on the topology parameter comprises: determining at least one master port and at least one slave port connected to each arbiter; obtaining a first data bit width of the at least one master port connected to each arbiter, and a first data bit width of the at least one slave port connected to each arbiter; setting the bit width parameter of each arbiter to be greater than or equal to a maximum value of the first data bit width of the at least one master port connected to each arbiter, and the first data bit width of the at least one slave port connected to each arbiter.

4. The topology generation method according to claim 2, characterized by, The arbitration parameter of the arbiter comprises a port mapping; and The determining the communication parameter based on the topology parameter comprises: determining at least one master port and at least one slave port connected to each arbiter; determining the port mapping of each arbiter based on the at least one master port and the at least one slave port connected to each arbiter, so that any one of the plurality of master ports is connected to a corresponding slave port through a unique path, wherein the port mapping comprises port identifiers or address information of the master ports corresponding to each arbiter, and / or port identifiers or address information of the slave ports corresponding to each arbiter.

5. The topological structure generating method according to any one of claims 1 to 4, characterized by, The at least one arbitrator constitutes an N-level arbitration structure, where N is an integer greater than 1.

6. The topological structure generating method according to any one of claims 1 to 5, characterized by, The topology parameter further comprises bus protocol information of the plurality of master ports and bus protocol information of the plurality of slave ports, and the communication parameter further comprises bus protocol configuration information. And, The communication parameter is determined based on the topology parameter, comprising: The bus protocol of the master port and the corresponding slave port is configured as the same protocol based on the mapping relationship between the plurality of master ports and the plurality of slave ports.

7. The topological structure generating method according to claim 6, wherein The bus protocol comprises at least one of: AXI, APB, AHB.

8. The topological structure generating method according to any one of claims 1 to 7, characterized by, The number of arbitrators and the port mapping can be set by a user.

9. The topology generation method of claim 8, wherein, It is detected that the topology structure between the plurality of master ports, the plurality of slave ports and the at least one arbitrator cannot be constructed based on the number of arbitrators and the port mapping set by the user; An error prompt information is generated.

10. The topological structure generating method according to claim 9, wherein, The method further comprises: A recommended number of arbitrators and a corresponding topology structure are provided to the user.

11. A communication method, comprising: The system on chip comprises: a plurality of master nodes corresponding to a plurality of master ports, a plurality of slave nodes corresponding to a plurality of slave ports and an interconnection network, wherein the interconnection network comprises at least one arbitrator, and the interconnection network is determined based on a topology structure file generated by the topology generation method of any one of claims 1 to 10; and The communication method comprises: The plurality of slave nodes corresponding to the plurality of slave ports send access requests through the plurality of slave ports, and the access requests are used to access the plurality of master nodes corresponding to the plurality of master ports, wherein At least two of the plurality of master ports correspond to the same slave port of the plurality of slave ports, and / or at least two of the plurality of slave ports correspond to the same master port of the plurality of master ports; The interconnection network acquires the access requests sent by the plurality of slave ports, and sends the access requests sent by the plurality of slave ports to the plurality of master nodes corresponding to the plurality of master ports through the master ports corresponding to the slave ports.

12. The method of claim 11, wherein, The communication method further comprises: The plurality of master nodes corresponding to the plurality of master ports send access request response information through the plurality of master ports, and the access request response information corresponds to the access requests received by the master nodes one by one; The interconnection network acquires the access request response information sent by the plurality of master ports, and sends the access request response information sent by the plurality of master ports to the plurality of slave nodes corresponding to the plurality of slave ports through the slave ports corresponding to the master ports.

13. An electronic device, comprising: Comprise: A memory for storing instructions executed by one or more processors of an electronic device, and A processor, one of the processors of the electronic device, for executing the topology generation method of any one of claims 1 to 10.

14. A chip, characterized by Comprise processing circuitry, storage medium, the storage medium stores computer program code; the computer program code is executed by the processing circuitry to implement the topology generation method of any one of claims 1 to 10, and / or the communication method of any one of claims 11 to 12. Comprise processing circuitry, storage medium, the storage medium stores computer program code; the computer program code is executed by the processing circuitry to implement the topology generation method of any one of claims 1 to 10, and / or the communication method of any one of claims 11 to 12.

15. A computer readable storage medium, characterized in that, The computer readable storage medium stores instructions which, when executed, implement the topology generation method of any one of claims 1 to 10, and / or the communication method of any one of claims 11 to 12.

16. A program product, characterized by The program product includes instructions which, when executed, implement the topology generation method of any one of claims 1 to 10, and / or the communication method of any one of claims 11 to 12.

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