A radio frequency power amplifier gain in-band fluctuation equalization circuit and equalization method

Abstract

The application discloses a kind of radio frequency power amplifier gain in-band fluctuation equalization circuit and equalization method, belong to amplifier technical field.It includes power division module, the input end of power division module is connected input signal, power division module has four-way output end, the input end of load is connected to the one-way output end of power division module, the input end of equalizer is connected to the two-way output end of power division module, the input end of second detection module is connected to the output end of equalizer, the input end of first detection module is connected to the three-way output end of power division module, the output end of first detection module, the output end of second detection module simultaneously connects the input end of control processing unit, the input end of voltage-controlled attenuator is simultaneously connected to the output end of control processing unit, four-way output end of power division module, the input end of radio frequency power amplifier is connected to the output end of voltage-controlled attenuator.The application reduces the compatibility of wideband power amplifier equalizer debugging complexity, it is easy to equalizer batch production, improves production efficiency.

Description

Technical Field

[0001] This invention belongs to the field of amplifier technology, specifically relating to an in-band gain ripple equalization circuit and equalization method for an RF power amplifier. Background Technology

[0002] In the design of broadband RF power amplifiers, the adjustment of the overall gain within the band primarily relies on active or passive equalizer technology. However, when the bandwidth is wide, even for the same model and solution, differences in the power amplifier modules and passive components can lead to inconsistent overall gain within the band. This means that each amplifier requires a custom-designed equalizer based on its specific needs, and even after adjustment, the final gain within the band cannot reach the ideal state. This results in incomplete over-input protection for the RF power amplifier and a high risk of over-input damage. Furthermore, the equalizer adjustment process for broadband RF power amplifiers is complex and inefficient due to the need to adjust to the specific conditions of each device, thus limiting production efficiency. Summary of the Invention

[0003] Purpose of the invention: To provide an in-band gain ripple equalization circuit and equalization method for an RF power amplifier, which solves the above-mentioned problems existing in the prior art.

[0004] Technical Solution: An automatic gain-in-band ripple equalization circuit for an RF power amplifier includes a power divider module. The input terminal of the power divider module is connected to an input signal. The power divider module has four output terminals. One output terminal of the power divider module is connected to the input terminal of a load. Two output terminals of the power divider module are connected to the input terminal of an equalizer. The output terminal of the equalizer is connected to the input terminal of a second detector module. Three output terminals of the power divider module are connected to the input terminal of a first detector module. The output terminals of the first and second detector modules are simultaneously connected to the input terminal of a control processing unit. The output terminal of the control processing unit and the four output terminals of the power divider module are simultaneously connected to the input terminal of a voltage-controlled attenuator. The output terminal of the voltage-controlled attenuator is connected to the input terminal of the RF power amplifier.

[0005] Preferably, the power divider module includes a first power divider, a second power divider, and a third power divider. The input terminal of the first power divider is connected to the input signal, the first output terminal of the first power divider is connected to the input terminal of the second power divider, the second output terminal of the first power divider is connected to the input terminal of the third power divider, the two output terminals of the second power divider are one output terminal and two output terminals respectively, and the two output terminals of the third power divider are three output terminals and four output terminals respectively.

[0006] Preferably, the first detection module includes a first detection circuit, which detects the output signal of the third power divider and converts the input radio frequency signal power into a voltage signal.

[0007] Preferably, the first detection circuit in the first detection module includes a chip U1, resistors R1, R3, R4, R5, R6, capacitors C1, C2, C3, C4, C5, C8, C9, C10, and connector J1. The input terminal of connector J1 is connected to the three output terminals of the power divider module. The output terminal of connector J1 is simultaneously connected to one end of capacitor C4 and one end of capacitor C5. The other end of capacitor C5 is grounded. The other end of capacitor C4 is simultaneously connected to one end of resistor R4 and pin 2 of chip U1. The other end of resistor R4 is simultaneously connected to one end of capacitor C8, one end of capacitor C9, and pin 4 of chip U1. The other end of the capacitor is connected to the other end of capacitor C9 and grounded. Pin 1 of the chip U1 is connected to one end of capacitor C3, one end of capacitor C2, one end of capacitor C1 and one end of resistor R1. The other ends of capacitor C3, capacitor C2 and capacitor C1 are all grounded. One end of resistor R3 is connected to pin 9 of chip U1 and the other end of resistor R3 is grounded. One end of resistor R5 is connected to pin 7 of chip U1. One end of resistor R6 is connected to pin 8 of chip U1 and the other end of resistor R5 is connected to the other end of resistor R6 and grounded. One end of capacitor C10 is connected to pin 6 of chip U1 and the input terminal of the control processing unit, and the other end of capacitor C10 is grounded.

[0008] Preferably, the chip U1 is an LTC5582 chip.

[0009] Preferably, the second detection module includes a second detection circuit, which detects the input signal of the third power divider and converts the input radio frequency signal power into a voltage signal. The second detection circuit and the first detection circuit use the same circuit.

[0010] Preferably, the signal receiving unit of the control processing unit has its input terminal connected to the output terminals of both the first and second detection modules. The output terminal of the signal receiving module is simultaneously connected to the input terminal of the differential component calculation unit and the input terminal of the real-time monitoring unit. The output terminal of the differential component calculation unit is simultaneously connected to the input terminal of the frequency calibration module, the input terminal of the storage module, and the input terminal of the real-time monitoring unit. The output terminal of the real-time monitoring unit is connected to the input terminal of the adjustment amount calculation unit. The input terminal of the adjustment amount calculation unit is also connected to the output terminal of the human-machine interaction unit. The voltage-controlled attenuation adjustment amount is calculated by the adjustment amount calculation unit, and the output terminal of the adjustment amount calculation unit is connected to the input terminal of the voltage-controlled attenuator via a digital-to-analog conversion unit.

[0011] An automatic equalization method for in-band gain ripple in a radio frequency power amplifier, implemented using the aforementioned automatic equalization circuit for in-band gain ripple in a radio frequency power amplifier, includes the following steps:

[0012] Step S1: The first detection module outputs signal V in1 The second detection module outputs signal V in2 The control processing unit receives signal V from the signal receiving unit. in1 and signal V in2 ;

[0013] Step S2: Calculate signal V using the differential component calculation unit. in1 and signal V in2 The difference component ΔV, that is, the signal V in1 and signal V in2 The input is fed into the subtractor, which outputs a difference component ΔV. The magnitude and polarity of the output difference component ΔV directly reflect the magnitude and direction of the deviation between the current frequency and the target frequency. Specifically, when ΔV = 0, it indicates that there is no error between the current frequency and the target frequency; when ΔV > 0, it indicates that the current frequency is higher or lower than the target frequency; and when ΔV < 0, it indicates that the direction of the current frequency is opposite to or deviates from the direction of the target frequency. The formula for calculating the difference component is ΔV = V in1 -V in2 ;

[0014] Step S3: Obtain the magnitude of the differential component ΔV through the frequency calibration module, lock the frequency of the input signal under the current differential component ΔV, establish the continuity relationship between the frequency of the input signal and the differential component ΔV, and obtain the monotonic relationship;

[0015] Step S4: Use a memory module to save the input signal P under the current differential component ΔV and the output power. Rfin The key value is generated and stored, that is, the difference component ΔV is used as the key, and the input signal P is used as the key. Rfin As a value, it forms a key value;

[0016] Step S5: Use the real-time monitoring unit to obtain the real-time change of the differential component ΔV, and use the adjustment calculation unit to calculate the voltage control attenuation adjustment amount;

[0017] Step S6: The voltage-controlled attenuation adjustment amount calculated by the adjustment amount calculation unit is converted into an analog signal and output to the voltage-controlled attenuator through the digital-to-analog conversion unit.

[0018] Preferably, in step S4, the input signal P Rfin The calculation process is as follows:

[0019] Given a signal with frequency Freq1, convert Freq1 into a difference component ΔV1 based on a monotonic relationship. The calculation formula is as follows:

[0020] ΔV1=a×Freq1+b

[0021] In the formula: a represents the slope of the line relating frequency and differential component within each interval of the differential component value, and b represents the intercept of the line relating frequency and differential component within each interval of the differential component value.

[0022] After calculating the differential component ΔV1, the input signal P is calculated based on the differential component ΔV1. Rfin1 The calculation formula is as follows:

[0023]

[0024] In the formula: c represents the slope of the straight line relating frequency to the amplitude of the input signal at rated power within each frequency interval, and d represents the intercept of the straight line relating frequency to the amplitude of the input signal at rated power within each frequency interval.

[0025] Preferably, the calculation formula for the adjustment amount in step S5 is as follows:

[0026] ;

[0027] In the formula: Offset represents the adjustment amount, P Rfin P represents the input signal. rated Indicates the rated power of the entire machine, G set This indicates the overall gain setting parameters.

[0028] Beneficial effects: This invention relates to an in-band gain ripple equalization circuit and equalization method for an RF power amplifier. Through an automatic equalization circuit, the gain ripple of the RF power amplifier in a wide bandwidth is controlled, thereby improving the performance of the product and controlling the in-band gain ripple of the finished product within a predetermined range. The over-input protection debugging of the RF power amplifier can be more comprehensive, reducing the risk of equipment damage due to over-input.

[0029] Secondly, the use of a voltage-controlled attenuator to automatically adjust the gain of each frequency point eliminates the influence of inconsistent in-band fluctuations of the same model of equipment due to device limitations, reduces the debugging complexity of broadband power amplifier equalizers, improves the compatibility of equalizers, facilitates mass production of equalizers, and improves production efficiency. Attached Figure Description

[0030] Figure 1 This is a system block diagram of the present invention;

[0031] Figure 2 This is a block diagram of the signal flow system of the present invention;

[0032] Figure 3This is a comparison chart of test data before and after calibration for the present invention;

[0033] Figure 4 This is a circuit diagram of the detector of the present invention;

[0034] Figure 5 This is a circuit diagram of the analog-to-digital conversion circuit of the present invention;

[0035] Figure 6 This is a circuit diagram of the voltage-controlled attenuation section of the present invention. Detailed Implementation

[0036] like Figures 1 to 6 As shown, this invention provides a technical solution: an automatic gain-band ripple equalization circuit for an RF power amplifier, comprising a power divider module, wherein the power divider module includes a first power divider, a second power divider, and a third power divider. The input terminal of the first power divider is connected to the input signal, the first output terminal of the first power divider is connected to the input terminal of the second power divider, the second output terminal of the first power divider is connected to the input terminal of the third power divider, the two output terminals of the second power divider are respectively a one-output terminal and a two-output terminal, the one-output terminal of the second power divider is connected to the load, the two output terminals of the second power divider are connected to the input terminal of an equalizer, the output terminal of the equalizer is connected to the input terminal of a second detector module, the two output terminals of the third power divider are respectively a three-output terminal and a four-output terminal, the three output terminals of the third power divider are connected to the input terminal of the first detector module, the output terminals of the first detector module and the second detector module are simultaneously connected to the input terminal of a control processing unit, the output terminal of the control processing unit and the four output terminals of the third power divider are simultaneously connected to the input terminal of a voltage-controlled attenuator, and the output terminal of the voltage-controlled attenuator is connected to the input terminal of the RF power amplifier. The specific circuit of the voltage-controlled attenuator is as follows: Figure 6 As shown, the first power divider splits the input signal into two signals with consistent gain and phase. Its purpose is to separate one signal for debugging without affecting the main signal. The second power divider eliminates the in-band insertion loss fluctuations and insertion loss effects of the third power divider, ensuring that the signals entering the first detector module and the equalizer maintain consistent amplitudes and that the differential component is always zero. The third power divider is used for signal splitting, with one path for monitoring the input signal magnitude and the other for the RF power amplifier input, facilitating data monitoring without affecting the main signal. A voltage-controlled attenuator is used to automatically adjust the gain at each frequency point, eliminating the influence of inconsistent in-band fluctuations of the same model of equipment due to device limitations. This reduces the debugging complexity of the broadband power amplifier equalizer, improves the compatibility of the equalizer, facilitates mass production of the equalizer, and increases production efficiency.

[0037] In a further embodiment, the first detection module includes a first detection circuit to detect the output signal of the third power divider and convert the input RF signal power into a voltage signal. The second detection module includes a second detection circuit to detect the output signal of the second power divider and convert the input RF signal power into a voltage signal. The second detection circuit and the first detection circuit use the same circuit. The first detection circuit in the first detection module includes a chip U1, resistors R1, R3, R4, R5, and R6, capacitors C1, C2, C3, C4, C5, C8, C9, and C10, and a connector J1. The input terminal of connector J1 is connected to the three output terminals of the power divider module, and the output terminal of connector J1 is simultaneously connected to one end of capacitor C4 and one end of capacitor C5. The other end of capacitor C5 is grounded. The other end of capacitor C4 is connected to one end of resistor R4 and pin 2 of chip U1. The other end of resistor R4 is connected to one end of capacitor C8, one end of capacitor C9 and pin 4 of chip U1. The other end of capacitor C8 is connected to the other end of capacitor C9 and grounded. Pin 1 of chip U1 is connected to one end of capacitor C3, one end of capacitor C2, one end of capacitor C1 and one end of resistor R1. The other ends of capacitor C3, capacitor C2 and capacitor C1 are all grounded. One end of resistor R3 is connected to pin 9 of chip U1 and the other end of resistor R3 is grounded. One end of resistor R5 is connected to pin 7 of chip U1. One end of resistor R6 is connected to pin 8 of chip U1 and the other end of resistor R5 is connected to the other end of resistor R6 and grounded. One end of capacitor C10 is connected to pin 6 of chip U1 and the input terminal of the control processing unit, and the other end of capacitor C10 is grounded.

[0038] In a further embodiment, the control processing unit is a signal receiving unit. The input of the signal receiving unit is simultaneously connected to the outputs of the first and second detection modules. The output of the signal receiving module is simultaneously connected to the input of the differential component calculation unit and the input of the real-time monitoring unit. The output of the differential component calculation unit is simultaneously connected to the input of the frequency calibration module, the input of the memory module, and the input of the real-time monitoring unit. The output of the real-time monitoring unit is connected to the input of the adjustment amount calculation unit. The input of the adjustment amount calculation unit is also connected to the output of the human-machine interaction unit. The voltage-controlled attenuation adjustment amount is calculated by the adjustment amount calculation unit. The output of the adjustment amount calculation unit is connected to the input of the voltage-controlled attenuator via a digital-to-analog converter unit. The specific circuit of the digital-to-analog converter unit is as follows: Figure 5 As shown, the input signal frequency is monitored in real time by the control processing unit, and the output power or gain of the whole machine is kept within a preset range by adjusting the voltage-controlled attenuator.

[0039] An automatic gain ripple equalization method for an RF power amplifier is disclosed. This method utilizes an automatic gain ripple equalization circuit as described above, initializes the device using host computer software, calibrates the rated power, and outputs a signal V through the first detection module. in1 The second detection module outputs signal V. in2 The signal receiving unit connected to the control processing unit receives signal V. in1 and signal V in2 By utilizing a continuous acquisition index retrieval method, calibration accuracy is improved and data volume is reduced, based on the frequency and V in the data. in1 and V in2 The linear relationship is calculated by the differential component calculation unit for signal V. in1 and signal V in2 The difference component ΔV, that is, the signal V in1 and signal V in2 The input is fed into the subtractor, which outputs a difference component ΔV. The magnitude and polarity of the output difference component ΔV directly reflect the magnitude and direction of the deviation between the current frequency and the target frequency. Specifically, when ΔV = 0, it indicates that there is no error between the current frequency and the target frequency; when ΔV > 0, it indicates that the current frequency is higher or lower than the target frequency; and when ΔV < 0, it indicates that the direction of the current frequency is opposite to or deviates from the direction of the target frequency. The formula for calculating the difference component is ΔV = V in1 -V in2 The magnitude of the differential component ΔV is obtained through the frequency calibration module, the frequency of the input signal under the current differential component ΔV is locked, the continuity relationship between the frequency of the input signal and the differential component ΔV is established, and the monotonic relationship is obtained.

[0040] Then, the input signal P at the current differential component ΔV and output power is saved using a memory module. Rfin The key value is generated and stored, that is, the difference component ΔV is used as the key, and the input signal P is used as the key. Rfin As a value, the key value is formed, where the input signal P Rfin The calculation process is as follows:

[0041] Given a signal with frequency Freq1, convert Freq1 into a difference component ΔV1 based on a monotonic relationship. The calculation formula is as follows:

[0042] ΔV1=a×Freq1+b

[0043] In the formula: a represents the slope of the line relating frequency and differential component within each interval of the differential component value, and b represents the intercept of the line relating frequency and differential component within each interval of the differential component value. The slope a and intercept b of the line are different between each cell. The calibration will sample two points in each interval, and the line between the two points will determine the slope a and intercept b of the line in this interval. In actual use, the slope a and intercept b of the line in the corresponding interval will be indexed through the interval where the differential component value is located.

[0044] After calculating the differential component ΔV1, the input signal P is calculated based on the differential component ΔV1. Rfin1 The calculation formula is as follows:

[0045]

[0046] In the formula: c represents the slope of the straight line relating frequency to the amplitude of the input signal at rated power within each frequency interval, and d represents the intercept of the straight line relating frequency to the amplitude of the input signal at rated power within each frequency interval. The slope c and intercept d are different between each cell. Calibration involves sampling two points within each cell, and the line drawn from these two points determines the slope c and intercept d of the straight line within that cell. In practical use, the slope c and intercept d of the straight line in the relevant interval are indexed through the smaller interval where the frequency is located, and P can be calculated from this. Rfin During calibration, the current frequency information can be obtained through software. However, in actual use, without connecting to a host computer, the signal frequency information cannot be obtained. Therefore, Freq must first be calculated using a formula, and then P must be calculated. Rfin The real-time change of the differential component ΔV is obtained through the real-time monitoring unit, and the voltage control attenuation adjustment is calculated in conjunction with the adjustment calculation unit. The calculation formula for the adjustment is as follows:

[0047] ;

[0048] In the formula: Offset represents the adjustment amount, P Rfin P represents the input signal. rated Indicates the rated power of the entire machine, G set This indicates the overall gain setting parameters.

[0049] The voltage-controlled attenuation adjustment value calculated by the adjustment calculation unit is converted into an analog signal and output to the voltage-controlled attenuator (VCO) through a digital-to-analog converter (DAC). This controls the attenuation of the VCO, thereby controlling the overall gain of the device. The attenuation error depends on the minimum step size (LSB) of the VCO. To meet the minimum gain requirement, the VCO must be controlled to produce a negative deviation, meaning the attenuation is less than the actual required attenuation. Figure 3 As shown, the gain band fluctuation of the RF power amplifier at rated power is significantly improved after recalibration.

[0050] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A radio frequency power amplifier gain in-band fluctuation automatic equalization circuit, characterized by, The power splitter module includes a first power splitter, a second power splitter and a third power splitter, the input end of the first power splitter is connected with the input signal, the first output end of the first power splitter is connected with the input end of the second power splitter, the second output end of the first power splitter is connected with the input end of the third power splitter, the two output ends of the second power splitter are respectively a one-way output end and a two-way output end, and the two output ends of the third power splitter are respectively a three-way output end and a four-way output end.

2. A gain in-band fluctuation automatic equalization circuit for a radio frequency power amplifier as recited in claim 1, characterized by, The first detection module includes a first detection circuit, and the first detection circuit is used for detecting the output signal of the third power splitter and converting the input radio frequency signal power into a voltage signal.

3. A gain in-band fluctuation auto-equalization circuit for a radio frequency power amplifier as recited in claim 2, wherein, The first detection circuit in the first detection module includes a chip U1, resistors R1, R3, R4, R5, R6, capacitors C1, C2, C3, C4, C5, C8, C9, C10 and a connector J1, the input end of the connector J1 is connected with the three-way output end of the power splitter module, the output end of the connector J1 is connected with one end of the capacitor C4 and one end of the capacitor C5, the other end of the capacitor C5 is grounded, the other end of the capacitor C4 is connected with one end of the resistor R4 and a pin 2 of the chip U1, the other end of the resistor R4 is connected with one end of the capacitor C8, one end of the capacitor C9 and a pin 4 of the chip U1, the other end of the capacitor C8 is connected with the other end of the capacitor C9 and grounded, a pin 1 of the chip U1 is connected with one end of the capacitor C3, one end of the capacitor C2, one end of the capacitor C1 and one end of the resistor R1, the other end of the capacitor C3, the other end of the capacitor C2 and the other end of the capacitor C1 are grounded, one end of the resistor R3 is connected with a pin 9 of the chip U1, the other end of the resistor R3 is grounded, one end of the resistor R5 is connected with a pin 7 of the chip U1, one end of the resistor R6 is connected with a pin 8 of the chip U1, the other end of the resistor R5 is connected with the other end of the resistor R6 and grounded, one end of the capacitor C10 is connected with a pin 6 of the chip U1 and the input end of the control processing unit, and the other end of the capacitor C10 is grounded.

4. A gain in-band fluctuation auto-equalization circuit for a radio frequency power amplifier as recited in claim 3, wherein, The chip U1 is an LTC5582 chip.

5. A gain in-band fluctuation auto-equalization circuit for a radio frequency power amplifier as recited in claim 4, wherein, The second detection module comprises a second detection circuit, which detects the output signal of the second power divider and converts the input radio frequency signal power into a voltage signal.

6. A gain in-band fluctuation automatic equalizer circuit for a radio frequency power amplifier as recited in claim 1, wherein, The control processing unit comprises a signal receiving unit, the input end of the signal receiving unit being connected to the output end of the first detection module and the output end of the second detection module, the output end of the signal receiving unit being connected to the input end of the differential component calculation unit and the input end of the real-time monitoring unit, the output end of the differential component calculation unit being connected to the input end of the frequency calibration module, the input end of the storage module and the input end of the real-time monitoring unit, the output end of the real-time monitoring unit being connected to the input end of the adjustment amount calculation unit, the input end of the adjustment amount calculation unit being further connected to the output end of the man-machine interaction unit, the voltage-controlled attenuation adjustment amount being calculated by the adjustment amount calculation unit, and the output end of the adjustment amount calculation unit being connected to the input end of the voltage-controlled attenuator through the digital-analog conversion unit.

7. A method for automatic equalization of gain in-band fluctuations of a radio frequency power amplifier, characterized in that, The gain in-band fluctuation automatic equalization circuit of the radio frequency power amplifier is realized by the method of any one of claims 1-6, comprising the following steps: Step S1, the first detection module output signal V in1 , the second detection module output signal V in2 , the control processing unit in the signal receiving unit receives signal V in1 and signal V in2 ; Step S2, calculate the difference component AV of the signal V in1 and the signal V in2 , that is, input the signal V in1 and the signal V in2 into a subtracter, output the difference component AV, the size and polarity of the output difference component AV directly reflect the deviation size and direction between the current frequency and the target frequency, that is, when the difference component AV=0, it means that there is no error between the current frequency and the target frequency, when the difference component AV>0, it means that the current frequency is higher or lower than the target frequency, when the difference component AV<0, it means that the direction of the current frequency is opposite or deviates from the direction of the target frequency, wherein the calculation formula of the difference component is AV=V in1 -V in2 ; In step S3, the frequency calibration module is used to obtain the size of the differential component AV, the frequency of the input signal under the current differential component AV is locked, the continuity relationship between the frequency of the input signal and the differential component AV is established, and a monotonic relationship is obtained. Step S4, saving the input signal P at the output power under the current difference amount AV by using the storage model Rfin , forming a key value for saving, i.e. the difference amount AV as a key, the input signal P Rfin as a value to form a key value; In step S5, the real-time monitoring unit is used to obtain the real-time change of the differential component AV, and the voltage-controlled attenuation adjustment amount is calculated by the adjustment amount calculation unit. In step S6, the voltage-controlled attenuation adjustment amount calculated by the adjustment amount calculation unit is converted into an analog signal by the digital-analog conversion unit and output to the voltage-controlled attenuator.

8. A method for automatic equalization of gain in-band fluctuations of a radio frequency power amplifier according to claim 7, characterized in that, The input signal P in step S4 Rfin The calculation process is as follows: The frequency Freq1 of an input signal is converted into the differential component AV1 according to the monotonic relationship, and the calculation formula is as follows: ΔV1=a×Freq1+b In the formula, a represents the slope of the straight line between the frequency and the differential component in each interval of the differential component value, and b represents the intercept of the straight line between the frequency and the differential component in each interval of the differential component value. After the calculation of the difference component AV1 is completed, the input signal P Rfin1 is calculated based on the difference component AV1, and the calculation formula is as follows: ； In the formula, c represents the slope of the straight line between the frequency and the input signal amplitude under the rated power in each interval of the frequency, and d represents the intercept of the straight line between the frequency and the input signal amplitude under the rated power in each interval of the frequency.

9. A method for automatic equalization of gain in-band fluctuations of a radio frequency power amplifier according to claim 7, characterized in that, The calculation formula of the voltage-controlled attenuation adjustment amount in step S5 is as follows: ； In the formula, Offset represents the voltage-controlled attenuation adjustment amount, P Rfin represents the input signal, P rated represents the whole machine rated power, G set represents the whole machine gain setting parameter.

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