Mask pattern generation method, mask, semiconductor structure and manufacturing method thereof

Abstract

The invention provides a mask pattern generation method, a mask, a semiconductor structure and a manufacturing method thereof. The mask pattern generation method comprises the following steps: acquiring a mask pattern template comprising a cutting channel region and a reference mark pattern comprising a graphic pattern; the reference mark pattern is divided into a plurality of reference mark areas; extracting contours of partial graphic patterns in each reference mark area by using the auxiliary graphs to obtain a plurality of auxiliary mark patterns, and arranging the auxiliary mark patterns in the cutting channel area; and respectively intercepting a part of the graphic pattern in each reference mark area to obtain a plurality of local mark patterns, and arranging the local mark patterns at the positions of the corresponding auxiliary mark patterns in the cutting channel area to obtain a target mask pattern, the plurality of local mark patterns transferred to the semiconductor structure are combined into an alignment mark pattern matched with the graphic pattern in the cutting channel of the semiconductor structure. According to the embodiment of the invention, the alignment precision in the processing process of the packaging technology is improved.

Description

TECHNICAL FIELD

[0001] Embodiments in the present application relate to the technical field of semiconductor manufacturing, and in particular to a mask pattern generation method, a mask, a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] In a semiconductor manufacturing process, after chip fabrication is completed on a wafer surface, the wafer needs to be processed by a packaging process. Specifically, the packaging process can include multiple process procedures such as plating, cutting, packaging, testing, etc. Among them, plating can refer to depositing a protective or functional film on the wafer surface to achieve physical protection of the chip. Packaging can refer to, after cutting the semiconductor structure into multiple chips, performing lead connection, mounting to a packaging substrate, setting a protective shell, etc. on each chip to achieve electrical interconnection between multiple chips and chip performance optimization.

[0003] To improve the process quality of each process procedure in the packaging process, alignment marks need to be set on the wafer to improve alignment accuracy. Chip target marks (CTM) have been widely used in the packaging process due to their advantages in size, symmetry, etc.

[0004] However, researchers have found in actual packaging process that the alignment accuracy is low when using the chip target mark provided by the prior art as an alignment reference for alignment. SUMMARY

[0005] Therefore, embodiments of the present application provide a mask pattern generation method, a mask, a semiconductor structure and a manufacturing method thereof to improve the alignment accuracy when using a chip target mark as an alignment reference for alignment.

[0006] In one aspect, one embodiment of the present application provides a method for generating a mask pattern, applied to a mask pattern design system; the method for generating the mask pattern comprises: obtaining a mask pattern template and a reference mark pattern; wherein the mask pattern template comprises a chip region and a scribe lane region surrounding the chip region; the reference mark pattern comprises a figure pattern and a background pattern; the reference mark pattern is divided into a plurality of non-overlapping reference mark regions; each of the reference mark regions contains part of the figure pattern and part of the background pattern; an outline of part of the figure pattern located in each of the reference mark regions is extracted by using an auxiliary figure to obtain a plurality of auxiliary mark patterns, and the plurality of auxiliary mark patterns are laid out in the scribe lane region; wherein the number of the auxiliary mark patterns is the same as the number of the reference mark regions; part of the figure pattern located in each of the reference mark regions is cut off to obtain a plurality of local mark patterns, and each of the local mark patterns is laid out at the position of the corresponding auxiliary mark pattern in the scribe lane region to obtain a target mask pattern, so that in the process of manufacturing a semiconductor structure according to the target mask pattern, a plurality of the local mark patterns transferred to the semiconductor structure are combined into an alignment mark pattern matching the figure pattern in the scribe lane of the semiconductor structure.

[0007] Optionally, the laying out of the plurality of auxiliary mark patterns in the scribe lane region comprises: laying out the plurality of auxiliary mark patterns in the scribe lane region at corners of the mask pattern template; wherein each of the auxiliary mark patterns is arranged on one side of the center line of the scribe lane region close to the chip region, and at least part of the boundary is fitted to the center line of the scribe lane region.

[0008] Optionally, after the plurality of auxiliary mark patterns are laid out in the scribe lane region, the method for generating the mask pattern further comprises: corresponding to the plurality of auxiliary mark patterns, laying out a plurality of protection mark patterns in the scribe lane region at corners of the mask pattern template to obtain a target mask pattern; wherein each of the protection mark patterns is arranged on one side of the center line of the scribe lane region away from the chip region, and at least covers a region defined by the following boundaries: a corner vertex of the mask pattern template, a first boundary of the auxiliary mark pattern, and an extension line formed by reversely extending a second boundary of the auxiliary mark pattern along a normal direction of the center line of the scribe lane region; the first boundary of the auxiliary mark pattern is a part of the boundary of the auxiliary mark pattern fitted to the center line of the scribe lane region; the second boundary of the auxiliary mark pattern is a part of the boundary of the auxiliary mark pattern extended along the normal direction of the center line of the scribe lane region.

[0009] Optionally, in the target mask pattern, the light transmittance of the protection mark pattern and the local mark pattern are different; wherein the light transmittance of the protection mark pattern is 0.

[0010] Optionally, the graphic pattern comprises a first sub-graphic pattern and a second sub-graphic pattern with the same contour shape; the first sub-graphic pattern and the second sub-graphic pattern respectively extend along a first direction and a second direction perpendicular to each other; wherein the length of the first sub-graphic pattern extending along the first direction is less than the length of the second sub-graphic pattern extending along the first direction, and the length of the first sub-graphic pattern extending along the second direction is less than the length of the second sub-graphic pattern extending along the second direction.

[0011] Optionally, the contour of the part of the graphic pattern located in each reference mark region is extracted by using an auxiliary graphic to obtain a plurality of auxiliary mark patterns, comprising: the contour of the part of the second sub-graphic pattern located in each reference mark region is extracted by using at least two auxiliary graphics arranged adjacent to each other to obtain a plurality of auxiliary mark patterns; wherein the auxiliary graphic is a rectangle.

[0012] Optionally, the part of the graphic pattern located in each reference mark region is cut respectively to obtain a plurality of local mark patterns, and each local mark pattern is arranged at the position of the corresponding auxiliary mark pattern in the cutting track region to obtain a target mask pattern, comprising: the part of the first sub-graphic pattern located in each reference mark region is cut respectively to obtain a plurality of first sub-graphic local mark patterns, and each first sub-graphic local mark pattern is arranged at the position of the corresponding auxiliary mark pattern in the cutting track region to obtain a first target mask pattern; the part of the second sub-graphic pattern located in each reference mark region is cut respectively to obtain a plurality of second sub-graphic local mark patterns, and each second sub-graphic local mark pattern is arranged at the position of the corresponding auxiliary mark pattern in the cutting track region to obtain a second target mask pattern; in the process of manufacturing a semiconductor structure according to the target mask pattern, the first target mask pattern and the second target mask pattern are transferred to different material layers of the semiconductor structure respectively.

[0013] In another aspect, one embodiment of the present application provides a mask manufactured based on a target mask pattern generated by the generation method of the mask pattern as described in the above embodiment; in the process of manufacturing a semiconductor structure according to the mask, a plurality of local mark patterns transferred to the semiconductor structure are combined into an alignment mark pattern matching the graphic pattern in the cutting track of the semiconductor structure.

[0014] In yet another aspect, one embodiment of the present application provides a semiconductor structure manufactured according to the target mask pattern generated by the method for generating a mask pattern as described above, or manufactured according to the mask as described above; a plurality of the local mark patterns transferred to the semiconductor structure are combined into an alignment mark pattern matching the graphic pattern in the scribe lane of the semiconductor structure.

[0015] In yet another aspect, one embodiment of the present application provides a method for manufacturing a semiconductor structure according to the target mask pattern generated by the method for generating a mask pattern as described above, or according to the mask as described above; the method for manufacturing a semiconductor structure comprises: transferring a plurality of the local mark patterns to the scribe lane of the semiconductor structure respectively by using a multiple-exposure process, so that the plurality of the local mark patterns are combined into an alignment mark pattern matching the graphic pattern in the scribe lane of the semiconductor structure.

[0016] In the embodiments of the present application, by obtaining a mask pattern template comprising a chip region and a scribe lane region, and a reference mark pattern divided into a plurality of reference mark regions, wherein each reference mark region contains a partial graphic pattern and a partial background pattern, subsequently extracting the contour of the partial graphic pattern in each reference mark region by using an auxiliary graphic to obtain a plurality of auxiliary mark patterns, and laying out the plurality of auxiliary mark patterns in the scribe lane region, then intercepting the partial graphic pattern in each reference mark region respectively to obtain a plurality of local mark patterns, and laying out each local mark pattern at the position of the corresponding auxiliary mark pattern in the scribe lane region to obtain a target mask pattern, so that in the process of manufacturing a semiconductor structure according to the target mask pattern, the plurality of local mark patterns transferred to the semiconductor structure are combined into an alignment mark pattern matching the graphic pattern in the scribe lane of the semiconductor structure, the unexpected effects achieved include: since the auxiliary mark pattern is obtained by extracting the contour of the graphic pattern, and the local mark pattern is obtained by intercepting the graphic pattern, therefore, the local transfer and recombination of the graphic pattern can be achieved without splitting the complete graphic data of the reference mark pattern, so that the alignment mark pattern formed by combination has the complete graphic features of the reference mark pattern, thereby improving the alignment accuracy in the packaging process. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed for describing the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0018] Figure 1 A schematic diagram of a first chip target mark pattern provided for the related art.

[0019] Figure 2 A schematic diagram of a second chip target mark pattern provided for the related art.

[0020] Figure 3 A schematic diagram of a chip target mark pattern size greater than a street region size provided for the related art.

[0021] Figure 4 A schematic diagram of splitting a chip target mark pattern provided for the related art.

[0022] Figure 5 A schematic diagram of disposing a split chip target mark pattern in a street region provided for the related art.

[0023] Figure 6 A schematic diagram of a flowchart of a mask pattern generation method provided for an embodiment of the present application.

[0024] Figure 7 A schematic diagram of a reference mark pattern provided for an embodiment of the present application.

[0025] Figure 8 A schematic diagram of extracting a partial pattern outline using an auxiliary pattern provided for an embodiment of the present application.

[0026] Figure 9 A schematic diagram of disposing a plurality of auxiliary mark patterns in a street region provided for an embodiment of the present application.

[0027] Figure 10 A schematic diagram of disposing a plurality of protection mark patterns in a street region provided for an embodiment of the present application.

[0028] Figure 11 A schematic diagram of respectively intercepting a partial first sub-pattern provided for an embodiment of the present application.

[0029] Figure 12 A schematic diagram of a first sub-pattern local mark pattern provided for an embodiment of the present application.

[0030] Figure 13 A schematic diagram of respectively intercepting a partial second sub-pattern provided for an embodiment of the present application.

[0031] Figure 14 A schematic diagram of a second sub-pattern local mark pattern provided for an embodiment of the present application.

[0032] Figure 15A schematic view of a plurality of first sub-pattern local mark patterns corresponding to a plurality of second sub-pattern local mark patterns according to an embodiment of the present application.

[0033] Figure 16 A schematic view of a plurality of first sub-pattern local mark patterns corresponding to a plurality of second sub-pattern local mark patterns according to an embodiment of the present application.

[0034] Figure 17 A schematic view of a plurality of local mark patterns combined into a alignment mark pattern in a scribe lane of a semiconductor structure according to an embodiment of the present application.

[0035] Structure label explanation 100, first chip target mark pattern; 100a, second chip target mark pattern; 101, first top metal layer mark pattern; 102, first passivation protection layer mark pattern; 101a, second top metal layer mark pattern; 102a, second passivation protection layer mark pattern; 110, first split mark pattern; 120, second split mark pattern; 130, third split mark pattern; 200, mask pattern template; 210, chip region; 211, chip pattern; 212, split lane region; 220, scribe lane region; 221, center line of scribe lane region; 300, reference mark pattern; 301, first sub-pattern; 302, second sub-pattern; 310, first reference mark region; 320, second reference mark region; 330, third reference mark region; 340, fourth reference mark region; 400, auxiliary mark pattern; 410, first auxiliary pattern; 420, second auxiliary pattern; 500, protection mark pattern; 600, first sub-pattern local mark pattern; 610, first extension; 620, second extension; 700, second sub-pattern local mark pattern; 710, third extension; 720, fourth extension; 800, alignment mark pattern; 801, first sub-alignment mark pattern; 802, second sub-alignment mark pattern; 900, scribe lane of semiconductor structure. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all embodiments of the present application.

[0037] The drawings provided in the embodiments of the present application only schematically illustrate the basic concepts of the present application, and only show the components related to the present application in the drawings, not drawn according to the number, shape and size of the components when actually implemented. The shape, number and proportion of each part can be changed when actually implemented, and the component layout form can also be more complex.

[0038] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "center" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application, and do not indicate or imply that the device or component referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. The terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features.

[0039] To realize high-density integration of semiconductor devices, the alignment accuracy of each link in the production of semiconductor devices is continuously improved. Chip target marks, which are widely used in packaging process treatment to improve the speed and accuracy of mark recognition system to recognize alignment marks, are widely used in packaging process treatment due to their large size and symmetrical arrangement in each direction. To determine the alignment reference in the film plating, packaging and other process execution in the packaging process, in related technologies, for each single exposure coverage area (Shot) on the surface of the semiconductor structure, chip target marks need to be made on the exposed top metal (TM) layer on the surface of the semiconductor structure before the film plating process is executed, and chip target marks need to be made on the passivation (PV) protective layer formed based on the film plating process after the film plating process is executed.

[0040] Chip target marks can be made based on chip target mark patterns in a mask pattern. To improve the alignment accuracy between different material layers, the size and / or shape of the chip target marks formed on the top metal layer are different from the chip target marks formed on the passivation protective layer. Accordingly, in the chip target mark pattern provided in related technologies, the mark patterns of the chip target marks corresponding to different material layers are different.

[0041] Please refer to Figure 1 and Figure 2For example, taking the first chip target mark pattern 100 and the second chip target mark pattern 100a provided by the related art as an example. In the first chip target mark pattern 100, the first top metal layer mark pattern 101 and the first passivation layer mark pattern 102 have the same shape and different sizes, that is, the size of the first top metal layer mark pattern 101 is smaller than the size of the first passivation layer mark pattern 102. In the second chip target mark pattern 100a, the second top metal layer mark pattern 101a and the second passivation layer mark pattern 102a have different sizes and shapes, that is, the size of the second top metal layer mark pattern 101a is smaller than the size of the second passivation layer mark pattern 102a, and the second top metal layer mark pattern 101a is additionally provided with a plurality of triangles for improving the alignment accuracy with respect to the second passivation layer mark pattern 102a.

[0042] For reference Figures 1 to 3 The mask pattern containing the chip target mark pattern can be made based on the mask pattern template 200. Specifically, the mask pattern template 200 can include a chip area 210 and a cutting path area 220 surrounding the chip area 210. Among them, inside the chip area 210, a separation path area 212 is formed between adjacent chip patterns 211. In order to reduce the reduction of alignment accuracy caused by damage to the chip target mark during the cutting of the chip, in the related art, during the process of designing the mask pattern template 200 based on the chip target mark pattern, researchers usually set the chip target mark pattern as a whole in the separation path area 212 to maintain the integrity of the chip target mark pattern structure. However, in the actual design process of the mask pattern template 200, researchers found that the chip target mark pattern cannot be set in the separation path area 212, and the specific reasons are analyzed as follows.

[0043] The chip target mark pattern has a length direction and a width direction perpendicular to each other. Since the overall size of the chip target mark pattern is calculated according to the maximum length X of the pattern along the length direction and the maximum width Y of the pattern along the width direction, taking the first chip target mark pattern 100 and the second chip target mark pattern 100a as an example, the size of the two chip target mark patterns is X Y. However, in the mask pattern template 200, along the length direction, the size of the separation path area 212 is X1, and X1

[0044] At this time, if the chip target mark pattern is directly set as a whole in the scribe lane area 212, the chip target mark pattern will overlap with the chip pattern 211. If the chip is manufactured based on the mask pattern template 200 in which the chip target mark pattern partially overlaps with the chip pattern 211, the chip area 210 can be damaged, the chip function and production yield can be affected, or the formed chip target mark can be incomplete and the alignment accuracy can be reduced. If the layout of the original chip pattern 211 on the mask pattern template 200 is modified to keep the chip target mark pattern complete, the area occupied by the scribe lane area 212 can be increased, thereby reducing the number of chips that can be accommodated on the semiconductor structure and reducing the production efficiency.

[0045] To solve the problem of overlap between the chip target mark pattern and the chip pattern, researchers try to split the design file of the chip target mark pattern, i.e., the GDS (Geometric Design System) format file. The specific splitting process is as follows.

[0046] Please refer to Figure 1 , Figure 4 and Figure 5 . Taking the first chip target mark pattern 100 as an example, in the first chip target mark pattern 100, the first top metal layer mark pattern 101 and the first passivation layer mark pattern 102 are both formed by two rectangles intersecting and overlapping along the length direction and the width direction. Researchers split the GDS file corresponding to the first chip target mark pattern 100 into three parts according to the shape characteristics of the first chip target mark pattern 100, forming a first split mark pattern 110, a second split mark pattern 120, and a third split mark pattern 130. Among them, along the length direction, the size of the first split mark pattern 110 and the third split mark pattern 130 is smaller than the size X1 of the scribe lane area 212; along the width direction, the size of the second split mark pattern 120 is smaller than the size Y1 of the scribe lane area 212. Then, the researchers set the first split mark pattern 110, the second split mark pattern 120, and the third split mark pattern 130 in the scribe lane area 212 according to the shape of the chip target mark pattern, so that the three split mark patterns are spliced into the shape of the complete chip target mark pattern, thereby solving the problem of overlap between the complete chip target mark pattern and the chip pattern.

[0047] In addition, in the process of transferring the complete chip target mark pattern to different material layers on the surface of the semiconductor structure, researchers can determine the coordinates of the complete chip target mark pattern based on the mask pattern template coordinate system, so that the chip target mark pattern is formed at the preset position of each material layer on the surface of the semiconductor structure. Among them, the mask pattern template coordinate system takes the center of the mask pattern template 200 as the coordinate origin.

[0048] After the complete chip target mark pattern is set in the split lane area 212 through the above splitting and splicing process, a mask is manufactured according to the obtained output mask pattern template, and the mask is applied to the actual photolithography process, and the researchers find that the alignment accuracy is low in the process of alignment based on the chip target mark manufactured by the chip target mark pattern formed by splitting and splicing, and it is difficult to meet the alignment accuracy requirement of the high-precision process node.

[0049] Further exploration of the reason why the above splitting and splicing process leads to low alignment accuracy based on the chip target mark shows that in the chip target mark pattern formed by splicing, the continuity of the pattern at the splicing boundary position is destroyed, and there is a small position offset and deformation accumulation in the photolithography transfer process of each split mark pattern, thereby causing the actual chip target mark pattern formed in the split lane area 212 to deviate from the design pattern of the chip target mark, and sub-micron alignment accuracy cannot be achieved.

[0050] Therefore, it is necessary to provide a mask pattern generation method which can form a complete chip target mark pattern in a mask pattern template without splitting the GDS file of the chip target mark pattern, and the chip target mark pattern does not overlap with the chip pattern.

[0051] Please refer to Figure 6 An embodiment of the present application provides a mask pattern generation method. The mask pattern generation method can be applied to a mask pattern design system. Specifically, the mask pattern design system can be a computer-aided design platform for generating mask pattern data required for a photolithography process. For example, the mask pattern design system can include a design data input and management module, a design pattern editing module, a design rule checking and verification module, and a design data integration and output module, etc. The mask pattern generation method can include steps S110, S120 and S130.

[0052] S110: Obtain a mask pattern template and a reference mark pattern.

[0053] In order to reduce the risk of alignment accuracy reduction caused by splitting the GDS file of the reference mark pattern under the condition that the reference mark pattern does not overlap with the chip pattern, the design pattern editing module in the mask pattern design system can be used to divide the reference mark pattern in the pattern editing window (Window) first, and then process each part of the reference mark pattern data obtained by division.

[0054] Please continue to refer to Figure 5In the embodiment, the mask pattern template (Frame) 200 can be a basic graphic structure defining a mask pattern layout frame. Specifically, the mask pattern template 200 provided by the embodiment of the present application is similar to the mask pattern template 200 provided by the related art. The mask pattern template 200 can be stored in GDSII format or OASIS format. The mask pattern template 200 can include a chip region 210 and a scribe lane region 220. The chip region 210 can be used to form a functional circuit of a semiconductor device. The chip region 210 can include a plurality of spaced-apart chip patterns 211 and a scribe lane region 212 between adjacent chip patterns 211. The chip pattern 211 can include a design pattern for manufacturing a circuit structure such as a transistor, an interconnection line, and a contact hole. The scribe lane region 212 can be a blank region without a circuit structure. The mask pattern template 200 can define arrangement of the plurality of chip patterns 211, size parameters of the chip pattern 211, width parameters of the scribe lane region 212, and size parameters of the chip region 210 as a whole. The scribe lane region 220 can be a blank region around the chip region 210 without a circuit structure, and can be used to set a process monitoring structure, an alignment mark, and a dicing groove, etc., and to determine a position for cutting a semiconductor structure to separate individual chips after the chip manufacturing is completed. The mask pattern template 200 can define width parameters of the scribe lane region 220 and the like.

[0055] Referring to Figure 7 In the embodiment, the reference mark pattern 300 can be a design pattern of an alignment mark. Specifically, the reference mark pattern 300 can be a chip target mark pattern. For example, similar to the packaging process in the related art, after the functional circuit of a semiconductor device on a semiconductor structure surface is manufactured, a graphic pattern in the reference mark pattern 300 is transferred to an exposed top metal layer and a passivation layer deposited on the top metal layer to form an alignment mark as a reference for performing a plating process, a packaging process, and the like.

[0056] In the embodiment, the reference mark pattern 300 can include a graphic pattern and a background pattern. The graphic pattern can be used to form an alignment mark. Specifically, the graphic pattern can include a first sub-graphic pattern 301 and a second sub-graphic pattern 302 having the same contour shape. The first sub-graphic pattern 301 can correspond to an alignment mark formed on a top metal layer, and the second sub-graphic pattern 302 can correspond to an alignment mark formed on a passivation layer.

[0057] To reduce the difficulty of alignment, in the embodiment, the first sub-pattern 301 and the second sub-pattern 302 can be symmetrical along a first direction A and symmetrical along a second direction B perpendicular to the first direction A. Specifically, the first sub-pattern 301 and the second sub-pattern 302 can each be in a “cross shape”, i.e., the first sub-pattern 301 and the second sub-pattern 302 can each be formed by the intersection of two rectangles extending along the first direction A and the second direction B, respectively. Since the passivation protective layer covers the top metal layer, to improve the overlay accuracy during the packaging process, the length of the first sub-pattern 301 extending along the first direction A is less than the length of the second sub-pattern 302 extending along the first direction A, and the length of the first sub-pattern 301 extending along the second direction B is less than the length of the second sub-pattern 302 extending along the second direction B, i.e., the size of the first sub-pattern 301 is less than the size of the second sub-pattern 302. The background pattern can be a part of the reference mark pattern 300 other than the pattern. Specifically, the background pattern can be a single-color filled area. For example, the fill color can be white.

[0058] In the embodiment, to obtain the mask pattern template and the reference mark pattern, the design data of the mask pattern template 200 and the design data of the reference mark pattern 300 provided by the mask pattern designer in the GDS format can be imported into a design data input and management module of a mask pattern design system, and the two design data can be format-converted by the design data input and management module so that the two design data can be presented in the form of images in a pattern editing window of a design pattern editing module of the mask pattern design system, and various pattern editing operations on the mask pattern template 200 and the reference mark pattern 300 can be completed in the pattern editing window.

[0059] To remove the background pattern in the reference mark pattern 300 and transfer only the pattern into the mask pattern template 200 to reduce the overlap between the reference mark pattern 300 and the chip pattern 211 in the chip region 210, in the embodiment, the reference mark pattern 300 can be divided into a plurality of non-overlapping reference mark regions. Specifically, the design pattern editing module in the mask pattern design system can be used to perform a pattern division (Monitor) operation to equally divide the reference mark pattern 300 presented in the pattern editing window into a plurality of reference mark regions, so that each reference mark region contains part of the pattern and part of the background pattern without affecting the GDS file of the reference mark pattern 300. For example, the reference mark pattern 300 can be divided into four reference mark regions, i.e., a first reference mark region 310, a second reference mark region 320, a third reference mark region 330, and a fourth reference mark region 340, along the center line of the reference mark pattern 300 in the first direction A and the center line of the reference mark pattern 300 in the second direction B.

[0060] S120: extracting the contour of the partial pattern of the graphic pattern in each reference mark region by using the auxiliary graphic, obtaining a plurality of auxiliary mark patterns, and arranging the plurality of auxiliary mark patterns in the cutting track region.

[0061] In order to enable the graphic pattern to be completely transferred to the surface of the semiconductor structure, for each reference mark region obtained by dividing the reference mark pattern, the contour of the partial graphic pattern therein can be extracted by using the auxiliary graphic, and the extracted partial graphic pattern can be used to occupy the cutting track region of the mask pattern template, thereby providing a position reference for the subsequent arrangement of the local mark pattern in the mask pattern template.

[0062] In the embodiment, the auxiliary graphic can be used to define the range of the pattern contour to be extracted. Specifically, in order to retain the actual contour of the partial graphic pattern in each reference mark region while removing the background pattern, the auxiliary graphic can be a rectangle.

[0063] Please refer to Figure 5 , Figure 7 and Figure 8 . Since the size of the first sub-graphic pattern 301 is smaller than the size of the second sub-graphic pattern 302, the size of the partial first sub-graphic pattern 301 in each reference mark region is smaller than the size of the second sub-graphic pattern 302 in each reference mark region. In order to make the position occupied by the auxiliary mark pattern 400 in the mask pattern template 200 suitable for the local mark pattern obtained by intercepting different sub-graphic patterns, in the embodiment, the contour of the partial graphic pattern in each reference mark region is extracted by using the auxiliary graphic to obtain a plurality of auxiliary mark patterns, which can include: the contour of the partial second sub-graphic pattern in each reference mark region is extracted by using at least two auxiliary graphics arranged adjacent to each other to obtain a plurality of auxiliary mark patterns. Specifically, in the pattern editing window, the contour of the partial second sub-graphic pattern in each reference mark region can be used to define the boundary of the auxiliary mark pattern by using the auxiliary graphic, thereby obtaining the auxiliary mark pattern.

[0064] As can be known from the forming process of the auxiliary mark pattern 400, in the present embodiment, the number of the auxiliary mark pattern 400 is the same as the number of the reference mark region. For example, when the number of the reference mark region is 4, the number of the auxiliary mark pattern 400 is also 4. Specifically, the auxiliary mark pattern 400 can correspond to the reference mark region. Among them, the auxiliary mark pattern 400 corresponding to the first reference mark region 310 and the auxiliary mark pattern 400 corresponding to the second reference mark region 320 are mutually symmetrical with the center line of the reference mark pattern 300 in the first direction A as the center of symmetry; the auxiliary mark pattern 400 corresponding to the first reference mark region 310 and the auxiliary mark pattern 400 corresponding to the fourth reference mark region 340 are mutually symmetrical with the center line of the reference mark pattern 300 in the second direction B as the center of symmetry, and the auxiliary mark pattern 400 corresponding to the first reference mark region 310 and the auxiliary mark pattern 400 corresponding to the third reference mark region 330 are diagonally symmetrical.

[0065] Please refer to Figure 7 and Figure 8 . Taking the auxiliary mark pattern 400 corresponding to the second reference mark region 320, that is, the auxiliary mark pattern 400 obtained by extracting the contour of the part of the second sub-pattern 302 in the second reference mark region 320 as an example, the auxiliary mark pattern 400 can be composed of a first auxiliary pattern 410 and a second auxiliary pattern 420 which are adjacent to each other, and the first auxiliary pattern 410 and the second auxiliary pattern 420 are both rectangles. In order to make the contour of the auxiliary mark pattern 400 match the contour of the part of the second sub-pattern 302 in each reference mark region, the sizes of the first auxiliary pattern 410 and the second auxiliary pattern 420 can be different. Specifically, the short side of the first auxiliary pattern 410 can be arranged adjacent to the long side of the second auxiliary pattern 420, and the length of the long side of the first auxiliary pattern 410 can be less than the length of the long side of the second auxiliary pattern 420.

[0066] Please refer to Figures 7 to 9To enable the multiple local mark patterns to be combined on the surface of the semiconductor structure to form a complete alignment mark pattern matching the pattern, and to enable the complete alignment mark pattern to be formed in the center of the scribe lane on the surface of the semiconductor structure, so as to reduce the difficulty of alignment and improve the accuracy of alignment, in the embodiment, the multiple auxiliary mark patterns can be arranged in the scribe lane region, which can include: arranging the multiple auxiliary mark patterns in the scribe lane region at the corners of the mask pattern template. Each auxiliary mark pattern 400 can be arranged on one side of the center line 221 of the scribe lane region close to the chip region 210, and at least part of the boundary of the auxiliary mark pattern 400 can be fitted to the center line 221 of the scribe lane region. Specifically, to improve the alignment accuracy in the process of combining the multiple local mark patterns to form the alignment mark pattern, the part of the boundary of the auxiliary mark pattern 400 along the division line of the multiple reference mark regions can be fitted to the center line 221 of the scribe lane region.

[0067] In the actual formation process of the auxiliary mark pattern 400, researchers have found that due to extraction operation errors and other reasons, the outline of the auxiliary mark pattern 400 can deviate from the outline of part of the second sub-pattern 302. At this time, if the auxiliary mark pattern 400 corresponding to the second reference mark region 320 is arranged at the lower left corner of the mask pattern template 200 according to the shape matching degree, the deviation can be inherited in the process of combining the alignment mark pattern, which can reduce the alignment accuracy of each local mark pattern, and can reduce the shape matching degree of the finally combined alignment mark pattern and the pattern.

[0068] To further improve the alignment accuracy in the process of combining the multiple local mark patterns to form the alignment mark pattern, the auxiliary mark pattern 400 corresponding to each reference mark region can be arranged at the corresponding corner of the mask pattern template 200 according to the relative position relationship between each reference mark region and the reference mark pattern 300 and the relative position relationship between each corner of the mask pattern template 200 and the mask pattern template 200. For example, the auxiliary mark pattern 400 corresponding to the second reference mark region 320 can be arranged at the upper right corner of the mask pattern template 200. To reduce the overlap between the auxiliary mark pattern 400 and the chip pattern 211 in the chip region 210, after the auxiliary mark pattern 400 is extracted, the auxiliary mark pattern 400 can be rotated counterclockwise by 90° at least once, so that the shape of the auxiliary mark pattern 400 matches the shape of the corresponding corner of the mask pattern template 200. For example, the auxiliary mark pattern 400 corresponding to the second reference mark region 320 can be arranged at the upper right corner of the mask pattern template 200 after being rotated counterclockwise by 90° twice.

[0069] Since the size of the mask pattern template 200 corresponds to the single-exposure coverage area in the photolithography process, after the partial mark pattern is arranged at the position of the auxiliary mark pattern 400 to obtain the target mask pattern, if single-exposure is performed based on the target mask pattern, the partial mark pattern transferred to the surface of the semiconductor structure will be distributed in each corner of the single-exposure coverage area on the surface of the semiconductor structure, and cannot be combined to form the alignment mark pattern. Therefore, multiple exposures need to be performed in sequence, so that the partial mark patterns in each corner of the single-exposure coverage areas adjacent to each other can be combined. For example, in the case where the alignment mark pattern is formed by combining 4 partial mark patterns, the alignment mark pattern can be formed by combining the partial mark patterns located in the corners of 2x2 single-exposure coverage areas adjacent to each other. However, in the process of performing multiple exposures in sequence, the exposure process performed later can damage the partial mark pattern transferred to the surface of the semiconductor structure by the exposure process performed earlier.

[0070] Please refer to Figure 10 To protect the partial mark pattern formed on the surface of the semiconductor structure in the process of performing multiple exposures, in some embodiments, after the plurality of auxiliary mark patterns are arranged in the scribe lane area, the method of generating the mask pattern can further include: corresponding to the plurality of auxiliary mark patterns, arranging a plurality of protection mark patterns in the scribe lane area at the corners of the mask pattern template. In this way, in the process of performing multiple exposures in sequence, the protection mark pattern 500 can be used to block at least part of the light of the exposure process performed later from irradiating on the partial mark pattern formed on the surface of the semiconductor structure. Specifically, to expand the protection range of the protection mark pattern 500, each protection mark pattern 500 can be arranged on the side of the center line 221 of the scribe lane area away from the chip area 210, and cover at least the area defined by the following boundaries: the edge corner vertex of the mask pattern template 200, the first boundary of the auxiliary mark pattern, and the extension line formed by reversely extending the second boundary of the auxiliary mark pattern along the normal direction of the center line 221 of the scribe lane area. The first boundary of the auxiliary mark pattern is the part of the boundary of the auxiliary mark pattern that is attached to the center line 221 of the scribe lane area. The second boundary of the auxiliary mark pattern is the part of the boundary of the auxiliary mark pattern that extends along the normal direction of the center line 221 of the scribe lane area.

[0071] In this embodiment, similar to the auxiliary mark pattern, the protection mark pattern 500 can be composed of two rectangles arranged next to each other. The length of the short side of the rectangle forming the protection mark pattern 500 is greater than the length of the short side of the first auxiliary pattern 410, and also greater than the length of the short side of the second auxiliary pattern 420.

[0072] Since the protection mark pattern 500 needs to block light, and the local mark pattern needs to transmit light to transfer the pattern, in this embodiment, the light transmittance of the protection mark pattern 500 and the local mark pattern is different in the target mask pattern manufactured based on the mask pattern template in which the protection mark pattern is formed. Specifically, the light transmittance of the protection mark pattern 500 can be 0.

[0073] S130: respectively intercepting part of the graphic pattern located in each reference mark region to obtain a plurality of local mark patterns, and laying each local mark pattern at the position of the corresponding auxiliary mark pattern in the street region to obtain a target mask pattern, so that in the process of manufacturing a semiconductor structure according to the target mask pattern, the plurality of local mark patterns transferred to the semiconductor structure are combined into an alignment mark pattern matching the graphic pattern in the street of the semiconductor structure.

[0074] To improve the matching degree between the alignment mark pattern formed on the surface of the semiconductor structure and the graphic pattern, after occupying the position of the auxiliary mark pattern in the street region of the mask pattern template, part of the graphic pattern located in each reference mark region can be respectively intercepted to obtain a plurality of local mark patterns, and the intercepted local mark pattern can be laid at the occupying position of the auxiliary mark pattern to obtain a target mask pattern, so that the alignment mark pattern can be formed by the plurality of local mark patterns in the process of photolithography based on the target mask pattern, realizing the transfer of the complete graphic pattern to the surface of the semiconductor structure without splitting the GDS file of the reference mark pattern.

[0075] In this embodiment, the local mark pattern can be obtained by directly intercepting the graphic pattern located in each reference mark region in the pattern editing window, so the local mark pattern can correspond to the reference mark region. There is also a corresponding relationship between the auxiliary mark pattern and the reference mark region, so the local mark pattern corresponds to the auxiliary mark pattern. For example, the local mark pattern obtained by intercepting part of the graphic pattern located in the first reference mark region corresponds to the auxiliary mark pattern obtained by extracting the contour of part of the graphic pattern located in the first reference mark region. On this basis, in this embodiment, laying each local mark pattern at the position of the corresponding auxiliary mark pattern in the street region can include: setting the local mark pattern on one side of the center line 221 of the street region close to the chip region 210, and the local mark pattern adheres to the center line 221 of the street region along part of the boundary of the plurality of reference mark region division lines.

[0076] To make the alignment mark patterns formed on different material layers on the surface of the semiconductor structure respectively match the first sub-pattern pattern and the second sub-pattern pattern, in the embodiment, the part of the pattern in each reference mark region is respectively cut to obtain a plurality of local mark patterns, and each local mark pattern is laid out at the position of the corresponding auxiliary mark pattern in the scribe lane region to obtain a target mask pattern, which can include: the part of the first sub-pattern in each reference mark region is respectively cut to obtain a plurality of first sub-pattern local mark patterns, and each first sub-pattern local mark pattern is laid out at the position of the corresponding auxiliary mark pattern in the scribe lane region to obtain a first target mask pattern; the part of the second sub-pattern in each reference mark region is respectively cut to obtain a plurality of second sub-pattern local mark patterns, and each second sub-pattern local mark pattern is laid out at the position of the corresponding auxiliary mark pattern in the scribe lane region to obtain a second target mask pattern.

[0077] Referring to Figure 11 and Figure 12 In the embodiment, the first sub-pattern local mark pattern can be the part of the pattern in each reference mark region cut from the first sub-pattern. Specifically, similar to the auxiliary mark pattern, the first sub-pattern local mark pattern can be composed of two rectangles arranged close to each other and different in size. Taking the first sub-pattern local mark pattern 600 obtained by cutting the part of the first sub-pattern in the second reference mark region 320 as an example, the first sub-pattern local mark pattern 600 can include a first extension 610 and a second extension 620.

[0078] It should be noted that although the first sub-pattern local mark pattern 600 is the same as or close to the contour of the auxiliary mark pattern, "extracting the contour of the part of the pattern in each reference mark region by using the auxiliary pattern in the pattern editing window" and "cutting the part of the pattern in each reference mark region in the pattern editing window" are two different pattern editing operation modes, that is, the extraction of the contour of the part of the pattern is close to the "framing" operation, and the auxiliary mark pattern substantially only contains the contour information of the part of the pattern, while the cutting of the part of the pattern is close to the "screenshot" operation, and the first sub-pattern local mark pattern 600 contains all the information of the part of the pattern.

[0079] Referring to Figure 13 and Figure 14In the present embodiment, the second sub-pattern local mark pattern can be a partial pattern located in each reference mark region and cut from the second sub-pattern. Specifically, similar to the auxiliary mark pattern, the second sub-pattern local mark pattern can be composed of two rectangles which are arranged next to each other and have different sizes. Taking the second sub-pattern local mark pattern 700 cut from the second sub-pattern located in the second reference mark region 320 as an example, the second sub-pattern local mark pattern 700 can include a third extension 710 and a fourth extension 720. The information contained in the second sub-pattern local mark pattern and the process of cutting the second sub-pattern local mark pattern are similar to those of the first sub-pattern local mark pattern, and thus will not be described here.

[0080] In the present embodiment, in the process of manufacturing the semiconductor structure according to the target mask pattern, the first target mask pattern and the second target mask pattern are respectively transferred to different material layers of the semiconductor structure. Specifically, in order to make the alignment mark pattern formed on the top metal layer of the semiconductor structure surface match the first sub-pattern in the reference mark pattern, the first target mask pattern can be transferred to the top metal layer of the semiconductor structure surface. And in order to make the alignment mark pattern formed on the passivation layer of the semiconductor structure surface match the second sub-pattern in the reference mark pattern, the second target mask pattern can be transferred to the passivation layer of the semiconductor structure surface.

[0081] Please refer to Figure 15 and Figure 16 . Since the target mask pattern is formed by arranging the local mark pattern at the position of the auxiliary mark pattern in the scribe lane region, in the present embodiment, in the scribe lane region of the target mask pattern, the protective mark pattern 500 is formed on the side of the center line of the scribe lane region away from the chip region. Specifically, in the first target mask pattern, the protective mark pattern 500 and the first extension 610 and the second extension 620 of the first sub-pattern local mark pattern are respectively formed on both sides of the center line 221 of the scribe lane region. In the second target mask pattern, the protective mark pattern 500 and the third extension 710 and the fourth extension 720 of the second sub-pattern local mark pattern are respectively formed on both sides of the center line 221 of the scribe lane region. In the first target mask pattern and the second target mask pattern, the size of the protective mark pattern and the position on the target mask pattern can be the same.

[0082] Another embodiment of the present application provides a mask. The mask can be manufactured based on the target mask pattern generated according to the generation method of the mask pattern as described in the above embodiments. In the process of manufacturing the semiconductor structure according to the mask, the plurality of local mark patterns transferred to the semiconductor structure can be combined into an alignment mark pattern matching the pattern in the scribe lane of the semiconductor structure.

[0083] Referring to Figure 17 Another embodiment of the present application provides a semiconductor structure, which can be manufactured according to the target mask pattern generated by the method for generating mask pattern as described in the above embodiment, or can be manufactured according to the mask as described in the above embodiment. The plurality of local mark patterns transferred to the semiconductor structure can be combined into an alignment mark pattern 800 matching the pattern in the scribe lane 900 of the semiconductor structure. Specifically, in the alignment mark pattern 800 formed in the scribe lane 900 of the semiconductor structure, the first sub-alignment mark pattern 801 can be formed in the top metal layer and matches the first sub-pattern. The second sub-alignment mark pattern 802 can be formed in the passivation layer and matches the second sub-pattern.

[0084] Another embodiment of the present application provides a method for manufacturing a semiconductor structure, which can manufacture the semiconductor structure according to the target mask pattern generated by the method for generating mask pattern as described in the above embodiment, or can manufacture the semiconductor structure according to the mask as described in the above embodiment. The method for manufacturing the semiconductor structure can include: transferring a plurality of local mark patterns into the scribe lane of the semiconductor structure respectively by using a plurality of exposure processes, so that the plurality of local mark patterns are combined into an alignment mark pattern matching the pattern in the scribe lane of the semiconductor structure.

[0085] The technical effects of the mask, the semiconductor structure and the method for manufacturing the semiconductor structure according to the above embodiments can be explained by referring to other embodiments of the present application, which will not be repeated here.

[0086] In the embodiment of the present application, a mask pattern template including a chip region and a scribe lane region is obtained, and a reference mark pattern divided into a plurality of reference mark regions is obtained, wherein each reference mark region contains part of a graphic pattern and part of a background pattern, then an outline of the part of the graphic pattern in each reference mark region is extracted by using an auxiliary graphic to obtain a plurality of auxiliary mark patterns, and the plurality of auxiliary mark patterns are arranged in the scribe lane region, then the part of the graphic pattern in each reference mark region is intercepted to obtain a plurality of local mark patterns, and each local mark pattern is arranged at the position of the corresponding auxiliary mark pattern in the scribe lane region to obtain a target mask pattern, so that in the process of manufacturing a semiconductor structure according to the target mask pattern, the plurality of local mark patterns transferred to the semiconductor structure are combined into an alignment mark pattern matching the graphic pattern in the scribe lane of the semiconductor structure, and the unexpected effects achieved include that the auxiliary mark pattern is obtained by extracting the outline of the part of the graphic pattern, the local mark pattern is obtained by intercepting the part of the graphic pattern, the auxiliary mark pattern is replaced by the local mark pattern after the auxiliary mark pattern occupies a position in the mask pattern template, so that the local transfer and recombination of the graphic pattern can be realized without splitting the GDS file of the reference mark pattern, the alignment mark pattern formed by combination has the complete graphic features of the reference mark pattern, and the pattern deviation of the chip target mark pattern formed by splitting and splicing is reduced, and the alignment accuracy in the packaging process is improved.

[0087] It can be understood that the specific examples in the present application are only to help those skilled in the art better understand the embodiments of the present application, and not to limit the scope of the present application.

[0088] It can be understood that in various embodiments in the present application, the size of the serial number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0089] It can be understood that the various embodiments described in the present application can be implemented alone or in combination, and the embodiments of the present application do not limit this.

[0090] Unless otherwise specified, all technical and scientific terms used in the embodiments of the present application have the same meanings as understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing the specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more of the listed items. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0091] In several embodiments provided in the present application, it should be understood that the disclosed mask and semiconductor structure can be implemented in other ways. For example, the above-described embodiments of the mask and semiconductor structure are only illustrative.

[0092] The above-described embodiments of the present application are only specific embodiments, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered in the scope of protection of the present application. Therefore, the scope of protection of the present application should be subject to the scope of protection of the claims.

Claims

1. A method of generating a mask pattern, characterized by, The application is applied to a mask pattern design system; the mask pattern generation method comprises: Obtaining a mask pattern template and a reference mark pattern; wherein the mask pattern template comprises a chip region and a scribe lane region surrounding the chip region; the reference mark pattern comprises a graphic pattern and a background pattern; the reference mark pattern is divided into a plurality of non-overlapping reference mark regions; each of the reference mark regions comprises part of the graphic pattern and part of the background pattern; Using an auxiliary graphic to extract the contour of part of the graphic pattern in each of the reference mark regions to obtain a plurality of auxiliary mark patterns, and arranging the plurality of auxiliary mark patterns in the scribe lane region; wherein the number of the auxiliary mark patterns is the same as the number of the reference mark regions; Respectively intercepting part of the graphic pattern in each of the reference mark regions to obtain a plurality of local mark patterns, and arranging each of the local mark patterns at the position of the corresponding auxiliary mark pattern in the scribe lane region to obtain a target mask pattern, so that in the process of manufacturing a semiconductor structure according to the target mask pattern, a plurality of the local mark patterns transferred to the semiconductor structure are combined into an alignment mark pattern matching the graphic pattern in the scribe lane of the semiconductor structure.

2. The method of claim 1, wherein Arranging the plurality of auxiliary mark patterns in the scribe lane region comprises: Arranging the plurality of auxiliary mark patterns in the scribe lane region of the mask pattern template corner; wherein each of the auxiliary mark patterns is arranged on one side of the center line of the scribe lane region close to the chip region, and at least part of the boundary is fitted to the center line of the scribe lane region.

3. The method of claim 2, wherein After arranging the plurality of auxiliary mark patterns in the scribe lane region, the mask pattern generation method further comprises: Corresponding to the plurality of auxiliary mark patterns, arranging a plurality of protection mark patterns in the scribe lane region of the mask pattern template corner to obtain a target mask pattern; wherein each of the protection mark patterns is arranged on one side of the center line of the scribe lane region away from the chip region, and at least covers the region defined by the following boundaries: the corner vertex of the mask pattern template, the first boundary of the auxiliary mark pattern, and the second boundary of the auxiliary mark pattern reversely extended along the normal direction of the center line of the scribe lane region to form an extension line; the first boundary of the auxiliary mark pattern is the part of the boundary of the auxiliary mark pattern fitted to the center line of the scribe lane region; the second boundary of the auxiliary mark pattern is the part of the boundary of the auxiliary mark pattern extended along the normal direction of the center line of the scribe lane region.

4. The method of claim 3, wherein In the target mask pattern, the light transmittance of the protection mark pattern and the local mark pattern is different; wherein the light transmittance of the protection mark pattern is 0.

5. The method of claim 1, wherein The graphic pattern comprises a first sub-graphic pattern and a second sub-graphic pattern with the same contour shape; the first sub-graphic pattern and the second sub-graphic pattern respectively extend along a first direction and a second direction perpendicular to each other; wherein the length of the first sub-graphic pattern extending along the first direction is less than the length of the second sub-graphic pattern extending along the first direction, and the length of the first sub-graphic pattern extending along the second direction is less than the length of the second sub-graphic pattern extending along the second direction.

6. The method of claim 5, wherein The contour of part of the graphic pattern in each of the reference mark regions is extracted by using an auxiliary graphic, and a plurality of auxiliary mark patterns are obtained, comprising: The contour of part of the second sub-graphic pattern in each of the reference mark regions is extracted by using at least two auxiliary graphics arranged adjacent to each other; wherein the auxiliary graphic is a rectangle.

7. The method of claim 5, wherein Part of the graphic pattern in each of the reference mark regions is cut respectively to obtain a plurality of local mark patterns, and each of the local mark patterns is arranged at the position of the corresponding auxiliary mark pattern in the cutting track region to obtain a target mask pattern, comprising: Part of the first sub-graphic pattern in each of the reference mark regions is cut respectively to obtain a plurality of first sub-graphic local mark patterns, and each of the first sub-graphic local mark patterns is arranged at the position of the corresponding auxiliary mark pattern in the cutting track region to obtain a first target mask pattern. Part of the second sub-graphic pattern in each of the reference mark regions is cut respectively to obtain a plurality of second sub-graphic local mark patterns, and each of the second sub-graphic local mark patterns is arranged at the position of the corresponding auxiliary mark pattern in the cutting track region to obtain a second target mask pattern; in the process of manufacturing the semiconductor structure according to the target mask pattern, the first target mask pattern and the second target mask pattern are respectively transferred to different material layers of the semiconductor structure.

8. A mask, characterized in that The mask is manufactured based on the target mask pattern generated by the mask pattern generation method according to any one of claims 1 to 7; in the process of manufacturing the semiconductor structure according to the mask, a plurality of the local mark patterns transferred to the semiconductor structure are combined into an alignment mark pattern matching the graphic pattern in the cutting track of the semiconductor structure.

9. A semiconductor structure, characterized by The semiconductor structure is manufactured according to the target mask pattern generated by the mask pattern generation method according to any one of claims 1 to 7, or according to the mask according to claim 8. A plurality of the local mark patterns transferred to the semiconductor structure are combined into an alignment mark pattern matching the graphic pattern in the cutting track of the semiconductor structure.

10. A method of manufacturing a semiconductor structure, characterized by, The manufacturing method of the semiconductor structure is used to manufacture the semiconductor structure according to the target mask pattern generated by the mask pattern generation method according to any one of claims 1 to 7, or according to the mask according to claim 8; The manufacturing method of the semiconductor structure comprises: The multiple local mark patterns are transferred into the dicing lane of the semiconductor structure respectively by a multiple-exposure process, so that the multiple local mark patterns are combined into an alignment mark pattern matching the pattern in the dicing lane of the semiconductor structure.

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