Distributed dynamic time sequence monitoring circuit and self-adaptive adjusting system

Abstract

The invention discloses a distributed dynamic time sequence monitoring circuit and a self-adaptive adjusting system, which comprise a plurality of monitoring units deployed in different IR voltage drop hot spot areas of a chip, each monitoring unit is configured as a delay chain, and the delay of the delay chain is determined by the local power supply voltage and temperature of the area where the monitoring unit is located. The delay variation is equal to the delay variation of the longest key path determined by simulation; the input end of the dynamic aggregation unit is connected with the monitoring unit, and the dynamic aggregation unit is used for comparing delays of all the input signals and outputting the input signal with the longest delay; a central monitor including a configurable delay pad circuit for providing a reference delay; the input end of the delay gasket circuit is connected with the output end of the dynamic aggregation unit, and the delay of the input signal with the longest delay and the reference delay are summed to obtain the total delay of the virtual key path for the real-time longest key path delay of the mirror image chip. According to the invention, non-intrusive monitoring can be realized, and all possible IR voltage drop hot spot areas can be fully covered.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and particularly relates to a distributed dynamic timing monitoring circuit and an adaptive adjustment system, and more particularly relates to an on-chip dynamic timing monitoring circuit for high-performance digital chips and an adaptive voltage and frequency scaling system based on the circuit. BACKGROUND

[0002] With the integrated circuit technology entering the post-Moore era, the design of high-performance chips (such as central processing units (CPUs), graphics processing units (GPUs), and AI accelerators) increasingly faces the contradiction between extreme performance and the stringent power wall. To ensure the absolute reliability of the chip under complex working conditions such as process, voltage, temperature (PVT) dynamic changes and transient IR drop, the traditional design method generally relies on static timing analysis (STA) based on "worst case", and reserves a large static timing margin as a protection zone. This conservative strategy, although ensuring functional correctness, sacrifices a large amount of energy efficiency, resulting in the chip working at a voltage level far exceeding the actual demand for a long time in most "better than worst case" actual running time, causing serious power waste.

[0003] To break this energy efficiency bottleneck, the industry has proposed a technology of dynamically eliminating redundant protection zones by monitoring timing margins on-chip in real time and performing adaptive voltage and frequency scaling (AVFS). However, the existing monitoring solutions have the following pain points:

[0004] 1. Conflict between invasiveness and monitoring accuracy: The timing of the critical path of high-performance circuits is extremely tight. The invasive solution of directly inserting a monitoring unit on the path will change the original path delay, which is unacceptable. The fundamental defect of the non-invasive critical path replica method is its static nature. Studies have shown that the actual longest critical path within the chip will dynamically migrate with changes in running load or PVT conditions. Simply replicating a few paths analyzed statically cannot cover the real longest delay path under all working conditions, and there is a risk of missing detection, which may cause the system to make incorrect adjustments at a critical moment due to incorrect monitoring information, causing calculation errors.

[0005] 2. Monitoring of dynamic IR-drop: Dynamic IR-drop is the most dominant uncertainty factor affecting timing. When the chip is performing compute-intensive tasks, the simultaneous toggling of massive logic gates will draw huge transient current, forming a dramatic and short-lived voltage dip in local regions. This voltage drop is difficult to predict, and its "hot spot" is often the region with the highest logic cell density. Traditional voltage sensors are bulky and difficult to deploy in these regions for accurate local monitoring. To counter this unpredictable voltage drop, designers have to resort to conservatism again, reserving a static voltage margin sufficient to combat the worst-case dynamic IR-drop, which again leads to power waste.

[0006] 3. Problem of regulation stability: Some existing AVFS systems will trigger the warning monitor frequently when the voltage approaches the chip's minimum safe operating voltage (Vmin), causing the control logic to repeatedly raise and lower the voltage near Vmin, resulting in oscillation. Not only does this waste regulation energy, but more seriously, it risks the system operating below the true Vmin at some transient, endangering system stability.

[0007] Therefore, there is an urgent need for a system that can non-invasively monitor the full-chip dynamic timing margin in real time and accurately, especially one that can effectively track the dynamic migration of critical paths and the impact of local dynamic IR-drop, and achieve stable and reliable adaptive regulation, to safely push the chip's operating point to its physical limit and maximize energy efficiency. SUMMARY

[0008] To solve the above problems, the present application provides a distributed dynamic timing monitoring circuit and an adaptive regulation system, which can achieve non-invasive monitoring and comprehensively cover all possible IR-drop hot spot regions, solving the monitoring problem of dynamic migration of critical paths.

[0009] To achieve the above technical purposes and effects, the present application realizes the following technical solutions:

[0010] In a first aspect, the present application provides a distributed dynamic timing monitoring circuit, comprising:

[0011] a plurality of monitoring units deployed in different IR-drop hot spot regions of the chip, each monitoring unit being configured as a delay chain, the delay of which being determined by the local supply voltage and temperature of the region in which it is located, and the delay variation of which being designed to be equal to the delay variation of the longest critical path determined by simulation;

[0012] a dynamic aggregation unit, the input end of which is connected to the output end of each monitoring unit, for comparing the delays of all input signals in real time and taking the input signal with the longest delay as the output signal;

[0013] The central monitor disposed in a stable voltage domain of the chip comprises a configurable delay pad circuit for providing a reference delay; an input end of the delay pad circuit is connected with an output end of the dynamic aggregation unit, a delay of an input signal with the longest delay is summed with the reference delay to obtain a total delay for mirroring a real-time longest critical path delay of the chip.

[0014] In combination with the first aspect, the monitoring unit comprises:

[0015] a plurality of first buffers, all of which are connected in sequence in a head-to-tail manner to form a first initial delay chain with taps;

[0016] a first selection circuit, each data input end of which is connected to a different tap of the first initial delay chain, for selecting different numbers of first buffers as a first final delay chain according to a process corner and a delay variation of a longest critical path determined by simulation.

[0017] In combination with the first aspect, the delay pad circuit comprises:

[0018] a plurality of second buffers, all of which are connected in sequence in a head-to-tail manner to form a second initial delay chain with taps;

[0019] a second selection circuit, each data input end of which is connected to a different tap of the second initial delay chain, for dynamically selecting different numbers of second buffers as a second final delay chain according to an output signal of an on-chip PVT sensor on the chip, a delay of the second final delay chain being the reference delay.

[0020] In combination with the first aspect, the method for determining the number of second buffers included in the second final delay chain comprises:

[0021] calculating a configuration bit value of the second selection circuit based on a power supply voltage signal, a process corner and a temperature signal of the chip output by the PVT sensor and a preset compensation function;

[0022] directly using the configuration bit value as a selection control signal of the second selection circuit to obtain the number of second buffers included in the second final delay chain.

[0023] In combination with the first aspect, the first buffers and the second buffers are standard logic units using an extremely high threshold voltage, an ultrahigh threshold voltage or a high threshold voltage process.

[0024] In combination with the first aspect, the dynamic aggregation unit comprises:

[0025] A plurality of PMOS transistors are connected in series and connected with an NMOS transistor to form a dynamic NOR circuit, the gate of the first PMOS transistor and the last NMOS transistor are connected with a half frequency of a system clock, and the gates of the intermediate PMOS transistors are connected with the output terminals of the monitoring units respectively;

[0026] A plurality of groups of D flip-flops, the clock input terminals of each group of D flip-flops are connected with the output terminal of the dynamic NOR circuit, and the data input terminals are connected with the output terminals of the corresponding monitoring units respectively;

[0027] The dynamic NOR circuit and the D flip-flops cooperate to identify the input signal with the longest delay through a circuit competition mechanism, and output a one-hot code identifying the source of the input signal with the longest delay.

[0028] In combination with the first aspect, the central monitor is deployed at an optimal signal convergence point, the optimal signal convergence point has the minimum total length of wiring from each monitoring unit to the optimal signal convergence point, and the propagation delay of the signals of each monitoring unit to the optimal signal convergence point tends to be balanced, and is obtained through an optimization algorithm.

[0029] In the second aspect, the application provides an adaptive adjustment system, comprising:

[0030] The distributed dynamic timing monitoring circuit of any one of the first aspect;

[0031] The clippable early warning timing monitoring unit is connected with the output terminal of the central monitor, and is used for monitoring the timing margin of the output signal of the delay pad circuit, and generating a pre-control signal and a pre-error signal according to different timing margin levels;

[0032] The adaptive voltage frequency adjustment control logic unit receives the pre-control signal and the pre-error signal, and adjusts the supply voltage or the working frequency of the chip according to the level combination state of the pre-control signal and the pre-error signal.

[0033] In combination with the second aspect, the clippable early warning timing monitoring unit comprises:

[0034] The main flip-flop has an input signal of the output signal of the delay pad circuit;

[0035] The first shadow path comprises a first additional delay unit and a first shadow flip-flop connected in series, and has an input signal of the output signal of the delay pad circuit;

[0036] The second shadow path comprises a second additional delay unit and a second shadow flip-flop connected in series, and has an input signal of the output signal of the delay pad circuit, wherein the delay of the first additional delay unit is smaller than the delay of the second additional delay unit;

[0037] The pre-control signal is generated by comparing the sampling result of the main flip-flop with the sampling result of the first shadow flip-flop through exclusive-OR logic comparison;

[0038] The pre-error signal is generated by comparing the sampling result of the main flip-flop with the sampling result of the second shadow flip-flop through exclusive-OR logic comparison.

[0039] In combination with the second aspect, optionally, the adaptive voltage and frequency adjustment control logic unit adopts a double-time-scale adjustment strategy, specifically including:

[0040] Slow voltage adjustment: after one workload instance ends, the adjustment direction of the supply voltage is determined according to the cumulative state of the pre-control signal and the pre-error signal, and the supply voltage is gradually adjusted before the next instance starts; the cumulative state refers to the ratio of the cumulative occupation period of the fast frequency adjustment to the total period of the workload instance;

[0041] Fast frequency adjustment: during the running of one workload instance, when the pre-error signal is triggered, the working frequency of the chip is immediately reduced.

[0042] Compared with the prior art, the present application has the following beneficial effects:

[0043] (1) Non-intrusive monitoring is realized, and all possible IR drop hot spot areas are comprehensively covered, solving the monitoring problem of dynamic migration of the critical path: by distributing the monitoring units in different IR drop hot spot areas, and based on the principle of "equivalent delay tracking" (i.e. making the delay change amount of the monitoring unit equivalent to the delay change amount of the longest critical path determined by simulation), a virtual critical path is mirrored, which is composed of the monitoring unit corresponding to the input signal with the longest delay, the dynamic aggregation unit and the delay pad circuit. In the later stage, only the virtual path needs to be monitored, without invading the original functional logic of the chip, so that the real longest critical path dynamically migrated due to changes in load and PVT (process corner, supply voltage and temperature) can be effectively tracked.

[0044] (2) Accurate capture of local effects, solve the dynamic IR drop monitoring problem: the monitoring unit is small in size, can be deployed in high density in the IR drop hotspot area, and accurately capture the influence of local and transient IR drop on timing. In the specific implementation process, in the back-end stage of chip design (after layout and routing), a special EDA tool such as Ansys RedHawk is used for dynamic IR drop simulation. Dynamic IR drop simulation can simulate the real current consumption of the chip when performing high-power computing tasks (such as large-scale parallel computing), and generate a "heat map" like on-chip voltage noise map, which will mark which area has the most serious and frequent voltage drop. The area exposed in the simulation is the "IR drop hotspot area", and the deployment strategy of the monitoring unit is to place the monitoring unit in these identified hotspot areas to achieve the most effective monitoring.

[0045] (3) Stable and reliable adaptive adjustment, solve the critical voltage point oscillation problem: through the double-layer early warning mechanism provided by the pre-warning type timing monitoring unit, the voltage oscillation near the critical voltage point of the traditional AVFS system is avoided. Combined with the double-time scale adjustment strategy, the chip operating point can be safely and stably pushed to the physical limit, and under the premise of eliminating timing violations, the redundant timing margin is maximized to significantly improve the energy efficiency of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can also be obtained according to these drawings without creative labor for those skilled in the art.

[0047] Figure 1 The overall architecture schematic diagram of the distributed dynamic timing monitoring circuit and the adaptive adjustment system of an embodiment of the present application;

[0048] Figure 2 The working principle schematic diagram of the distributed dynamic timing monitoring circuit of an embodiment of the present application;

[0049] Figure 3 The circuit implementation and process angle adaptive structure schematic diagram of the monitoring unit of an embodiment of the present application;

[0050] Figure 4 The circuit structure and working principle schematic diagram of the dynamic aggregation unit of an embodiment of the present application;

[0051] Figure 5 The PVT-aware delay pad circuit schematic diagram of an embodiment of the present application;

[0052] Figure 6 This is a schematic diagram illustrating the problem of frequent voltage regulation caused by early warning monitoring units in existing technologies.

[0053] Figure 7 This is a schematic diagram of the circuit structure of a clampable early warning timing monitoring unit according to an embodiment of the present invention;

[0054] Figure 8 This is a schematic diagram of the working state of a clampable early warning timing monitoring unit according to an embodiment of the present invention;

[0055] Figure 9 This is a schematic diagram illustrating the use of a clampable early warning timing monitoring unit according to an embodiment of the present invention;

[0056] Figure 10 This is a schematic diagram of the control logic of an adaptive voltage and frequency regulation control logic unit guided by a clampable early warning timing monitoring unit according to an embodiment of the present invention. Detailed Implementation

[0057] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may include different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0059] In the description of the present application, if the meaning of several is one or more, the meaning of multiple is two or more, greater than, less than, more than, etc. are understood as not including the number, above, below, within, etc. are understood as including the number. If it is described as first, second, it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the sequence of indicated technical features.

[0060] In the description of the present application, the description of the reference terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0061] The application principle of the present application will be described in detail below in combination with the drawings.

[0062] Embodiment 1

[0063] The present application provides a distributed dynamic timing monitoring circuit, comprising:

[0064] A plurality of monitoring units deployed in different IR voltage drop hot spot regions of a chip, each monitoring unit being configured as a delay chain, the delay of which being determined by the local power supply voltage and temperature of the region where it is located, and the delay variation of which being designed to be equal to the delay variation of the longest critical path determined by simulation;

[0065] A dynamic aggregation unit, the input end of which is connected to the output end of each monitoring unit, for comparing the delays of all input signals in real time, and taking the input signal with the longest delay as the output signal;

[0066] A central monitor deployed in the stable voltage domain of the chip, comprising a configurable delay shim circuit for providing a reference delay; the input end of the delay shim circuit is connected to the output end of the dynamic aggregation unit, and the delay of the input signal with the longest delay is summed with the reference delay to obtain the total delay for mirroring the real-time longest critical path delay of the chip.

[0067] Based on the above scheme, non-invasive monitoring can be achieved, and all possible IR drop hot spot areas are comprehensively covered, solving the monitoring problem of dynamic migration of the critical path. Specifically, by distributing the monitoring units in different IR drop hot spot areas, and based on the principle of "equivalent delay tracking" (i.e. making the delay change amount of the monitoring unit equivalent to the delay change amount of the longest critical path), a virtual critical path is mirrored, which is composed of the monitoring unit corresponding to the input signal with the longest delay, the dynamic aggregation unit and the delay pad circuit. In the later stage, only the virtual path needs to be monitored, without invading the original function logic of the chip, so that the real longest critical path dynamically migrated due to load and PVT (process angle, voltage and temperature) changes can be effectively tracked.

[0068] The traditional non-invasive monitoring method is to copy a static critical path, and the goal is to make the total delay of the copied path equal to the total delay of the real longest critical path. However, the defect of this method is that the real longest critical path will dynamically migrate, and the copied path A may no longer be the bottleneck at the next moment, and the bottleneck becomes the copied path B, resulting in monitoring failure. Therefore, in the embodiment of the present application, when the delay of the longest critical path at any position on the chip increases by ΔDelay_circuit (such as 200ps) due to IR drop, the delay of the monitoring unit deployed in this area also needs to be increased by an almost equal value ΔDelay_unit (about 200ps). By adjusting the number of buffers in the monitoring unit, ΔDelay_unit ≈ ΔDelay_circuit is ensured, and ΔDelay_unit is completed in the design stage to ensure that the monitoring unit can accurately simulate the degree of "slowing down" of the real circuit due to voltage drop.

[0069] In one specific embodiment of the present application, the monitoring unit comprises:

[0070] A plurality of first buffers, all the first buffers being connected in series with their heads and tails connected together to form a first initial delay chain with taps; in the specific implementation process, the first buffer can also be replaced by two inverters connected in series;

[0071] A first selection circuit, each data input end of which is connected to a different tap of the first initial delay chain, for selecting different numbers of first buffers as a first final delay chain according to the process angle of the chip and the delay change amount of the longest critical path determined by simulation.

[0072] In the above scheme, the structure of the monitoring unit is specifically limited to achieve the matching relationship between the delay variation of the monitoring unit and the simulation-determined longest critical path delay variation at different process corners. In the specific implementation process, the structure design of the monitoring unit is completed in the chip design and simulation stage, and different numbers of first buffers are selected at different process corners. For each process corner (for example, the SS process corner), the layout post-netlist of the entire chip is simulated using an industry standard circuit simulation tool (such as HSPICE / FineSim). By applying a stimulus, the increase in the delay of the longest critical path when the voltage decreases from a nominal value (such as 0.9V) to a certain value (such as 0.8V) at the process corner can be obtained, denoted as ΔDelay_circuit. Similarly, at the same changed voltage at the SS process corner, the delay increment ΔDelay_unit of the delay chain (monitoring unit) composed of different numbers of first buffers is obtained; by adjusting the number of first buffers (for example, from 5, 6, 7, and so on), a stage (for example, 6 stages) is found, so that ΔDelay_unit and ΔDelay_circuit are closest. Repeat the foregoing steps for other process corners that need to be considered, such as the FF process corner and the TT process corner, to find the best matching number of first buffers (for example, 15 stages for the TT corner and 24 stages for the FF corner) for them respectively. Finally, these matching results are fixed in the hardware structure, that is, the total length of the delay chain is the longest required length (24 stages), and the taps are set at the 6th stage, the 15th stage, and the 24th stage and connected to different input terminals of the first selection circuit. In the specific implementation process, the first selection circuit can be implemented by using a multiplexer (MUX).

[0073] In a specific implementation of an embodiment of the present application, the first buffer is a standard logic unit using an extremely high threshold voltage, an ultrahigh threshold voltage, or a high threshold voltage process.

[0074] In the above scheme, the first buffer (that is, the standard logic unit) using a high threshold voltage (High-Vth, HVT), an extremely high threshold voltage (EHVT), or an ultrahigh threshold voltage (UHVT) is used to achieve high voltage sensitivity. When the threshold voltage Vth of the standard logic unit is higher, if the supply voltage VDD of the chip decreases (for example, dynamic IR drop), the change in gate delay will be greater, the number of stages of standard logic units required to produce the same change will be less, the overall area will be smaller, and the layout and routing overhead will be smaller. Therefore, the monitoring unit can be densely deployed in the IR drop hotspot area of the chip logic, and high spatial resolution monitoring can be achieved.

[0075] In a specific implementation of an embodiment of the present application, the dynamic aggregation unit includes:

[0076] A number of PMOS transistors, each of which is connected in series with the first and last one to form a dynamic NOR gate, the gate of the first PMOS transistor is connected to a half frequency clock signal, the gates of the intermediate PMOS transistors are connected to the outputs of the N monitoring units respectively; the dynamic NOR gate is essentially a dynamic NOR gate or similar dynamic logic gate. The first PMOS transistor is a PMOS transistor for pre-charging, the intermediate PMOS transistors are PMOS pull-up transistors controlled by the output signals of the monitoring units, and the last NMOS transistor is an NMOS transistor for resetting;

[0077] A number of D flip-flops, the clock input of each D flip-flop is connected to the output of the dynamic NOR gate, and the data input of each D flip-flop is connected to the output of the corresponding monitoring unit;

[0078] The dynamic NOR gate and the D flip-flops cooperate to identify the input signal with the longest delay through a circuit competition mechanism, and output a one-hot code indicating the source of the input signal with the longest delay.

[0079] In the above scheme, the core principle is to directly complete comparison in the time domain by using the dynamic NOR gate, rather than numerical operation in the digital domain. The working principle of the dynamic aggregation unit is as follows:

[0080] 1. Reset / pre-charge phase: at the high level of the half frequency clock signal, the output node of the dynamic NOR gate is reset to an initial state (low level GND);

[0081] 2. Evaluation / competition phase: at the low level of the half frequency clock signal, the evaluation circuit starts to work. The output signals of the N monitoring units simultaneously act on the N pull-up transistors (PMOS) in series. The signal that arrives latest (i.e. with the longest delay) among these signals will pull up the output node.

[0082] 3. Sampling / latching phase: the level jump edge (rising edge from low to high) of the output node of the dynamic NOR gate is used as a global sampling clock to latch the input of a group of D flip-flops. The D input of the flip-flops is directly connected to the original output signals of the N monitoring units.

[0083] 4. One-hot code generation: Since the sampling clock is generated when the "slowest signal" reaches the end point, at this time, only the flip-flop input corresponding to the "slowest signal" still maintains a high level, while all the "faster signals" have passed through, and the flip-flop input corresponding to the "faster signals" has become a low level. Therefore, the result of the latch naturally forms a one-hot code, that is, only one bit is '1', and the rest are all '0'. The position of the '1' uniquely identifies the source of the longest delay signal.

[0084] In one specific embodiment of the present application, the delay pad circuit comprises:

[0085] A plurality of second buffers, all of which are connected in series and form a second initial delay chain with taps; in the specific implementation process, the second buffer can also be replaced by two inverters connected in series;

[0086] A second selection circuit, each data input end of which is connected to a different tap of the second initial delay chain, for dynamically selecting different numbers of second buffers as a second final delay chain according to the output signal of the on-chip PVT sensor on the chip, the delay of the second final delay chain being the reference delay.

[0087] In the above scheme, the specific structure of the delay pad circuit is a programmable delay chain, as shown in Figure 5 which is composed of a series of second buffers or inverters (i.e., standard logic units) connected in series. A plurality of tap points are also provided on the delay chain, and the second selection circuit uses a multiplexer (MUX), the plurality of data input ends of which are connected to the different tap points. A set of digital configuration bits input from the outside is used as the selection control signal of the multiplexer (MUX), and by changing the set of configuration bits, different tap points can be selected as the output, thereby achieving stepwise adjustment of the total delay in a large range (for example, from 100 ps to 1000 ps). The adjustable delay is the "reference delay".

[0088] In one specific embodiment of the present application, the method for determining the number of second buffers included in the second final delay chain comprises:

[0089] Based on the global power supply voltage signal, process corner, temperature signal of the chip output by the PVT sensor, and a preset compensation function, the configuration bit value of the second selection circuit is calculated;

[0090] The configuration bit value is directly used as the selection control signal of the second selection circuit, and the number of second buffers included in the second final delay chain is obtained. In the specific implementation process, the second selection circuit can be implemented by using a multiplexer (MUX).

[0091] In the above scheme, the principle of dynamically selecting different numbers of second buffers for dynamic adjustment according to the output signal of the on-chip PVT sensor on the chip is a closed-loop compensation mechanism, which is specifically as follows:

[0092] 1. Perception: A special PVT sensor is integrated on the chip to monitor the process angle (P), the global supply voltage (V), and the temperature (T) of the chip in real time, and output corresponding digital code values.

[0093] 2. Calculation: The digital signals of parameters P, V, and T are sent to a small digital control logic unit, which internally stores a compensation function previously calibrated through simulation and chip testing. In this embodiment, the compensation function is a three-plane fitting function (corresponding to SS, TT, and FF three process angles), which is in the form of: configuration bit = p00 + p10 * V + p01 * T. Wherein, V and T are the global supply voltage and temperature of the chip, which are obtained by real-time measurement by the PVT sensor, and p00, p10, and p01 are preset coefficients. The digital control logic unit will calculate the "configuration bit" value required to maintain a constant delay under the current P, V, and T conditions in real time.

[0094] 3. Execution: The calculated "configuration bit" value is directly used as the selection control signal of the second selection circuit (i.e., the multiplexer) in the delay pad circuit.

[0095] Workflow example: Assuming that the temperature rises, causing the delay pad circuit itself to become faster. The PVT sensor detects that the temperature T rises, and the control logic calculates a new, larger "configuration bit" value according to the compensation function. This new configuration bit causes the MUX to select a longer delay path, thereby offsetting the increased delay due to the temperature rise, ultimately restoring and maintaining the total output delay of the delay pad. The voltage change is the same.

[0096] In one specific implementation of the embodiment of the present application, the central monitor is deployed at an optimal signal convergence point, the optimal signal convergence point has the minimum total length of wiring from each monitoring unit to the optimal signal convergence point, and the propagation delay of signals from each monitoring unit to the optimal signal convergence point tends to be balanced, and is obtained through an optimization algorithm.

[0097] Embodiment 2

[0098] In the embodiment of the present application, an adaptive adjustment system is provided, as shown in Figure 1 , which includes:

[0099] The distributed dynamic timing monitoring circuit of any one of Embodiment 1;

[0100] A pre-warning type timing monitoring unit with clampable input terminal connected with output terminal of the central monitor, used for monitoring timing margin of the output signal of the delay pad circuit, and generating pre-control signal and pre-error signal according to different timing margin level;

[0101] An adaptive voltage frequency adjustment control logic unit receiving the pre-control signal and pre-error signal, and adjusting supply voltage or working frequency of the chip according to level combination state of the pre-control signal and pre-error signal. In a specific implementation process, the pre-warning type timing monitoring unit with clampable and the adaptive voltage frequency adjustment control logic unit jointly constitute an adaptive adjustment unit, which is specifically described in Figure 1 ;

[0102] In a specific implementation of the embodiment of the application, the pre-warning type timing monitoring unit with clampable comprises:

[0103] A main flip-flop with input signal being the output signal of the delay pad circuit;

[0104] A first shadow path comprising a first additional delay unit and a first shadow flip-flop connected in sequence, with input signal being the output signal of the delay pad circuit;

[0105] A second shadow path comprising a second additional delay unit and a second shadow flip-flop connected in sequence, with input signal being the output signal of the delay pad circuit, wherein the delay of the first additional delay unit is less than that of the second additional delay unit;

[0106] The pre-control signal is generated by exclusive-OR logic comparison between sampling result of the main flip-flop and sampling result of the first shadow flip-flop;

[0107] The pre-error signal is generated by exclusive-OR logic comparison between sampling result of the main flip-flop and sampling result of the second shadow flip-flop.

[0108] In a specific implementation of the embodiment of the application, the adaptive voltage frequency adjustment control logic unit adopts a double-time-scale adjustment strategy, comprising:

[0109] Slow voltage adjustment: after one working load instance ends, the adjustment direction of supply voltage is determined according to cumulative state of the pre-control signal and pre-error signal, and the supply voltage is gradually adjusted before the next instance starts; the cumulative state refers to the ratio of cumulative occupation period of fast frequency adjustment to total period of working load instance;

[0110] Fast frequency adjustment: during running of one working load instance, when the pre-error signal is triggered, the working frequency of the chip is immediately reduced.

[0111] In the implementation process, the pre-alarming timing monitoring unit generates pre-control signals and pre-error signals according to different timing margin levels, including:

[0112] Timing margin level one: safe zone: PRE-CTRL=0, PRE-ERR=0. It indicates that the timing margin is very sufficient, and the system is absolutely safe. PRE-CTRL is a pre-control signal, and PRE-ERR is a pre-error signal.

[0113] Timing margin level two: alert zone: PRE-CTRL=1, PRE-ERR=0. It indicates that the timing margin is starting to tighten, and has entered the set guard band range, which needs to be vigilant, but there is no risk of timing error. This is the ideal working state of the system.

[0114] Timing margin level three: danger zone: PRE-ERR=1. It indicates that the timing margin is almost exhausted, and timing violations will occur or have occurred, which is an emergency state that must take immediate measures.

[0115] The control logic of the adaptive voltage frequency adjustment control logic unit is to make corresponding adjustment decisions according to which of the three timing margin levels the system is currently in.

[0116] The adaptive adjustment system in the embodiment of the application will be described in detail below in combination with a specific implementation.

[0117] Referring to Figure 1 and Figure 2 The adaptive adjustment system provided by the embodiment includes a distributed dynamic timing monitoring circuit, a pre-alarming timing monitoring unit, and an adaptive voltage frequency adjustment control logic unit. The core idea of the distributed dynamic timing monitoring circuit is to decouple the functions of "distributed sensing" and "centralized processing" in physics, which includes a plurality of monitoring units, a dynamic aggregation unit, and a central monitor.

[0118] 1. Specific implementation of the distributed dynamic timing monitoring circuit

[0119] The core of the monitoring unit of the embodiment is to realize "equivalent delay tracking". To achieve this purpose, each monitoring unit is composed of a plurality of first buffers (BUFF) in series using an extremely high threshold voltage (EHVT) process. The input signal of the monitoring unit is a clock signal obtained by dividing the system clock by two, which is used to simulate the flip-flop activity of the continuously activated data path. The delay of the first buffer (BUFF) shows high sensitivity to the fluctuations of the power supply voltage of the chip, and can accurately reflect the influence of IR drop on timing. The design goal is not to simply copy a particular key path, but to make the delay variation of each monitoring unit accurately "mirror" the delay variation of the longest critical path in the chip caused by IR drop.

[0120] The specific calibration process is as follows: first, the longest critical path delay of the chip under the nominal voltage and the voltage reduced by 100mV (simulating a typical IR drop) is obtained by a circuit simulation tool (such as HSPICE), and the delay increment ΔDelay_circuit is calculated. Then, the number of first buffers (BUFF) in the monitoring unit is adjusted, and the delay under the nominal voltage and the voltage reduced by 100mV is simulated, and the delay increment ΔDelay_unit is calculated. Adjust the number of first buffers (BUFF) in the monitoring unit until ΔDelay_unit ≈ ΔDelay_circuit. Such design can skillfully avoid the problem of dynamic migration of critical path with working conditions.

[0121] Referring to Figure 3 To cope with the influence of different process corners, the monitoring unit of the embodiment includes a multiplexer (MUX) used as a first selection circuit. According to the process corner determined during the chip factory test (such as SS slow, TT typical, FF fast), different lengths of buffer chains are selected by the configuration bit of the multiplexer (MUX), to ensure that the tracking accuracy can be maintained under various process corners.

[0122] The dynamic aggregation unit of the embodiment, referring to Figure 4which is a customized dynamic NOR gate. The output signals of all N monitoring units together control a pull-up network consisting of (N+1) PMOS transistors. During the evaluation phase, the output of the dynamic aggregation unit will change with the latest arriving monitoring signal (representing the IR drop hotspot region with the worst case). The change of this output signal is used as a global sampling clock to trigger a set of D flip-flops, which finally form a one-hot code uniquely identifying the monitoring unit number with the worst case. The dynamic NOR gate topology itself requires much less transistors than the equivalent logic implemented by cascading standard logic gates (e.g. 4-input NOR gate and 2-input AND gate), and can share source / drain regions and use the tightest routing rules to eliminate the "dead space" caused by cell boundaries and fixed pin locations in standard cell library design. Therefore, the dynamic NOR gate structure in this invention is compact, and has significant advantages in delay and area compared to the traditional aggregation scheme using cascaded standard cells, thus enhancing the response speed of the monitoring system to dynamic IR drop. Specifically: the traditional scheme needs to use multiple levels of logic gates (e.g. cascaded 4-input NOR gate and 2-input AND gate) to implement the aggregation of multiple signals, and the signals need to pass through several levels of gate circuits one after another, each level adding delay. The dynamic NOR gate in the embodiment of this invention compresses this process into one logic level, and all input signals directly "compete" in one evaluation phase, with the shortest transistor path from input to output. According to the post-simulation results, for a dynamic aggregation unit with 8 monitoring unit inputs, this design can reduce the aggregation delay by more than 60% (compared to cascaded 4-input NOR gate and 2-input AND gate).

[0123] The central monitor of this embodiment is deployed at an optimal signal convergence point. To determine this location, first identify multiple IR drop hotspot regions on the chip through dynamic IR drop simulation to guide the deployment of monitoring units. After deployment, an optimization method is used to find an optimal signal convergence point in the low logic density region of the stable voltage domain of the chip. The goal of this optimization method is to make the distribution of the wiring distances from the optimal signal convergence point to each monitoring unit relatively balanced, and the total distance is as low as possible, thus minimizing the inconsistency of signal transmission delay introduced by interconnection line parasitic effects, ensuring monitoring accuracy.

[0124] 2. Specific implementation of adaptive adjustment system

[0125] The central monitor of this embodiment contains a PVT-aware delay pad circuit inside, see Figure 5The delay pad circuit is composed of a series of second buffer chains, which are selected by a second selection circuit (in the specific implementation process, a multiplexer can be selected), and the total delay is controlled by a set of configuration bits. The integrated voltage, temperature, and process corner sensors on the chip provide real-time PVT information, which is input to a small control logic for dynamically adjusting the configuration bits of the multiplexer (MUX). Through a plane fitting function, the control logic can generate corresponding multiplexer (MUX) control bits according to the changes of voltage, temperature, and process corner, so as to offset the effects of global PVT changes and provide a constant length reference delay under different working conditions.

[0126] The clamped pre-warning type timing monitoring unit of the embodiment, with reference to Figure 7 To solve the oscillation problem near the critical voltage point (as shown in the prior art Figure 6 , the clamped pre-warning type timing monitoring unit bypasses two delay length progressive shadow paths from the main functional path: a first shadow path with shorter additional delay and a second shadow path with longer additional delay.

[0127] The main functional path refers to the output of the delay pad circuit directly connected to the data input end of the main flip-flop, and the main flip-flop is a D-type flip-flop (the uppermost DFF in Figure 7 ). There is no additional artificial delay on the main functional path, which represents the normal and fastest signal path.

[0128] Shadow path: "Shadow path" refers to two other paths branching from the same input signal (D) in parallel with the main functional path.

[0129] The circuit of the first shadow path is: the input signal (D) first passes through a first additional delay unit, and then is connected to the data input end of the first shadow flip-flop (the DFF in the second row), and the first shadow flip-flop is a D-type flip-flop.

[0130] The circuit of the second shadow path is: the input signal (D) first passes through another second additional delay unit, and then is connected to the data input end of the second shadow flip-flop (the DFF in the third row), and the second shadow flip-flop is a D-type flip-flop.

[0131] The first additional delay unit and the second additional delay unit are realized by connecting standard logic gates in series, and the most commonly used is a buffer (Buffer) or inverter (Inverter) chain.

[0132] "Short additional delay" is realized by connecting a smaller number of buffers (for example, 3).

[0133] The "long additional delay" is achieved by cascading a larger number of buffers (e.g. 6).

[0134] By comparing the sampling results of the main functional path and the first shadow path, a pre-control signal (PRE-CTRL) is generated. By comparing the sampling results of the main functional path and the second shadow path, a pre-error signal (PRE-ERR) is generated. The combination of these two signals defines three key system operating states: a safe zone (PRE-CTRL = 0, PRE-ERR = 0), an alert zone (PRE-CTRL = 1, PRE-ERR = 0) and a danger zone (PRE-ERR = 1), see Figure 8 . Referring to Figure 9 , the target of the adaptive voltage frequency scaling control logic unit is to precisely "clamp" the operating voltage in the alert zone, achieving smooth voltage scaling and effectively avoiding voltage oscillation. In a specific implementation, the adaptive voltage frequency scaling control logic unit is generally implemented using an AVFS controller.

[0135] The adaptive voltage frequency scaling control unit (i.e. the AVFS controller) of the present embodiment, referring to Figure 10 , adopts a dual-time-scale regulation strategy to cooperatively cope with slow and fast deviation sources.

[0136] Slow voltage scaling (low-power optimization and margin recovery): This scaling makes decisions between two complete workload instances. During the running of an instance, if the system is always in the safe zone (PRE-CTRL = 0), it indicates that the current chip supply voltage is too high, and there is room for voltage reduction. Therefore, before the next instance starts running, the AVFS controller will slowly reduce the chip supply voltage VDD. Conversely, if the system enters the danger zone too frequently and triggers fast frequency scaling (for example, the cumulative occupancy period exceeds 1% of the total period of the instance) in an instance, it indicates that the current chip supply voltage is too low, and the AVFS controller will slowly increase the chip supply voltage VDD before the next instance starts to recover the safe timing margin.

[0137] Fast frequency scaling (risk avoidance): This scaling is performed in real time within a workload instance. If an emergency situation of the pre-error signal (PRE-ERR = 1) occurs instantaneously, indicating that a severe deviation that may cause a timing error has occurred (usually IR pressure drop). At this time, the control logic immediately switches the system clock to a half-frequency clock, doubles the clock period, and provides double the setup time for the data path, thereby immediately avoiding the occurrence of timing errors.

[0138] The final goal of the embodiment is to stabilize the driving system in the "clamping" state of PRE-CTRL=1 and PRE-ERR=0 for most of the running time, so as to eliminate timing violations while compressing the working margin to approach the physical critical point, thereby achieving high energy efficiency operation.

[0139] In the specific implementation process, the AVFS controller generates control instructions and sends them to two other key functional modules on the chip: the power management unit and the clock management unit.

[0140] When the control instruction is sent to the power management unit, it means that the instruction power management unit will increase or decrease the supply voltage VDD by a minimum step.

[0141] When the control instruction is sent to the clock management unit, it means that the instruction clock management unit will immediately switch the system clock to the half-frequency clock in an emergency.

[0142] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the protection scope of the present application.

[0143] The basic principles and main features of the present application and the advantages of the present application have been shown and described above. It should be understood by those skilled in the art that the present application is not limited by the above embodiments, and the above embodiments and descriptions in the specification are only to illustrate the principles of the present application. Without departing from the spirit and scope of the present application, various changes and improvements can be made to the present application, and these changes and improvements all fall within the scope of the claimed present application. The scope of protection of the present application is defined by the appended claims and their equivalents.

Claims

1. A distributed dynamic timing monitoring circuit, comprising: The application relates to a chip real-time longest critical path delay mirror system. The application comprises: a plurality of monitoring units arranged in different IR voltage drop hotspot regions of a chip, each monitoring unit being configured as a delay chain, the delay of which is determined by the local power supply voltage and temperature of the region where the monitoring unit is arranged, and the delay variation of which is designed to be equal to the delay variation of the longest critical path determined by simulation; a dynamic aggregation unit, the input ends of which are connected to the output ends of the monitoring units respectively, for comparing the delays of all input signals in real time and taking the input signal with the longest delay as an output signal; 2. The distributed dynamic timing monitoring circuit of claim 1, wherein, a central monitor arranged in a stable voltage domain of the chip, comprising a configurable delay shim circuit for providing a reference delay; the input end of the delay shim circuit is connected to the output end of the dynamic aggregation unit, and the delay of the input signal with the longest delay is summed with the reference delay to obtain a total delay for mirroring the real-time longest critical path delay of the chip. The monitoring unit comprises: a plurality of first buffers, all of which are connected in series and form a first initial delay chain with taps; 3. The distributed dynamic timing monitoring circuit of claim 1, wherein: a first selection circuit, the data input ends of which are connected to different taps of the first initial delay chain respectively, for selecting different numbers of first buffers as a first final delay chain according to the process corner of the chip and the delay variation of the longest critical path determined by simulation. The delay shim circuit comprises: a plurality of second buffers, all of which are connected in series and form a second initial delay chain with taps; 4. The distributed dynamic timing monitoring circuit of claim 3, wherein: a second selection circuit, the data input ends of which are connected to different taps of the second initial delay chain respectively, for dynamically selecting different numbers of second buffers as a second final delay chain according to the output signal of the on-chip PVT sensor on the chip, and the delay of the second final delay chain is the reference delay. The determination method of the number of second buffers included in the second final delay chain comprises: calculating the configuration bit value of the second selection circuit based on the power supply voltage signal, the process corner and the temperature signal of the chip output by the PVT sensor and a preset compensation function; 5. The distributed dynamic timing monitoring circuit of claim 2 or 3, wherein: directly using the configuration bit value as the selection control signal of the second selection circuit to obtain the number of second buffers included in the second final delay chain.

6. The distributed dynamic timing monitoring circuit of claim 1, wherein, The first buffer and the second buffer are standard logic units adopting an extremely high threshold voltage, an ultrahigh threshold voltage or a high threshold voltage process. The dynamic aggregation unit comprises: a plurality of PMOS tubes, each of which is connected in series and connected to an NMOS tube to form a dynamic NOR circuit, the gate of the first PMOS tube and the gate of the last NMOS tube are connected to the half frequency of the system clock, and the gates of the intermediate PMOS tubes are connected to the output ends of the monitoring units respectively; a plurality of groups of D flip-flops, the clock input ends of each group of D flip-flops are connected to the output end of the dynamic NOR circuit, and the data input ends are connected to the output ends of the corresponding monitoring units; the dynamic NOR circuit and the D flip-flops cooperate to identify the input signal with the longest delay through a circuit competition mechanism and output a one-hot code identifying the source of the input signal with the longest delay.

7. The distributed dynamic timing monitoring circuit of claim 1, wherein, The central monitor is deployed at an optimal signal convergence point, which is obtained by an optimization algorithm, aiming at minimizing the total length of wiring from each monitoring unit to the optimal signal convergence point and equalizing the propagation delay of each monitoring unit signal to the optimal signal convergence point.

8. An adaptive regulation system, characterized by The distributed dynamic timing monitoring circuit comprises: The distributed dynamic timing monitoring circuit according to any one of claims 1-7; The clamped pre-warning timing monitoring unit is connected to the output end of the central monitor, and is used for monitoring the timing margin of the output signal of the delay pad circuit and generating a pre-control signal and a pre-error signal according to different timing margin levels; The adaptive voltage frequency adjustment control logic unit receives the pre-control signal and the pre-error signal, and adjusts the supply voltage or the working frequency of the chip according to the level combination state of the pre-control signal and the pre-error signal.

9. An adaptive conditioning system according to claim 8, wherein, The clamped pre-warning timing monitoring unit comprises: A main flip-flop, which takes the output signal of the delay pad circuit as an input signal; A first shadow path, which comprises a first additional delay unit and a first shadow flip-flop connected in sequence, and takes the output signal of the delay pad circuit as an input signal; A second shadow path, which comprises a second additional delay unit and a second shadow flip-flop connected in sequence, and takes the output signal of the delay pad circuit as an input signal, wherein the delay of the first additional delay unit is smaller than that of the second additional delay unit; The pre-control signal is generated by an exclusive-OR logic comparison between the sampling result of the main flip-flop and the sampling result of the first shadow flip-flop; The pre-error signal is generated by an exclusive-OR logic comparison between the sampling result of the main flip-flop and the sampling result of the second shadow flip-flop.

10. The self-adjusting system of claim 8, wherein, The adaptive voltage frequency adjustment control logic unit adopts a double-time-scale adjustment strategy, specifically comprising: Slow voltage adjustment: after the end of a working load instance, the adjustment direction of the supply voltage is determined according to the cumulative state of the pre-control signal and the pre-error signal, and the supply voltage is gradually adjusted before the start of the next instance; the cumulative state refers to the ratio of the cumulative occupation period of the fast frequency adjustment to the total period of the working load instance; Fast frequency adjustment: during the running of a working load instance, when the pre-error signal is triggered, the working frequency of the chip is immediately reduced.

Images