Memory testing method and device, electronic equipment and computer readable storage medium

Abstract

The invention provides a memory testing method and device, electronic equipment and a computer readable storage medium, and belongs to the technical field of memory testing. The method comprises the following steps: acquiring the number of application cores, and labeling each application core; obtaining a memory test range of a memory to be tested, distributing a plurality of blocks to be tested for each application core according to the memory test range and the number of the application cores, and numbering the distributed blocks to be tested of each application core; according to the mark number of each application core and the serial number of each to-be-tested block, determining a target test algorithm of each to-be-tested block allocated to each application core from at least two preset test algorithms; and executing a corresponding target test algorithm on each distributed to-be-tested block in parallel through each application core, and obtaining a test result of each to-be-tested block. Therefore, each application core runs different types of preset test algorithms in parallel in the allocated to-be-tested block, so that the diversity test of the memory at the same time is realized, the memory test flexibility and accuracy are improved, and the test time is saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory testing, and particularly relates to a memory testing method and device, electronic equipment and a computer readable storage medium. BACKGROUND

[0002] When memory testing is performed in a Unified Extensible Firmware Interface (UEFI) environment, the following three methods can be used: 1. A built-in diagnostic tool of a server or motherboard UEFI firmware is used to perform memory testing. 2. A third-party professional memory testing tool (such as a mainstream testing software Memtest86) is used to perform testing. 3. A UEFI application is used to perform memory testing.

[0003] In the first method, most server and motherboard manufacturers integrate such testing tools. This method is simple to operate and can directly run preset testing algorithms, but it has the limitation of being relatively basic and fixed, and cannot realize algorithm customization or support user self-configuration of memory testing ranges. The second method uses a professional memory testing tool, which has the advantage of integrating multiple testing algorithms and can meet regular testing requirements. However, it also has the defect of fixed functions. If custom configuration of the memory testing range is required, the source code authorization of Memtest86 must be obtained, which not only has high costs, but also faces continuous huge investment in subsequent software updates and maintenance. In addition, the development schedule and technical route will be subject to the supplier. In the third method, the system is in a single-core mode, and multiple memory testing algorithms can be simply executed in sequence in a single-core serial mode to verify the basic memory business logic. In summary, the existing memory testing scheme has the problem of single testing. SUMMARY

[0004] To solve the above technical problems, the present application provides a memory testing method, device, electronic equipment and computer readable storage medium.

[0005] In a first aspect, the present application provides a memory testing method, which comprises: obtaining an application core number, and labeling each application core; obtaining a memory testing range of a to-be-tested memory, allocating multiple to-be-tested blocks to each application core according to the memory testing range and the application core number, and numbering each to-be-tested block allocated to each application core; determine a target test algorithm of each of the to-be-tested blocks to which each of the application cores is assigned from at least two preset test algorithms according to the index of each of the application cores and the serial number of each of the to-be-tested blocks; wherein the target test algorithms of two adjacent to-be-tested blocks to which each of the application cores is assigned are different; perform the corresponding target test algorithm on each of the assigned to-be-tested blocks in parallel by each of the application cores, and obtain a test result of each of the to-be-tested blocks.

[0006] In an optional implementation, the indexing of each of the application cores comprises: alternately indexing each of the application cores with a first preset index and a second preset index, or continuously indexing each of the application cores.

[0007] In an optional implementation, the numbering of each of the to-be-tested blocks to which each of the application cores is assigned comprises: continuously numbering each of the to-be-tested blocks to which each of the application cores is assigned.

[0008] In an optional implementation, the at least two preset test algorithms comprise a first test algorithm and a second test algorithm. In the case of alternately indexing each of the application cores with a first preset index and a second preset index, the determining of the target test algorithm of each of the to-be-tested blocks to which each of the application cores is assigned from at least two preset test algorithms according to the index of each of the application cores and the serial number of each of the to-be-tested blocks comprises: in the case of the index of the current application core being the first preset index and the serial number of the to-be-tested block of the current application core being even, or in the case of the index of the current application core being the second preset index and the serial number of the to-be-tested block of the current application core being odd, determining the first test algorithm or the second test algorithm as the target test algorithm; in the case of the index of the current application core being the second preset index and the serial number of the to-be-tested block of the current application core being even, or in the case of the index of the current application core being the first preset index and the serial number of the to-be-tested block of the current application core being odd, determining the second test algorithm or the first test algorithm as the target test algorithm.

[0009] In an optional implementation, the number of preset test algorithms is N. The determining of the target test algorithm of each of the to-be-tested blocks to which each of the application cores is assigned from at least two preset test algorithms according to the index of each of the application cores and the serial number of each of the to-be-tested blocks comprises: In a case where each of the application cores is a continuous index, the target test algorithm of each of the to-be-tested blocks of each of the application cores is determined in a preset execution order of the N preset test algorithms.

[0010] In an optional embodiment, the preset execution order of the N preset test algorithms corresponding to the two adjacent application cores is different.

[0011] In an optional embodiment, the allocating a plurality of to-be-tested blocks to each of the application cores according to the memory test range and the number of the application cores comprises: determining a block size of the to-be-tested blocks according to the memory test range and the number of the application cores; allocating a plurality of the to-be-tested blocks to each of the application cores according to the block size.

[0012] In a second aspect, the present application provides a memory testing device, which comprises: an obtaining module, configured to obtain a number of application cores and label each of the application cores; an allocating module, configured to obtain a memory test range of a to-be-tested memory, allocate a plurality of to-be-tested blocks to each of the application cores according to the memory test range and the number of the application cores, and number each of the to-be-tested blocks allocated to each of the application cores; a determining module, configured to determine a target test algorithm of each of the to-be-tested blocks allocated to each of the application cores from at least two preset test algorithms according to the index of each of the application cores and the serial number of each of the to-be-tested blocks; wherein the target test algorithm of two adjacent to-be-tested blocks allocated to each of the application cores is different; a parallel executing module, configured to execute the corresponding target test algorithm on each of the allocated to-be-tested blocks in parallel by each of the application cores in parallel, and obtain a test result of each of the to-be-tested blocks.

[0013] In a third aspect, the present application provides an electronic device, which comprises a memory and a processor, wherein the memory stores a computer program, and the computer program executes the memory testing method of any one of the preceding embodiments when the processor runs.

[0014] In a fourth aspect, the present application provides a computer readable storage medium, which stores a computer program, and the computer program executes the memory testing method of any one of the preceding embodiments when running on a processor.

[0015] The memory test method provided in the application comprises the following steps: obtaining the number of application cores, and labeling each application core; obtaining a memory test range of a to-be-tested memory, and allocating a plurality of to-be-tested blocks to each application core according to the memory test range and the number of application cores; numbering each to-be-tested block allocated to each application core; determining a target test algorithm of each to-be-tested block allocated to each application core from at least two preset test algorithms according to the label of each application core and the serial number of each to-be-tested block; wherein the target test algorithms of two adjacent to-be-tested blocks allocated to each application core are different; and performing the corresponding target test algorithm on each allocated to-be-tested block in parallel through each application core, and obtaining the test result of each to-be-tested block. In this way, each application core runs different categories of preset test algorithms in parallel on the allocated to-be-tested blocks, ensures that each application core can effectively run different categories of preset test algorithms, realizes the diversity test of the memory at the same time, improves the flexibility and accuracy of the memory test, and saves the test time. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the present application, the drawings needed in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope of protection of the present application. In each drawing, similar components are denoted by similar reference numerals.

[0017] Figure 1 A flowchart of the memory test method provided in the present application is shown; Figure 2 Another flowchart of the memory test method provided in the present application is shown; Figure 3 A parallel test schematic diagram of a single test algorithm provided in the present application is shown; Figure 4 A parallel test schematic diagram of two test algorithms provided in the present application is shown; Figure 5 A parallel test schematic diagram of three test algorithms provided in the present application is shown; Figure 6 A structural schematic diagram of the memory test device provided in the present application is shown. DETAILED DESCRIPTION

[0018] The technical solutions in the present application will be described in detail below with reference to the drawings in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments.

[0019] The components of the application described and illustrated herein can be arranged and designed in a wide variety of different configurations. Therefore, the following detailed description of the embodiments of the application, as provided in the accompanying drawings, is not intended to limit the scope of the application, but merely represent selected embodiments of the application. All other embodiments not explicitly described or shown herein are within the scope of the application.

[0020] Hereinafter, the terms "include", "have", and their conjugates, used in the various embodiments of the present application, merely indicate the presence of the features, numbers, steps, operations, elements, components, or combinations thereof, and do not exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0021] In addition, the terms "first", "second", "third", and the like are used only to distinguish descriptions, and are not to be understood as indicating or implying relative importance.

[0022] Unless otherwise defined, all terms used herein (including technical terms and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present application belong. The terms (such as terms defined in a generally used dictionary) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having idealized or overly formal meanings, unless clearly defined in various embodiments of the present application.

[0023] Embodiment 1 The present application provides a memory test method, which is used for UEFI multi-application core parallel mode, each application core runs different categories of preset test algorithms in parallel, ensures that each application core can effectively run different categories of preset test algorithms, solves the problem of single test existing in the existing memory test scheme, realizes the diversity test of memory at the same time, and improves the flexibility of memory test.

[0024] Referring to Figure 1 , the memory test method comprises: Step S101, obtaining the number of application cores, and labeling each application core.

[0025] In this embodiment, the Bootstrap Processor (BSP) obtains the number of Application Processors (APs). The number of application cores is determined according to actual conditions, for example, the number of application cores is 2, 3, or N, which is not limited herein. Each application core can be labeled according to a preset labeling manner.

[0026] In an embodiment, the step of labeling each application core comprises: alternately labeling each application core with a first preset label and a second preset label, orcontinuously labeling each application core.

[0027] In the embodiment, the first preset label and the second preset label can be different values, for example, the first preset label is 0 and the second preset label is 1, or other different values, which are not limited herein. If there are three application cores, a first application core, a second application core and a third application core, the first application core can be labeled as 1, the second application core as 0 and the third application core as 1, or the first application core can be labeled as 0, the second application core as 1 and the third application core as 0.

[0028] In the embodiment, each application core can be continuously numbered from 0, for example, if there are three application cores, a first application core, a second application core and a third application core, the first application core can be labeled as 0, the second application core as 1 and the third application core as 2, or the numbering can start from 1 or 2, for example, the first application core can be labeled as 2, the second application core as 3 and the third application core as 4, which are not limited herein.

[0029] In step S102, a memory test range of a memory to be tested is obtained, and a plurality of test blocks are allocated to each application core according to the memory test range and the number of application cores, and each test block allocated to each application core is numbered.

[0030] In the embodiment, the memory test range of the memory to be tested can be all or part of the capacity range of the memory to be tested, which is determined according to actual conditions. In this way, the memory to be tested is divided into a plurality of blocks for memory testing, which can greatly save testing time.

[0031] In an embodiment, the step of allocating a plurality of test blocks to each application core according to the memory test range and the number of application cores comprises: determining a block size of the test blocks according to the memory test range and the number of application cores; and allocating a plurality of test blocks to each application core according to the block size.

[0032] For example, a BSP obtains a memory test range and a number of application cores, determines a block size (BlockSize) according to the memory test range and the number of application cores, and allocates a test block to each application core according to the block size.

[0033] In an embodiment, the step of numbering each test block allocated to each application core comprises: Each of the to-be-tested blocks allocated to each of the application cores is sequentially numbered.

[0034] For example, N to-be-tested blocks are allocated to each of the application cores according to the memory test range and the number of the application cores, and the serial numbers of the N to-be-tested blocks can be 0, 1, 2, …, N-1.

[0035] In step S103, a target test algorithm of each to-be-tested block allocated to each of the application cores is determined from at least two preset test algorithms according to the serial number of each to-be-tested block and the label of each of the application cores, wherein the target test algorithms of two adjacent to-be-tested blocks allocated to each of the application cores are different.

[0036] In an embodiment, the memory boosting manners of different preset test algorithms are different. It can be understood that the core idea of memory testing is to increase the pressure on the memory to find potential problems. The preset test algorithms have the following manners of increasing pressure: 1, changing background data, 2, addressing manner, 3, increasing forced write instruction (WriteThrough), 4, controlling Block Size, 5, simulating physical address access memory, 6, increasing the frequency and complexity of memory access. A single algorithm will only focus on one point, and if only a single preset test algorithm is used, there will be a single test problem that only targets a certain test point. By running different preset test algorithms in parallel at the same time, multiple tasks can be simulated, multiple pressure modes can be combined, and the characteristics of mixed loads in a multi-task concurrent scenario can be simulated, and more accurate test results can be obtained.

[0037] In an embodiment, the at least two preset test algorithms include a first test algorithm and a second test algorithm. In the case of alternately labeling each of the application cores with a first preset label and a second preset label, the target test algorithm of each to-be-tested block allocated to each of the application cores is determined from at least two preset test algorithms according to the serial number of each to-be-tested block and the label of each of the application cores, including: In the case that the label of the current application core is the first preset label and the serial number of the current to-be-tested block of the current application core is even, or in the case that the label of the current application core is the second preset label and the serial number of the current to-be-tested block of the current application core is odd, the first test algorithm or the second test algorithm is determined as the target test algorithm. In a case that the label of the current application core is the second preset label and the number of the current block to be tested of the current application core is even, or in a case that the label of the current application core is the first preset label and the number of the current block to be tested of the current application core is odd, the second test algorithm or the first test algorithm is determined as the target test algorithm.

[0038] Referring to Figure 2 , assuming that the first test algorithm is represented by PatternA and the second test algorithm is represented by PatternB, the corresponding memory test process is as follows: Step S1, acquiring PatternA and PatternB.

[0039] It can be understood that PatternA and PatternB are both used to call different algorithms by using the same interface, for example as follows: int Sample_Pattern( IN EFI_PHYSICAL_ADDRESS Addr,IN UINT64 Size,INUINT64 Tester_id,IN VOIDTest_params) The parameters are as follows: Add represents the starting address of the test memory to be allocated; Size represents the size of the test region, i.e. BlockSize; Tester_id represents the application core for testing the current memory region; Test_params represents the test parameter configuration. In this embodiment, different prediction test algorithms are called to run in the above manner.

[0040] Step S2, determining the number of application cores.

[0041] In this embodiment, the number of Application Processors (AP) cores is acquired by the BSP. If there are N application cores, which are the first application core, the second application core,..., and the Nth application core, the N application cores are labeled respectively, the first application core is represented by 0, the second application core is represented by 1, the third application core is represented by 0, the fourth application core is represented by 1, and so on, 0, 1, 0, 1, and so on, are used to label the N application cores.

[0042] Step S3, allocating blocks to be tested according to the memory test range and the number of application cores.

[0043] For example, if each application core can allocate N blocks to be tested (Block), the block number (BlockNum) can be sequentially ordered, for example, from 0 to n-1 (counting from 0).

[0044] Step S4, judging the label of each application core and the serial number of each block to be tested, determining the corresponding target test algorithm.

[0045] Step S5, in the case that the label of the current application core is 0 and the serial number of the current block to be tested of the current application core is even, determining the target test algorithm as Pattern A and running Pattern A.

[0046] Step S6, in the case that the label of the current application core is 1 and the serial number of the current block to be tested of the current application core is even, determining the target test algorithm as Pattern B and running Pattern B.

[0047] Step S7, in the case that the label of the current application core is 0 and the serial number of the current block to be tested of the current application core is odd, running Pattern B.

[0048] Step S8, in the case that the label of the current application core is 1 and the serial number of the current block to be tested of the current application core is odd, running Pattern A.

[0049] Step S9, judging whether there is an unprocessed block to be tested.

[0050] In the embodiment, if there is an unprocessed block to be tested, steps S4-S8 are executed to continue the allocation and execute the corresponding Pattern A or Pattern B. If there is no block to be processed, the process ends.

[0051] Referring to Figure 3 , the BSP first acquires the memory test range, then acquires the number of application cores, such as Core 0, Core 1, …, Core n, allocates the current memory test range to each application core, and configures the block size of the block to be tested in each application core. Figure 3 In the embodiment, the application core Core 0 runs Pattern A, the application cores Core 1, …, Core N-1 also run Pattern A, and the memory test is performed on different blocks. From the serial running algorithm to the parallel running algorithm, but at the same time, only a single Pattern A is run, and different categories of test algorithms cannot be compatible at the same time.

[0052] In a real server running environment, various application programs are executed simultaneously, and various memory access operations are performed. In a long running process, the data transformation mode and the address access sequence present a complex superposition effect in a long running process. Current mainstream memory test schemes are mostly based on preset fixed access modes, and it is difficult to simulate the mixed load characteristics in the multi-task concurrent scene. The multi-task concurrent mixed scene can be simulated by running different algorithms in parallel time, and the existing memory test schemes do not cover this, which is the problem of single test scene of the existing memory test software.

[0053] Referring to Figure 4 In Figure 4 , the application core with label 0 runs PatternA on the even-numbered blocks to be tested, and the application core with label 1 runs PatternB on the even-numbered blocks to be tested. The application core with label 0 runs PatternB on the odd-numbered blocks to be tested; and the application core with label 1 runs PatternA on the odd-numbered blocks to be tested. At the same time, two different algorithms PatternA and PatternB are run in parallel.

[0054] In this embodiment, the blocks to be tested of the memory to be tested are run in parallel according to the odd blocks and the even blocks in terms of block number. Different test algorithms are used to test different test errors in a shorter test time, improve the error catching efficiency, and make the test results more consistent with the actual application scene.

[0055] In an embodiment, the number of preset test algorithms is N; and the target test algorithm of each block to be tested allocated to each application core is determined from at least two preset test algorithms according to the label of each application core and the serial number of each block to be tested, comprising: In the case where each application core has a continuous label, the target test algorithm of each block to be tested of each application core is determined in turn according to the preset execution order of the N preset test algorithms.

[0056] In an embodiment, the preset execution order of the N preset test algorithms corresponding to the adjacent two application cores is different.

[0057] In this embodiment, not only two algorithms are configured according to the memory odd and even blocks, but also multiple parallel algorithms can be configured, and the maximum configurable number is usually determined by the number of application cores. For example, three preset test algorithms are configured to run in parallel, which can be configured according to the following Figure 5The preset test algorithms are Pattern A, Pattern B and Pattern C, and the preset execution order of Pattern A, Pattern B and Pattern C can be Pattern A-Pattern B-Pattern C, Pattern B-Pattern C-Pattern A, Pattern C-Pattern A-Pattern B, and the like, which is not limited herein. Referring to Figure 5 The number of the to-be-tested blocks allocated to each application core can be a multiple of 3 or a non-multiple of 3. For the application core with the label 0, the to-be-tested blocks with the serial numbers divisible by 3 run Pattern A, the to-be-tested blocks with the serial numbers divisible by 3 with a remainder of 1 run Pattern B, and the to-be-tested blocks with the serial numbers divisible by 3 with a remainder of 2 run Pattern C. For the application core with the label 1, the to-be-tested blocks with the serial numbers divisible by 3 run Pattern B, the to-be-tested blocks with the serial numbers divisible by 3 with a remainder of 1 run Pattern C, and the to-be-tested blocks with the serial numbers divisible by 3 with a remainder of 2 run Pattern A. For the application core with the label 2, the to-be-tested blocks with the serial numbers divisible by 3 run Pattern C, the to-be-tested blocks with the serial numbers divisible by 3 with a remainder of 1 run Pattern A, and the to-be-tested blocks with the serial numbers divisible by 3 with a remainder of 2 run Pattern B.

[0058] In the embodiment, not only the odd and even blocks of the to-be-tested blocks split according to the memory run two algorithms in parallel, but also multiple algorithms can be run in parallel to simulate more running scenarios and improve the accuracy of the test.

[0059] It can be understood that the memory test is not simply reading and writing the memory, and the stress on the memory should be increased as much as possible to find potential problems. At the same time, because the test time is the cost, it is necessary to improve the efficiency of the test and the efficiency of the error detection as much as possible. Different preset test algorithms have different emphases, and have different running times. When multiple preset test algorithms are executed in parallel, it may cause an application core to run after other application cores are running. At this time, the application core that completes first has to wait for the application core that completes later, causing a waste of time. For example, Pattern A test 1G memory needs 60 seconds, and Pattern B test 1G memory needs 600 seconds. Assuming that there are 2 application cores executing Pattern A and Pattern B in parallel, without internal splitting, the first application core completes Pattern A in 60 seconds, and then it is idle waiting for the end of Pattern B of the second application program. Finally, they take 600 seconds together. If the 1G memory is divided into 2 blocks, each block is 0.5G, the first application core runs Pattern A on the first block for 30 seconds and runs Pattern B for 300 seconds; the second application core runs Pattern B on the first block for 300 seconds and runs Pattern A on the second block for 30 seconds; finally, they take 330 seconds together, which saves the test time and improves the efficiency of the test.

[0060] In this way, in the UEFI environment, the parallel execution of different preset test algorithms by multiple application cores can apply different test pressures to the memory through different preset test algorithms, which not only simulates the scenario of concurrent access to the memory by multiple different types of applications, but also simulates the scenario of access in different application cores, thereby improving the scenario richness of the memory test.

[0061] In step S104, the target test algorithm corresponding to each allocated test block is executed in parallel by each application core, and the test result of each test block is obtained.

[0062] In the early stage of system startup, the requirement of running different memory test algorithms in parallel at the same time is realized. Because different memory test algorithms have different test emphases, different test pressures are applied to the memory at the same time. When the different application cores perform memory test in the test block, the memory error information of the test can be uniformly sent to the BSP, and the BSP actively outputs the error information of each application core. When multiple application cores execute complex algorithm business logic in parallel, the master core (i.e., the BSP) can concurrently output the memory error information monitored by each application core in different memory test algorithms, thereby solving the resource competition problem.

[0063] The memory test method provided in the embodiment comprises the following steps: obtaining the number of application cores, and labeling each application core; obtaining a memory test range of a memory to be tested, and allocating a plurality of test blocks to each application core according to the memory test range and the number of application cores; numbering each test block allocated to each application core; determining a target test algorithm of each test block allocated to each application core from at least two preset test algorithms according to the label of each application core and the serial number of each test block; wherein the target test algorithms of two adjacent test blocks allocated to each application core are different; and executing the corresponding target test algorithm on each allocated test block in parallel through each application core, and obtaining the test result of each test block. In this way, each application core runs different categories of preset test algorithms on the allocated test blocks in parallel, which ensures that each application core can effectively run different categories of preset test algorithms, realizes the diversity test of the memory at the same time, improves the flexibility and accuracy of the memory test, and saves the test time.

[0064] Embodiment 2 In addition, the application provides a memory test device.

[0065] As shown in Figure 6 The memory test device 600 comprises: An obtaining module 601, configured to obtain the number of application cores, and label each application core; An allocating module 602, configured to obtain a memory test range of a memory to be tested, and allocate a plurality of test blocks to each application core according to the memory test range and the number of application cores, and number each test block allocated to each application core; A determining module 603, configured to determine a target test algorithm of each test block allocated to each application core from at least two preset test algorithms according to the label of each application core and the serial number of each test block; wherein the target test algorithms of two adjacent test blocks allocated to each application core are different; A parallel executing module 604, configured to execute the corresponding target test algorithm on each allocated test block in parallel through each application core in parallel, and obtain the test result of each test block.

[0066] In an embodiment, the obtaining module 601 is further configured to alternately label each application core with a first preset label and a second preset label, or continuously label each application core.

[0067] In an embodiment, the allocating module 602 is further configured to continuously number each test block allocated to each application core.

[0068] In an embodiment, the at least two preset test algorithms include a first test algorithm and a second test algorithm; the assigning module 602 is further configured to determine a block size of the to-be-tested block according to the memory test range and the number of application cores; The block size is used to assign a plurality of to-be-tested blocks to each of the application cores.

[0069] In an embodiment, the at least two preset test algorithms include a first test algorithm and a second test algorithm; the determining module 603 is further configured to, in a case where each of the application cores is alternately labeled with a first preset label and a second preset label, determine the first test algorithm or the second test algorithm as the target test algorithm in a case where a label of a current application core is the first preset label and a number of a current to-be-tested block of the current application core is even, or in a case where the label of the current application core is the second preset label and the number of the current to-be-tested block of the current application core is odd. In a case where a label of a current application core is the second preset label and a number of a current to-be-tested block of the current application core is even, or in a case where the label of the current application core is the first preset label and the number of the current to-be-tested block of the current application core is odd, the second test algorithm or the first test algorithm is determined as the target test algorithm.

[0070] In an embodiment, the number of preset test algorithms is N; the determining module 603 is further configured to, in a case where each of the application cores is a continuous label, determine the target test algorithm of each to-be-tested block of each of the application cores in a preset execution order of N preset test algorithms.

[0071] In an embodiment, preset execution orders of N preset test algorithms corresponding to two adjacent application cores are different.

[0072] In an embodiment, the assigning module 602 is further configured to determine a block size of the to-be-tested block according to the memory test range and the number of application cores; The block size is used to assign a plurality of to-be-tested blocks to each of the application cores.

[0073] The memory testing device 500 provided by the embodiment can implement the memory testing method provided by Embodiment 1, and thus details are not repeated here.

[0074] The memory testing device provided in the embodiment obtains the number of application cores, and labels each application core; obtains a memory testing range of a memory to be tested, allocates a plurality of testing blocks to each application core according to the memory testing range and the number of application cores, and numbers each testing block allocated to each application core; determines a target testing algorithm of each testing block allocated to each application core from at least two preset testing algorithms according to the label of each application core and the serial number of each testing block; wherein the target testing algorithms of two adjacent testing blocks allocated to each application core are different; each application core executes the corresponding target testing algorithm on each allocated testing block in parallel, and obtains the testing result of each testing block. In this way, each application core runs different categories of preset testing algorithms on the allocated testing blocks in parallel, ensures that each application core can effectively run different categories of preset testing algorithms, realizes the diversity testing of the memory at the same time, improves the flexibility and accuracy of the memory testing, and saves the testing time.

[0075] Embodiment 3 In addition, the present application provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the computer program executes the memory testing method provided in embodiment 1 when running on the processor.

[0076] The electronic device provided in the embodiment can implement the memory testing method provided in embodiment 1, and thus the details are not repeated here.

[0077] Embodiment 4 The present application also provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program implements the memory testing method provided in embodiment 1 when executed by a processor.

[0078] In the embodiment, the computer readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0079] The computer readable storage medium provided in the embodiment can implement the memory testing method provided in embodiment 1, and thus the details are not repeated here.

[0080] It should be noted that, in the present document, the terms "comprises / comprising" or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0081] From the above description of the embodiments, it is clear that the above-mentioned method can be realized by means of software and a necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, or optical disk) and includes a number of instructions for causing a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present application.

[0082] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-described specific embodiments, and the above-described specific embodiments are merely illustrative rather than limiting. Those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope of protection of the claims.

Claims

1. A memory testing method, characterized in that, The method includes: Obtain the number of application cores and label each application core; Obtain the memory test range of the memory to be tested, allocate multiple test blocks to each application core according to the memory test range and the number of application cores, and number each test block allocated to each application core. Based on the label of each application core and the sequence number of each test block, the target test algorithm for each test block assigned to each application core is determined from at least two preset test algorithms; wherein the target test algorithms for two adjacent test blocks assigned to each application core are different. The target test algorithm is executed in parallel on each of the assigned test blocks by each application core, and the test results of each test block are obtained.

2. The method according to claim 1, characterized in that, The labeling of each application core includes: Each of the application cores is alternately labeled using a first preset label and a second preset label, or... Each application core is sequentially numbered.

3. The method according to claim 2, characterized in that, The step of numbering the test blocks allocated to each of the application cores includes: Each of the test blocks assigned to each of the application cores is sequentially numbered.

4. The method according to claim 3, characterized in that, At least two preset test algorithms, including a first test algorithm and a second test algorithm; When each application core is alternately labeled with a first preset label and a second preset label, the step of determining the target test algorithm for each application core assigned to each test block from at least two preset test algorithms, based on the label of each application core and the sequence number of each test block, includes: If the label of the current application core is the first preset label and the number of the current test block of the current application core is even, or if the label of the current application core is the second preset label and the number of the current test block of the current application core is odd, the first test algorithm or the second test algorithm is determined as the target test algorithm. If the current application core is labeled with the second preset label and the current test block number of the current application core is even, or if the current application core is labeled with the first preset label and the current test block number of the current application core is odd, the second test algorithm or the first test algorithm is determined as the target test algorithm.

5. The method according to claim 3, characterized in that, The number of preset test algorithms is N; The step of determining the target test algorithm for each application core assigned to each test block from at least two preset test algorithms, based on the label of each application core and the sequence number of each test block, includes: When the application cores are numbered consecutively, the target test algorithm for each block to be tested in each application core is determined sequentially according to the preset execution order of N preset test algorithms.

6. The method according to claim 5, characterized in that, The preset execution order of the N preset test algorithms corresponding to two adjacent application cores is different.

7. The method according to claim 1, characterized in that, The process of allocating multiple test blocks to each application core based on the memory test range and the number of application cores includes: The block size of the block to be tested is determined based on the memory test range and the number of application cores; Multiple test blocks are allocated to each application core according to the block size.

8. A memory testing device, characterized in that, The device includes: The acquisition module is used to obtain the number of application cores and label each application core. The allocation module is used to obtain the memory test range of the memory to be tested, allocate multiple test blocks to each application core according to the memory test range and the number of application cores, and number each test block allocated to each application core. The determining module is configured to determine the target test algorithm for each application core assigned to each test block from at least two preset test algorithms, based on the label of each application core and the sequence number of each test block; wherein the target test algorithms for two adjacent test blocks assigned to each application core are different. The parallel execution module is used to execute the corresponding target test algorithm in parallel on each of the allocated test blocks through each of the application cores, and to obtain the test results of each of the test blocks.

9. An electronic device, characterized in that, The device includes a memory and a processor, wherein the memory stores a computer program that executes the memory testing method according to any one of claims 1 to 7 when the processor is running.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when run on a processor, executes the memory testing method according to any one of claims 1 to 7.

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