Back contact solar cell, preparation method thereof and photovoltaic module

Abstract

The invention discloses a back contact solar cell, a preparation method thereof and a photovoltaic module, and relates to the field of photovoltaic technology. According to the preparation method of the back contact solar cell provided by the invention, the grid line groove is formed in the first passivation layer by using the deep ultraviolet laser, and the deep ultraviolet laser has relatively high photon energy which is higher than chemical bond energy of a passivation layer material, so that chemical bonds can be broken through a photochemical effect instead of depending on a thermal effect to melt the material. The heat affected zone of deep ultraviolet laser grooving is small, generated thermal stress is small, and edge warping of the first passivation layer caused by thermal expansion difference can be restrained. The metal seed layer formed through subsequent deposition can be well attached to the inner surface of the grid line groove and the outer surface of the first passivation layer in the grid line area, the metal seed layer is good in integrity and has good adhesive force, and the manufactured back contact solar cell has good reliability and cell performance.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and more specifically, to back-contact solar cells, their fabrication methods, and photovoltaic modules. Background Technology

[0002] In laser grooving technology, copper is typically used as the metal seed layer. A laser is first used to groove the solar cell, removing the passivation layer in a localized area to expose the underlying doped polysilicon. A seed layer is then deposited on the laser-grooved surface. However, during laser grooving, uneven laser energy causes the passivation layer at the groove edge to warp. When depositing the metal seed layer, the warped area cannot be covered, leaving the doped polysilicon layer exposed and without metal to collect charge carriers. Furthermore, during etching the metal seed layer, the etching solution enters the interface between the metal seed layer and the doped polysilicon layer through the gaps, affecting the adhesion of the metal seed layer. Therefore, the difficulty in overcoming the passivation layer edge warping problem during laser grooving negatively impacts the reliability and performance of back-contact solar cells.

[0003] Therefore, this application is hereby submitted. Summary of the Invention

[0004] The purpose of this application is to provide a back-contact solar cell, a method for its fabrication, and a photovoltaic module, which can improve the reliability and performance of the back-contact solar cell.

[0005] This application is implemented as follows: In a first aspect, this application provides a method for fabricating a back-contact solar cell, comprising: A battery substrate is obtained, comprising a silicon substrate, a doped polysilicon layer, and a first passivation layer covering the surface of the doped polysilicon layer. The battery substrate has a gate line region and a non-gate line region. A gate trench is created on the first passivation layer in the gate region using a deep ultraviolet laser, and the bottom of the gate trench exposes a doped polysilicon layer. A metal seed layer is deposited in the gate line region, which covers the inner wall of the gate line trench and the outer surface of the first passivation layer in the gate line region. Conductive wires are welded onto a metal seed layer.

[0006] In an optional implementation, the wavelength of the deep ultraviolet laser is 250nm~280nm.

[0007] In an optional implementation, the pulse width of the deep ultraviolet laser is less than 100 ps.

[0008] In an optional implementation, the energy density of the deep ultraviolet laser is 230 mJ / cm². 2 ~300mJ / cm 2 .

[0009] In an optional implementation, the step of depositing a metal seed layer in the gate line region includes: Deposit a metal seed layer in the grid line region and at least part of the non-grid line region; Create a metal seed layer that covers the gate line area using a mask, and then etch away the metal seed layer in the non-gate line areas. Remove the mask.

[0010] In an optional implementation, the metal seed layer is deposited using the following method: A copper diffusion barrier layer was deposited on the battery substrate using magnetron sputtering. A copper layer is deposited on a copper diffusion barrier layer using magnetron sputtering, and the copper layer and the copper diffusion barrier layer together form a metal seed layer.

[0011] In an optional embodiment, the welding temperature is less than 200°C during the step of welding the conductive wire onto the metal seed layer.

[0012] Secondly, this application provides a back-contact solar cell, comprising: The battery substrate includes a silicon substrate, a doped polycrystalline silicon layer, a first passivation layer covering the surface of the doped polycrystalline silicon layer, and a second passivation layer covering the front side of the silicon substrate. The battery substrate has a gate line region and a non-gate line region. Gate trench, the gate trench is located in the gate area, and the bottom of the gate trench exposes the doped polysilicon layer; A metal seed layer covers the inner wall of the gate trench and the outer surface of the first passivation layer in the gate region. The conductive wire is connected to the metal seed layer by welding to form a conductive connection. in, The angle between the edge of the first passivation layer near the gate trench and the doped polysilicon layer is 0°. The doped polysilicon layer includes an n-type doped polysilicon layer and a p-type doped polysilicon layer located on the back side of the silicon substrate. A tunneling oxide layer is provided between the n-type doped polysilicon layer and the silicon substrate, and between the p-type doped polysilicon layer and the silicon substrate. The n-type doped polysilicon layer and the p-type doped polysilicon layer are separated by an isolation trench. The side of the n-type doped polysilicon layer and the p-type doped polysilicon layer facing away from the silicon substrate and the inner wall of the isolation trench are covered with a first passivation layer.

[0013] In an optional implementation, the width of the grid trench is 20~50μm.

[0014] In an optional implementation, the thickness of the metal seed layer is 150 nm to 600 nm.

[0015] In an optional embodiment, the metal seed layer includes a copper diffusion barrier layer; The copper diffusion barrier layer contains 90 wt.% to 95 wt.% aluminum, with the balance being at least one of Ni, Cr, W, Ti, NiCr, NiW, TiW, and NiMo.

[0016] In an alternative implementation, conductive wires fill the gate trenches and cover them with a metal seed layer.

[0017] In an optional embodiment, the portion of the conductive wire outside the gate trench has two slopes arranged at an angle, the two slopes meeting at the end of the conductive wire away from the silicon substrate. The angle between the two slopes is 55° to 65°.

[0018] In an optional embodiment, the width of the conductive wire is 30μm to 50μm, wherein the width direction of the conductive wire is consistent with the width direction of the gate trench. The conductive wire protrudes from the outer surface of the first passivation layer at a height of 10μm~15μm along the thickness direction of the battery substrate.

[0019] Thirdly, this application provides a photovoltaic module, including the back-contact solar cell of the aforementioned embodiments.

[0020] This application has the following beneficial effects: The method for fabricating a back-contact solar cell provided in this application includes: obtaining a cell substrate, the cell substrate comprising a silicon substrate, a doped polycrystalline silicon layer, and a first passivation layer covering the surface of the doped polycrystalline silicon layer, the cell substrate having a grid line region and a non-grid line region; using a deep ultraviolet picosecond laser to form grid line trenches on the first passivation layer in the grid line region, the bottom of the grid line trenches exposing the doped polycrystalline silicon layer; depositing a metal seed layer in the grid line region, the metal seed layer covering the inner wall of the grid line trenches and the outer surface of the first passivation layer in the grid line region; and welding conductive wires onto the metal seed layer. The method for fabricating a back-contact solar cell provided in this application uses a deep ultraviolet laser to form grid line trenches on the first passivation layer. The deep ultraviolet laser has high photon energy, higher than the chemical bond energy of the passivation layer material, thus breaking chemical bonds through photochemical action rather than relying on thermal effects to melt the material. Using a deep ultraviolet laser to form the trenches results in a small heat-affected zone and low thermal stress, which can suppress edge warping of the first passivation layer caused by differences in thermal expansion. Furthermore, the passivation layer material has an extremely high absorption coefficient for deep ultraviolet lasers and a shallow absorption depth. Therefore, the side of the first passivation layer closest to the doped polysilicon layer does not accumulate much heat, and thus it is less prone to warping upwards due to thermal expansion. The fabrication method provided in this application ensures that the angle between the edge of the first passivation layer and the doped polysilicon layer is 0°, allowing the edge of the first passivation layer to adhere as closely as possible to the doped polysilicon layer. Therefore, the deposited metal seed layer adheres well to the inner surface of the gate trench and the outer surface of the first passivation layer in the gate region, exhibiting good integrity (i.e., no cracks). There is almost no gap between the edge of the first passivation layer and the doped polysilicon layer, and the adhesion between the metal seed layer and the doped polysilicon layer is good, making it difficult for the etching solution used in the wet etching process to enter the gaps and penetrate between the metal seed layer and the doped polysilicon layer. This ensures that the metal seed layer has excellent adhesion. Therefore, the back-contact solar cell provided in this application has better reliability and battery performance. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A scanning electron microscope image of the existing process after laser-driven grid trenching; Figure 2 This is a scanning electron microscope image of the metal seed layer deposited in the existing process; Figure 3This is a flowchart of a method for preparing a back-contact solar cell in one embodiment of this application; Figure 4 This is a partial cross-sectional view of the battery substrate in one embodiment of this application; Figure 5 This is a schematic diagram of the grid trench after it is opened in one embodiment of this application; Figure 6 This is a scanning electron microscope image of the battery substrate after the grid trenches have been formed in one embodiment of this application; Figure 7 This is a schematic diagram of the gate line region after depositing a metal seed layer in one embodiment of this application; Figure 8 This is a schematic diagram of a metal seed layer covering the mask-covered grid line region in one embodiment of this application; Figure 9 This is a schematic diagram of the metal seed layer in the non-gate area after it has been removed in one embodiment of this application; Figure 10 This is a schematic diagram of the mask being removed in one embodiment of this application; Figure 11 This is a schematic diagram of the conductive wire after welding in one embodiment of this application; Figure 12 This is a schematic diagram of light being reflected to the battery substrate by a conductive wire in one embodiment of this application.

[0023] Key component markings: 100 - Battery substrate; 101 - Gate line region; 102 - Non-gate line region; 103 - Isolation trench; 110 - Silicon substrate; 120 - Tunneling oxide layer; 130 - p-type doped polysilicon layer; 140 - n-type doped polysilicon layer; 150 - First passivation layer; 151 - Gate line trench; 160 - Second passivation layer; 200 - Gate line; 210 - Metal seed layer; 211 - Copper diffusion barrier layer; 212 - Copper layer; 220 - Conductive wire; 221 - Slope; 300 - Mask. Detailed Implementation

[0024] In the field of back-contact solar cells, related technologies employ lasers to create grid trenches on the passivation layer of the cell substrate, exposing the underlying doped polycrystalline silicon layer. A seed layer is then created using a combination of physical vapor deposition and electroplating processes, ensuring the metal seed layer completely covers the trenched area. The metal seed layer is then etched to retain the grid area, and conductive wires are finally stacked onto it to complete the fabrication of the back-contact solar cell. However, the lasers used in this process are typically ultraviolet lasers (e.g., 355nm wavelength), green lasers (e.g., 532nm wavelength), or infrared lasers (e.g., 1064nm wavelength), with an energy density of 1 J / cm². 2 ~5 J / cm 2Laser grooving relies on high temperatures to melt or even vaporize the passivation layer material, thus forming trenches. When part of the passivation layer melts or even vaporizes under heat, it can easily "burst" open, causing warping at the edges. Furthermore, at the edges of the passivation layer, the temperature on the side closer to the doped polysilicon layer is higher than the surface, resulting in greater expansion on the lower side of the passivation layer and less expansion on the surface, easily leading to upward warping. In addition, the heat-affected zone of laser grooving is relatively large. Due to the difference in thermal expansion coefficients between the doped polysilicon layer and the passivation layer, the passivation layer remaining on the battery substrate (especially at the edges) is prone to peeling off from the doped polysilicon layer. In related processes, the warping angle of the passivation layer edge relative to the plane of the silicon substrate is 20°~60°, and the warping height can reach 150nm~500nm. Figure 1 A scanning electron microscope image of the existing process after laser-driven grid trenching; Figure 2 This is a scanning electron microscope (SEM) image of a metal seed layer deposited using a current process. Figure 1 and Figure 2 As shown, when the edge of the passivation layer adjacent to the trench warps away from the doped polysilicon layer due to thermal stress, a gap is formed between the lower surface of the passivation layer and the doped polysilicon layer. During subsequent fabrication of the metal seed layer, the seed layer cannot adhere tightly to the battery substrate, resulting in poor adhesion and even breakage at the warping point, leading to poor integrity. Furthermore, the material of the metal seed layer cannot enter the gap between the passivation layer and the doped polysilicon layer, thus failing to collect charge carriers. In the presence of subsequent wet processes (such as wet etching of the metal seed layer, wet mask removal, etc.), the solution easily enters this gap, continuously corroding the metal seed layer and affecting the interface between the metal seed layer and the doped polysilicon layer, further reducing the adhesion between them.

[0025] Therefore, this application provides a method for fabricating a back-contact solar cell. By using a deep ultraviolet laser to create gate trenches on the passivation layer, the edge warping of the passivation layer is reduced, increasing the coverage area between the subsequently fabricated metal seed layer and the doped polycrystalline silicon layer, ultimately improving the performance and reliability of the back-contact solar cell. Furthermore, this application also provides a back-contact solar cell and a back-contact solar cell including the above-described back-contact solar cell.

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0027] Figure 3 This is a flowchart illustrating a method for fabricating a back-contact solar cell in one embodiment of this application. Figure 3As shown, the method for fabricating a back-contact solar cell provided in this application includes the following steps: Step S100: Obtain a battery substrate 100. The battery substrate 100 includes a silicon substrate 110, a doped polysilicon layer, and a first passivation layer 150 covering the surface of the doped polysilicon layer. The battery substrate 100 has a gate line region 101 and a non-gate line region 102.

[0028] Figure 4 This is a partial cross-sectional view of the battery substrate 100 in one embodiment of this application. Figure 4 As shown, the back-contact solar cell to be fabricated in this embodiment is a back-contact cell. Therefore, the doped polycrystalline silicon layer includes an n-type doped polycrystalline silicon layer 140 and a p-type doped polycrystalline silicon layer 130 located on the back side of the silicon substrate 110. A tunneling oxide layer 120 is provided between the n-type doped polycrystalline silicon layer 140 and the silicon substrate 110, and between the p-type doped polycrystalline silicon layer 130 and the silicon substrate 110. The n-type doped polycrystalline silicon layer 140 and the p-type doped polycrystalline silicon layer 130 are separated by an isolation trench 103. A first passivation layer 150 is covered on the side of the n-type doped polycrystalline silicon layer 140 facing away from the silicon substrate 110 and on the inner wall of the isolation trench 103. In this embodiment, the region where the p-type doped polycrystalline silicon layer 130 is located is defined as the p-region, and the n-type doped polycrystalline silicon layer 140 is defined as the n-region. Multiple p-regions and multiple n-regions are alternately arranged (only one n-region and one p-region are shown in the figure). The battery substrate 100 also includes a second passivation layer 160 covering the front side of the silicon substrate 110. In this application, the front side of the silicon substrate 110 corresponds to the light-facing side, i.e. Figure 4 The upper side of the silicon substrate 110; the back side of the silicon substrate 110 corresponds to the backlight side, i.e. Figure 4 The same understanding applies to the lower side of the battery substrate 100, the front and back sides of the battery substrate 100, and the front and back sides of the back contact solar cell. The grid area 101 of the battery substrate 100 is the area covered by the grid lines 200 after the battery is manufactured; the non-grid area 102 is the area not covered by the grid lines 200 (see...). Figure 11 The area covered; in Figure 4 In the diagram, the grid line region 101 and the non-grid line region 102 are separated by a dashed line. In this embodiment, the grid line region 101 of the battery substrate 100 is distributed on the back side, so the entire front area of ​​the battery substrate 100 is used to receive sunlight, which is beneficial to improving battery efficiency.

[0029] In this embodiment, a portion of the p-type doped polysilicon layer 130 and a portion of the n-type doped polysilicon layer 140 are located in the gate line region 101; another portion of the p-type doped polysilicon layer 130, another portion of the n-type doped polysilicon layer 140, and the isolation trench 103 are located in the non-gate line region 102.

[0030] In this embodiment, the silicon substrate 110 is made of monocrystalline silicon; in other embodiments, the silicon substrate 110 may also be made of monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, silicon carbide, etc.

[0031] Optionally, the first passivation layer 150 is made of silicon nitride, aluminum oxide, and silicon oxynitride; or, the first passivation layer 150 is a composite layer structure composed of at least two of silicon nitride, aluminum oxide, and silicon oxynitride. The second passivation layer 160 is made of silicon nitride, aluminum oxide, and silicon oxynitride; or, the second passivation layer 160 is a composite layer structure composed of at least two of silicon nitride, aluminum oxide, and silicon oxynitride.

[0032] Optionally, the front side of the silicon substrate 110 is textured. Textured surfaces can reduce light reflection, increase the light absorption rate of the cell substrate 100, and reduce the surface recombination rate, thereby improving cell efficiency.

[0033] In step S200, a gate trench 151 is formed on the first passivation layer 150 in the gate region 101 using a deep ultraviolet laser, and the bottom of the gate trench 151 exposes a doped polysilicon layer.

[0034] Figure 5 This is a schematic diagram showing the grid groove 151 after being formed in one embodiment of this application. Figure 5 As shown, the gate trench 151 is located within the gate line region 101, and the first passivation layer 150, adjacent to the edge of the gate trench 151, is also located within the gate line region 101. The end face of the edge of the first passivation layer 150 forms the sidewall of the gate trench 151. The bottom wall of the gate trench 151 is formed by a doped polysilicon layer. Since both the p-type doped polysilicon layer 130 and the n-type doped polysilicon layer 140 need to connect to the gate line 200, there are several gate trenches 151 (only two are shown in the figure). The bottom wall of a portion of the gate trenches 151 is formed by the p-type doped polysilicon layer 130, and the bottom wall of a portion of the gate trenches 151 is formed by the n-type doped polysilicon layer 140. The bottom wall and sidewall of the gate trench 151 together form the inner wall of the gate trench 151.

[0035] In this application, trenches are created on the first passivation layer 150 using a deep ultraviolet (DUV) laser. The DUV laser has a shorter wavelength than UV, green, and infrared lasers, resulting in higher photon energy. For example, a 193 nm DUV laser corresponds to a photon energy of approximately 6.4 eV, and a 266 nm DUV laser corresponds to a photon energy of approximately 4.7 eV. Taking silicon nitride (Si-N) as the material of the first passivation layer 150, the Si-N chemical bond energy is approximately 3.2 eV to 4.6 eV. The photon energy of the DUV laser is greater than the Si-N chemical bond energy, allowing the chemical bonds in the first passivation layer 150 to be broken through photochemical action. This causes the portion of the first passivation layer 150 affected by the DUV laser to form plasma and be removed. This process does not rely on thermal melting. Moreover, the laser grooving method in this application is to peel off layer by layer by breaking chemical bonds (similar to "photolithography"), rather than the thermal ablation of traditional lasers. The heat-affected zone (HAZ) is extremely small and hardly generates thermal stress, which can effectively suppress the edge warping of the first passivation layer 150 caused by thermal expansion differences.

[0036] Furthermore, the first passivation layer 150 (silicon nitride and / or aluminum oxide) has an extremely high absorption coefficient for deep ultraviolet lasers. Taking silicon nitride as an example, its absorption depth at 193nm is only 10nm~20nm. Therefore, almost all the laser energy is absorbed by the surface of the first passivation layer 150. The first passivation layer 150 is gradually removed from the side away from the doped polycrystalline silicon layer to the side closer to the doped polycrystalline silicon layer, which avoids excessive energy penetration, thus preventing thermal damage and interface stress accumulation in the doped polycrystalline silicon layer or silicon substrate 110. During the laser grooving process, the heat-affected zone is small, and the total heat generation is also small. Heat is not likely to accumulate in large quantities at the interface between the doped polycrystalline silicon layer and the first passivation layer 150. It is less likely that the lower surface of the first passivation layer 150 will melt, vaporize, or burst open. It is also less likely that the thermal expansion of the inner side of the first passivation layer 150 will be greater than that of the outer side due to the higher temperature. This can alleviate the problem of warping of the first passivation layer 150.

[0037] Optionally, the wavelength of the deep ultraviolet laser is 250nm~280nm, for example, a 266nm deep ultraviolet laser can be used. In other optional embodiments, the wavelength of the deep ultraviolet laser can be adjusted as needed, for example, a deep ultraviolet laser with a shorter wavelength and higher photon energy can be used; for example, a 193nm deep ultraviolet laser can be selected.

[0038] Optionally, the pulse width of the deep ultraviolet laser is less than 100 ps, ​​i.e., a deep ultraviolet picosecond laser is selected. The pulse width of the deep ultraviolet laser can be any value or a value between any two points from 1 ps, 10 ps, ​​20 ps, ​​30 ps, ​​40 ps, ​​50 ps, ​​60 ps, ​​70 ps, ​​80 ps, ​​90 ps, ​​and 100 ps. The pulse width is the pulse duration. The smaller the pulse width, the more concentrated the energy released by the laser per unit time, the higher the peak power, and the stronger the photomechanical effect, to etch away the first passivation layer 150.

[0039] Optionally, the energy density of the deep ultraviolet laser is 230 mJ / cm². 2 ~300mJ / cm 2 For example, an energy density of 230 mJ / cm³ 2 240mJ / cm 2 250mJ / cm 2 260mJ / cm 2 270mJ / cm 2 280mJ / cm 2 290mJ / cm 2 300mJ / cm 2 Any value in the range or the value between any two points.

[0040] Optionally, the width of the grid trench 151 is 20μm to 50μm. The spot diameter of the deep ultraviolet laser is 20μm to 50μm, and the spot diameter of the deep ultraviolet laser corresponds to the width of the grid trench 151.

[0041] By optimizing the laser process and using deep ultraviolet lasers to create grooves in the first passivation layer 150, the edges of the first passivation layer 150 can be made to be non-warped or only slightly warped. Non-warping of the first passivation layer 150 means that the edges of the first passivation layer 150 are in close contact with the doped polycrystalline silicon layer; slight warping means that the warping angle of the first passivation layer 150 is less than 10° and the warping height is less than 100nm.

[0042] Figure 6 This is a scanning electron microscope (SEM) image of the battery substrate 100 after the grid trench 151 is formed in one embodiment of this application. Figure 6 As shown, the deep ultraviolet laser film-opening method provided in this application provides a smooth inner wall of the gate trench 151, and the edge of the first passivation layer 150 adjacent to the gate trench 151 is closely attached to the doped polysilicon layer, without any edge warping.

[0043] In step S300, a metal seed layer 210 is deposited in the gate line region 101. The metal seed layer 210 covers the inner wall of the gate line trench 151 and the outer surface of the first passivation layer 150 of the gate line region 101.

[0044] It should be understood that the doped polysilicon layer needs to be connected to the subsequently placed conductive wire 220 via the metal seed layer 210 (see...). Figure 11 To form an electrical connection, the metal seed layer 210 needs to cover the bottom wall of the gate trench 151 to connect with the doped polysilicon layer. The width of the subsequently placed conductive wire 220 is greater than that of the gate trench 151. To ensure good electrical contact between the conductive wire 220 and the metal seed layer 210, the metal seed layer 210 covers not only the bottom wall of the gate trench 151, but also the side walls of the gate trench 151 and the outer surface of the first passivation layer 150 of the gate region 101. The metal seed layer 210 at these locations will also adhere to and contact the conductive wire 220.

[0045] In this embodiment, the step of depositing a metal seed layer 210 in the gate line region 101 may specifically include: Step S310: Deposit a metal seed layer 210 in the gate line region 101 and at least a portion of the non-gate line region 102; Figure 7 This is a schematic diagram of the deposition of a metal seed layer 210 in one embodiment of this application. Figure 7 As shown, the metal seed layer 210 covers the entire back side of the battery substrate 100, including the gate line region 101 and the non-gate line region 102. Optionally, the thickness of the metal seed layer 210 is 150 nm to 600 nm.

[0046] Alternatively, the metal seed layer 210 is deposited using the following method: Step S311: A copper diffusion barrier layer 211 is deposited on the battery substrate 100 using magnetron sputtering. In step S312, a copper layer 212 is deposited on the copper diffusion barrier layer 211 using magnetron sputtering. The copper layer 212 and the copper diffusion barrier layer 211 together form a metal seed layer 210.

[0047] In this embodiment, the metal seed layer 210 includes a copper diffusion barrier layer 211 and a copper layer 212. Since copper diffusion into silicon can adversely affect the electrical performance and long-term stability of the battery, a copper diffusion barrier layer 211 is deposited first, and then a copper layer 212 is deposited on the copper diffusion barrier layer 211. The copper diffusion barrier layer 211 can prevent copper in the copper layer 212 from diffusing into the doped polycrystalline silicon layer or even the silicon substrate 110, thereby improving battery performance.

[0048] Optionally, in the step of sputtering and depositing the copper diffusion barrier layer 211, the sputtering target-substrate distance is 80mm~100mm, and the magnetron sputtering power density is 2 W / cm². 2 ~8 W / cm 2The argon flow rate was 500 sccm~1000 sccm, the battery substrate temperature was 100℃~150℃, the sputtering pressure was 0.3Pa~0.5Pa, and the sputtering time was 5min~10min. In the copper layer deposition step 212, the sputtering target-substrate distance was 80 mm~100 mm, and the magnetron sputtering power density was 2 W / cm³. 2 ~8 W / cm 2 Argon flow rate 500-1000 sccm, battery substrate temperature 100℃ less than 100℃, sputtering pressure 0.3Pa~0.5Pa, sputtering time 5min~20min.

[0049] In this embodiment, both the copper diffusion barrier layer 211 and the copper layer 212 are prepared by magnetron sputtering. Compared with the process of first preparing the copper diffusion barrier layer and a thinner copper layer by magnetron sputtering and then thickening the copper layer by electroplating, the method of preparing the metal seed layer 210 in this embodiment omits the electroplating process, thus making it simpler and more efficient and reducing production costs.

[0050] Optionally, the thickness of the copper diffusion barrier layer 211 is 50nm~100nm, and the thickness of the copper layer 212 is 100nm~500nm.

[0051] Optionally, the copper diffusion barrier layer 211 comprises 90 wt.% to 95 wt.% aluminum, with the balance being at least one of Ni, Cr, W, Ti, NiCr, NiW, TiW, and NiMo. Therefore, the target material used in the step of sputtering the copper diffusion barrier layer 211 should comprise 90 wt.% to 95 wt.% aluminum, with the balance being at least one of Ni, Cr, W, Ti, NiCr, NiW, TiW, and NiMo.

[0052] Step S320: Create a mask 300 to cover the metal seed layer 210 of the gate line region 101, and etch away the metal seed layer 210 of the non-gate line region 102.

[0053] Figure 8 This is a schematic diagram of the metal seed layer 210 of the mask 300 covering the gate line region 101 in one embodiment of this application; Figure 9 This is a schematic diagram showing the metal seed layer 210 of the non-gateline region 102 after removal in one embodiment of this application. Figure 8 As shown, the metal seed layer 210 of the gate line region 101 covered by the mask 300 includes the metal seed layer 210 on the sidewall and bottom wall of the gate line trench 151, and the metal seed layer 210 located on the outer surface of the first passivation layer 150 of the gate line region 101; while the metal seed layer 210 of the non-gate line region 102 is not covered by the mask 300.

[0054] Optionally, the mask 300 is made of an acid-resistant material, such as silicon nitride or silicon oxynitride. This allows the mask 300 to effectively protect the metal seed layer 210 of the gate region 101 from corrosion when using an acidic solution to remove the seed layer of the non-gate region 102.

[0055] Optionally, the metal seed layer 210 in the non-gateline region 102 can be removed by an acid solution or an alkaline solution, such as sulfuric acid solution or sodium hydroxide solution. The final result is as follows: Figure 9 The structure shown.

[0056] Step S330, remove the mask 300.

[0057] Alternatively, an alkaline solution can be used to remove the mask 300, thereby exposing the metal seed layer 210 that covers only the gate line region 101. Figure 10 This is a schematic diagram of the mask 300 after removal in one embodiment of this application. It can be understood that because the edge of the first passivation layer 150 is smoothly attached to the doped polysilicon layer without warping or with only slight warping, the metal seed layer 210 of the gate region 101 can adhere relatively tightly to the battery substrate 100, without any cracks. During wet removal of the mask 300, the solution will not remain in the cracks and continue to corrode the metal seed layer 210. The metal seed layer 210 has high integrity, thus exhibiting better electrical performance.

[0058] Step S400: Weld conductive wire 220 onto metal seed layer 210.

[0059] Figure 11 This is a schematic diagram showing the conductive wire 220 after welding in one embodiment of this application. Figure 11 As shown, in this embodiment, the conductive wire 220 fills the gate trench 151 and covers the metal seed layer 210. Specifically, a portion of the conductive wire 220 is located inside the gate trench 151 and is attached to the metal seed layer 210 on the sidewall and bottom wall of the gate trench 151; another portion of the conductive wire 220 is located outside the gate trench 151 and is attached to the metal seed layer 210 on the outside of the first passivation layer 150.

[0060] Optionally, the width of the conductive wire 220 is 30μm to 50μm, wherein the width direction of the conductive wire 220 is consistent with the width direction of the grid trench 151. Optionally, the height of the conductive wire 220 protruding from the outer surface of the first passivation layer 150 along the thickness direction of the battery substrate 100 is 10μm to 15μm.

[0061] Optionally, the conductive wire 220 has a triangular or triangular cross-sectional shape. The portion of the conductive wire 220 outside the grid trench 151 has two slopes 221 arranged at an angle, which meet at the end of the conductive wire 220 away from the silicon substrate 110. It can be understood that if the outer surface of the conductive wire 220 is set to a plane parallel to the silicon substrate 110, light illuminating the conductive wire 220 will be reflected away from the battery substrate 100. However, by setting the outer surface of the conductive wire 220 to two slopes 221 arranged at an angle, it is beneficial to reflect light illuminating the surface of the conductive wire 220 back to the battery substrate 100, where it is absorbed and used for power generation. Figure 12 This is a schematic diagram showing light being reflected by conductive wire 220 to battery substrate 100 in one embodiment of this application. Figure 12 As shown, light perpendicular to the battery substrate 100 is reflected and then reaches the surface of the first passivation layer 150.

[0062] Optionally, the included angle between the two slopes 221 is 55° to 65°.

[0063] Optionally, the conductive wire 220 has a rectangular cross-sectional shape.

[0064] Optionally, in the step of welding the conductive wire 220 onto the metal seed layer 210, the welding temperature is less than 200°C. A lower welding temperature can prevent unnecessary diffusion of some materials in the battery substrate 100 (such as the doped polysilicon layer and passivation layer), and also reduce the risk of damage to the battery substrate 100 due to thermal stress. Furthermore, since the metal seed layer 210 is relatively thin, if the welding temperature is too high, it may cause the metal seed layer 210 to melt, alloy, or undergo other forms of damage, thereby affecting the ohmic contact quality between the conductive wire 220 and the battery substrate 100. Low-temperature welding helps maintain the integrity of the metal seed layer 210 and its interface with the underlying material.

[0065] The cost comparison between the back-contact solar cell fabrication method of this application embodiment and the existing process for fabricating grid lines using printed silver paste is shown in the table below.

[0066]

[0067] It can be seen that the method for preparing back-contact solar cells provided in this application can reduce the process cost of back-contact solar cells by 0.04 to 0.06 yuan / W.

[0068] This application also provides a back-contact solar cell, the structure of which can be referred to... Figure 11 The back-contact solar cell provided in this application includes: The battery substrate 100 includes a silicon substrate 110, a doped polysilicon layer, a first passivation layer 150 covering the surface of the doped polysilicon layer, and a second passivation layer 160 covering the front side of the silicon substrate 110. The battery substrate 100 has a gate line region 101 and a non-gate line region 102. Gate trench 151 is located in gate region 101, and the bottom of gate trench 151 exposes a doped polysilicon layer. Metal seed layer 210 covers the inner wall of gate trench 151 and the outer surface of the first passivation layer 150 of gate region 101. The conductive wire 220 is electrically connected to the metal seed layer 210 by welding. Wherein, the angle between the edge of the first passivation layer 150 near the gate trench 151 and the doped polysilicon layer is equal to 0°; The doped polysilicon layer includes an n-type doped polysilicon layer 140 and a p-type doped polysilicon layer 130 located on the back side of the silicon substrate 110. A tunneling oxide layer 120 is provided between the n-type doped polysilicon layer 140 and the silicon substrate 110, and between the p-type doped polysilicon layer 130 and the silicon substrate 110. The n-type doped polysilicon layer 140 and the p-type doped polysilicon layer 130 are separated by an isolation trench 103. The side of the n-type doped polysilicon layer 140 and the p-type doped polysilicon layer 130 facing away from the silicon substrate 110 and the inner wall of the isolation trench 103 are covered with a first passivation layer 150.

[0069] Optionally, the width of the grid trench is 20~50μm.

[0070] Optionally, the thickness of the metal seed layer is 150 nm to 600 nm. Further, the metal seed layer includes a copper diffusion barrier layer 211 and a copper layer 212 stacked together, with a conductive wire connected to the copper layer 212.

[0071] Optionally, the thickness of the copper diffusion barrier layer 211 is 50nm~100nm, and the thickness of the copper layer 212 is 100nm~500nm.

[0072] Optionally, the copper diffusion barrier layer comprises 90 wt.% to 95 wt.% aluminum, with the balance being at least one of Ni, Cr, W, Ti, NiCr, NiW, TiW, and NiMo.

[0073] Optionally, conductive wires fill the gate trenches and cover them with a metal seed layer. Optionally, the width of the conductive wires is 30μm to 50μm, wherein the width direction of the conductive wires is consistent with the width direction of the gate trenches; the height of the conductive wires protruding from the outer surface of the first passivation layer along the thickness direction of the battery substrate is 10μm to 15μm.

[0074] Optionally, the portion of the conductive filament 220 outside the gate trench 151 has two slopes 221 arranged at an angle, the two slopes 221 converging at the end of the conductive filament 220 away from the silicon substrate 110. The angle between the two slopes 221 is 55° to 65°. In other optional embodiments, the cross-sectional shape of the conductive filament 220 may also be rectangular.

[0075] It should be understood that the back contact solar cell provided in the embodiments of this application can be prepared by the preparation method of the back contact solar cell provided in the foregoing embodiments of this application.

[0076] This application also provides a photovoltaic module (not shown in the figure), including the back-contact solar cell provided in the above embodiments.

[0077] In summary, the method for fabricating a back-contact solar cell provided in this application includes: obtaining a cell substrate 100, the cell substrate 100 including a silicon substrate 110, a doped polycrystalline silicon layer, and a first passivation layer 150 covering the surface of the doped polycrystalline silicon layer, the cell substrate 100 having a grid line region 101 and a non-grid line region 102; using a deep ultraviolet picosecond laser to form a grid line trench 151 on the first passivation layer 150 in the grid line region 101, the bottom of the grid line trench 151 exposing the doped polycrystalline silicon layer; depositing a metal seed layer 210 in the grid line region 101, the metal seed layer 210 covering the inner wall of the grid line trench 151 and the outer surface of the first passivation layer 150 in the grid line region 101; and welding a conductive wire 220 on the metal seed layer 210. The back-contact solar cell fabrication method provided in this application uses a deep ultraviolet (DUV) laser to create gate trenches 151 on the first passivation layer 150. The DUV laser has high photon energy, exceeding the chemical bond energy of the passivation layer material, thus breaking chemical bonds through photochemical action rather than relying on thermal melting. The DUV laser-based trenching results in a small heat-affected zone and low thermal stress, suppressing edge warping of the first passivation layer 150 due to thermal expansion differences. Furthermore, the passivation layer material has an extremely high absorption coefficient and shallow absorption depth for DUV lasers, so the side of the first passivation layer 150 closest to the doped polysilicon layer does not accumulate much heat and is less prone to upward warping due to thermal expansion. Through the fabrication method provided in this application, the angle between the edge of the first passivation layer 150 and the doped polysilicon layer is 0°, allowing the edge of the first passivation layer 150 to adhere as closely as possible to the doped polysilicon layer. Therefore, the deposited metal seed layer 210 can adhere well to the inner surface of the gate trench 151 and the outer surface of the first passivation layer 150 of the gate region 101, and has good integrity (i.e., no cracks). There is almost no gap between the edge of the first passivation layer 150 and the doped polysilicon layer. At the same time, the good integrity of the metal seed layer 210 makes it difficult for the etching solution used in the wet etching process to enter the gaps and penetrate between the metal seed layer 210 and the doped polysilicon layer, thus ensuring that the metal seed layer 210 has good adhesion. Therefore, the back contact solar cell provided in this embodiment has better reliability and cell performance.

[0078] This application provides a back-contact solar cell, which is prepared by the above-described method and features low cost, high reliability, and high cell efficiency.

[0079] This application also provides a photovoltaic module, including a back-contact solar cell prepared by the above-described method, which has the characteristics of low cost, high reliability, and high cell efficiency.

[0080] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a back-contact solar cell, characterized in that, include: A battery substrate is obtained, the battery substrate comprising a silicon substrate, a doped polycrystalline silicon layer and a first passivation layer covering the surface of the doped polycrystalline silicon layer, the battery substrate having a gate line region and a non-gate line region; A deep ultraviolet laser is used to create a gate trench on the first passivation layer in the gate region, and the bottom of the gate trench exposes the doped polysilicon layer. A metal seed layer is deposited in the gate line region, the metal seed layer covering the inner wall of the gate line trench and the outer surface of the first passivation layer in the gate line region; A conductive wire is welded onto the metal seed layer.

2. The method for preparing a back-contact solar cell according to claim 1, characterized in that, The wavelength of the deep ultraviolet laser is 250nm~280nm.

3. The method for preparing a back-contact solar cell according to claim 1, characterized in that, The pulse width of the deep ultraviolet laser is less than 100 ps.

4. The method for preparing a back-contact solar cell according to claim 1, characterized in that, The energy density of the deep ultraviolet laser is 230mJ / cm2~300mJ / cm2.

5. The method for preparing a back-contact solar cell according to any one of claims 1-4, characterized in that, The step of depositing a metal seed layer in the gate line region includes: A metal seed layer is deposited in the gate line region and at least a portion of the non-gate line region; A mask is fabricated to cover the metal seed layer of the gate line region, and the metal seed layer of the non-gate line region is etched away. Remove the mask.

6. The method for preparing a back-contact solar cell according to any one of claims 1-4, characterized in that, The metal seed layer was deposited using the following method: A copper diffusion barrier layer was deposited on the battery substrate using magnetron sputtering. A copper layer is deposited on the copper diffusion barrier layer using magnetron sputtering, and the copper layer and the copper diffusion barrier layer together form the metal seed layer.

7. The method for preparing a back-contact solar cell according to any one of claims 1-4, characterized in that, In the step of welding conductive wires onto the metal seed layer, the welding temperature is less than 200°C.

8. A back-contact solar cell, characterized in that, include: A battery substrate, comprising a silicon substrate, a doped polycrystalline silicon layer, a first passivation layer covering the surface of the doped polycrystalline silicon layer, and a second passivation layer covering the front side of the silicon substrate, wherein the battery substrate has a gate line region and a non-gate line region. A gate trench, the gate trench being located in the gate region, and the bottom of the gate trench exposing the doped polysilicon layer; A metal seed layer, the metal seed layer covering the inner wall of the gate trench and the outer surface of the first passivation layer of the gate region; A conductive wire, wherein the conductive wire is electrically connected to the metal seed layer by welding; in, The angle between the edge of the first passivation layer near the gate trench and the doped polysilicon layer is equal to 0°; The doped polysilicon layer includes an n-type doped polysilicon layer and a p-type doped polysilicon layer located on the back side of the silicon substrate. A tunneling oxide layer is provided between the n-type doped polysilicon layer and the silicon substrate, and between the p-type doped polysilicon layer and the silicon substrate. The n-type doped polysilicon layer and the p-type doped polysilicon layer are separated by an isolation trench. The side of the n-type doped polysilicon layer and the p-type doped polysilicon layer facing away from the silicon substrate and the inner wall of the isolation trench are covered with the first passivation layer.

9. The back-contact solar cell according to claim 8, characterized in that, The width of the grid trench is 20~50μm.

10. The back-contact solar cell according to claim 8, characterized in that, The thickness of the metal seed layer is 150nm~600nm.

11. The back-contact solar cell according to claim 8, characterized in that, The metal seed layer includes a copper diffusion barrier layer; The copper diffusion barrier layer comprises 90 wt.% to 95 wt.% aluminum, with the balance being at least one of Ni, Cr, W, Ti, NiCr, NiW, TiW, and NiMo.

12. The back-contact solar cell according to claim 8, characterized in that, The conductive wire fills the grid trench and covers the metal seed layer.

13. The back-contact solar cell according to claim 8, characterized in that, The portion of the conductive wire outside the gate trench has two slopes arranged at an angle, and the two slopes meet at the end of the conductive wire away from the silicon substrate. The included angle between the two slopes is 55° to 65°.

14. The back-contact solar cell according to claim 8, characterized in that, The width of the conductive wire is 30μm~50μm, wherein the width direction of the conductive wire is consistent with the width direction of the gate trench; The conductive wire protrudes from the outer surface of the first passivation layer at a height of 10μm~15μm along the thickness direction of the battery substrate.

15. A photovoltaic module, characterized in that, Includes the back-contact solar cell according to any one of claims 8-14.

Images