Chip dynamic power consumption scheduling method and system based on intelligent algorithm

Abstract

The invention relates to the technical field of chip design, and discloses a chip dynamic power consumption scheduling method and system based on an intelligent algorithm. The method comprises the following steps of: firstly, acquiring instruction stream data operated by a chip in real time, extracting a feature vector comprising an instruction dynamic change vector and context associated data, and determining a power consumption prediction mapping parameter according to the feature vector; and when the parameter exceeds a preset threshold value, an accurate power consumption prediction result is generated by adjusting the weight of the convolutional neural network. Subsequently, a synchronous timing demand is calculated based on the instruction switching frequency and the data dependency, and an initial power supply configuration is determined. By monitoring task load classification signals, the power consumption distribution proportion is adjusted when the signals are lower than a threshold value, the optimized power supply configuration is obtained, and the improvement index of the resource distribution efficiency is calculated according to the optimized power supply configuration. And finally, according to the index, dynamically adjusting a limiting condition of a scheduling period, and forming a self-adaptive optimization framework, thereby realizing accurate prediction and dynamic optimization scheduling of the chip power consumption.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a chip dynamic power consumption scheduling method and system based on intelligent algorithms. Background Technology

[0002] Chip power management is a core area of ​​modern electronics and smart devices, directly determining the energy efficiency, performance stability and lifespan of devices. Especially in IoT terminals, artificial intelligence computing devices and autonomous driving systems, chips need to dynamically balance high-performance computing and low-power operation to adapt to diverse task load scenarios. Therefore, precise power scheduling based on reinforcement learning for dynamic changes in instruction flow has become a hot research area.

[0003] In one existing technology, power management of a chip is achieved through a static or semi-static power allocation strategy. This involves setting the power supply parameters and power allocation ratio of functional units according to preset task types and resource requirement rules, while using traditional linear modeling methods to predict power demand, thereby achieving basic power control.

[0004] However, since the power supply parameters and allocation ratios are fixed, and traditional linear modeling struggles to depict the non-linear mapping between instruction types and power consumption, it cannot adaptively adjust to the dynamic changes in the instruction flow and real-time switching of task loads during chip operation. This results in low accuracy in chip power consumption prediction and issues such as performance bottlenecks under high loads and resource waste under low loads. Therefore, existing technologies suffer from low resource allocation efficiency during chip operation. Summary of the Invention

[0005] This invention provides a chip dynamic power consumption scheduling method and system based on intelligent algorithms to solve the problem of low resource allocation efficiency when the chip is working.

[0006] In a first aspect, to address the aforementioned technical problems, this invention provides a chip dynamic power consumption scheduling method based on intelligent algorithms, comprising: The instruction stream data during chip operation is acquired in real time, and the instruction feature vector is extracted using a convolutional neural network to obtain the instruction dynamic change vector and instruction context association data; Based on the instruction dynamic change vector and the instruction context association data, a power consumption nonlinear mapping relationship is constructed, and power consumption prediction mapping parameters are determined. If the power consumption prediction mapping parameters exceed the preset performance and energy efficiency constraint threshold, adjust the weights of the convolutional neural network, verify the stability of the power consumption prediction mapping parameters, and obtain the power consumption prediction result. The command switching frequency and data dependency strength are obtained, and combined with the power consumption prediction results, the synchronization timing requirements of the power supply state are calculated to determine the initial power supply configuration. Based on the initial power supply configuration, the task load classification signal is monitored. If the task load classification signal is lower than a preset signal threshold, the power consumption allocation ratio is adjusted to determine the optimized power supply configuration. Based on the optimized power supply configuration, the power consumption allocation ratio is further adjusted to obtain the resource allocation efficiency improvement index; Based on the resource allocation efficiency improvement indicators and the constraints of the dynamic adjustment cycle, a dynamic adjustment framework is determined.

[0007] Secondly, the present invention provides a chip dynamic power consumption scheduling system based on intelligent algorithms, comprising: The feature extraction module is used to collect instruction stream data during chip operation in real time, and uses a convolutional neural network to extract instruction feature vectors to obtain instruction dynamic change vectors and instruction context association data. The mapping modeling module is used to construct a power consumption nonlinear mapping relationship and determine power consumption prediction mapping parameters based on the instruction dynamic change vector and the instruction context association data. The parameter verification module is used to adjust the weights of the convolutional neural network when the power prediction mapping parameters exceed the preset performance and energy efficiency constraint threshold, to verify the stability of the power prediction mapping parameters and obtain the power prediction result. The power supply optimization module is used to obtain the instruction switching frequency and data dependency strength, and in combination with the power consumption prediction results, calculate the synchronization timing requirements of the power supply state and determine the initial power supply configuration. The power allocation module is used to monitor the task load classification signal according to the initial power supply configuration. If the task load classification signal is lower than a preset signal threshold, the power allocation ratio is adjusted to determine the optimized power supply configuration. The resource allocation module is used to further adjust the power consumption allocation ratio based on the optimized power supply configuration to obtain the resource allocation efficiency improvement index. The framework generation module is used to determine the dynamically adjusted framework by dynamically adjusting the periodic constraints based on the resource allocation efficiency improvement indicators.

[0008] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention extracts instruction type features and combination sequences from dynamic instruction streams using a convolutional neural network and constructs a nonlinear mapping model based on reinforcement learning, which can accurately capture the complex nonlinear relationship between instruction type, combination, and power consumption. Compared with traditional static or semi-static strategies, this invention can predict power consumption requirements under different task loads in real time and accurately, solving the problem of low resource allocation efficiency during chip operation in the prior art. (2) By acquiring transition data of low-load tasks and calculating the synchronization timing requirements of the power supply status of functional units, the present invention achieves optimized power supply configuration when switching from high-load to low-load tasks. When a low-load task is detected, the system can automatically and quickly reduce power consumption allocation and functional unit activation level, effectively avoiding resource waste under low load, while ensuring the performance requirements of high-load tasks.

[0009] (3) This invention introduces a feedback loop correction mechanism and dynamically updates the power consumption nonlinear mapping relationship based on resource allocation efficiency indicators and system constraints, forming a complete "monitoring-prediction-decision-execution-feedback" closed-loop system. This framework has the ability to learn and optimize itself, and can continuously adapt to changing instruction flows and workloads, thereby improving the stability and efficiency of chip power consumption management in the long term. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the chip dynamic power consumption scheduling method based on intelligent algorithms provided in the first embodiment of the present invention; Figure 2 This is a schematic diagram of the chip dynamic power consumption scheduling system based on intelligent algorithms provided in the second embodiment of the present invention. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] Reference Figure 1 The first embodiment of the present invention provides a chip dynamic power consumption scheduling method based on intelligent algorithms, including the following steps: S11: Real-time acquisition of instruction stream data during chip operation; use convolutional neural network to extract instruction feature vectors to obtain instruction dynamic change vectors and instruction context association data; S12, Based on the instruction dynamic change vector and the instruction context association data, construct a power consumption nonlinear mapping relationship and determine the power consumption prediction mapping parameters; S13, if the power consumption prediction mapping parameter exceeds the preset performance and energy efficiency constraint threshold, adjust the weights of the convolutional neural network, verify the stability of the power consumption prediction mapping parameter, and obtain the power consumption prediction result. S14, obtain the instruction switching frequency and data dependency strength, and combine them with the power consumption prediction results to calculate the synchronization timing requirements of the power supply state and determine the initial power supply configuration; S15, based on the initial power supply configuration, monitor the task load classification signal; if the task load classification signal is lower than a preset signal threshold, adjust the power consumption allocation ratio and determine the optimized power supply configuration. S16, Based on the optimized power supply configuration, continue to adjust the power consumption allocation ratio to obtain the resource allocation efficiency improvement index; S17. Based on the resource allocation efficiency improvement indicators and the constraints of the dynamic adjustment cycle, determine the dynamic adjustment framework.

[0013] In step S11, instruction stream data during chip operation is acquired in real time, and instruction feature vectors are extracted using a convolutional neural network to obtain instruction dynamic change vectors and instruction context association data, including: The instruction stream data during chip operation is acquired in real time to obtain the original instruction sequence; A convolutional neural network is used to extract the instruction feature vector from the original instruction sequence; If the instruction feature vector satisfies a preset instruction threshold, then a dynamic instruction change vector is generated based on the instruction feature vector. Based on the instruction dynamic change vector, the instruction context association strength is calculated to obtain the preliminary quantization representation matrix; The preliminary quantization representation matrix is ​​matched with a preset context association library to obtain instruction context association data.

[0014] It should be noted that the execution instruction stream data is captured in real time by the chip's built-in performance monitoring unit. The instruction stream data includes, but is not limited to, instruction types such as arithmetic operations, logical operations, loading, and storage, operand addresses, and program counter information, to obtain the original instruction sequence.

[0015] When extracting instruction feature vectors, the opcode of each instruction is mapped to a unique high-dimensional encoding vector. Each opcode is mapped to a 100-dimensional vector, where only the corresponding position of the opcode is 1, and the rest are 0. Subsequently, the preprocessed instruction sequence is input into a pre-designed and trained one-dimensional convolutional neural network. The structure of the one-dimensional convolutional neural network is as follows: an input layer receives a sliding window of a fixed-length instruction sequence, with a window length L=128. For real-time instruction streams, a sliding mechanism with a stride S=64 is used, and zero padding is used for short sequences; a one-dimensional convolutional layer uses 16 convolutional kernels with widths of 3, 5, and 7, with a stride of 1, and a ReLU activation function is introduced after the convolutional layer; then a one-dimensional max pooling layer is connected, with a pooling window size of 2 and a stride of 2; finally, a flattening layer and a fully connected layer are used for feature integration and dimensionality reduction, outputting a K=64-dimensional instruction feature vector. Training continues until the absolute decrease value of the loss function on the validation set is lower than the preset decrease threshold of 0.001 for each of the five consecutive training epochs, at which point the model is considered converged. The preset decrease threshold of 0.001 is based on the analysis of typical chip power consumption data (e.g., in the range of 1-10W), and the corresponding absolute error (1mW) meets the power consumption prediction accuracy requirements for most application scenarios. In practical applications, this threshold can be adaptively adjusted according to the power consumption range and performance targets of the specific chip.

[0016] Specifically, while extracting CNN features from a window of instruction sequence of length L=128, the number of branch instructions is counted, and their proportion to the total number of instructions is calculated. If this proportion is greater than or equal to a preset instruction threshold of 0.7, the current instruction pattern is considered stable, and the instruction feature vector output by the CNN is directly used as the instruction dynamic change vector. Otherwise, it means that the instruction pattern changes frequently, and temporal context analysis is required. The instruction feature vector is set as the current time step. After the preset instruction threshold judgment is completed, the instruction feature vector is stored in real time in a FIFO circular buffer of depth N=50. At this time, the latest 50 consecutive feature vectors are read from the buffer, and the input sequence is formed in chronological order and input into the pre-trained LSTM network. The LSTM model is trained offline with the goal of predicting the chip power consumption value of the next time step. After the LSTM processes the sequence, the hidden state of its last time step is adjusted in dimension through a fully connected layer and mapped to an instruction dynamic change vector with the same dimension as the CNN feature vector.

[0017] The LSTM network employs a single-layer structure with 64 hidden units, and its input dimension is consistent with that of the CNN feature vector. During offline training, the network is supervised using historical instruction sequences and corresponding chip power consumption data. The training objective is to predict the chip power consumption value at the next time step. Mean squared error (MSE) is used as the loss function during training, and the Adam optimizer is used for parameter optimization. The learning rate is set to 0.001, the batch size is 32, and the training cycle is 500 epochs. An early stopping strategy is employed on the validation set to prevent overfitting. It should be noted that the preset instruction threshold of 0.7 is based on ablation experiments during model training. The experiments compare the MSE of power consumption prediction on the validation set and the LSTM call frequency under different thresholds. The results show that setting the preset instruction threshold to 0.7 achieves the optimal balance between prediction accuracy and computational cost, and the preset instruction threshold can also be adaptively adjusted in practical applications.

[0018] In one embodiment, the chip's instruction set is categorized into M main instruction types, such as {arithmetic operations, logical operations, load, store, branch, others}, where M=6. The window length for the same instruction sequence is L=128. The frequency of each instruction type is counted and normalized to obtain an M-dimensional instruction type activity vector. Then, a fixed-capacity FIFO buffer of T=100 is maintained to store historical activity vector sequences. The transition probability between instruction types is used as the correlation strength index. For all possible instruction type pairs (Type_i, Type_j), the correlation strength is calculated by counting the number of events in the continuous time series represented by the T vectors in the buffer that satisfy the condition that the activity of Type_i at time t is higher than a threshold λ and the activity of Type_j at time t+1 is higher than the threshold λ, and then dividing by the total number of times the activity of Type_i at time t is higher than the threshold λ. The threshold λ can be set according to the historical data distribution, for example, by taking the median of the activity values ​​or through experimental calibration. Finally, iterate through all M x M possible instruction type pairs, calculate the transition probability of each pair, and thus fill in and obtain an M x M preliminary quantization representation matrix. The row index of this matrix represents the predecessor instruction type (Type_i), the column index represents the successor instruction type (Type_j), and the matrix element values ​​are the corresponding association strengths.

[0019] Then, the real-time generated preliminary quantized matrix is ​​matched with the standard pattern matrix in the preset context association library. The preset context association library is constructed through offline analysis, collecting historical matrix data under different load scenarios, generating representative standard pattern matrices through cluster analysis, and labeling them with semantic load type tags (e.g., "computation-intensive"). During matching, the Euclidean distance d between the real-time matrix and each standard pattern matrix is ​​calculated. A preset association threshold θ is set, determined through distance distribution statistics and ROC curve analysis of the training data. During the training phase, the distance distribution between all historical matrices and their corresponding standard pattern matrices is statistically analyzed, and distance distribution curves for positive and negative samples are plotted. The optimal discrimination point is determined through ROC curve analysis, i.e., the point where the difference between the true positive rate and the false positive rate is greatest, or, based on actual application requirements, the point with the highest true positive rate while the false positive rate is below 5%. The corresponding distance value is the threshold θ. This optimally distinguishes between normal and abnormal patterns. If a standard pattern exists such that d < θ, the match is successful. At this point, the corresponding load type label is output, and the confidence metric is quantified into a similarity index, confidence = 1 - d / θ. If d ≥ θ for all standard patterns, then output the label "Unknown Pattern" with a confidence level of 0. The final output instruction context association data is structured information containing semantic payload type and quantized confidence level.

[0020] In step S12, based on the instruction dynamic change vector and the instruction context association data, a power consumption nonlinear mapping relationship is constructed, and power consumption prediction mapping parameters are determined, including: By processing the instruction dynamic change vector and the instruction context association data through a convolutional neural network, the operation density distribution is extracted to obtain a preliminary power consumption mapping input. Based on the initial power consumption mapping input, the data dependency strength is calculated to generate initial parameters for the nonlinear mapping. If the preliminary parameters of the nonlinear mapping exceed the preset intensity distribution threshold, the preliminary power consumption mapping input is adjusted to obtain the core parameters of the nonlinear mapping. Based on the core parameters of the nonlinear mapping, a power consumption nonlinear mapping relationship is constructed to obtain the mapping function; According to the mapping function, the operation density distribution and the data dependency strength are input and calculated to obtain the execution result, and the power consumption prediction mapping parameters are determined based on the execution result.

[0021] The instruction dynamic change vector and instruction context associated data are concatenated to form a fused feature vector.

[0022] The fused vector is reshaped into a two-dimensional feature map and scanned using 64 3x3 convolutional kernels. These kernels capture local collaborative patterns across domains. Each 3x3 kernel, during its sliding window operation, simultaneously covers adjacent feature dimensions from three different domains: the instruction dynamics vector, the load type embedding vector, and the confidence scalar. During model training, the nine weight parameters of the convolutional kernels are optimized using backpropagation, gradually transforming each kernel into a specific local pattern detector. The outputs of the convolutional layers, after activation and pooling, are integrated and dimensionality-reduced through fully connected layers, outputting a fixed-dimensional operation density distribution feature vector. Each dimension of this vector quantifies the intensity of a specific operation pattern, serving as the initial power consumption mapping input. The convolutional neural network parameters include: 64 convolutional kernels, a 1-stride sliding window, consistent padding to maintain the feature map's spatial dimension, the use of ReLU activation to introduce non-linear features, and 2x2 max pooling for dimensionality reduction after convolution.

[0023] The payload type in the instruction context association data is embedded as a 32-dimensional vector, encoded using a trainable embedding lookup table. This process begins with the digitization of discrete payload type labels. First, text labels such as "computation-intensive" and "memory bottleneck" are mapped to unique integer indices. During initialization, a trainable embedding matrix is ​​created with dimensions [total payload types, 32], where 32 is the preset semantic space dimension. During forward propagation, the corresponding 32-dimensional row vector is extracted from the embedding matrix based on the payload type's integer index as a distributed representation of that type. The parameters of this embedding matrix are optimized during model training using a backpropagation algorithm, bringing semantically similar payload types closer together in the 32-dimensional space, while widening the distance between semantically different types. Ultimately, each payload type receives a 32-dimensional vector representation rich in semantic information.

[0024] It should be noted that each dimension of the vector in the initial power consumption mapping input corresponds to a predefined semantic label of a basic operation mode. A preset activity threshold is used to binarize each dimension of the vector, and the semantic labels corresponding to dimensions with intensity exceeding the threshold are extracted to form the active operation set for the current time step. The active symbol sets of consecutive time steps are then arranged sequentially to form a symbolic operation sequence. Next, an association rule algorithm is used to analyze this sequence and calculate the data dependency strength of key operation mode pairs. Then, the data dependency strength is mapped to the initial parameters of the nonlinear function in the power consumption prediction model. The set of initial parameters corresponding to all key dependencies constitutes the initial parameters of the nonlinear mapping. The preset activity threshold is generally the 75th-85th percentile of the distribution of intensity values ​​across all dimensions.

[0025] The association rule algorithm can utilize the FP-Growth algorithm. The algorithm process includes: First, scanning the entire symbolic operation sequence database, counting the frequency of each individual operation pattern, and filtering by setting a minimum support count to obtain frequent 1-itemsets, which are then sorted in descending order of frequency to generate a head table. Next, a second data scan is performed to construct an FP-tree. Patterns in each sequence are sorted according to the head table order and inserted into the tree. Paths sharing the same prefix are merged, forming a compressed data structure. Subsequently, the algorithm enters a recursive mining phase, constructing a conditional pattern base for each suffix pattern starting from the bottom item of the head table. Conditional sub-databases are collected by tracing all prefix paths reaching that node in the FP-tree. Based on this conditional pattern base, a conditional FP-tree is recursively constructed, and all frequent patterns ending with that suffix are discovered through pattern concatenation, such as {A,B,C}, {B,C}, etc. Finally, the support of all output frequent itemsets (e.g., the support of {A,B,C} is 1) is used as the data dependency strength distribution. It should be noted that... , This represents the support level from pattern A to pattern B. Represents a sequence The number of times it appears in the dataset. This represents the total number of sequences in the dataset. Data dependency strength can be mapped using the Sigmoid function. For example, a quantitative relationship between support and the Sigmoid parameter can be established through regression analysis. A support of 0.75 maps to an initial slope of 1.2 for the Sigmoid function, meaning the initial parameter for the nonlinear mapping is 1.2.

[0026] If the initial nonlinear mapping parameters exceed a preset intensity distribution threshold, the step of generating the initial nonlinear mapping parameters is repeated to adjust the initial power consumption mapping input and obtain the core nonlinear mapping parameters. For example, if the initial nonlinear mapping parameters exceed the preset intensity distribution threshold of 0.8, the initial power consumption mapping input is adjusted, and the initial nonlinear mapping parameters are normalized using a nonlinear compression function, reducing them from 0.9 to 0.76. Using the adjusted initial nonlinear mapping parameters, the data dependency strength is recalculated to obtain the core power consumption nonlinear mapping parameters. The nonlinear compression function is: in, To preset the intensity distribution threshold, based on the maximum value distribution of the initial parameters of the nonlinear mapping in historical data, the 95th percentile of 0.8 was chosen as the threshold to ensure coverage of most normal operating conditions. A simulated dataset was constructed using the core parameters of the power consumption nonlinear mapping, with each instruction sequence labeled with a simulated power consumption value. The simulated dataset was trained using a deep Q-network, and the agent optimized the mapping function through a reward mechanism, ultimately optimizing all the core parameters of the power consumption nonlinear mapping to obtain the final mapping function.

[0027] It should be noted that the process of constructing the simulated dataset includes: firstly, randomly generating 1000 virtual instruction sequences; for each sequence, by adjusting key variables such as instruction mixing ratio, data dependency strength and pattern, and instruction-level parallelism, constructing scenarios covering typical chip workloads from sparse computation to intensive memory access. Then, each synthesized sequence is input into an initial power function composed of nonlinear mapping core parameters. It is worth noting that the deep Q-network experience replay buffer has a capacity of 100,000, and data correlation is broken by randomly sampling batches of 64 experiences; a dual-network structure is adopted, where the target network synchronizes parameters from the online network every 100 training steps; the exploration strategy uses an ε-greedy mechanism, with the ε value starting from 1.0 and gradually decreasing to 0.01 at a decay rate of 0.995. The training hyperparameters use the Adam optimizer with a learning rate of 0.001 and a discount factor of 0.99.

[0028] In the deep Q-network, each state is a data point in the simulated dataset. Each action is an agent's fine-tuning of one or more power-related nonlinear mapping core parameters in the initial mapping function, for example, adjusting the slope from 1.2 to 1.25. After taking an action in a given state, the agent uses the adjusted new mapping function to predict the power consumption. The predicted value (…) ) and the simulated power consumption values ​​labeled in the dataset ( Compare the results and calculate the prediction error. The specific calculation method is as follows: If the prediction error decreases, a positive reward is given. If the prediction error increases, a negative reward is given. Ultimately, the agent learns an optimal action. This maximizes the long-term cumulative reward. Applying this action to the power consumption nonlinear mapping function, the core parameters of the power consumption nonlinear mapping are finally optimized, and the optimized function is the mapping function.

[0029] The final optimization process for the core parameters of the power consumption nonlinear mapping includes updating the corresponding core parameters in the mapping function based on the Q-maximization principle using the gradient backpropagation algorithm. For continuous parameter spaces, a deterministic policy gradient method is used to directly calculate the gradient of the target action with respect to the parameters. ,in The parameter set of the mapping function is updated via gradient ascent. ,in Let be the learning rate of the mapping function. For discrete parameter adjustment, a soft maximization strategy with parameterized action space is adopted, directly applying the parameter adjustment amount corresponding to the optimal action to the current mapping function. After multiple rounds of iterative optimization, the final determined power-consuming nonlinear mapping function is obtained.

[0030] The operation density distribution and the data dependency strength are input into the mapping function. The mapping function calculates for each input and outputs the corresponding simulated power consumption prediction value. This set of inputs and outputs constitutes the execution result. The execution result is compared with the simulated power consumption value, and the root mean square error (RMSE) is calculated. If the error is lower than a preset error threshold, it indicates that the training mapping function performs stably in the simulation environment. At this point, all parameters inside the function are directly determined as the final power consumption prediction mapping parameters. If the error is higher than the error threshold, an adjustment mechanism is triggered. Then, the adjusted parameters are compared again with the benchmark power consumption value, and the RMSE is calculated until the error is lower than the error threshold. The set of parameters that finally meets the condition is determined as the power consumption prediction mapping parameters. The adjustment mechanism includes setting an adjustment coefficient, for example, 0.9, and multiplying the key parameters inside the function by this coefficient. Then, the RMSE of the adjusted parameters is compared with the error threshold. If it is higher than the error threshold, the adjustment continues; if it is lower than the error threshold, the adjustment ends. The setting of the adjustment coefficient adopts an adaptive strategy based on historical adjustment effects. The initial adjustment coefficient is set to 0.9. In each subsequent adjustment, the trend of the RMSE during the first three adjustments is analyzed. If the error continues to decrease, the current adjustment factor is maintained; if the error oscillates or increases, the adjustment factor is reduced by 0.95.

[0031] It should be noted that when setting the preset error threshold, it is essential to ensure that the accuracy of power consumption prediction is sufficient to support the effective execution of upper-level management strategies. For example, if the dynamic voltage and frequency adjustment strategy requires power consumption to be controlled within a target value of ±10%, then the preset error threshold must be much less than 10%, such as set to 5%, to leave sufficient margin for the control loop.

[0032] In step S13, if the power consumption prediction mapping parameters exceed a preset performance and energy efficiency constraint threshold, the weights of the convolutional neural network are adjusted, the stability of the power consumption prediction mapping parameters is verified, and a power consumption prediction result is obtained, including: If the power consumption prediction mapping parameters exceed the preset performance and energy efficiency constraint threshold, the weights of the convolutional neural network are adjusted to obtain the adjusted weights. Based on the adjusted weights, historical data of instruction stream timestamps and instruction switching frequencies are obtained and processed to extract stability features; If the stability feature satisfies the preset stability condition, then the preliminary verification mapping parameters are determined; The task load distribution is extracted from the preliminary verification mapping parameters, and a preliminary power consumption prediction result is generated based on the task load distribution and the data dependency strength. Based on the preliminary power consumption prediction results, the power consumption adjustment parameters are optimized to obtain the final power consumption prediction results.

[0033] It should be noted that the power consumption prediction mapping parameters are compared with a preset performance and energy efficiency constraint threshold. If the result exceeds the performance and energy efficiency constraint threshold, the gradient of the loss with respect to the weights of all layers of the convolutional neural network in S11 is calculated through backpropagation. Then, the gradient descent method is used to fine-tune the weights of the convolutional neural network along the reverse direction of the gradient. After one round of weight update, the adjusted weights are obtained. It should be noted that the formula used to fine-tune the convolutional neural network is: in, These are the original weights. This is the gradient of the weight, and η is the learning rate, which can be set to a very small value, such as 0.01, to ensure smooth weight adjustment. These are the adjusted new weights.

[0034] The loss function is defined as the deviation between the predicted value and the constraint threshold. in, To predict peak power consumption, This is the constraint threshold.

[0035] It should be noted that the performance and energy efficiency constraint threshold is set based on the chip's energy efficiency curve, typically at the point where the curve begins to show an inflection point. For example, if the performance and energy efficiency constraint threshold is set to a peak power consumption of 100mW, and the mapping parameters predict a peak power consumption of 120mW, this exceeds the threshold, indicating that the model may be overestimating energy consumption. In this case, the weight values ​​of specific layers are reduced for the overestimated portion, such as reducing the weight of the fully connected layer from 1.5 to 1.2, thus making the prediction closer to the actual energy consumption.

[0036] It's worth noting that recent (e.g., the past 5 minutes) instruction stream timestamps and instruction switching frequency data are retrieved to form a time series. Then, a recurrent neural network (RNN) is used to analyze this time series, capturing the periodic patterns of instruction switching. Finally, volatility, a quantitative indicator representing the stability of the sequence, is extracted from the RNN's output layer as a stability feature.

[0037] It should be noted that the instruction stream timestamp records the precise execution time of each instruction, used to analyze the timing characteristics of instruction execution. The instruction switching frequency is calculated by counting the number of times the instruction type changes within a unit time window (e.g., every 1 millisecond), reflecting the frequency of instruction type changes per unit time. Stability characteristics include the periodic pattern of instruction switching.

[0038] The recurrent neural network (RNN) uses an LSTM with the Adam optimizer, a learning rate of 0.001, 1000 training epochs, and a batch size of 32. Training data consists of instruction switching frequency time series collected over the past three months, with a uniform sequence length of 300 time steps (corresponding to 5-minute sampling). Input features are z-score standardized. Mean squared error loss is used, with L2 regularization (coefficient 0.01) to prevent overfitting. Early stopping is employed during training; training terminates when the validation set loss fails to decrease for 10 consecutive epochs. Hidden layers are single-layer LSTM structures with 64 hidden units, and the output layer is a fully connected linear layer. All parameters are initialized using Xavier, and the gradient clipping threshold is set to 1.0. In the output layer of an RNN, the process of extracting a quantitative indicator representing sequence stability involves the following steps: The recurrent neural network processes each data point in the sequence sequentially. At each time step, the network combines the current input with the hidden state from the previous time step to calculate a new hidden state. As processing progresses, the hidden state is continuously updated, accumulating contextual information for the entire sequence. After processing the last data point, the final hidden state contains the complete features of the entire sequence. Fully connected layers map the hidden state to multiple output nodes, use linear activation functions for regression tasks, and then convert volatility into a percentage form through normalization. The calculation formula for each recurrent neural network unit can be set as: in, For the new state, The input weights are obtained through prior training. For the current input, These are the recurrent weights, obtained through prior training. The old state For bias terms, This is the hyperbolic tangent function. The fully connected layer uses the ReLU function to... The output is a percentage of fluctuation, which represents the stability feature. For example, a sequence of instruction switching frequencies: [9, 11, 10, 12, 8] (unit: times / millisecond) is sequentially input into a recurrent neural network. Each input yields an updated hidden state. The final result The input is then fed into a fully connected layer, which outputs 0.06 through the ReLU function, which represents a volatility of 6%. 6% is the stability characteristic.

[0039] For example, if the stability characteristic is 6%, i.e., the volatility is 6%, and the preset stability condition is a volatility of less than 15%, satisfying the preset stability condition indicates that the instruction flow has strong regularity. Therefore, the power consumption prediction mapping parameters can be output as the preliminary verification mapping parameters. The preset stability condition is a balance point found based on analyzing the relationship between historical load patterns, control system stability requirements, and model prediction accuracy, which maximizes the reliability and effectiveness of the power consumption management strategy.

[0040] It should be noted that by running one or more standardized benchmark programs, such as matrix multiplication and image processing kernels, and using the current preliminary verification mapping parameters, the resource utilization of each functional unit of the chip is monitored in real time when performing these tasks, resulting in a quantified task load distribution. The Apriori algorithm is used to calculate the relationship between the task load distribution and the data dependency strength, obtaining a quantified load-dependency association strength. This load-dependency association strength is input into a nonlinear regression model to obtain preliminary power consumption prediction results. The Apriori algorithm is the same as described above and will not be repeated here; the input layer of the nonlinear regression model receives a feature vector, such as [ALU utilization, Mem utilization, Branch utilization, data dependency strength]. The hidden layer contains a fully connected layer using ReLU as the activation function, and the output layer uses a linear activation function to directly output the predicted power consumption value. The model is trained offline using supervised learning and the Adam optimizer. The initial learning rate is set to 0.001, and a learning rate decay strategy is adopted, decreasing to 0.9 every 50 epochs. The batch size was set to 64, the training cycle was 500 rounds, and an early stopping mechanism was used during training. Training was terminated when the validation set loss did not decrease for 20 consecutive rounds to prevent overfitting. Training data came from a massive amount of historical chip operation records, covering various working scenarios from low to high load. The dataset was divided into training, validation, and test sets in a 7:2:1 ratio. After training, power consumption predictions were generated. ,in. The weight matrix from the input layer to the hidden layer The bias vector of the hidden layer. For activation function, The weight vector from the hidden layer to the output layer. For the bias scalar of the output layer, This represents the predicted power consumption. For example, running a dense matrix operation task, we observed that the arithmetic logic unit (ALU) utilization was 90%, the memory access unit (Memory) utilization was 70%, and the branch prediction unit (BRF) utilization was 10%. The distribution [90%, 70%, 10%] represents the load characteristics of this type of dense matrix operation task. Using the Apriori algorithm, we found that the load distribution [high ALU utilization, high Mem utilization] has a correlation strength of 0.8 with high data dependencies such as load-store operations. Inputting [90%, 70%, 10%] and 0.8 into a nonlinear regression model yields a preliminary power consumption prediction of 60mW.

[0041] Based on the preliminary power consumption prediction results, the Q-learning algorithm is used to optimize the operation density parameters. The state is defined as the preliminary power consumption prediction result, and the action space consists of five discrete operation instructions for adjusting the power consumption parameters: parameter increases / decreases in units of 0.01, larger adjustments in units of 0.05, and keeping the parameters unchanged. These parameters are internal model weights or coefficients directly related to operation density, data dependency strength, etc. The reward is a feedback signal based on the prediction accuracy; for example, a reward... Where R represents the reward value and ε represents the prediction error, i.e., | ,in For predicted values, The true value is represented by I(·), which is an indicator function that takes the value 1 when the condition is met and 0 otherwise. This means that a positive reward is only obtained when the model's prediction error is below the strict threshold of 5%. The power consumption prediction result is obtained through 1000 iterations. The iterations are set with a learning rate α = 0.1, a discount factor γ = 0.9, and an exploration rate ε that linearly decreases from 1.0 to 0.01. An ε-greedy action selection is used, and the Q-value is finally updated using the Bellman equation. For example, the reward function is set to receive a positive reward when the prediction error is below 5%. Assuming the initial operation density parameter is 0.7, adjusted to 0.65 after 1000 Q-learning iterations, the optimized model predicts a peak power consumption of 110mW in high-load tasks, with the error reduced to 3%.

[0042] In step S14, the instruction switching frequency and data dependency strength are obtained, and combined with the power consumption prediction results, the synchronization timing requirements of the power supply state are calculated to determine the initial power supply configuration, including: Acquire command switching frequency and data dependency strength; The instruction switching frequency and the data dependency strength are preprocessed to extract frequency change features and dependency strength distribution features, thereby obtaining a set of data features; Based on the data feature set, the activation timing requirements of the computing unit are determined. If the activation timing requirements exceed the preset timing stability threshold, the activation triggering conditions of the unit are adjusted, and the activation timing set is determined. Power supply status data is extracted from the activation timing set, and the synchronization timing requirements of the power supply status data are processed and calculated to obtain a synchronization timing requirement set. Based on the set of synchronization timing requirements, the allocation parameters of the power supply status are determined, and the initial power supply configuration is generated.

[0043] Instruction switching frequency is calculated by counting the number of times instruction types change within a unit time window (e.g., every 1 millisecond), reflecting the frequency of instruction type changes per unit time. Data dependency strength reflects the degree of data correlation between instructions and can be calculated through the "Calculate Data Dependency Strength" step in step S12.

[0044] The instruction switching frequency and data dependency strength are processed using an autoregressive model. For frequency variation characteristics, the rate of change of the frequency variation characteristic sequence within a time window is calculated through linear fitting to obtain the trend slope. The standard deviation or variance of the frequency variation characteristic within this time window is calculated to obtain volatility. For dependency strength distribution characteristics, the mean, median, maximum (peak), and minimum values ​​of dependency strength are calculated to obtain distribution statistics. The main periodic components and their strengths are extracted using a fast Fourier transform to obtain periodic characteristics. All the extracted features (trend slope, volatility, peak, periodic characteristics, etc.) are combined into a structured, fixed-dimensional feature vector. This feature vector is the data feature set.

[0045] The autoregressive model adopts the AR(p) form, and its mathematical expression is as follows: in, Let c represent the observed value at the current moment, and c be a constant term obtained by fitting the data from historical training data using maximum likelihood estimation. These are autoregressive coefficients, representing the degree of influence of historical values ​​on the current value. The model order represents the number of historical data points considered. The white noise error term is estimated from data during model fitting. The activation timing requirements of the computational unit are calculated. If these requirements exceed a preset timing stability threshold, the triggering conditions are dynamically adjusted using a PID algorithm. Then, the activation behavior of the functional unit is recalculated or simulated using the adjusted triggering conditions, resulting in a new, stable set of activation timings. The timing requirement vector is defined as [activation frequency (times / millisecond), activation duration (microseconds)], where the activation frequency is the average number of times the unit needs to be activated per unit time, calculated using the formula... .in, The slope of the frequency trend. The current reference frequency, This is for predicting the time window. Activation duration is the average time required for each activation, calculated using the following formula: , Dependence on intensity peak, Main cycle intensity, This is the base activation duration for this functional unit.

[0046] Dynamically adjusting trigger conditions using a PID algorithm includes calculating the deviation between the current active volatility and the target volatility. in, The current monitored fluctuation rate of the activation frequency of functional units. The target volatility is defined as the preset time-series stability threshold. The adjustment amount for the trigger condition is calculated based on the PID control law. in, , , These are the proportional, integral, and derivative coefficients, respectively. PID parameters can be tuned by observing the system response under simulated loads, for example, using... =-0.03, =-0.005, Using -0.01 as the initial value, the feedforward compensation function can be approximated by the load characteristic model, such as... ΔT_ff =α ( L_current - L_base ), where α is the load-trigger condition correlation coefficient, which is calibrated through load-trigger condition experiments. L_base This represents the baseline load value, i.e., the set standard load reference value. L_current This represents the current load intensity characteristic value. For example, to compensate for the impact of increased load intensity, the feedforward compensation amount is calculated based on real-time collected command stream data using a pre-established load-trigger condition relationship model: in, This represents the current load intensity characteristic value. This is the compensation function calibrated through experiments.

[0047] Set the adjusted trigger condition parameters as follows: T_new=T_initial+ΔT+ΔT_ff in T_new For the adjusted trigger condition parameters (such as the new instruction queue depth threshold). ΔT This indicates the PID feedback adjustment amount. T_initialThe initial trigger condition parameters are defined as follows. For example, the initial trigger condition T_initial = 0.8, meaning the initial trigger threshold is 0.8. The calculated PID adjustment ΔT = -0.2 and the feedforward compensation ΔT_ff = -0.05. Therefore, the new trigger condition is T_new = 0.8 + (-0.2) + (-0.05) = 0.55. Based on this, the activation threshold of the calculation unit is dynamically adjusted from 0.8 to 0.55, thereby achieving smoother activation control and effectively suppressing fluctuations.

[0048] It is worth noting that power supply state data is extracted from the activation time series. Power supply states can be simplified to high power supply states (i.e., the unit is in an active working state) and low power supply states (i.e., the unit is in an idle or low-power sleep state). Each functional unit is represented as a power supply state time series. Then, a Markov chain model is used to establish a joint state space for each pair of functional units that need to cooperate, such as a computing unit and a memory access unit. By analyzing historical or predicted power supply state data, the probabilities of state transitions are statistically analyzed to construct a state transition probability matrix.

[0049] It should be noted that the state space of a Markov chain defines a joint state for each pair of functional units that need to cooperate (such as a computation unit CU and a memory access unit MU). Each unit has two states, H (high power supply) and L (low power supply). Therefore, the joint state space is S={(CU_H,MU_H),(CU_H,MU_L),(CU_L,MU_H),(CU_L,MU_L)}. This is a set containing four states. The state transition probability matrix P is a 4x4 matrix, where each element P{ij} represents the probability of transitioning from state i to state j. The training process of the Markov chain model includes: First, creating a 4x4 counting matrix C, initializing all elements to 0, and traversing the historical power supply state sequence. Then, for each consecutive time step (t,t+1), at time t, determining its corresponding joint state i. At time t+1, determining its corresponding joint state j (e.g., (CU_L,MU_H)). Afterward, incrementing the corresponding element C_{ij} in the counting matrix C by 1. Iterate through each row i of the counting matrix C, and divide each count C{ij} in that row by the sum ΣkC{ik} of that row to obtain the probability of transitioning from state i to all possible states j, thus obtaining the state transition probability matrix P.

[0050] It should be noted that the formula for calculating synchronization requirements is as follows: in, This represents the expected frequency of transition from state i to state j, i.e., the synchronization requirement. Let represent the probability of state i in the steady-state probability distribution of a Markov chain. Indicates from state i Transition to state j For example, after analyzing the activation timing set, the transition probability shows that the compute unit is in a high-power state 50% of the time during high-load tasks, and the memory access unit is in a high-power state 30% of the time during high-load tasks. Model analysis reveals that the most critical path is that when the compute unit switches from "high" to "low", the memory access unit must simultaneously switch from "low" to "high" to receive the computation results. This specific coordinated switching event is predicted by the model to occur 3 times per second, at which point the synchronization timing requirement set is {(compute unit, memory access unit): 3 times / second, (compute unit, cache control unit): 1 time / second,...}.

[0051] Based on the set of synchronization timing requirements, the Q-learning algorithm is used to determine the power supply state allocation parameters and generate an initial power supply configuration. In the Q-learning algorithm, the state is defined as the set of synchronization timing requirements and the current task load classification, and the action is defined as adjusting the power supply state allocation parameters. These parameters are core variables determining the power supply strategy, such as power supply priority, power channel allocation, and state switching lead time. The reward is defined as... in , , It's weight. C Indicates the power supply conflict rate. P Indicates a percentage performance improvement. E This represents the system's energy consumption. This function explicitly rewards strategies with low conflict, high performance, and low energy consumption. After multiple iterations of Q-learning, an optimal set of parameters is output, which is the initial power supply configuration. In the Q-learning algorithm, the following parameter configuration is used: learning rate α = 0.1, discount factor γ = 0.9, and exploration rate ε is linearly decayed from 1.0 to 0.01. The training process involves 1000 iterations, with 64 sets of experience samples sampled per batch. The target network synchronizes its online network parameters every 100 steps. The experience replay buffer capacity is set to 10000, and training begins when the buffer is 50% full. The reward function weights are configured as (w1, w2, w3) = (0.5, 0.3, 0.2). The Q-network uses a three-layer fully connected structure with a hidden layer dimension of 128, and all parameters are initialized using He.

[0052] For example, the set of synchronization timing requirements is {(computation, memory access): 3 times / second}, and the task load is classified as (e.g., "high load, computation-intensive"). After 1000 iterations, the Q-learning algorithm converges to a set of optimal power supply state allocation parameters, with the power supply priority of the computation unit = 0.9, and a dedicated power supply channel is allocated to the (computation unit, memory access unit) pair. The state switching lead is 2 clock cycles.

[0053] In step S15, the step of monitoring the task load classification signal according to the initial power supply configuration, and adjusting the power consumption allocation ratio to determine the optimized power supply configuration if the task load classification signal is lower than a preset signal threshold, includes: The initial power supply configuration is executed, the task load classification signal is monitored and preprocessed in real time, and the load classification features are extracted to obtain the load classification feature set. Based on the load classification feature set, the power allocation ratio is adjusted to generate a power allocation set; Based on the power consumption allocation set and the activation level data of the processing unit, the energy consumption distribution is calculated to obtain the energy consumption distribution set; For the energy consumption distribution set, the Q-learning algorithm is used to optimize the power supply configuration parameters and determine the optimal power supply configuration.

[0054] First, the initial power supply configuration is executed, while simultaneously monitoring raw signals reflecting task load in real time, including instruction execution rate, memory access frequency, and instruction mixing ratio. Next, the raw signals are denoised and normalized using a min-max normalization method. Here, `max` is taken from the peak value observed during the training phase based on the chip's historical performance data under typical workloads, and `min` is taken from the stable minimum value observed in the lowest load benchmark test. Then, the preprocessed signals are analyzed, including calculating the slope or linear fitting coefficients of the signal within a short window; extracting the periodic components and their amplitudes using a Fast Fourier Transform; and calculating the mean, variance, and peak value of the signal. Finally, all the features extracted from the signals are combined into a structured, fixed-dimensional feature vector. This feature vector is the load classification feature set. For example, the load classification feature set can be represented as: {mean instruction rate: 90, peak instruction rate: 120, instruction rate periodicity: 0.75, memory access uniformity: 0.4,...}.

[0055] In one embodiment, low-load tasks are identified based on load classification characteristics. Then, the corresponding optimized configuration is retrieved from a predefined "load state-power ratio" policy library. During the adjustment process using the optimized configuration, it is crucial to ensure that the power ratio switching is smooth and gradual, rather than abrupt. For example, the ratio can be adjusted in 1% increments to prevent instability caused by drastic changes in resource allocation. After adjustment, a structured power allocation set is generated, recording the new power ratio of each functional unit and the expected duration and application conditions of this configuration. It should be noted that the condition for a low-load task is that the utilization rate of critical hardware resources is consistently below a certain threshold (e.g., 20%-30%) of their peak capacity. For example, in the initial power supply configuration, compute units account for 60% and memory access units account for 40%. For low-load scenarios, the policy library instructs that the power ratio of compute units be reduced to 40%, and the power ratio of memory access units be adjusted to 30%. After adjustment, the power allocation set is as follows: the power ratio of compute units remains stable at 40% for 10 minutes, and the power ratio of memory access units remains at 30% for 8 minutes.

[0056] It should be noted that the process of building the "load state-power ratio" strategy library includes: first, running a benchmark test program covering various typical workloads to collect characteristic data and corresponding optimal power allocation ratios under different load states; then, determining standardized power allocation configurations for each load state category through statistical analysis and optimization calculations; and finally forming a fully validated mapping relationship library between load states and power allocation ratios.

[0057] It is worth noting that the actual activation data of each functional unit is monitored and recorded in real time, i.e., the percentage of time a functional unit is in an active working state per unit time, while the state switching frequency of the functional unit is also accurately recorded. The activation duration and switching frequency of each unit are multiplied by a preset power consumption model to calculate the specific energy consumption of that unit within the statistical period. The energy consumption calculation results of all these units are summarized and standardized to form a structured energy consumption distribution set. This set records the actual contribution ratio of each functional unit to the total energy consumption under a specific power allocation strategy. The preset power consumption model includes the chip's energy consumption under different operating states. Based on the circuit netlist of each functional unit, precise power consumption simulation is performed under different operating conditions using SPICE-level simulation tools. By scanning various operating states, a complete power consumption model including static power consumption, dynamic power consumption, and state switching power consumption is established. The energy consumption distribution set is input into a Q-learning algorithm, and the state space... , The percentage of energy consumption for the unit with the highest energy consumption. The degree of imbalance in energy consumption distribution. Total energy consumption, Classify task load. Among them, , , Obtained from the energy consumption distribution set. The reward function is derived from task load characteristics. The action space involves fine-tuning power supply configuration parameters, such as adjusting the power supply priority of each unit, sleep timeout time, or the bias point of the voltage-frequency curve. ,in For energy waste rate, This is a performance penalty; the value is positive when the task completion time exceeds a preset time threshold, and 0 otherwise. This is a tradeoff coefficient. An optimized power supply configuration was obtained through 1000 iterations of pre-training in a simulated environment. The preset time threshold is determined based on the critical task performance targets that the chip needs to guarantee; for example, if a real-time computing task requires a single-frame processing time ≤16ms, the threshold is set to 16ms. The tradeoff coefficient, λ, is selected through Pareto front analysis to ensure the system operates at the optimal energy consumption-performance balance point, representing the energy waste rate. ,in, As a baseline energy consumption, This represents the actual total energy consumption. For example, the initial power supply configuration results in an 8% energy waste rate. Through Q-learning iterative adjustments, higher power supply priorities are prioritized for computing units, such as increasing the priority from 0.5 to 0.7. This optimization generates the first set of power supply configurations.

[0058] In step S16, based on the optimized power supply configuration, the power consumption allocation ratio is further adjusted to obtain an improvement index for resource allocation efficiency, including: The optimized power supply configuration is executed, the dynamic change vector of the instruction is obtained and processed, and dynamic features are extracted to obtain a dynamic feature set; Based on the dynamic feature set, the power consumption allocation ratio is adjusted to generate a resource allocation set; If the resource allocation set does not match the preset resource allocation threshold, the power consumption allocation ratio is adjusted to obtain a corrected power consumption set. Based on the corrected power consumption set, the resource allocation efficiency data is processed to obtain the resource allocation efficiency improvement index.

[0059] First, the integrated hardware performance monitoring unit within the chip captures the dynamic behavior of the instruction stream in real time, acquiring a continuous sequence of dynamic instruction change vectors. These vector data contain multi-dimensional information such as instruction type distribution, instantaneous rate of change of execution frequency, and data dependencies between instructions. The acquired vector sequences are then processed online. This process includes performing a Fast Fourier Transform on the instruction execution frequency sequence to extract its periodic features; calculating the information entropy value of the instruction type distribution sequence to quantify the randomness and stability of instruction mixing; and performing autocorrelation analysis on the data dependency sequence to capture its temporal correlation patterns. All these analysis results are combined in real time into a comprehensive dynamic feature set, which quantitatively characterizes the dynamic behavior pattern of the instruction stream under optimized power supply conditions.

[0060] Based on the dynamic feature set, the chip resource allocation ratio is finely adjusted. By analyzing key indicators such as instruction type distribution entropy, execution frequency fluctuation patterns, and dependency strength in the dynamic feature set, the core characteristics of the current instruction stream are identified. When the proportion of arithmetic logic instructions exceeds a set threshold, the execution frequency remains high and stable, and the data dependencies exhibit a regular computational chain structure, a resource reallocation process is initiated to obtain a resource allocation set. The resource reallocation process first reads the current resource allocation baseline configuration, and then gradually allocates power consumption according to a preset load characteristic-resource configuration mapping rule. This adjustment is smoothly completed through multiple control cycles, with each cycle allowing only a limited range of proportional changes; for example, the power allocation ratio can change by a maximum of 5% in one cycle. It should be noted that the preset load characteristic-resource configuration mapping rule is derived by running various types of programs on the chip to summarize the optimal power allocation ratio setting for different loads, resulting in the best performance and most energy-efficient power consumption.

[0061] If the resource allocation set does not match the preset resource allocation threshold, then according to step S162, the power consumption allocation ratio continues to be adjusted until it matches the preset resource allocation threshold, thus obtaining a corrected power consumption set. The preset resource allocation threshold is determined based on resource allocation when running critical applications. For example, for real-time image processing tasks, the preset resource allocation threshold may require the resource allocation ratio of the computing unit to be no less than 55% to ensure the real-time requirement that the processing time per frame does not exceed 16ms; while for data throughput-intensive tasks, it requires the resource allocation ratio of the storage unit to be no less than 30% to ensure a data throughput of no less than 500MB / s.

[0062] It is worth noting that a complete benchmark test cycle was stably run on the chip based on the corrected power consumption configuration, during which key performance counter data was continuously collected, including raw indicators such as task completion time of computing units, data throughput of storage units, and overall system energy consumption. Then, based on the corrected power consumption set, a linear regression algorithm was used to process the resource allocation efficiency data. The dependent variable of this model is an efficiency indicator such as task completion time or throughput, while the independent variables include the final power consumption allocation ratio of each functional unit, task type feature vectors, and interaction terms between them. By performing regression analysis on the measured efficiency data under the current corrected configuration and the efficiency data under the historical benchmark configuration, and by creating dummy variables for each task type and incorporating them as independent variables into the regression analysis, the model can separate the benchmark impact of the inherent characteristics of task types on efficiency.

[0063] In step S17, based on the resource allocation efficiency improvement index and the constraints of the dynamic adjustment cycle, a dynamic adjustment framework is determined, including: Extract performance and energy efficiency constraint data from the resource allocation efficiency improvement indicators; Based on the performance and energy efficiency constraint data, the clock cycle constraint is dynamically adjusted to obtain the first fusion constraint set; Based on the first fusion constraint set, the power consumption nonlinear mapping relationship is updated to obtain the first updated mapping relationship; Determine whether the first updated mapping relationship satisfies the preset balance condition. If it does not, adjust the first fusion constraint set to obtain the second fusion constraint set. If it does, directly output the first fusion constraint set as the second fusion constraint set. Based on the second set of fusion constraints, the first update mapping relationship is processed to determine the initial adjustment parameters for chip power management, thereby obtaining a set of adjustment parameters; Based on the set of adjustment parameters, matching dynamic parameters are obtained from a preset resource threshold library to determine the dynamic adjustment framework for chip power consumption management.

[0064] The resource allocation efficiency improvement indicators are correlated with the currently running baseline task type to obtain performance and energy efficiency constraint data. For example, for compute-intensive tasks, a 10% efficiency improvement in computing units is converted into an absolute performance constraint of "task completion time not exceeding 2 seconds"; for data-intensive tasks, a 5% efficiency improvement in storage units is quantified as a bandwidth constraint of "data throughput not less than 500MB / s". The final output constraint dataset clearly defines the specific goals to be achieved in the next stage of dynamic adjustment. The quantification rules are based on a lookup table method, creating a quantification lookup table using historical data. Based on the lookup table, the resource allocation efficiency improvement indicators and the currently running baseline task type are converted into performance and energy efficiency constraint data.

[0065] It should be noted that tasks with a very high instruction ratio (>60%) can be defined as intensive tasks. For example, tasks with a logic unit instruction ratio (>60%) are defined as compute-intensive tasks, and tasks with a memory access instruction ratio (>60%) are defined as data-intensive tasks. This ratio is based on historical data analysis.

[0066] First, data such as resource allocation efficiency indicators and command flow characteristics changes over the past 5 minutes are constructed into a high-frequency sampling time series with a sampling frequency of 1kHz. An autoregressive integral moving average model is used to analyze its periodicity and fluctuation characteristics. Then, the stable periodic pattern of the system efficiency indicators is identified, and the optimal adjustment frequency is derived accordingly. Simultaneously, the moving standard deviation and peak value of the efficiency indicators are calculated. These time-series derived constraints are then multidimensionally fused with the original absolute performance energy efficiency constraints, ultimately generating the first fused constraint set. It should be noted that the autoregressive integral moving average model is denoted as... Where d is the difference order, usually 1, and p and q are the orders of autoregression and moving average, respectively. These are the autoregressive coefficients. The coefficients are moving averages. During training, historical resource allocation efficiency time series data from the past few months are first input. Based on the ACF and PACF plots of the differencing series, the initial range of values ​​for p and q is determined. Then, for candidate (p, d, q) combinations, maximum likelihood estimation is used to estimate all autoregressive coefficients in the model. and moving average coefficient Finally, calculate the AIC or BIC value for each candidate model, and select the one with the smallest value as the final model.

[0067] Based on the first set of fusion constraints, a reinforcement learning-driven online model update process is initiated. Specifically, using the current power consumption nonlinear mapping relationship as the initial policy network, a state space containing dynamic features such as instruction frequency and data dependency strength is constructed, represented as s=[x,c]=[instruction frequency, data dependency strength, ..., adjustment period threshold, fluctuation upper limit, performance lower limit]. The first set of fusion constraints is encoded into the reward function. ,in, Basic rewards, These are penalties for adjusting the cycle, fluctuation limit, and performance floor, respectively. This represents the corresponding penalty weight.

[0068] A positive reward of +1 is given when the model's predicted power allocation scheme simultaneously meets the adjustment cycle requirement, fluctuation range limit, and performance baseline; if the prediction leads to any violation of constraints, such as excessive fluctuation or substandard performance, a penalty of -0.5 is imposed. Through interaction with the environment, the agent continuously attempts to map input features to power output and adjusts model parameters based on immediate rewards. After 500 rounds of offline pre-training in a simulated environment, the first updated mapping relationship is finally generated.

[0069] It should be noted that the reinforcement learning model employs an actor-critic framework, using the policy gradient theorem to update the actor network by maximizing the expected Q-value. Training is conducted offline in a simulated environment with a learning rate of Actor=0.001, Critic=0.002, discount factor γ=0.95, replay buffer size=10000, batch size=64, target network update coefficient τ=0.01, and exploration noise using the OU process, θ=0.15, σ=0.2. Determine whether the first updated mapping relationship meets the preset balance condition. If not, query the historical operation database to find fluctuation patterns that are highly similar in key fluctuation characteristics at similar fluctuation levels (generally set to historical cases where the fluctuation rate difference does not exceed 1%) and still maintain system stability. Then, based on this prior knowledge, relax the constraints in the first fusion constraint set. The new constraints can be set as follows: ,in For the old constraints, The standard deviation of the constraint set is used to obtain the second fused constraint set. If satisfied, the first fused constraint set is directly output as the second fused constraint set. For example, when the first update mapping relationship causes a volatility of 16% in the test, exceeding the volatility threshold of 15%, while other constraints do not exceed the threshold, the upper limit of volatility is adjusted to 18% according to the mean plus standard deviation method, while other constraints remain unchanged. This generates the second fused constraint set. It should be noted that the preset balance condition is to run various loads on the chip while monitoring all key indicators such as performance, power consumption, temperature, and stability to find the optimal balance condition. For example, the preset balance condition can be set to a task completion time of no more than 2.0 seconds, an energy waste rate of no more than 5%, a power output volatility of less than 15%, and a strategy adjustment interval of more than 30 seconds.

[0070] Based on the second set of fused constraints, a linear programming model is constructed with the core objective of minimizing the total system power consumption. Conditions such as periodicity and fluctuation limits in the second set of constraints are transformed into model constraints, and the input-output characteristics represented by the first update mapping relationship are embedded into the objective function. After calculation, the linear programming model outputs the optimal power allocation scheme that satisfies all constraints, forming preliminary adjustment parameters, thus obtaining the set of adjustment parameters. It should be noted that the decision variables in the linear programming model are the unknowns to be optimized, i.e., the power consumption allocation of each functional unit. The objective function is the linear function to be minimized, i.e., the total system power consumption. The expression for the total system power consumption is: ,in, : Calculate the unit power consumption ratio, : Power consumption ratio of storage units Other / communication unit power consumption ratio. Constraints are set according to the second fusion constraint set. The process of embedding the input-output characteristics represented by the first update mapping relationship into the objective function includes: firstly, performing local sampling in the input space of the first update mapping relationship to obtain a set of sample points. Then, using this set of sample points, a simple linear model is fitted through linear regression. .in For instruction frequency, For data dependency strength, For weight parameters, As a bias term, this linear model is a local linear approximation of the first update mapping at the current working point. Finally, a linear surrogate model is used. To predict the minimum power consumption ratio required by each unit to meet the performance baseline, we use this as a constraint condition for the linear programming model.

[0071] It should be noted that key values ​​in the adjustment parameter set (such as 55% of the computing unit power consumption) are used as query keys to perform multi-dimensional matching searches in the resource threshold library to obtain associated dynamic operating parameters, including real-time control parameters such as the execution frequency limit of 300 times / second and the instruction dependency ratio of 30%. Then, the association rule analysis engine Sabre is used to fuse and verify these dynamic parameters with the adjustment parameter set. By calculating the support and confidence of parameter combinations, it is determined whether the framework generation conditions are met. When the association strength of the key parameter combination exceeds the preset threshold, it is confirmed that the generation conditions of the dynamic adjustment framework have been met. The final output chip power management dynamic adjustment framework is a comprehensive system that includes static power allocation strategies, dynamic operating parameter constraints, and association verification rules.

[0072] In summary, this invention discloses a chip dynamic power consumption scheduling method based on intelligent algorithms, which solves the problem of low resource allocation efficiency during chip operation.

[0073] Reference Figure 2 The second embodiment of the present invention provides a chip dynamic power consumption scheduling device based on intelligent algorithms, comprising: The feature extraction module is used to collect instruction stream data during chip operation in real time, and uses a convolutional neural network to extract instruction feature vectors to obtain instruction dynamic change vectors and instruction context association data. The mapping modeling module is used to construct a power consumption nonlinear mapping relationship and determine power consumption prediction mapping parameters based on the instruction dynamic change vector and the instruction context association data. The parameter verification module is used to adjust the weights of the convolutional neural network when the power prediction mapping parameters exceed the preset performance and energy efficiency constraint threshold, to verify the stability of the power prediction mapping parameters and obtain the power prediction result. The power supply optimization module is used to obtain the instruction switching frequency and data dependency strength, and in combination with the power consumption prediction results, calculate the synchronization timing requirements of the power supply state and determine the initial power supply configuration. The power allocation module is used to monitor the task load classification signal according to the initial power supply configuration. If the task load classification signal is lower than a preset signal threshold, the power allocation ratio is adjusted to determine the optimized power supply configuration. The resource allocation module is used to further adjust the power consumption allocation ratio based on the optimized power supply configuration to obtain the resource allocation efficiency improvement index. The framework generation module is used to determine the dynamically adjusted framework by dynamically adjusting the periodic constraints based on the resource allocation efficiency improvement indicators.

[0074] It should be noted that the chip dynamic power consumption scheduling device based on intelligent algorithm provided in this embodiment of the invention is used to execute all the process steps of the chip dynamic power consumption scheduling method based on intelligent algorithm in the above embodiment. The working principle and beneficial effect of the two are one-to-one, so they will not be described again.

[0075] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0076] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A chip dynamic power consumption scheduling method based on intelligent algorithms, characterized in that, include: The instruction stream data during chip operation is acquired in real time, and the instruction feature vector is extracted using a convolutional neural network to obtain the instruction dynamic change vector and instruction context association data; Based on the instruction dynamic change vector and the instruction context association data, a power consumption nonlinear mapping relationship is constructed, and power consumption prediction mapping parameters are determined. If the power consumption prediction mapping parameters exceed the preset performance and energy efficiency constraint threshold, adjust the weights of the convolutional neural network, verify the stability of the power consumption prediction mapping parameters, and obtain the power consumption prediction result. The command switching frequency and data dependency strength are obtained, and combined with the power consumption prediction results, the synchronization timing requirements of the power supply state are calculated to determine the initial power supply configuration. Based on the initial power supply configuration, the task load classification signal is monitored. If the task load classification signal is lower than a preset signal threshold, the power consumption allocation ratio is adjusted to determine the optimized power supply configuration. Based on the optimized power supply configuration, the power consumption allocation ratio is further adjusted to obtain the resource allocation efficiency improvement index; Based on the resource allocation efficiency improvement indicators and the constraints of the dynamic adjustment cycle, a dynamic adjustment framework is determined.

2. The chip dynamic power consumption scheduling method based on intelligent algorithms according to claim 1, characterized in that, The real-time acquisition of instruction stream data during chip operation uses a convolutional neural network to extract instruction feature vectors, obtaining instruction dynamic change vectors and instruction context association data, including: The instruction stream data during chip operation is acquired in real time to obtain the original instruction sequence; A convolutional neural network is used to extract the instruction feature vector from the original instruction sequence; If the instruction feature vector satisfies a preset instruction threshold, then a dynamic instruction change vector is generated based on the instruction feature vector. Based on the instruction dynamic change vector, the instruction context association strength is calculated to obtain the preliminary quantization representation matrix; The preliminary quantization representation matrix is ​​matched with a preset context association library to obtain instruction context association data.

3. The chip dynamic power consumption scheduling method based on intelligent algorithms according to claim 1, characterized in that, The step of constructing a power consumption nonlinear mapping relationship and determining power consumption prediction mapping parameters based on the instruction dynamic change vector and the instruction context association data includes: By processing the instruction dynamic change vector and the instruction context association data through a convolutional neural network, the operation density distribution is extracted to obtain a preliminary power consumption mapping input. Based on the initial power consumption mapping input, the data dependency strength is calculated to generate initial parameters for the nonlinear mapping. If the preliminary parameters of the nonlinear mapping exceed the preset intensity distribution threshold, the preliminary power consumption mapping input is adjusted to obtain the core parameters of the nonlinear mapping. Based on the core parameters of the nonlinear mapping, a power consumption nonlinear mapping relationship is constructed to obtain the mapping function; According to the mapping function, the operation density distribution and the data dependency strength are input and calculated to obtain the execution result, and the power consumption prediction mapping parameters are determined based on the execution result.

4. The chip dynamic power consumption scheduling method based on intelligent algorithms according to claim 3, characterized in that, If the power prediction mapping parameters exceed a preset performance and energy efficiency constraint threshold, the weights of the convolutional neural network are adjusted to verify the stability of the power prediction mapping parameters and obtain the power prediction result, including: If the power consumption prediction mapping parameters exceed the preset performance and energy efficiency constraint threshold, the weights of the convolutional neural network are adjusted to obtain the adjusted weights. Based on the adjusted weights, historical data of instruction stream timestamps and instruction switching frequencies are obtained and processed to extract stability features. If the stability feature satisfies the preset stability condition, then the preliminary verification mapping parameters are determined; The task load distribution is extracted from the preliminary verification mapping parameters, and preliminary power consumption prediction results are generated based on the task load distribution and the data dependency strength. Based on the preliminary power consumption prediction results, the power consumption adjustment parameters are optimized to obtain the final power consumption prediction results.

5. The chip dynamic power consumption scheduling method based on intelligent algorithms according to claim 1, characterized in that, The process of acquiring the instruction switching frequency and data dependency strength, and combining this with the power consumption prediction results to calculate the synchronization timing requirements of the power supply state and determine the initial power supply configuration includes: Acquire command switching frequency and data dependency strength; The instruction switching frequency and the data dependency strength are preprocessed to extract frequency change features and dependency strength distribution features, thereby obtaining a set of data features; Based on the data feature set, the activation timing requirements of the computing unit are determined. If the activation timing requirements exceed the preset timing stability threshold, the activation triggering conditions of the unit are adjusted, and the activation timing set is determined. Power supply status data is extracted from the activation timing set, and the synchronization timing requirements of the power supply status data are processed and calculated to obtain a synchronization timing requirement set. Based on the set of synchronization timing requirements, the allocation parameters of the power supply status are determined, and the initial power supply configuration is generated.

6. The chip dynamic power consumption scheduling method based on intelligent algorithms according to claim 1, characterized in that, The step of monitoring the task load classification signal based on the initial power supply configuration, and adjusting the power consumption allocation ratio to determine the optimized power supply configuration if the task load classification signal is lower than a preset signal threshold, includes: The initial power supply configuration is executed, the task load classification signal is monitored and preprocessed in real time, and the load classification features are extracted to obtain the load classification feature set. Based on the load classification feature set, the power allocation ratio is adjusted to generate a power allocation set; Based on the power consumption allocation set and the activation level data of the processing unit, the energy consumption distribution is calculated to obtain the energy consumption distribution set; For the energy consumption distribution set, the Q-learning algorithm is used to optimize the power supply configuration parameters and determine the optimal power supply configuration.

7. The chip dynamic power consumption scheduling method based on intelligent algorithms according to claim 1, characterized in that, The step of further adjusting the power consumption allocation ratio based on the optimized power supply configuration to obtain an improvement index for resource allocation efficiency includes: The optimized power supply configuration is executed, the dynamic change vector of the instruction is obtained and processed, and dynamic features are extracted to obtain a dynamic feature set; Based on the dynamic feature set, the power consumption allocation ratio is adjusted to generate a resource allocation set; If the resource allocation set does not match the preset resource allocation threshold, the power consumption allocation ratio is adjusted to obtain a corrected power consumption set. Based on the corrected power consumption set, the resource allocation efficiency data is processed to obtain the resource allocation efficiency improvement index.

8. The chip dynamic power consumption scheduling method based on intelligent algorithms according to claim 1, characterized in that, The dynamic adjustment framework, determined based on the resource allocation efficiency improvement indicators and the constraints of the dynamic adjustment cycle, includes: Extract performance and energy efficiency constraint data from the resource allocation efficiency improvement indicators; Based on the performance and energy efficiency constraint data, the clock cycle constraint is dynamically adjusted to obtain the first fusion constraint set; Based on the first fusion constraint set, the power consumption nonlinear mapping relationship is updated to obtain the first updated mapping relationship; Determine whether the first updated mapping relationship satisfies the preset balance condition. If it does not, adjust the first fusion constraint set to obtain the second fusion constraint set. If it does, directly output the first fusion constraint set as the second fusion constraint set. Based on the second set of fusion constraints, the first update mapping relationship is processed to determine the initial adjustment parameters for chip power management, thereby obtaining a set of adjustment parameters; Based on the set of adjustment parameters, matching dynamic parameters are obtained from a preset resource threshold library to determine the dynamic adjustment framework for chip power consumption management.

9. A chip dynamic power consumption scheduling system based on intelligent algorithms, characterized in that, include: The feature extraction module is used to collect instruction stream data during chip operation in real time, and uses a convolutional neural network to extract instruction feature vectors to obtain instruction dynamic change vectors and instruction context association data. The mapping modeling module is used to construct a power consumption nonlinear mapping relationship and determine power consumption prediction mapping parameters based on the instruction dynamic change vector and the instruction context association data. The parameter verification module is used to adjust the weights of the convolutional neural network when the power prediction mapping parameters exceed the preset performance and energy efficiency constraint threshold, to verify the stability of the power prediction mapping parameters and obtain the power prediction result. The power supply optimization module is used to obtain the instruction switching frequency and data dependency strength, and, in combination with the power consumption prediction results, calculate the synchronization timing requirements of the power supply state and determine the initial power supply configuration. The power allocation module is used to monitor the task load classification signal according to the initial power supply configuration. If the task load classification signal is lower than a preset signal threshold, the power allocation ratio is adjusted to determine the optimized power supply configuration. The resource allocation module is used to further adjust the power consumption allocation ratio based on the optimized power supply configuration to obtain the resource allocation efficiency improvement index. The framework generation module is used to determine the dynamically adjusted framework by dynamically adjusting the periodic constraints based on the resource allocation efficiency improvement indicators.

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