Gate driving circuit and gate driving method of power converter

Abstract

The invention discloses a gate driving circuit and a gate driving method for a power converter. The power converter comprises an upper tube and a lower tube which are connected in series, and the gate driving circuit comprises an upper tube driving unit which is configured to generate a first gate driving signal for the upper tube according to a first logic signal; the delay compensation unit is configured to perform delay compensation on a second logic signal to generate an intermediate logic signal, and the delay time corresponds to the conduction response time of the upper tube; and a lower tube driving unit configured to generate a second gate driving signal for the lower tube according to the intermediate logic signal. The gate drive circuit dynamically adjusts the turn-off time of the lower tube according to the turn-on response time of the upper tube so as to realize adaptive dead zone control, thereby improving the reliability and conversion efficiency of the power converter.

Description

Technical Field

[0001] This application relates to switching power supply technology, and more specifically, to gate drive circuits and gate drive methods for power converters. Background Technology

[0002] In power supply chips, power converters typically consist of a high-side transistor and a low-side transistor connected in series. Energy conversion and transfer are achieved through the alternating switching of these two transistors on and off. To prevent a shoot-through short circuit caused by both transistors being on simultaneously, a dead time needs to be set during the switching process. This dead time is the period during which both transistors are off, ensuring the safe and reliable operation of the circuit.

[0003] Traditional dead-time control methods typically employ long, fixed delays. However, excessively long dead times can lead to chip efficiency losses. As power chips are increasingly moving towards higher frequencies and larger turn-on ratios, long dead times result in a larger minimum on-time under light loads, limiting the maximum turn-on ratio. To shorten the dead time, the drive logic of the upper and lower MOSFET drivers can be designed to be as identical as possible. Because the drive logic and circuit structure of the upper and lower MOSFET drivers are symmetrical, the difference in propagation delay between them can be significantly reduced, thus avoiding shoot-through risks during switching without requiring excessive safety margins.

[0004] However, the upper transistor experiences a Miller plateau during turn-on, where its gate voltage is clamped near a Miller voltage related to the load state, resulting in a slower gate voltage rise and a relatively increased turn-on delay. In contrast, the lower transistor experiences a smaller drain voltage change during turn-on, with a less pronounced Miller effect and a shorter turn-on delay. Therefore, even if the upper and lower transistor drive units are symmetrical in logic and circuit structure, timing mismatches may still occur due to differences in device characteristics. To avoid shoot-through risks caused by this difference, a safety margin related to the load state must still be reserved in the dead time between the lower transistor's turn-off and the upper transistor's turn-on. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a gate drive circuit and gate drive method for a power converter, wherein the turn-off time of the lower transistor is dynamically adjusted according to the turn-on response time of the upper transistor to achieve adaptive dead-time control, thereby improving the reliability and conversion efficiency of the power converter.

[0006] According to one aspect of the present invention, a gate drive circuit for a power converter is provided, the power converter including an upper transistor and a lower transistor connected in series, the gate drive circuit comprising: an upper transistor drive unit configured to generate a first gate drive signal for the upper transistor according to a first logic signal; a delay compensation unit configured to perform delay compensation on a second logic signal to generate an intermediate logic signal, the delay time corresponding to the turn-on response time of the upper transistor; and a lower transistor drive unit configured to generate a second gate drive signal for the lower transistor according to the intermediate logic signal.

[0007] Optionally, the delay compensation unit is configured such that the delay time is less than the time it takes for the gate voltage of the upper transistor to rise from zero to its Miller plateau voltage.

[0008] Optionally, the delay compensation unit includes: a current module configured to generate an injection current proportional to the load current of the power converter; and a first analog transistor having the same conductivity type as the upper transistor and having a width-to-length ratio scaled by a first predetermined ratio, wherein the gate of the first analog transistor receives an analog gate drive signal that rises synchronously with the first gate drive signal, and its drain generates the intermediate logic signal; wherein the current module provides the injection current to the drain of the first analog transistor.

[0009] Optionally, both the first analog transistor and the upper transistor are high-voltage NMOS devices.

[0010] Optionally, the upper transistor driving unit includes: a first pull-up transistor and a first pull-down transistor connected in series, generating the first gate driving signal at the intermediate node between them, wherein the first pull-up transistor and the first pull-down transistor are respectively used to pull up and pull down the level of the first gate driving signal.

[0011] Optionally, the width-to-length ratio of the first analog transistor and the upper transistor is equal.

[0012] Optionally, the delay compensation unit further includes: a second analog transistor having the same conductivity type as the first pull-up transistor and having its aspect ratio scaled according to a second predetermined ratio; and a second pull-down transistor connected in series with the second analog transistor, generating the analog gate drive signal at the intermediate node between the two, wherein the second analog transistor and the second pull-down transistor are used to pull up and pull down the level of the analog gate drive signal, respectively.

[0013] Optionally, the width-to-length ratio of the second analog transistor and the first pull-up transistor is equal.

[0014] Optionally, the width-to-length ratio of the first analog transistor, the second analog transistor, the upper transistor, and the first pull-up transistor conforms to the following formula:

[0015] Where Wh and Lh represent the width and length of the upper transistor, respectively; Wp1 and Lp1 represent the width and length of the first pull-up transistor in the upper transistor drive unit, respectively; W1 and L1 represent the width and length of the first analog transistor, respectively; and Wp2 and Lp2 represent the width and length of the second analog transistor, respectively.

[0016] Optionally, the upper transistor driving unit further includes a third transistor connected in parallel with the first pull-up transistor, used to achieve fast driving after the first pull-up transistor rises to the Miller plateau voltage.

[0017] Optionally, the current module includes: a current source for generating a first current corresponding to the load current of the power converter; and a first current mirror for mirroring the first current to the drain of the first analog transistor to generate the injected current.

[0018] Optionally, the current source further includes: a voltage-to-current conversion unit for converting the compensation voltage in the control loop of the power converter into a compensation current; and a second current mirror for mirroring the compensation current into the first current.

[0019] Optionally, the first logic signal and the second logic signal are complementary signals generated by the control circuit of the power converter.

[0020] Optionally, the first logic signal and the second logic signal are in-phase signals generated by the control circuit of the power converter.

[0021] According to another aspect of the present invention, a gate driving method for a power converter is provided, the power converter including an upper transistor and a lower transistor connected in series, the gate driving method comprising: controlling the turn-off time of the lower transistor according to the turn-on response time of the upper transistor to dynamically adjust the dead time.

[0022] Optionally, the method further includes: generating a first gate drive signal for the upper transistor based on a first logic signal, wherein the step of controlling the turn-on time of the lower transistor based on the turn-on response time of the upper transistor includes: performing delay compensation on a second logic signal to generate an intermediate logic signal, the delay time corresponding to the turn-on response time of the upper transistor; and generating a second gate drive signal for the lower transistor based on the intermediate logic signal.

[0023] Optionally, the delay time is less than the time it takes for the gate voltage of the upper transistor to rise from zero to its Miller plateau voltage.

[0024] Optionally, the step of delay compensation for the second logic signal includes: obtaining an injection current proportional to the load current of the power converter; obtaining an analog gate drive signal that rises synchronously with the first gate drive signal; and obtaining the intermediate logic signal based on the analog gate drive signal and the injection current.

[0025] Optionally, the step of obtaining the intermediate logic signal includes: providing the analog gate drive signal to the gate of the first analog transistor; providing the injection current to the drain of the first analog transistor; and obtaining the intermediate logic signal at the drain of the first analog transistor, wherein the first analog transistor and the upper transistor have the same conductivity type and their aspect ratio is scaled according to a first predetermined ratio.

[0026] Optionally, the step of generating the injection current includes: converting the compensation voltage in the control loop of the power converter into a compensation current; and mirroring the compensation current into the injection current.

[0027] Optionally, the first logic signal and the second logic signal are complementary signals generated by the control circuit of the power converter.

[0028] Optionally, the first logic signal and the second logic signal are in-phase signals generated by the control circuit of the power converter.

[0029] According to the gate drive circuit of this disclosure embodiment, the delay compensation unit is configured to perform delay compensation on the second logic signal to generate an intermediate logic signal, the delay time corresponding to the turn-on response time of the upper transistor. This gate drive circuit simulates the conduction characteristics of the upper transistor in the drive signal path of the lower transistor to obtain the turn-on response time of the upper transistor. Therefore, it can dynamically adjust the turn-off time of the lower transistor according to the turn-on response time of the upper transistor to achieve adaptive dead-time control, thereby improving the reliability and conversion efficiency of the power converter. Attached Figure Description

[0030] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0031] Figure 1 A schematic circuit diagram of a power converter according to the prior art is shown;

[0032] Figure 2 Show Figure 1 The waveform diagram of the power converter shown is as follows;

[0033] Figure 3 A schematic circuit diagram of a power converter according to a first embodiment of the present disclosure is shown;

[0034] Figure 4Show Figure 3 The waveform diagram of the power converter shown is as follows;

[0035] Figure 5 Show Figure 3 A schematic circuit diagram of the upper transistor drive unit in the power converter shown.

[0036] Figure 6 Show Figure 3 A schematic circuit diagram of the lower transistor drive unit in the power converter shown.

[0037] Figure 7 Show Figure 3 A schematic circuit diagram of a first example of a delay compensation unit in a power converter shown;

[0038] Figure 8 Show Figure 3 A schematic circuit diagram of a second example of a delay compensation unit in a power converter; and

[0039] Figure 9 A flowchart illustrating a gate driving method according to a second embodiment of the present disclosure is shown. Detailed Implementation

[0040] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0041] This invention can be presented in various forms, some of which will be described below.

[0042] In this document, the term "power stage" includes a switching module and an energy storage element connected thereto to achieve power conversion. For example, a switching module includes an upper and lower transistor connected in series, used to alternately turn on and off under the action of a control signal to charge and discharge the energy storage element, thereby achieving voltage conversion. The term "switching node" refers to the intermediate node connecting the switching module and the energy storage element. The term "energy storage element" includes inductors and capacitors. Depending on the type of energy storage element, capacitive power converters and inductive power converters can be constructed. Depending on the connection method of the energy storage element, different topology power converters can be constructed.

[0043] In this paper, the term "turn-on response time" refers to the moment when the drain voltage of a transistor begins to change during the transition from the off state to the on state. In other words, before this moment, the gate voltage of the transistor is in the rising phase while the drain voltage remains constant; after this moment, the drain voltage of the transistor begins to decrease or increase during the conduction process.

[0044] This disclosure applies to power converters of various topologies, including but not limited to: any one of BUCK-type power converters, BOOST-type power converters, and BUCK-BOOST-type power converters. The following description primarily uses a BUCK-type power converter as an example; however, this disclosure is not limited thereto.

[0045] Figure 1 A schematic circuit diagram of a power converter according to the prior art is shown. The power converter 100 includes a main circuit and a drive circuit 10.

[0046] The main circuit of the power converter 100 includes an upper transistor Q1 and a lower transistor Q2 connected in series between the DC voltage input terminal and the ground terminal, and an inductor L connected between the switching node SW between the upper transistor Q1 and the lower transistor Q2 and the DC voltage output terminal. The main circuit also includes an output capacitor Co connected between the DC voltage output terminal and the ground terminal to filter out ripple components in the DC output voltage Vo. Furthermore, a load resistor RL is connected between the DC voltage output terminal and the ground terminal to represent the load in the actual operating scenario.

[0047] The drive circuit 10 of the power converter 100 includes a control circuit 110, an upper MOSFET drive unit 120, a lower MOSFET drive unit 130, a first delay compensation unit 140, and a second delay compensation unit 150.

[0048] The control circuit 110 generates a first logic signal S1 and a second logic signal S2 that are complementary to each other based on the inductor current detection signal Isen and the voltage feedback signal Vfb from the main circuit. The internal circuitry of the control circuit 110 is known in the art; only the logic unit 111 in the control circuit 110 is shown in the figures. It is understood that the internal circuitry of the control circuit 110 also includes a voltage loop for generating a compensation voltage Vcomp based on the error signal between the voltage feedback signal Vfb and the reference voltage Vref, and a current loop for comparing the compensation voltage Vcomp with the inductor current detection signal Isen to achieve current control (peak control or valley control). It is understood that the internal circuitry of the control circuit 110 is related to the specific control method implemented, and this disclosure is not limited to any particular internal circuitry.

[0049] In the pulse width modulation (PWM) mode of the power converter 100, the voltage loop and current loop of the control circuit 110 jointly generate the off signal OFF. Further, the logic unit 111 receives the off signal OFF and the clock signal as the on signal ON, and generates the PWM signal based on these two signals, namely, the complementary first logic signal S1 and the second logic signal S2. Under this modulation mechanism, the clock signal is used to limit the switching period of the PWM signal, while the compensation voltage Vcomp is used to limit the duty cycle of the PWM signal. By adjusting the level of Vcomp, the on-time of the PWM signal can be changed, thereby achieving closed-loop control of the output voltage. The voltage loop determines the steady-state accuracy of the output voltage, and the current loop determines the transient response speed. Their combined effect enables the power converter to achieve fast and stable voltage regulation under both steady-state and dynamic conditions.

[0050] The first delay compensation unit 140 and the second delay compensation unit 150 are respectively used to delay the predetermined edges of the first logic signal S1 and the second logic signal S2 to achieve dead time control. For example, the effective level of the first logic signal S1 and the second logic signal S2 is a high level, and the predetermined edge is a rising edge. The first delay compensation unit 140 delays the rising edge of the first logic signal S1 to obtain a first dead time dT1, that is, the dead time between the lower transistor Q2 being turned off and the upper transistor Q1 being turned on. The second delay compensation unit 150 delays the rising edge of the second logic signal S2 to obtain a second dead time dT2, that is, the dead time between the upper transistor Q1 being turned off and the lower transistor Q2 being turned on.

[0051] The upper-side drive unit 120 and the lower-side drive unit 130 generate a first gate drive signal HG and a second gate drive signal LG based on the delayed intermediate logic signals S1A and S2A, respectively. The drive units perform level shifting and power amplification on the logic signals to enhance the drive capability, thereby controlling the conduction states of the upper-side transistor Q1 and the lower-side transistor Q2. The drive units also isolate the control circuit from the upper-side transistor Q1 and the lower-side transistor Q2 in the main circuit to ensure that the control circuit can operate safely and stably in the low-voltage domain. The drive units can employ a half-bridge driver or a buffer structure. The half-bridge driver can be implemented using a totem-pole circuit, and the buffer structure can be implemented using a voltage follower or an inverter.

[0052] Figure 2 Show Figure 1The diagram shows the operating waveforms of the power converter. In the diagram, ON, S1A, and S2A represent the turn-on signal inside the control circuit 110, the intermediate logic signal received by the upper transistor drive unit 120, and the intermediate logic signal received by the lower transistor drive unit 130, respectively. HG and LG represent the first gate drive signal provided by the upper transistor drive unit 120 and the second gate drive signal provided by the lower transistor drive unit 130, respectively. Vsw represents the switching node voltage between the upper transistor Q1 and the lower transistor Q2.

[0053] As described above, the ON signal inside the control circuit 110 is a clock signal used to define the switching period of the PWM signal. This switching period corresponds to the time period between time t0 and t4 in the figure.

[0054] At time t0, the ON signal inside the control circuit 110 flips from low to high, starting the clock cycle of the PWM signal. Since the clock signal is a pulse signal, the ON signal flips from high to low during the switching cycle. In this embodiment, the rising edge of the ON signal is the valid edge, and the falling edge is the invalid edge.

[0055] The intermediate logic signal S2A flips from high to low, turning off the lower transistor Q2. At this time, since the intermediate logic signal S1A is still low, the upper transistor Q1 remains off. The inductor current freewheels through the body diode of the lower transistor Q2, and the switching node voltage Vsw begins to decrease.

[0056] At time t1, the intermediate logic signal S1A flips from low to high after a dead time dT1 in the first delay compensation unit 140. The first gate drive signal HG of the upper transistor Q1 then rises. When it reaches the threshold voltage Vth, the upper transistor Q1 begins to conduct. Subsequently, it reaches the Miller plateau, and the switching node voltage Vsw rises accordingly. After passing the Miller plateau, the upper transistor Q1 is fully turned on, and the switching node voltage Vsw remains high.

[0057] At time t2, after the intermediate logic signal S1A passes through the high-level phase related to the compensation voltage Vcomp in the control loop, it flips from high to low. The gate voltage of the upper transistor Q1 drops rapidly, and Q1 is turned off, causing the switching node voltage Vsw to begin decreasing. At this time, since the intermediate logic signal S2A is still low, the lower transistor Q2 remains off. The inductor current freewheels through the body diode of the lower transistor Q2, and the switching node voltage Vsw continues to decrease.

[0058] At time t3, after the intermediate logic signal S2A is delayed by the second delay compensation unit 150 for a dead time dT2, it flips from low to high. The second gate drive signal LG of the lower transistor Q2 then rises, and when it reaches the threshold voltage Vth, the lower transistor Q2 begins to conduct. At this time, the switching node voltage Vsw is clamped to a low level due to the conduction of the lower transistor Q2.

[0059] At time t4, the ON signal inside the control circuit 110 flips from low level to high level, starting the next clock cycle of the PWM signal.

[0060] The power converter described above, based on existing technology, employs a long fixed delay in its dead-time control method. The first logic signal S1 and the second logic signal S2 generated by the control circuit are complementary signals. The first delay compensation unit performs a fixed delay on the rising edge of the first logic signal S1 to obtain the dead time dT1. The second delay compensation unit performs a fixed delay on the rising edge of the second logic signal S2 to obtain the dead time dT2. The gate-source voltage of the upper transistor is relative to the switching node, while the gate-source voltage of the lower transistor is relative to ground. Due to the source potential difference between the upper and lower transistors, the source potential of the upper transistor rises during conduction. Therefore, the upper transistor experiences a Miller plateau phase, meaning its gate voltage is clamped near the Miller voltage related to the load state, resulting in a slower gate voltage rise rate. In contrast, the drain voltage change is smaller when the lower transistor is turned on, and the Miller effect is not significant.

[0061] Furthermore, the Miller plateau voltage of the upper transistor during conduction is related to the load current. When the load current increases, the Miller capacitance charging current between the gate and drain increases, causing the Miller plateau voltage level to rise accordingly, thus extending the gate voltage rise time of the upper transistor. Therefore, a safety margin related to the load state is reserved in the dead time dT1 between the lower transistor's turn-off and the upper transistor's turn-on, so that the predetermined dead time dT1 is greater than the delay time from the gate drive signal flipping to the start of the drain voltage rise of the upper transistor, thereby ensuring that the upper and lower transistors do not conduct simultaneously.

[0062] However, dead-time control methods using fixed dead time are often based on the most unfavorable operating conditions (such as heavy load or high temperature), thus requiring a large safety margin. Consequently, under light load or normal operating conditions, an excessively long dead time leads to a prolonged switching interval between the upper and lower transistors, increased output voltage waveform distortion, and reduced conversion efficiency. Furthermore, fixed dead time cannot adapt to changes in load conditions. When the load current changes, the dynamic characteristics of the upper and lower transistors, such as their turn-on and turn-off delays and Miller plateau duration, all change. Fixed dead time cannot compensate for these changes, easily leading to efficiency losses under light loads and increased shoot-through risk under heavy loads.

[0063] Figure 3 A schematic circuit diagram of a power converter according to a first embodiment of the present disclosure is shown. The power converter 200 includes a main circuit and a drive circuit 20.

[0064] The main circuit of the power converter 200 includes an upper transistor Q1 and a lower transistor Q2 connected in series between the DC voltage input terminal and the ground terminal, and an inductor L connected between the switching node SW between the upper transistor Q1 and the lower transistor Q2 and the DC voltage output terminal. The main circuit also includes an output capacitor Co connected between the DC voltage output terminal and the ground terminal to filter out ripple components in the DC output voltage Vo. Furthermore, a load resistor RL is connected between the DC voltage output terminal and the ground terminal to represent the load in the actual operating scenario.

[0065] In this embodiment, the upper transistor Q1 and the lower transistor Q2 are both NMOS transistors. However, this disclosure is not limited thereto; the upper transistor Q1 and the lower transistor Q2 may have opposite conductivity types or other equivalent transistor structures.

[0066] The drive circuit 20 of the power converter 200 includes a control circuit 110, an upper MOSFET drive unit 120, a lower MOSFET drive unit 130, and a delay compensation unit 240.

[0067] The control circuit 110 generates a first logic signal S1 and a second logic signal S2 that are complementary to each other based on the inductor current detection signal Isen and the voltage feedback signal Vfb from the main circuit. The internal circuitry of the control circuit 110 is known in the art; only the logic unit 111 in the control circuit 110 is shown in the figures. It is understood that the internal circuitry of the control circuit 110 also includes a voltage loop for generating a compensation voltage Vcomp based on the error signal between the voltage feedback signal Vfb and the reference voltage Vref, and a current loop for comparing the compensation voltage Vcomp with the inductor current detection signal Isen to achieve current control (peak control or valley control). It is understood that the internal circuitry of the control circuit 110 is related to the specific control method implemented, and this disclosure is not limited to any particular internal circuitry.

[0068] In the pulse width modulation (PWM) mode of the power converter 200, the voltage loop and current loop of the control circuit 110 jointly generate the off signal OFF. Further, the logic unit 111 receives the off signal OFF and the clock signal as the on signal ON, and generates the PWM signal based on these two signals, namely, the complementary first logic signal S1 and the second logic signal S2. Under this modulation mechanism, the clock signal is used to limit the switching period of the PWM signal, while the compensation voltage Vcomp is used to limit the duty cycle of the PWM signal. By adjusting the level of Vcomp, the on-time of the PWM signal can be changed, thereby achieving closed-loop control of the output voltage. The voltage loop determines the steady-state accuracy of the output voltage, and the current loop determines the transient response speed. Their combined effect enables the power converter to achieve fast and stable voltage regulation under both steady-state and dynamic conditions.

[0069] The delay compensation unit 240 is used to delay a predetermined edge of the second logic signal S2 to achieve dead-time control. For example, the effective level of the first logic signal S1 and the second logic signal S2 is high, and the predetermined edge is a falling edge. The delay compensation unit 240 delays the falling edge of the second logic signal S2 to obtain a delay time dT3.

[0070] In this embodiment, the delay compensation unit 240 dynamically adjusts the turn-off time of the lower transistor based on the turn-on response time of the upper transistor Q1 to achieve adaptive dead-time control. For example, the turn-on response time of the upper transistor Q1 is the time it takes for its gate voltage to rise from zero to its Miller plateau voltage. When the gate voltage of the upper transistor Q1 reaches the Miller plateau voltage, the drain voltage of the upper transistor Q1 begins to change. Figure 1 Unlike the power converter shown, in this embodiment, the delay compensation unit 240 does not directly set a fixed dead time between the turn-off of the lower transistor Q2 and the turn-on of the upper transistor Q1. Instead, the delay compensation unit 240 uses an analog transistor to detect the turn-on response time of the upper transistor Q1, delaying the turn-off trigger time of the lower transistor Q2 to the turn-on response time of the upper transistor Q1, thereby minimizing the dead time between the turn-off of the lower transistor Q2 and the turn-on of the upper transistor Q1.

[0071] The upper-side drive unit 120 and the lower-side drive unit 130 generate a first gate drive signal HG and a second gate drive signal LG based on the first logic signal S1 and the delayed intermediate logic signal S2B, respectively. The drive units perform level shifting and power amplification on the logic signals to enhance the drive capability, thereby controlling the conduction states of the upper-side MOSFET Q1 and the lower-side MOSFET Q2. The drive units also isolate the control circuit from the upper-side MOSFET Q1 and the lower-side MOSFET Q2 in the main circuit to ensure that the control circuit can operate safely and stably in the low-voltage domain. The drive units can employ a half-bridge driver or a buffer structure. The half-bridge driver can be implemented using a totem-pole circuit, and the buffer structure can be implemented using a voltage follower or an inverter.

[0072] See Figure 5 For example, the upper tube drive unit 120 adopts a half-bridge driver structure.

[0073] The upper-side drive unit 120 includes an inverter 121, a level shifter 122, and transistors Q11 to Q13. The inverter 121 receives the first logic signal S1 and inverts it. The level shifter 122 shifts the inverted signal from the low-voltage domain to the high-voltage domain to obtain the intermediate logic signal S1B. Transistors Q11 to Q13 constitute a half-bridge driver. Transistors Q11 and Q12 are a pull-up transistor and a pull-down transistor connected in series between the bootstrap voltage Vboot and the switching node voltage Vsw. The gates of transistors Q11 and Q12 are connected to the output of the level shifter 122 to receive the intermediate logic signal S1B. Transistor Q13 is connected in parallel with transistor Q11, and its gate receives a delayed signal of the intermediate logic signal S1B. Transistor Q11 acts as the first pull-up transistor, providing a slow pull-up path, and transistor Q13 acts as the second pull-up transistor, providing a fast pull-up path. The slow pull-up path is turned on immediately in response to the rising edge of the first logic signal S1, causing the first gate drive signal HG to begin to rise slowly; the fast pull-up path is turned on under the signal trigger after the delay of the first logic signal S1, accelerating the rise of the first gate drive signal HG to cross the Miller platform.

[0074] In this embodiment, pull-up transistors Q11 and Q13 are PMOS transistors, and pull-down transistor Q13 is an NMOS transistor. However, this disclosure is not limited thereto; the pull-up transistors and pull-down transistors may employ opposite conductivity types or other equivalent transistor structures.

[0075] See Figure 6 For example, the lower gate drive unit 130 includes a buffer 131. The second gate drive signal LG is in phase with the intermediate logic signal S2B and can quickly follow the changes in the intermediate logic signal S2B.

[0076] Figure 4 Show Figure 3 The diagram shows the operating waveforms of the power converter. In the diagram, ON, S1, S2, and S2B represent the turn-on signal inside the control circuit 110, the first logic signal provided by the control circuit 110, the second logic signal provided by the control circuit 110, and the intermediate logic signal received by the lower transistor drive unit 130, respectively. HG and LG represent the first gate drive signal provided by the upper transistor drive unit 120 and the second gate drive signal provided by the lower transistor drive unit 130, respectively. HG_SIM represents the analog gate drive signal inside the delay compensation unit 240, and Vsw represents the switching node voltage between the upper transistor Q1 and the lower transistor Q2.

[0077] As described above, the ON signal inside the control circuit 110 is a clock signal used to define the switching period of the PWM signal. This switching period corresponds to the time period between time t0 and t4 in the figure.

[0078] At time t0, the ON signal inside the control circuit 110 flips from low to high, starting the clock cycle of the PWM signal. Since the clock signal is a pulse signal, the ON signal flips from high to low during the switching cycle. In this embodiment, the rising edge of the ON signal is the valid edge, and the falling edge is the invalid edge.

[0079] The first logic signal S1 and the second logic signal S2 are complementary logic signals. When the first logic signal S1 flips from low to high, the first gate drive signal HG of the upper transistor Q1 rises accordingly. The second logic signal S2 flips from high to low. At this time, the switching node voltage Vsw is clamped at a low level. The intermediate logic signal S2B provided by the delay compensation unit 240 remains high. The second gate drive signal LG of the lower transistor Q2 remains high, and the lower transistor Q2 maintains the on state of the previous clock cycle.

[0080] At time t1, the first gate drive signal HG of the upper transistor Q1 rises to the threshold voltage Vth1, and the upper transistor Q1 begins to conduct. The analog gate drive signal HG_SIM inside the delay compensation unit 240 rises to the threshold voltage Vth2, and the analog transistor corresponding to the upper transistor Q1 begins to conduct. Before reaching the Miller plateau, the drain voltage of the upper transistor Q1 remains unchanged, and the switching node voltage Vsw is clamped low by the lower transistor Q2. Before reaching the Miller plateau, the drain voltage of the analog transistor remains unchanged, the intermediate logic signal S2B provided by the delay compensation unit 240 remains high, and the lower transistor Q2 continues to conduct.

[0081] At time t2, the first gate drive signal HG of the upper transistor Q1 rises to the Miller plateau voltage. The drain voltage of the upper transistor Q1 begins to change, and the switching node voltage Vsw rises accordingly. The analog gate drive signal HG_SIM inside the delay compensation unit 240 rises to the Miller plateau voltage. The drain voltage of the analog transistor begins to change, and the intermediate logic signal S2B provided by the delay compensation unit 240 decreases accordingly. The toggling time of the intermediate logic signal S2B corresponds to the turn-on response time of the upper transistor Q1.

[0082] The rise of the first gate drive signal HG demonstrates the dual-path pull-up characteristics of the upper-side gate drive unit 120. Starting from time t1, the slow path responds first to the rising edge of the first logic signal S1, causing the voltage of the first gate drive signal HG to rise slowly. At time t2, the first gate drive signal HG reaches the Miller plateau. Subsequently, the fast path responds to the delayed S1 signal, accelerating the rise of the first gate drive signal HG to quickly cross the Miller plateau. The first gate drive signal HG quickly reaches a steady-state high level, causing the upper-side transistor Q1 to rapidly enter the saturation conduction state.

[0083] The rise of the analog gate drive signal HG_SIM reflects the slow-path pull-up characteristic of the upper-side gate drive unit 120. Starting from time t1, the slow-path response in the delay compensation unit 240 responds to the falling edge of the second logic signal S2, causing the analog gate drive signal HG_SIM voltage to rise slowly. At time t2, the analog gate drive signal HG_SIM reaches the Miller plateau. After passing the Miller plateau, the analog gate drive signal HG_SIM continues to rise until it reaches a steady-state high level.

[0084] In this embodiment, the simulated gate drive signal HG_SIM in the delay compensation unit 240 is used to simulate the conduction characteristics of the upper transistor Q1 to determine the toggling timing of the second gate drive signal LG. Starting from time t1, the simulated gate drive signal HG_SIM gradually increases under slow path drive. At time t2, the first gate drive signal HG reaches the Miller plateau, the intermediate logic signal S2B toggles from high to low, and the second gate drive signal LG toggles from high to low, thereby turning off the lower transistor Q2. Therefore, the turn-off triggering time of the lower transistor Q2 can be delayed to the conduction response time of the upper transistor Q1, minimizing the dead time between the turn-off of the lower transistor Q2 and the turn-on of the upper transistor Q1.

[0085] At time t3, after the high-level phase related to the compensation voltage Vcomp in the control loop, the first logic signal S1 flips from high to low, and the second logic signal S2 flips from low to high. At this time, the inductor current freewheels through the body diode of the lower transistor Q2, and the switching node voltage Vsw continues to decrease.

[0086] The second gate drive signal LG of the lower transistor Q2 then increases, and when it rises to the threshold voltage Vth, the lower transistor Q2 begins to conduct. At this time, the switching node voltage Vsw is clamped to a low level due to the conduction of the lower transistor Q2.

[0087] At time t4, the ON signal inside the control circuit 110 flips from low level to high level, starting the next clock cycle of the PWM signal.

[0088] According to embodiments of the power converter disclosed herein, adaptive dead-time control is employed in the dead-time control method. The first logic signal S1 and the second logic signal S2 generated by the control circuit are complementary signals. The delay compensation unit simulates the conduction characteristics of the upper transistor to obtain the turn-off delay time dT3 of the lower transistor. This delay time dT3 corresponds to the conduction response time of the upper transistor. The gate drive circuit simulates the conduction characteristics of the upper transistor in the drive signal path of the lower transistor to obtain the conduction response time of the upper transistor. Therefore, the turn-off time of the lower transistor can be dynamically adjusted according to the conduction response time of the upper transistor, improving the reliability and conversion efficiency of the power converter.

[0089] Figure 7 Show Figure 3 A schematic circuit diagram of a first example of a delay compensation unit in a power converter shown.

[0090] The delay compensation unit 240 includes a first analog transistor Q1_SIM and a second analog transistor Q11_SIM, which are used to simulate the upper transistor Q1 and the lower transistor Q11_SIM, respectively. Figure 5 The pull-up transistor Q11 in the upper transistor drive unit 120 shown.

[0091] The second analog transistor Q11_SIM is used to obtain the propagation delay in the upper-side drive path. In this embodiment, the second analog transistor Q11_SIM is a PMOS transistor, and the pull-down transistor Q31 is an NMOS transistor. However, this disclosure is not limited to this; the second analog transistor Q11_SIM can have the same conductivity type as the corresponding pull-up transistor of the half-bridge driver in the upper-side drive unit 120.

[0092] The delay compensation unit 240 also includes a pull-down transistor Q31 connected in series with the second analog transistor Q11_SIM. The second analog transistor Q11_SIM and the pull-down transistor Q31 are connected in series between the supply voltage Vcc and ground, forming a delay compensation unit. Figure 5The structure is similar to the half-bridge driver in the upper transistor drive unit 120 shown, thereby replicating the propagation delay characteristics of the upper transistor drive signal. The gates of the second analog transistor Q11_SIM and the pull-down transistor Q31 receive the second logic signal S2, and the intermediate node between them generates the analog gate drive signal HG_SIM. In this embodiment, since the slow path of the upper transistor drive unit 120 is related to dead-time control, the delay compensation unit 240 only simulates the propagation delay of the slow path.

[0093] The first analog transistor Q1_SIM is used to obtain the turn-on delay of the upper transistor. In this embodiment, the first analog transistor Q1_SIM is an NMOS transistor. However, this disclosure is not limited thereto; the first analog transistor Q1_SIM can have the same conduction type as the upper transistor in the main circuit.

[0094] The gate of the first analog transistor Q1_SIM receives the analog gate drive signal HG_SIM. The delay compensation unit 240 also includes a current module for injecting a current Iin proportional to the load current of the power converter. This current module provides the injected current Iin to the drain of the first analog transistor Q1_SIM. The current module includes a current source 241 and transistors Q32 and Q33 connected as a first current mirror. Transistor Q32 is connected in series with the current source 241 between the supply voltage Vcc and ground, and transistor Q33 is connected in series with the first analog transistor Q1_SIM between the supply voltage Vcc and ground. The gates of transistors Q32 and Q33 are interconnected and connected to the drain of transistor Q32, thus forming the first current mirror structure. The first current generated by the current source 241 is mirrored by the first current mirror to form the injected current Iin, which is used to approximately characterize the drain current of the upper transistor Q1.

[0095] According to the current model of a transistor in saturation conduction, it can be understood that after the gate-source voltage Vgs of the upper transistor Q1 exceeds the threshold voltage Vth1, the upper transistor Q1 starts to conduct. The gate-source voltage Vgs1 in saturation conduction is as shown in formula (1): (1) Wherein, IL represents the drain current flowing through the upper transistor Q1 (corresponding to the inductor current of the main circuit in the power converter), Vth1 represents the threshold voltage of the upper transistor Q1, and k1 represents the proportional coefficient related to the device characteristics of the upper transistor Q1, the value of which is determined by the channel width-to-length ratio, etc.

[0096] Furthermore, the conduction delay t1 of the upper tube Q1 is as shown in formula (2): (2) Where R1 represents the equivalent input resistance of the gate of the upper transistor Q1, C1 represents the equivalent input capacitance of the upper transistor Q1, Vcc represents the charging voltage of the RC circuit of the gate of the upper transistor Q1, Vgs1 represents the gate-source voltage of the upper transistor Q1 when it is saturated and conducting, IL represents the drain current flowing through the upper transistor Q1 (corresponding to the inductor current of the main circuit in the power converter), Vth1 represents the threshold voltage of the upper transistor Q1, and k1 represents the proportional coefficient related to the device characteristics of the upper transistor Q1, the value of which is determined by the channel width-to-length ratio of the upper transistor Q1, etc.

[0097] Similarly, the turn-on delay t2 of the first analog transistor Q1_SIM in the delay compensation unit 240 is as shown in formula (3): (3) Where R2 represents the equivalent input resistance of the gate of the first analog transistor Q1_SIM, C2 represents the equivalent input capacitance of the first analog transistor Q1_SIM, Vcc represents the charging voltage of the RC circuit of the gate of the first analog transistor Q1_SIM, Vgs2 represents the gate-source voltage of the first analog transistor Q1_SIM when it is saturated and conducting, IB1 represents the drain current flowing through the first analog transistor Q1_SIM, Vth2 represents the threshold voltage of the first analog transistor Q1_SIM, and k2 represents a scaling factor related to the device characteristics of the first analog transistor Q1_SIM, the value of which is determined by the channel width-to-length ratio of the first analog transistor Q1_SIM, etc.

[0098] Assume that the following formulas (4) to (6) are satisfied: (4) (5) (6), Therefore, according to formulas (2) and (3), t1 = t2. At this time, the delay time dT3 obtained by the delay compensation unit includes at least the turn-on delay t2 of the first analog transistor Q1_SIM, that is, the turn-on delay t1 of the upper transistor Q1, so that the turn-off time of the lower transistor Q2 can be dynamically adjusted according to the turn-on response time of the upper transistor Q1 to achieve adaptive dead-time control.

[0099] Furthermore, in the drive path of the upper transistor Q1, there is also a propagation delay related to the slow path in the upper transistor drive unit 120. In the delay compensation unit 240, the second analog transistor Q11_SIM is used to simulate the propagation delay in the upper transistor drive path. At this time, the delay time dT3 obtained by the delay compensation unit includes not only the turn-on delay t2 of the first analog transistor Q1_SIM, i.e., the turn-on delay t1 of the upper transistor Q1, but also the propagation delay in the upper transistor drive path, further improving the accuracy of adaptive dead-time control.

[0100] Therefore, the first analog transistor Q1_SIM and the pull-up transistor Q1 are both high-voltage MOS transistors of the same conductivity type. The second analog transistor Q11_SIM and the first pull-up transistor Q11 are both high-voltage MOS transistors of the same conductivity type.

[0101] The width-to-length ratio of the first analog transistor Q1_SIM, the second analog transistor Q11_SIM, the upper transistor Q1, and the first pull-up transistor Q11 conforms to the following formula (7): (7) Where Wh and Lh represent the width and length of the upper transistor Q1, respectively; Wp1 and Lp1 represent the width and length of the pull-up transistor Q11 in the upper transistor driving unit, respectively; W1 and L1 represent the width and length of the first analog transistor Q1_SIM in the delay compensation unit, respectively; and Wp2 and Lp2 represent the width and length of the second analog transistor Q11_SIM in the delay compensation unit, respectively.

[0102] When the width-to-length ratio of the first analog transistor Q1_SIM relative to the pull-up transistor Q1 is scaled according to the first predetermined ratio Ks1, and the width-to-length ratio of the second analog transistor Q11_SIM relative to the first pull-up transistor Q11 is also scaled according to the second ratio Ks2, when Ks1=Ks2, formula (1) can be satisfied. Therefore, the delay characteristics of the analog path of the delay compensation unit 240 are consistent with those of the actual driving path.

[0103] When the length of the first analog transistor Q1_SIM is equal to that of the pull-up transistor Q1 and its width is scaled proportionally, and the length of the second analog transistor Q11_SIM is equal to that of the first pull-up transistor Q11 and its width is scaled proportionally, the following can be derived from formula (7). Figure 7 Formula (8) shown: (8)

[0104] In this embodiment, the delay compensation unit 240 uses a first analog transistor Q1_SIM and a second analog transistor Q11_SIM to simulate the turn-on delay of the upper transistor and the propagation delay in the drive path, so as to obtain the delay time dT3 of the lower transistor Q2. The delay compensation unit 340 can accurately simulate the turn-on delay related to the threshold voltage of the upper transistor Q1.

[0105] The adaptive dead-time control method implemented by the delay compensation unit 240 can dynamically adjust the delay time of the lower transistor according to changes in process, voltage, and temperature. By setting the first current of the current source, a large safety margin can be maintained, ensuring that the delay time of the lower transistor is always less than the conduction response time of the upper transistor. This avoids simultaneous conduction of the upper and lower transistors, effectively preventing the generation of shoot-through current, thereby improving the safety, stability, and reliability of the system. Furthermore, since the delay time of the lower transistor is after the conduction trigger moment of the upper transistor, the dead time can also be reduced, thereby improving the power conversion efficiency of the system.

[0106] Figure 8 Show Figure 3 A schematic circuit diagram of a second example of a delay compensation unit in a power converter is shown.

[0107] The delay compensation unit 340 includes a first analog transistor Q1_SIM, a second analog transistor Q11_SIM, and transistors Q31 to Q33. Similar to the first example, the first analog transistor Q1_SIM is used to obtain the turn-on delay of the upper transistor, and the second analog transistor Q11_SIM is used to obtain the propagation delay of the upper transistor's drive path. This will not be described in detail in this example.

[0108] The delay compensation unit 340 also includes a current source 341. Unlike the first example, the current source 341 includes a voltage-to-current conversion unit 11 and transistors Q33 and Q34 connected as a second current mirror. The voltage-to-current conversion unit 11 converts the compensation voltage Vcomp in the voltage loop of the control circuit 110 into a compensation current ipk. Furthermore, the second current mirror mirrors the compensation current ipk into a first current output by the current source 341.

[0109] For a current-mode power converter, the load current is the average value of the inductor current IL. The compensation voltage Vcomp in the voltage loop of control circuit 110 is positively correlated with the load current. In this example, the compensation current ipk is proportional to IL / (Mh / W1). After being mirrored sequentially by the second current mirror and the first current mirror, the injected current Iin is obtained, which is used to accurately characterize the drain current of the upper transistor Q1. This injected current Iin is provided to the drain of the first analog transistor Q1_SIM as the drain current IB1, which satisfies the above formula (6).

[0110] In this embodiment, the delay compensation unit 340 uses a first analog transistor Q1_SIM and a second analog transistor Q11_SIM to simulate the turn-on delay of the upper transistor and the propagation delay in the drive path, so as to obtain the delay time dT3 of the lower transistor Q2. The delay compensation unit 340 can accurately simulate the turn-on delay related to the threshold voltage and Miller effect of the upper transistor Q1.

[0111] Specifically, the delay compensation unit 340 dynamically adjusts the delay time dT3 according to the change in load current to dynamically compensate for the Miller effect of the upper transistor Q1. Due to the Miller effect, the conduction delay of the upper transistor Q1 also changes accordingly when the load current changes. The larger the load current, the larger the inductor current IL, the larger the drain current of the upper transistor Q1, the longer the duration of the Miller plateau, and the longer the conduction delay of the upper transistor Q1. The current source 341 in the delay compensation unit 340 generates an injection current Iin that varies with the load current. The larger the load current, the larger the drain current of the first analog transistor Q1_SIM, the longer the duration of the Miller plateau of the first analog transistor Q1_SIM, and the longer the conduction delay of the first analog transistor Q1_SIM. At this time, the delay time dT3 obtained by the delay compensation unit 340 increases accordingly. Therefore, the delay compensation unit 340 can accurately simulate the conduction delay related to the threshold voltage of the upper transistor Q1 and the Miller plateau effect.

[0112] The adaptive dead-time control method implemented by this delay compensation unit can dynamically adjust the delay time of the lower transistor based on changes in process technology, voltage, load current, and temperature. Since the delay time of the lower transistor is always less than the turn-on response time of the upper transistor, simultaneous conduction of both transistors can be avoided, effectively preventing shoot-through current and thus improving system safety, stability, and reliability. Furthermore, because the delay compensation unit can accurately simulate the turn-on delay related to the threshold voltage and Miller plateau effect of the upper transistor, the delay time of the lower transistor can approach the turn-on response time of the upper transistor, and the dead time can be minimized, thereby further improving the system's power conversion efficiency.

[0113] Figure 9 A flowchart of a gate driving method according to a second embodiment of the present disclosure is shown. The power converter includes an upper transistor Q1 and a lower transistor Q2 connected in series. The gate driving method controls the turn-off time of the lower transistor Q2 based on the turn-on response time of the upper transistor Q1 in the power converter to dynamically adjust the dead time.

[0114] The gate driving method includes steps S01 to S03.

[0115] In step S01, a first gate drive signal HG for the upper transistor Q1 is generated according to the first logic signal S1.

[0116] In step S02, the second logic signal S2 is delayed to generate the intermediate logic signal S2B.

[0117] In step S03, a second gate drive signal LG for the lower transistor Q2 is generated based on the intermediate logic signal S2B.

[0118] The first logic signal S1 and the second logic signal S2 are complementary or in-phase signals generated by the control circuit of the power converter.

[0119] The delay time for this delay compensation corresponds to the turn-on response time of the upper transistor Q1. Preferably, the delay time is less than the time it takes for the gate voltage of the upper transistor Q1 to rise from zero to its Miller plateau voltage.

[0120] In step S02 above, an injection current Iin proportional to the load current of the power converter is obtained, and an analog gate drive signal HG_SIM that rises synchronously with the first gate drive signal HG is obtained. An intermediate logic signal S2B is obtained based on the analog gate drive signal HG_SIM and the injection current Iin. Preferably, the analog gate drive signal HG_SIM is provided to the gate of the first analog transistor Q1_SIM, and the injection current is provided to the drain of the first analog transistor Q1_SIM. The first analog transistor Q1_SIM has the same conductivity type as the upper transistor Q1, and its aspect ratio is scaled according to a first predetermined ratio. The intermediate logic signal S2B is obtained at the drain of the first analog transistor Q1_SIM.

[0121] Preferably, the step of generating the injection current Iin includes: converting the compensation voltage Vcomp in the control loop of the power converter into a compensation current; and mirroring the compensation current into the injection current Iin.

[0122] In the above embodiments, the delay compensation unit includes a first analog transistor and a second analog transistor, which respectively simulate the turn-on delay of the upper transistor and the propagation delay in the upper transistor drive path. However, this disclosure is not limited thereto. In some implementations, depending on the circuit design of the upper transistor drive unit, the delay compensation unit can ignore the propagation delay in the upper transistor drive path, or use a fixed delay to approximate the propagation delay, thus eliminating the need for the second analog transistor and achieving delay compensation solely through the first analog transistor. In other implementations, depending on the circuit design of the upper transistor drive unit, the delay compensation unit 240 may require more analog transistors to accurately simulate the delays at each stage in the drive path, thereby further improving the accuracy of delay compensation. Therefore, this disclosure is not limited to a specific number of analog transistors, and can be flexibly adjusted according to the propagation delay in the upper transistor drive path.

[0123] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0124] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A gate drive circuit for a power converter, the power converter including an upper transistor and a lower transistor connected in series, the gate drive circuit comprising: The upper transistor driving unit is configured to generate a first gate driving signal for the upper transistor according to a first logic signal; The delay compensation unit is configured to perform delay compensation on the second logic signal to generate an intermediate logic signal, and the delay time corresponds to the conduction response time of the upper transistor. as well as The lower transistor drive unit is configured to generate a second gate drive signal for the lower transistor based on the intermediate logic signal.

2. The gate driving circuit according to claim 1, wherein, The delay compensation unit is configured such that the delay time is less than the time it takes for the gate voltage of the upper transistor to rise from zero to its Miller plateau voltage.

3. The gate driving circuit according to claim 1 or 2, wherein, The delay compensation unit includes: A current module is configured to generate an injection current proportional to the load current of the power converter; and The first analog transistor has the same conductivity type as the upper transistor and its width-to-length ratio is scaled according to a first predetermined ratio. The gate of the first analog transistor receives an analog gate drive signal that rises synchronously with the first gate drive signal, and its drain generates the intermediate logic signal. The current module provides the injected current to the drain of the first analog transistor.

4. The gate driving circuit according to claim 3, wherein, Both the first analog transistor and the upper transistor are high-voltage NMOS devices.

5. The gate driving circuit according to claim 3, wherein, The upper tube drive unit includes: The first pull-up transistor and the first pull-down transistor, connected in series, generate the first gate drive signal at their midpoint. The first pull-up transistor and the first pull-down transistor are used to pull up and pull down the level of the first gate drive signal, respectively.

6. The gate driving circuit according to claim 5, wherein, The width-to-length ratio of the first analog transistor and the upper transistor is equal.

7. The gate driving circuit according to claim 5, wherein, The delay compensation unit further includes: The second analog transistor has the same conductivity type as the first pull-up transistor and its aspect ratio is scaled according to a second predetermined ratio; and The second pull-down transistor is connected in series with the second analog transistor, and generates the analog gate drive signal at the midpoint between the two. The second analog transistor and the second pull-down transistor are used to pull up and pull down the level of the analog gate drive signal, respectively.

8. The gate driving circuit according to claim 7, wherein, The width-to-length ratio of the second analog transistor and the first pull-up transistor is the same.

9. The gate driving circuit according to claim 5, wherein, The width-to-length ratio of the first analog transistor, the second analog transistor, the upper transistor, and the first pull-up transistor conforms to the following formula: Where Wh and Lh represent the width and length of the upper transistor, respectively; Wp1 and Lp1 represent the width and length of the first pull-up transistor in the upper transistor drive unit, respectively; W1 and L1 represent the width and length of the first analog transistor, respectively; and Wp2 and Lp2 represent the width and length of the second analog transistor, respectively.

10. The gate drive circuit according to claim 5 or 6, wherein, The upper tube drive unit also includes: A third transistor, connected in parallel with the first pull-up transistor, is used to enable fast drive after the first pull-up transistor rises to the Miller plateau voltage.

11. The gate driving circuit according to claim 3, wherein, The current module includes: A current source for generating a first current corresponding to the load current of the power converter; and A first current mirror is used to mirror the first current to the drain of the first analog transistor to generate the injected current.

12. The gate driving circuit according to claim 11, wherein, The current source also includes: A voltage-to-current conversion unit is used to convert the compensation voltage in the control loop of the power converter into a compensation current; and The second current mirror is used to mirror the compensation current into the first current.

13. The gate driving circuit according to claim 1, wherein, The first logic signal and the second logic signal are complementary signals generated by the control circuit of the power converter.

14. The gate driving circuit according to claim 1, wherein, The first logic signal and the second logic signal are in-phase signals generated by the control circuit of the power converter.

15. A gate driving method for a power converter, the power converter including an upper transistor and a lower transistor connected in series, the gate driving method comprising: The turn-off time of the lower tube is controlled based on the conduction response time of the upper tube to dynamically adjust the dead time.

16. The gate driving method according to claim 15, further comprising: A first gate drive signal for the upper transistor is generated based on the first logic signal. The step of controlling the conduction time of the lower tube based on the conduction response time of the upper tube includes: The second logic signal is delayed to generate an intermediate logic signal, the delay time corresponding to the turn-on response time of the upper transistor; and A second gate drive signal for the lower transistor is generated based on the intermediate logic signal.

17. The gate driving method according to claim 16, wherein, The delay time is less than the time it takes for the gate voltage of the upper transistor to rise from zero to its Miller plateau voltage.

18. The gate driving method according to claim 16 or 17, wherein, The step of delay compensation for the second logic signal includes: Obtain an injection current that is proportional to the load current of the power converter; Obtain an analog gate drive signal that rises synchronously with the first gate drive signal; and The intermediate logic signal is obtained based on the analog gate drive signal and the injected current.

19. The gate driving method according to claim 18, wherein, The steps for obtaining the intermediate logic signal include: The analog gate drive signal is provided to the gate of the first analog transistor; The injected current is provided to the drain of the first analog transistor; and The intermediate logic signal is obtained at the drain of the first analog transistor. The first analog transistor and the upper transistor have the same conductivity type and their width-to-length ratio is scaled according to a first predetermined ratio.

20. The gate driving method according to claim 18, wherein, The step of generating the injected current includes: The compensation voltage in the control loop of the power converter is converted into a compensation current. The compensation current is mirrored as the injection current.

21. The gate driving method according to claim 16, wherein, The first logic signal and the second logic signal are complementary signals generated by the control circuit of the power converter.

22. The gate driving method according to claim 16, wherein, The first logic signal and the second logic signal are in-phase signals generated by the control circuit of the power converter.

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